ralink_reg.h revision 1.5
1 /* $NetBSD: ralink_reg.h,v 1.5 2014/04/19 12:48:03 matt Exp $ */ 2 /*- 3 * Copyright (c) 2011 CradlePoint Technology, Inc. 4 * All rights reserved. 5 * 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY CRADLEPOINT TECHNOLOGY, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains the configuration parameters for the RT3052 board. 31 */ 32 33 #ifndef _RALINK_REG_H_ 34 #define _RALINK_REG_H_ 35 36 #include <mips/cpuregs.h> 37 38 #if defined(RT3050) 39 #define RA_CLOCK_RATE 320000000 40 #define RA_BUS_FREQ (RA_CLOCK_RATE / 3) 41 #define RA_UART_FREQ RA_BUS_FREQ 42 #elif defined(RT3052) 43 #define RA_CLOCK_RATE 384000000 44 #define RA_BUS_FREQ (RA_CLOCK_RATE / 3) 45 #define RA_UART_FREQ RA_BUS_FREQ 46 #elif defined(RT3883) 47 #if 0 48 #define RA_CLOCK_RATE 480000000 49 #else 50 #define RA_CLOCK_RATE 500000000 51 #endif 52 #define RA_BUS_FREQ 166000000 /* DDR speed */ 53 #define RA_UART_FREQ 40000000 54 #else 55 /* Ralink dev board */ 56 #define RA_CLOCK_RATE 384000000 57 #define RA_BUS_FREQ (RA_CLOCK_RATE / 3) 58 #define RA_UART_FREQ RA_BUS_FREQ 59 #endif 60 61 #define RA_BAUDRATE CONSPEED 62 #define RA_SERIAL_CLKDIV 16 63 64 #define RA_SRAM_BASE 0x00000000 65 #define RA_SRAM_END 0x0FFFFFFF 66 #define RA_SYSCTL_BASE 0x10000000 67 #define RA_TIMER_BASE 0x10000100 68 #define RA_INTCTL_BASE 0x10000200 69 #define RA_MEMCTL_BASE 0x10000300 70 #if defined(RT3052) || defined(RT3050) 71 #define RA_PCM_BASE 0x10000400 72 #endif 73 #define RA_UART_BASE 0x10000500 74 #define RA_PIO_BASE 0x10000600 75 #if defined(RT3052) || defined(RT3050) 76 #define RA_GDMA_BASE 0x10000700 77 #elif defined(RT3883) 78 #define RA_FLASHCTL_BASE 0x10000700 79 #endif 80 #define RA_NANDCTL_BASE 0x10000800 81 #define RA_I2C_BASE 0x10000900 82 #define RA_I2S_BASE 0x10000A00 83 #define RA_SPI_BASE 0x10000B00 84 #define RA_UART_LITE_BASE 0x10000C00 85 #if defined(RT3883) 86 #define RA_PCM_BASE 0x10002000 87 #define RA_GDMA_BASE 0x10002800 88 #define RA_CODEC1_BASE 0x10003000 89 #define RA_CODEC2_BASE 0x10003800 90 #endif 91 #define RA_FRAME_ENGINE_BASE 0x10100000 92 #define RA_ETH_SW_BASE 0x10110000 93 #define RA_ROM_BASE 0x10118000 94 #if defined(RT3883) || defined(MT7620) 95 #define RA_USB_DEVICE_BASE 0x10120000 96 #if defined(MT7620) 97 #define RA_SDHC_BASE 0x10130000 98 #endif 99 #define RA_PCI_BASE 0x10140000 100 #define RA_PCIWIN_BASE 0x10150000 101 #endif 102 #define RA_11N_MAC_BASE 0x10180000 103 #define RA_USB_OTG_BASE 0x101C0000 104 #if defined(RT3883) || defined(MT7620) 105 #define RA_USB_HOST_BASE 0x101C0000 106 #endif 107 #if defined(RT3052) || defined(RT3050) 108 #define RA_FLASH_BASE 0x1F000000 109 #define RA_FLASH_END 0x1F7FFFFF 110 #elif defined(RT3883) 111 #define RA_FLASH_BASE 0x1C000000 112 #define RA_FLASH_END 0x1DFFFFFF 113 #endif 114 115 #define RA_IOREG_VADDR(base, offset) \ 116 (volatile uint32_t *)MIPS_PHYS_TO_KSEG1((base) + (offset)) 117 118 #define FLD_GET(val,pos,mask) (((val) >> (pos)) & (mask)) 119 #define FLD_SET(val,pos,mask) (((val) & (mask)) << (pos)) 120 121 /* 122 * System Control Registers 123 */ 124 #define RA_SYSCTL_ID0 0x00 125 #define RA_SYSCTL_ID1 0x04 126 #define RA_SYSCTL_REVID 0x0c 127 #define RA_SYSCTL_CFG0 0x10 128 #define RA_SYSCTL_CFG1 0x14 129 #define RA_SYSCTL_CLKCFG0 0x2C 130 #define RA_SYSCTL_CLKCFG1 0x30 131 #define RA_SYSCTL_RST 0x34 132 #define RA_SYSCTL_RSTSTAT 0x38 133 #define RA_SYSCTL_GPIOMODE 0x60 134 135 #if defined(RT3050) || defined(RT3052) 136 #define SYSCTL_CFG0_INIC_EE_SDRAM __BIT(29) 137 #define SYSCTL_CFG0_INIC_8MB_SDRAM __BIT(28) 138 #define SYSCTL_CFG0_GE0_MODE __BITS(24,25) 139 #define SYSCTL_CFG0_BYPASS_PLL __BIT(21) 140 #define SYSCTL_CFG0_BE __BIT(20) 141 #define SYSCTL_CFG0_CPU_CLK_SEL __BIT(18) 142 #define SYSCTL_CFG0_BOOT_FROM __BITS(16,17) 143 #define SYSCTL_CFG0_TEST_CODE __BITS(8,15) 144 #define SYSCTL_CFG0_SRAM_CS_MODE __BITS(2,3) 145 #define SYSCTL_CFG0_SDRAM_CLK_DRV __BIT(0) 146 #elif defined(RT3883) 147 #define SYSCTL_CFG0_BE __BIT(19) 148 #define SYSCTL_CFG0_DRAM_SIZE __BITS(12,14) 149 #define SYSCTL_CFG0_DRAM_2MB 0 150 #define SYSCTL_CFG0_DRAM_8MB 1 151 #define SYSCTL_CFG0_DRAM_16MB 2 152 #define SYSCTL_CFG0_DRAM_32MB 3 153 #define SYSCTL_CFG0_DRAM_64MB 4 154 #define SYSCTL_CFG0_DRAM_128MB 5 155 #define SYSCTL_CFG0_DRAM_256MB 6 156 #elif defined(MT7620) 157 #define SYSCTL_CFG0_TEST_CODE __BITS(31,24) 158 #define SYSCTL_CFG0_BS_SHADOW __BITS(22,12) 159 #define SYSCTL_CFG0_DRAM_FROM_EE __BIT(8) 160 #define SYSCTL_CFG0_DBG_JTAG_MODE __BIT(7) 161 #define SYSCTL_CFG0_XTAL_FREQ_SEL __BIT(6) 162 #define SYSCTL_CFG0_DRAM_TYPE __BITS(5,4) 163 #define SYSCTL_CFG0_CHIP_MODE __BITS(3,0) 164 #endif 165 166 #if defined(RT3883) || defined(MT7620) 167 /* 3883 doesn't have memo regs, use teststat instead */ 168 #define RA_SYSCTL_MEMO0 0x18 169 #define RA_SYSCTL_MEMO1 0x1C 170 #else 171 #define RA_SYSCTL_MEMO0 0x68 172 #define RA_SYSCTL_MEMO1 0x6C 173 #endif 174 175 #define RST_PPE __BIT(31) 176 #define RST_SDHC __BIT(30) 177 #define RST_MIPS_CNT __BIT(28) 178 #define RST_PCIE0 __BIT(26) 179 #define RST_UHST0 __BIT(25) 180 #define RST_EPHY __BIT(24) 181 #define RST_SW __BIT(23) 182 #define RST_OTG __BIT(22) 183 #define RST_FE __BIT(21) 184 #define RST_WLAN __BIT(20) 185 #define RST_UARTL __BIT(19) 186 #define RST_SPI __BIT(18) 187 #define RST_I2S __BIT(17) 188 #define RST_I2C __BIT(16) 189 #define RST_NAND __BIT(15) 190 #define RST_DMA __BIT(14) 191 #define RST_PIO __BIT(13) 192 #define RST_UART __BIT(12) 193 #define RST_PCM __BIT(11) 194 #define RST_MC __BIT(10) 195 #define RST_INTC __BIT(9) 196 #define RST_TIMER __BIT(8) 197 #define RST_GE2 __BIT(7) 198 #define RST_GE1 __BIT(6) 199 #define RST_SYS __BIT(0) 200 #define GPIOMODE_RGMII __BIT(9) 201 #define GPIOMODE_SDRAM __BIT(8) 202 #define GPIOMODE_MDIO __BIT(7) 203 #define GPIOMODE_JTAG __BIT(6) 204 #define GPIOMODE_UARTL __BIT(5) 205 #define GPIOMODE_UARTF2 __BIT(4) 206 #define GPIOMODE_UARTF1 __BIT(3) 207 #define GPIOMODE_UARTF0 __BIT(2) 208 #define GPIOMODE_UARTF_0_2 \ 209 (GPIOMODE_UARTF0|GPIOMODE_UARTF1|GPIOMODE_UARTF2) 210 #define GPIOMODE_SPI __BIT(1) 211 #define GPIOMODE_I2C __BIT(0) 212 213 /* 214 * Timer Registers 215 */ 216 #define RA_TIMER_STAT 0x00 217 #define RA_TIMER_0_LOAD 0x10 218 #define RA_TIMER_0_VALUE 0x14 219 #define RA_TIMER_0_CNTRL 0x18 220 #define RA_TIMER_1_LOAD 0x20 221 #define RA_TIMER_1_VALUE 0x24 222 #define RA_TIMER_1_CNTRL 0x28 223 224 #define TIMER_1_RESET __BIT(5) 225 #define TIMER_0_RESET __BIT(4) 226 #define TIMER_1_INT_STATUS __BIT(1) 227 #define TIMER_0_INT_STATUS __BIT(0) 228 #define TIMER_TEST_EN __BIT(15) 229 #define TIMER_EN __BIT(7) 230 #define TIMER_MODE(x) (((x) & 0x3) << 4) 231 #define TIMER_MODE_FREE 0 232 #define TIMER_MODE_PERIODIC 1 233 #define TIMER_MODE_TIMEOUT 2 234 #define TIMER_MODE_WDOG 3 /* only valid for TIMER_1 */ 235 #define TIMER_PRESCALE(x) (((x) & 0xf) << 0) 236 #define TIMER_PRESCALE_DIV_1 0 237 #define TIMER_PRESCALE_DIV_4 1 238 #define TIMER_PRESCALE_DIV_8 2 239 #define TIMER_PRESCALE_DIV_16 3 240 #define TIMER_PRESCALE_DIV_32 4 241 #define TIMER_PRESCALE_DIV_64 5 242 #define TIMER_PRESCALE_DIV_128 6 243 #define TIMER_PRESCALE_DIV_256 7 244 #define TIMER_PRESCALE_DIV_512 8 245 #define TIMER_PRESCALE_DIV_1024 9 246 #define TIMER_PRESCALE_DIV_2048 10 247 #define TIMER_PRESCALE_DIV_4096 11 248 #define TIMER_PRESCALE_DIV_8192 12 249 #define TIMER_PRESCALE_DIV_16384 13 250 #define TIMER_PRESCALE_DIV_32768 14 251 #define TIMER_PRESCALE_DIV_65536 15 252 253 /* 254 * Interrupt Controller Registers 255 */ 256 #define RA_INTCTL_IRQ0STAT 0x00 257 #define RA_INTCTL_IRQ1STAT 0x04 258 #define RA_INTCTL_TYPE 0x20 259 #define RA_INTCTL_RAW 0x30 260 #define RA_INTCTL_ENABLE 0x34 261 #define RA_INTCTL_DISABLE 0x38 262 263 264 #define INT_GLOBAL __BIT(31) 265 #define INT_UDEV __BIT(19) 266 #define INT_USB __BIT(18) 267 #define INT_ETHSW __BIT(17) 268 #define INT_R2P __BIT(15) 269 #define INT_SDHC __BIT(14) 270 #define INT_UARTL __BIT(12) 271 #define INT_SPI __BIT(11) 272 #define INT_I2S __BIT(10) 273 #define INT_PERF __BIT(9) 274 #define INT_NAND __BIT(8) 275 #define INT_DMA __BIT(7) 276 #define INT_PIO __BIT(6) 277 #define INT_UARTF __BIT(5) 278 #define INT_PCM __BIT(4) 279 #define INT_ILLACC __BIT(3) 280 #define INT_WDOG __BIT(2) 281 #define INT_TIMER0 __BIT(1) 282 #define INT_SYSCTL __BIT(0) 283 284 /* 285 * Ralink Linear CPU Interrupt Mapping For Lists 286 */ 287 #define RA_IRQ_LOW 0 288 #define RA_IRQ_HIGH 1 289 #define RA_IRQ_PCI 2 290 #define RA_IRQ_FENGINE 3 291 #define RA_IRQ_WLAN 4 292 #define RA_IRQ_TIMER 5 293 #define RA_IRQ_SYSCTL 6 294 #define RA_IRQ_TIMER0 7 295 #define RA_IRQ_WDOG 8 296 #define RA_IRQ_ILLACC 9 297 #define RA_IRQ_PCM 10 298 #define RA_IRQ_UARTF 11 299 #define RA_IRQ_PIO 12 300 #define RA_IRQ_DMA 13 301 #define RA_IRQ_NAND 14 302 #define RA_IRQ_PERF 15 303 #define RA_IRQ_I2S 16 304 #define RA_IRQ_UARTL 17 305 #define RA_IRQ_ETHSW 18 306 #define RA_IRQ_USB 19 307 #define RA_IRQ_MAX 20 308 309 /* 310 * General Purpose I/O 311 */ 312 #define RA_PIO_00_23_INT 0x00 313 #define RA_PIO_00_23_EDGE_INT 0x04 314 #define RA_PIO_00_23_INT_RISE_EN 0x08 315 #define RA_PIO_00_23_INT_FALL_EN 0x0C 316 #define RA_PIO_00_23_DATA 0x20 317 #define RA_PIO_00_23_DIR 0x24 318 #define RA_PIO_00_23_POLARITY 0x28 319 #define RA_PIO_00_23_SET_BIT 0x2C 320 #define RA_PIO_00_23_CLR_BIT 0x30 321 #define RA_PIO_00_23_TGL_BIT 0x34 322 #define RA_PIO_24_39_INT 0x38 323 #define RA_PIO_24_39_EDGE_INT 0x3C 324 #define RA_PIO_24_39_INT_RISE_EN 0x40 325 #define RA_PIO_24_39_INT_FALL_EN 0x44 326 #define RA_PIO_24_39_DATA 0x48 327 #define RA_PIO_24_39_DIR 0x4C 328 #define RA_PIO_24_39_POLARITY 0x50 329 #define RA_PIO_24_39_SET_BIT 0x54 330 #define RA_PIO_24_39_CLR_BIT 0x58 331 #define RA_PIO_24_39_TGL_BIT 0x5C 332 #define RA_PIO_40_51_INT 0x60 333 #define RA_PIO_40_51_EDGE_INT 0x64 334 #define RA_PIO_40_51_INT_RISE_EN 0x68 335 #define RA_PIO_40_51_INT_FALL_EN 0x6C 336 #define RA_PIO_40_51_DATA 0x70 337 #define RA_PIO_40_51_DIR 0x74 338 #define RA_PIO_40_51_POLARITY 0x78 339 #define RA_PIO_40_51_SET_BIT 0x7C 340 #define RA_PIO_40_51_CLR_BIT 0x80 341 #define RA_PIO_40_51_TGL_BIT 0x84 342 #define RA_PIO_72_95_INT 0x88 343 #define RA_PIO_72_95_EDGE_INT 0x8c 344 #define RA_PIO_72_95_INT_RISE_EN 0x90 345 #define RA_PIO_72_95_INT_FALL_EN 0x94 346 #define RA_PIO_72_95_DATA 0x98 347 #define RA_PIO_72_95_DIR 0x9c 348 #define RA_PIO_72_95_POLARITY 0xa0 349 #define RA_PIO_72_95_SET_BIT 0xa4 350 #define RA_PIO_72_95_CLR_BIT 0xa8 351 #define RA_PIO_72_95_TGL_BIT 0xac 352 353 354 /* 355 * UART registers 356 */ 357 358 #define RA_UART_RBR 0x00 359 #define RA_UART_TBR 0x04 360 #define RA_UART_IER 0x08 361 #define RA_UART_IIR 0x0C 362 #define RA_UART_FCR 0x10 363 #define RA_UART_LCR 0x14 364 #define RA_UART_MCR 0x18 365 #define RA_UART_LSR 0x1C 366 #define RA_UART_MSR 0x20 367 #define RA_UART_DLL 0x28 368 369 370 #define UART_IER_ELSI __BIT(2) 371 /* Receiver Line Status Interrupt Enable */ 372 #define UART_IER_ETBEI __BIT(1) 373 /* Transmit Buffer Empty Interrupt Enable */ 374 #define UART_IER_ERBFI __BIT(0) 375 /* Data Ready or Character Time-Out Interrupt Enable */ 376 377 #define UART_IIR_FIFOES1 __BIT(7) /* FIFO Mode Enable Status */ 378 #define UART_IIR_FIFOES0 __BIT(6) /* FIFO Mode Enable Status */ 379 #define UART_IIR_IID3 __BIT(3) /* Interrupt Source Encoded */ 380 #define UART_IIR_IID2 __BIT(2) /* Interrupt Source Encoded */ 381 #define UART_IIR_IID1 __BIT(1) /* Interrupt Source Encoded */ 382 #define UART_IIR_IP __BIT(0) /* Interrupt Pending (active low) */ 383 384 #define UART_FCR_RXTRIG1 __BIT(7) /* Receiver Interrupt Trigger Level */ 385 #define UART_FCR_RXTRIG0 __BIT(6) /* Receiver Interrupt Trigger Level */ 386 #define UART_FCR_TXTRIG1 __BIT(5) /* Transmitter Interrupt Trigger Level */ 387 #define UART_FCR_TXTRIG0 __BIT(4) /* Transmitter Interrupt Trigger Level */ 388 #define UART_FCR_DMAMODE __BIT(3) /* Enable DMA transfers */ 389 #define UART_FCR_TXRST __BIT(2) /* Reset Transmitter FIFO */ 390 #define UART_FCR_RXRST __BIT(1) /* Reset Receiver FIFO */ 391 #define UART_FCR_FIFOE __BIT(0) /* Transmit and Receive FIFO Enable */ 392 393 #define UART_LCR_DLAB __BIT(7) /* Divisor Latch Access Bit */ 394 #define UART_LCR_SB __BIT(6) /* Set Break */ 395 #define UART_LCR_STKYP __BIT(5) /* Sticky Parity */ 396 #define UART_LCR_EPS __BIT(4) /* Even Parity Select */ 397 #define UART_LCR_PEN __BIT(3) /* Parity Enable */ 398 #define UART_LCR_STB __BIT(2) /* Stop Bit */ 399 #define UART_LCR_WLS1 __BIT(1) /* Word Length Select */ 400 #define UART_LCR_WLS0 __BIT(0) /* Word Length Select */ 401 402 #define UART_MCR_LOOP __BIT(4) /* Loop-back Mode Enable */ 403 404 #define UART_MSR_DCD __BIT(7) /* Data Carrier Detect */ 405 #define UART_MSR_RI __BIT(6) /* Ring Indicator */ 406 #define UART_MSR_DSR __BIT(5) /* Data Set Ready */ 407 #define UART_MSR_CTS __BIT(4) /* Clear To Send */ 408 #define UART_MSR_DDCD __BIT(3) /* Delta Data Carrier Detect */ 409 #define UART_MSR_TERI __BIT(2) /* Trailing Edge Ring Indicator */ 410 #define UART_MSR_DDSR __BIT(1) /* Delta Data Set Ready */ 411 #define UART_MSR_DCTS __BIT(0) /* Delta Clear To Send */ 412 413 #define UART_LSR_FIFOE __BIT(7) /* FIFO Error Status */ 414 #define UART_LSR_TEMT __BIT(6) /* Transmitter Empty */ 415 #define UART_LSR_TDRQ __BIT(5) /* Transmit Data Request */ 416 #define UART_LSR_BI __BIT(4) /* Break Interrupt */ 417 #define UART_LSR_FE __BIT(3) /* Framing Error */ 418 #define UART_LSR_PE __BIT(2) /* Parity Error */ 419 #define UART_LSR_OE __BIT(1) /* Overrun Error */ 420 #define UART_LSR_DR __BIT(0) /* Data Ready */ 421 422 /* 423 * I2C registers 424 */ 425 #define RA_I2C_CONFIG 0x00 426 #define RA_I2C_CLKDIV 0x04 427 #define RA_I2C_DEVADDR 0x08 428 #define RA_I2C_ADDR 0x0C 429 #define RA_I2C_DATAOUT 0x10 430 #define RA_I2C_DATAIN 0x14 431 #define RA_I2C_STATUS 0x18 432 #define RA_I2C_STARTXFR 0x1C 433 #define RA_I2C_BYTECNT 0x20 434 435 #define I2C_CONFIG_ADDRLEN(x) (((x) & 0x7) << 5) 436 #define I2C_CONFIG_ADDRLEN_7 6 437 #define I2C_CONFIG_ADDRLEN_8 7 438 #define I2C_CONFIG_DEVADLEN(x) (((x) & 0x7) << 2) 439 #define I2C_CONFIG_DEVADLEN_6 5 440 #define I2C_CONFIG_DEVADLEN_7 6 441 #define I2C_CONFIG_ADDRDIS __BIT(1) 442 #define I2C_CONFIG_DEVDIS __BIT(0) 443 #define I2C_STATUS_STARTERR __BIT(4) 444 #define I2C_STATUS_ACKERR __BIT(3) 445 #define I2C_STATUS_DATARDY __BIT(2) 446 #define I2C_STATUS_SDOEMPTY __BIT(1) 447 #define I2C_STATUS_BUSY __BIT(0) 448 449 /* 450 * SPI registers 451 */ 452 #define RA_SPI_STATUS 0x00 453 #define RA_SPI_CONFIG 0x10 454 #define RA_SPI_CONTROL 0x14 455 #define RA_SPI_DATA 0x20 456 457 #define SPI_STATUS_BUSY __BIT(0) 458 #define SPI_CONFIG_MSBFIRST __BIT(8) 459 #define SPI_CONFIG_CLK __BIT(6) 460 #define SPI_CONFIG_RXCLKEDGE_FALL __BIT(5) 461 #define SPI_CONFIG_TXCLKEDGE_FALL __BIT(4) 462 #define SPI_CONFIG_TRISTATE __BIT(3) 463 #define SPI_CONFIG_RATE(x) ((x) & 0x7) 464 #define SPI_CONFIG_RATE_DIV_2 0 465 #define SPI_CONFIG_RATE_DIV_4 1 466 #define SPI_CONFIG_RATE_DIV_8 2 467 #define SPI_CONFIG_RATE_DIV_16 3 468 #define SPI_CONFIG_RATE_DIV_32 4 469 #define SPI_CONFIG_RATE_DIV_64 5 470 #define SPI_CONFIG_RATE_DIV_128 6 471 #define SPI_CONFIG_RATE_DIV_NONE 7 472 #define SPI_CONTROL_TRISTATE __BIT(3) 473 #define SPI_CONTROL_STARTWR __BIT(2) 474 #define SPI_CONTROL_STARTRD __BIT(1) 475 #define SPI_CONTROL_ENABLE_LOW (0 << 0) 476 #define SPI_CONTROL_ENABLE_HIGH __BIT(0) 477 #define SPI_DATA_VAL(x) ((x) & 0xff) 478 479 /* 480 * Frame Engine registers 481 */ 482 #define RA_FE_MDIO_ACCESS 0x000 483 #define RA_FE_MDIO_CFG1 0x004 484 #define RA_FE_GLOBAL_CFG 0x008 485 #define RA_FE_GLOBAL_RESET 0x00C 486 #define RA_FE_INT_STATUS 0x010 487 #define RA_FE_INT_ENABLE 0x014 488 #define RA_FE_MDIO_CFG2 0x018 489 #define RA_FE_TIME_STAMP 0x01C 490 #define RA_FE_GDMA1_FWD_CFG 0x020 491 #define RA_FE_GDMA1_SCHED_CFG 0x024 492 #define RA_FE_GDMA1_SHAPE_CFG 0x028 493 #define RA_FE_GDMA1_MAC_LSB 0x02C 494 #define RA_FE_GDMA1_MAC_MSB 0x030 495 #define RA_FE_PSE_FQ_CFG 0x040 496 #define RA_FE_CDMA_FC_CFG 0x044 497 #define RA_FE_GDMA1_FC_CFG 0x048 498 #define RA_FE_GDMA2_FC_CFG 0x04C 499 #define RA_FE_CDMA_OQ_STA 0x050 500 #define RA_FE_GDMA1_OQ_STA 0x054 501 #define RA_FE_GDMA2_OQ_STA 0x058 502 #define RA_FE_PSE_IQ_STA 0x05C 503 #define RA_FE_GDMA2_FWD_CFG 0x060 504 #define RA_FE_GDMA2_SCHED_CFG 0x064 505 #define RA_FE_GDMA2_SHAPE_CFG 0x068 506 #define RA_FE_GDMA2_MAC_LSB 0x06C 507 #define RA_FE_GDMA2_MAC_MSB 0x070 508 #define RA_FE_CDMA_CSG_CFG 0x080 509 #define RA_FE_CDMA_SCHED_CFG 0x084 510 #define RA_FE_PPPOE_SID_0001 0x088 511 #define RA_FE_PPPOE_SID_0203 0x08C 512 #define RA_FE_PPPOE_SID_0405 0x090 513 #define RA_FE_PPPOE_SID_0607 0x094 514 #define RA_FE_PPPOE_SID_0809 0x098 515 #define RA_FE_PPPOE_SID_1011 0x09C 516 #define RA_FE_PPPOE_SID_1213 0x0A0 517 #define RA_FE_PPPOE_SID_1415 0x0A4 518 #define RA_FE_VLAN_ID_0001 0x0A8 519 #define RA_FE_VLAN_ID_0203 0x0AC 520 #define RA_FE_VLAN_ID_0405 0x0B0 521 #define RA_FE_VLAN_ID_0607 0x0B4 522 #define RA_FE_VLAN_ID_0809 0x0B8 523 #define RA_FE_VLAN_ID_1011 0x0BC 524 #define RA_FE_VLAN_ID_1213 0x0C0 525 #define RA_FE_VLAN_ID_1415 0x0C4 526 #define RA_FE_PDMA_GLOBAL_CFG 0x100 527 #define RA_FE_PDMA_RESET_IDX 0x104 528 #define RA_FE_PDMA_SCHED_CFG 0x108 529 #define RA_FE_PDMA_DLY_INT_CFG 0x10C 530 #define RA_FE_PDMA_TX0_PTR 0x110 531 #define RA_FE_PDMA_TX0_COUNT 0x114 532 #define RA_FE_PDMA_TX0_CPU_IDX 0x118 533 #define RA_FE_PDMA_TX0_DMA_IDX 0x11C 534 #define RA_FE_PDMA_TX1_PTR 0x120 535 #define RA_FE_PDMA_TX1_COUNT 0x124 536 #define RA_FE_PDMA_TX1_CPU_IDX 0x128 537 #define RA_FE_PDMA_TX1_DMA_IDX 0x12C 538 #define RA_FE_PDMA_RX0_PTR 0x130 539 #define RA_FE_PDMA_RX0_COUNT 0x134 540 #define RA_FE_PDMA_RX0_CPU_IDX 0x138 541 #define RA_FE_PDMA_RX0_DMA_IDX 0x13C 542 #define RA_FE_PDMA_TX2_PTR 0x140 543 #define RA_FE_PDMA_TX2_COUNT 0x144 544 #define RA_FE_PDMA_TX2_CPU_IDX 0x148 545 #define RA_FE_PDMA_TX2_DMA_IDX 0x14C 546 #define RA_FE_PDMA_TX3_PTR 0x150 547 #define RA_FE_PDMA_TX3_COUNT 0x154 548 #define RA_FE_PDMA_TX3_CPU_IDX 0x158 549 #define RA_FE_PDMA_TX3_DMA_IDX 0x15C 550 #define RA_FE_PDMA_FC_CFG 0x1F0 551 /* TODO: FE_COUNTERS */ 552 553 #define MDIO_ACCESS_TRG __BIT(31) 554 #define MDIO_ACCESS_WR __BIT(30) 555 #define MDIO_ACCESS_PHY_ADDR(x) (((x) & 0x1f) << 24) 556 #define MDIO_ACCESS_REG(x) (((x) & 0x1f) << 16) 557 #define MDIO_ACCESS_DATA(x) ((x) & 0xffff) 558 #define MDIO_CFG_AUTO_POLL __BIT(29) 559 #define MDIO_CFG_PHY_ADDR(x) (((x) & 0x1f) << 24) 560 #define MDIO_CFG_BP_EN __BIT(16) 561 #define MDIO_CFG_FORCE_CFG __BIT(15) 562 #define MDIO_CFG_SPEED(x) (((x) & 0x3) << 13) 563 #define MDIO_CFG_SPEED_1000M 2 564 #define MDIO_CFG_SPEED_100M 1 565 #define MDIO_CFG_SPEED_10M 0 566 #define MDIO_CFG_FULL_DUPLEX __BIT(12) 567 #define MDIO_CFG_FC_TX __BIT(11) 568 #define MDIO_CFG_FC_RX __BIT(10) 569 #define MDIO_CFG_LINK_DOWN __BIT(9) 570 #define MDIO_CFG_AUTO_DONE __BIT(8) 571 #define MDIO_CFG_MDC_CLKDIV(x) (((x) & 0x3) << 6) 572 #define MDIO_CFG_MDC_512KHZ 3 573 #define MDIO_CFG_MDC_1MHZ 2 574 #define MDIO_CFG_MDC_2MHZ 1 575 #define MDIO_CFG_MDC_4MHZ 0 576 #define MDIO_CFG_TURBO_50MHZ __BIT(5) 577 #define MDIO_CFG_TURBO_EN __BIT(4) 578 #define MDIO_CFG_RX_CLK_SKEW (((x) & 0x3) << 2) 579 #define MDIO_CFG_RX_SKEW_INV 3 580 #define MDIO_CFG_RX_SKEW_400PS 2 581 #define MDIO_CFG_RX_SKEW_200PS 1 582 #define MDIO_CFG_RX_SKEW_ZERO 0 583 #define MDIO_CFG_TX_CLK_MODE(x) (((x) & 0x1) << 0) 584 #define MDIO_CFG_TX_CLK_MODE_3COM 1 585 #define MDIO_CFG_TX_CLK_MODE_HP 0 586 #define FE_GLOBAL_CFG_EXT_VLAN(x) (((x) & 0xffff) << 16) 587 #define FE_GLOBAL_CFG_US_CLK(x) (((x) & 0xff) << 8) 588 #define FE_GLOBAL_CFG_L2_SPACE(x) (((x) & 0xf) << 4) 589 #define FE_GLOBAL_RESET_PSE __BIT(0) 590 #define FE_INT_PPE_COUNT_HIGH __BIT(31) 591 #define FE_INT_DMA_COUNT_HIGH __BIT(29) 592 #define FE_INT_PSE_P2_FC_ASSERT __BIT(26) 593 #define FE_INT_PSE_FC_DROP __BIT(24) 594 #define FE_INT_GDMA_DROP_OTHER __BIT(23) 595 #define FE_INT_PSE_P1_FC_ASSERT __BIT(22) 596 #define FE_INT_PSE_P0_FC_ASSERT __BIT(21) 597 #define FE_INT_PSE_FQ_EMPTY __BIT(20) 598 #define FE_INT_TX_COHERENT __BIT(17) 599 #define FE_INT_RX_COHERENT __BIT(16) 600 #define FE_INT_TX3 __BIT(11) 601 #define FE_INT_TX2 __BIT(10) 602 #define FE_INT_TX1 __BIT(9) 603 #define FE_INT_TX0 __BIT(8) 604 #define FE_INT_RX __BIT(2) 605 #define FE_INT_TX_DELAY __BIT(1) 606 #define FE_INT_RX_DELAY __BIT(0) 607 #define FE_GDMA_FWD_CFG_JUMBO_LEN(x) (((x) & 0xf) << 28) 608 #define FE_GDMA_FWD_CFG_DROP_256B __BIT(23) 609 #define FE_GDMA_FWD_CFG_IP4_CRC_EN __BIT(22) 610 #define FE_GDMA_FWD_CFG_TCP_CRC_EN __BIT(21) 611 #define FE_GDMA_FWD_CFG_UDP_CRC_EN __BIT(20) 612 #define FE_GDMA_FWD_CFG_JUMBO_EN __BIT(19) 613 #define FE_GDMA_FWD_CFG_DIS_TX_PAD __BIT(18) 614 #define FE_GDMA_FWD_CFG_DIS_TX_CRC __BIT(17) 615 #define FE_GDMA_FWD_CFG_STRIP_RX_CRC __BIT(16) 616 #define FE_GDMA_FWD_CFG_UNICA_PORT(x) (((x) & 0x3) << 12) 617 #define FE_GDMA_FWD_CFG_BROAD_PORT(x) (((x) & 0x3) << 8) 618 #define FE_GDMA_FWD_CFG_MULTI_PORT(x) (((x) & 0x3) << 6) 619 #define FE_GDMA_FWD_CFG_OTHER_PORT(x) (((x) & 0x3) << 0) 620 #define FE_GDMA_FWD_CFG_PORT_DROP 7 621 #define FE_GDMA_FWD_CFG_PORT_PPE 6 622 #define FE_GDMA_FWD_CFG_PORT_GDMA2 2 623 #define FE_GDMA_FWD_CFG_PORT_GDMA1 1 624 #define FE_GDMA_FWD_CFG_PORT_CPU 0 625 #define FE_PSE_FQ_MAX_COUNT(x) (((x) & 0xff) << 24) 626 #define FE_PSE_FQ_FC_RELEASE(x) (((x) & 0xff) << 16) 627 #define FE_PSE_FQ_FC_ASSERT(x) (((x) & 0xff) << 8) 628 #define FE_PSE_FQ_FC_DROP(x) (((x) & 0xff) << 0) 629 #define FE_CDMA_CSG_CFG_VLAN_TAG(x) (((x) & 0xffff) << 16) 630 #define FE_CDMA_CSG_CFG_IP4_CRC_EN __BIT(2) 631 #define FE_CDMA_CSG_CFG_UDP_CRC_EN __BIT(1) 632 #define FE_CDMA_CSG_CFG_TCP_CRC_EN __BIT(0) 633 #define FE_PDMA_GLOBAL_CFG_HDR_SEG_LEN __BIT(16) 634 #define FE_PDMA_GLOBAL_CFG_TX_WB_DDONE __BIT(6) 635 #define FE_PDMA_GLOBAL_CFG_BURST_SZ(x) (((x) & 0x3) << 4) 636 #define FE_PDMA_GLOBAL_CFG_BURST_SZ_4 (0 << 4) 637 #define FE_PDMA_GLOBAL_CFG_BURST_SZ_8 __BIT(4) 638 #define FE_PDMA_GLOBAL_CFG_BURST_SZ_16 (2 << 4) 639 #define FE_PDMA_GLOBAL_CFG_RX_DMA_BUSY __BIT(3) 640 #define FE_PDMA_GLOBAL_CFG_RX_DMA_EN __BIT(2) 641 #define FE_PDMA_GLOBAL_CFG_TX_DMA_BUSY __BIT(1) 642 #define FE_PDMA_GLOBAL_CFG_TX_DMA_EN __BIT(0) 643 #define PDMA_RST_RX0 __BIT(16) 644 #define PDMA_RST_TX3 __BIT(3) 645 #define PDMA_RST_TX2 __BIT(2) 646 #define PDMA_RST_TX1 __BIT(1) 647 #define PDMA_RST_TX0 __BIT(0) 648 649 /* 650 * 10/100 Switch registers 651 */ 652 653 #define RA_ETH_SW_ISR 0x00 654 #define RA_ETH_SW_IMR 0x04 655 #define RA_ETH_SW_FCT0 0x08 656 #define RA_ETH_SW_FCT1 0x0C 657 #define RA_ETH_SW_PFC0 0x10 658 #define RA_ETH_SW_PFC1 0x14 659 #define RA_ETH_SW_PFC2 0x18 660 #define RA_ETH_SW_QCS0 0x1C 661 #define RA_ETH_SW_QCS1 0x20 662 #define RA_ETH_SW_ATS 0x24 663 #define RA_ETH_SW_ATS0 0x28 664 #define RA_ETH_SW_ATS1 0x2C 665 #define RA_ETH_SW_ATS2 0x30 666 #define RA_ETH_SW_WMAD0 0x34 667 #define RA_ETH_SW_WMAD1 0x38 668 #define RA_ETH_SW_WMAD2 0x3C 669 #define RA_ETH_SW_PVIDC0 0x40 670 #define RA_ETH_SW_PVIDC1 0x44 671 #define RA_ETH_SW_PVIDC2 0x48 672 #define RA_ETH_SW_PVIDC3 0x4C 673 #define RA_ETH_SW_VLANI0 0x50 674 #define RA_ETH_SW_VLANI1 0x54 675 #define RA_ETH_SW_VLANI2 0x58 676 #define RA_ETH_SW_VLANI3 0x5C 677 #define RA_ETH_SW_VLANI4 0x60 678 #define RA_ETH_SW_VLANI5 0x64 679 #define RA_ETH_SW_VLANI6 0x68 680 #define RA_ETH_SW_VLANI7 0x6C 681 #define RA_ETH_SW_VMSC0 0x70 682 #define RA_ETH_SW_VMSC1 0x74 683 #define RA_ETH_SW_VMSC2 0x78 684 #define RA_ETH_SW_VMSC3 0x7C 685 #define RA_ETH_SW_POA 0x80 686 #define RA_ETH_SW_FPA 0x84 687 #define RA_ETH_SW_PTS 0x88 688 #define RA_ETH_SW_SOCPC 0x8C 689 #define RA_ETH_SW_POC0 0x90 690 #define RA_ETH_SW_POC1 0x94 691 #define RA_ETH_SW_POC2 0x98 692 #define RA_ETH_SW_SWGC 0x9C 693 #define RA_ETH_SW_RST 0xA0 694 #define RA_ETH_SW_LEDP0 0xA4 695 #define RA_ETH_SW_LEDP1 0xA8 696 #define RA_ETH_SW_LEDP2 0xAC 697 #define RA_ETH_SW_LEDP3 0xB0 698 #define RA_ETH_SW_LEDP4 0xB4 699 #define RA_ETH_SW_WDOG 0xB8 700 #define RA_ETH_SW_DBG 0xBC 701 #define RA_ETH_SW_PCTL0 0xC0 702 #define RA_ETH_SW_PCTL1 0xC4 703 #define RA_ETH_SW_FPORT 0xC8 704 #define RA_ETH_SW_FTC2 0xCC 705 #define RA_ETH_SW_QSS0 0xD0 706 #define RA_ETH_SW_QSS1 0xD4 707 #define RA_ETH_SW_DBGC 0xD8 708 #define RA_ETH_SW_MTI1 0xDC 709 #define RA_ETH_SW_PPC 0xE0 710 #define RA_ETH_SW_SGC2 0xE4 711 #define RA_ETH_SW_PCNT0 0xE8 712 #define RA_ETH_SW_PCNT1 0xEC 713 #define RA_ETH_SW_PCNT2 0xF0 714 #define RA_ETH_SW_PCNT3 0xF4 715 #define RA_ETH_SW_PCNT4 0xF8 716 #define RA_ETH_SW_PCNT5 0xFC 717 718 #define ISR_WDOG1_EXPIRED __BIT(29) 719 #define ISR_WDOG0_EXPIRED __BIT(28) 720 #define ISR_HAS_INTRUDER __BIT(27) 721 #define ISR_PORT_STS_CHNG __BIT(26) 722 #define ISR_BRDCAST_STORM __BIT(25) 723 #define ISR_MUST_DROP_LAN __BIT(24) 724 #define ISR_GLOB_QUE_FULL __BIT(23) 725 #define ISR_LAN_QUE6_FULL __BIT(20) 726 #define ISR_LAN_QUE5_FULL __BIT(19) 727 #define ISR_LAN_QUE4_FULL __BIT(18) 728 #define ISR_LAN_QUE3_FULL __BIT(17) 729 #define ISR_LAN_QUE2_FULL __BIT(16) 730 #define ISR_LAN_QUE1_FULL __BIT(15) 731 #define ISR_LAN_QUE0_FULL __BIT(14) 732 #define FTC0_REL_THR 24 733 #define FTC0_SET_THR 16 734 #define FTC0_DROP_REL_THR 8 735 #define FTC0_DROP_SET_THR 0 736 #define FTC1_PER_PORT_THR 0 737 #define PCTL0_WR_VAL(x) (((x) & 0xffff) << 16) 738 #define PCTL0_RD_CMD __BIT(14) 739 #define PCTL0_WR_CMD __BIT(13) 740 #define PCTL0_REG(x) (((x) & 0x1f) << 8) 741 #define PCTL0_ADDR(x) (((x) & 0x1f) << 0) 742 #define PCTL1_RD_VAL(x) (((x) >> 16) & 0xffff) 743 #define PCTL1_RD_DONE __BIT(1) /* read clear */ 744 #define PCTL1_WR_DONE __BIT(0) /* read clear */ 745 #define SGC2_WL_FC_EN __BIT(30) 746 #define SGC2_PORT5_IS_LAN __BIT(29) 747 #define SGC2_PORT4_IS_LAN __BIT(28) 748 #define SGC2_PORT3_IS_LAN __BIT(27) 749 #define SGC2_PORT2_IS_LAN __BIT(26) 750 #define SGC2_PORT1_IS_LAN __BIT(25) 751 #define SGC2_PORT0_IS_LAN __BIT(24) 752 #define SGC2_TX_CPU_TPID(x) ((x) << 16) 753 #define SGC2_ARBITER_LAN_EN __BIT(11) 754 #define SGC2_CPU_TPID_EN __BIT(10) 755 #define SGC2_DBL_TAG_EN5 __BIT(5) 756 #define SGC2_DBL_TAG_EN4 __BIT(4) 757 #define SGC2_DBL_TAG_EN3 __BIT(3) 758 #define SGC2_DBL_TAG_EN2 __BIT(2) 759 #define SGC2_DBL_TAG_EN1 __BIT(1) 760 #define SGC2_DBL_TAG_EN0 __BIT(0) 761 762 763 #define FTC_THR_MSK 0xff 764 765 #define PFC0_MTCC_LIMIT 24 766 #define PFC0_TURN_OFF_CF 16 767 #define PFC0_TURN_OFF_CF_MSK 0xff 768 #define PFC0_VO_NUM 12 769 #define PFC0_CL_NUM 8 770 #define PFC0_BE_NUM 4 771 #define PFC0_BK_NUM 0 772 #define PFC0_NUM_MSK 0xf 773 774 #define PFC1_P6_Q1_EN __BIT(31) 775 #define PFC1_P6_TOS_EN __BIT(30) 776 #define PFC1_P5_TOS_EN __BIT(29) 777 #define PFC1_P4_TOS_EN __BIT(28) 778 #define PFC1_P3_TOS_EN __BIT(27) 779 780 #define PFC1_P1_TOS_EN __BIT(25) 781 #define PFC1_P0_TOS_EN __BIT(24) 782 #define PFC1_PORT_PRI6 12 783 #define PFC1_PORT_PRI5 10 784 #define PFC1_PORT_PRI4 8 785 #define PFC1_PORT_PRI3 6 786 #define PFC1_PORT_PRI2 4 787 #define PFC1_PORT_PRI1 2 788 #define PFC1_PORT_PRI0 0 789 #define PFC1_PORT_MSK 0x3 790 791 #define PFC2_PRI_THR_VO 24 792 #define PFC2_PRI_THR_CL 16 793 #define PFC2_PRI_THR_BE 8 794 #define PFC2_PRI_THR_BK 0 795 #define PFC2_PRI_THR_MSK 0xff 796 797 #define GQC0_EMPTY_BLOCKS 0 798 #define GQC0_EMPTY_BLOCKS_MSK 0xff 799 800 /* 801 * USB OTG Registers 802 */ 803 #define RA_USB_OTG_OTG_CNTRL 0x000 804 #define RA_USB_OTG_OTG_INT 0x004 805 #define RA_USB_OTG_AHB_CFG 0x008 806 #define RA_USB_OTG_CFG 0x00C 807 #define RA_USB_OTG_RESET 0x010 808 #define RA_USB_OTG_INT 0x014 809 #define RA_USB_OTG_INT_MASK 0x018 810 #define RA_USB_OTG_RX_STAT 0x01C 811 #define RA_USB_OTG_RX_POP_STAT 0x020 812 #define RA_USB_OTG_RX_FIFO_SZ 0x024 813 #define RA_USB_OTG_TX_FIFO_SZ 0x028 814 #define RA_USB_OTG_TX_FIFO_STAT 0x02C 815 #define RA_USB_OTG_I2C_ACCESS 0x030 816 #define RA_USB_OTG_PHY_CTL 0x034 817 #define RA_USB_OTG_GPIO 0x038 818 #define RA_USB_OTG_GUID 0x03C 819 #define RA_USB_OTG_SNPSID 0x040 820 #define RA_USB_OTG_HWCFG1 0x044 821 #define RA_USB_OTG_HWCFG2 0x048 822 #define RA_USB_OTG_HWCFG3 0x04C 823 #define RA_USB_OTG_HWCFG4 0x050 824 #define RA_USB_OTG_HC_TX_FIFO_SZ 0x100 825 #define RA_USB_OTG_DV_TX_FIFO_SZ 0x104 826 #define RA_USB_OTG_HC_CFG 0x400 827 #define RA_USB_OTG_HC_FRM_INTRVL 0x404 828 #define RA_USB_OTG_HC_FRM_NUM 0x408 829 #define RA_USB_OTG_HC_TX_STAT 0x410 830 #define RA_USB_OTG_HC_INT 0x414 831 #define RA_USB_OTG_HC_INT_MASK 0x418 832 #define RA_USB_OTG_HC_PORT 0x440 833 #define RA_USB_OTG_HC_CH_CFG 0x500 834 #define RA_USB_OTG_HC_CH_SPLT 0x504 835 #define RA_USB_OTG_HC_CH_INT 0x508 836 #define RA_USB_OTG_HC_CH_INT_MASK 0x50C 837 #define RA_USB_OTG_HC_CH_XFER 0x510 838 #define RA_USB_OTG_HC_CH_DMA_ADDR 0x514 839 #define RA_USB_OTG_DV_CFG 0x800 840 #define RA_USB_OTG_DV_CTL 0x804 841 #define RA_USB_OTG_DV_STAT 0x808 842 #define RA_USB_OTG_DV_IN_INT_MASK 0x810 843 #define RA_USB_OTG_DV_OUT_INT_MASK 0x814 844 #define RA_USB_OTG_DV_ALL_INT 0x818 845 #define RA_USB_OTG_DV_EP_INT_MASK 0x81c 846 #define RA_USB_OTG_DV_IN_SEQ_RQ1 0x820 847 #define RA_USB_OTG_DV_IN_SEQ_RQ2 0x824 848 #define RA_USB_OTG_DV_IN_SEQ_RQ3 0x830 849 #define RA_USB_OTG_DV_IN_SEQ_RQ4 0x834 850 #define RA_USB_OTG_DV_VBUS_DISCH 0x828 851 #define RA_USB_OTG_DV_VBUS_PULSE 0x82c 852 #define RA_USB_OTG_DV_THRESH_CTL 0x830 853 #define RA_USB_OTG_DV_IN_FIFO_INT 0x834 854 #define RA_USB_OTG_DV_IN0_CTL 0x900 855 856 #define OTG_OTG_CNTRL_B_SESS_VALID __BIT(19) 857 #define OTG_OTG_CNTRL_A_SESS_VALID __BIT(18) 858 #define OTG_OTG_CNTRL_DEBOUNCE_SHORT __BIT(17) 859 #define OTG_OTG_CNTRL_CONNID_STATUS __BIT(16) 860 #define OTG_OTG_CNTRL_DV_HNP_EN __BIT(11) 861 #define OTG_OTG_CNTRL_HC_SET_HNP_EN __BIT(10) 862 #define OTG_OTG_CNTRL_HNP_REQ __BIT(9) 863 #define OTG_OTG_CNTRL_HNP_SUCCESS __BIT(8) 864 #define OTG_OTG_CNTRL_SESS_REQ __BIT(1) 865 #define OTG_OTG_CNTRL_SESS_REQ_SUCCESS __BIT(0) 866 #define OTG_OTG_INT_DEBOUNCE_DONE __BIT(19) 867 #define OTG_OTG_INT_ADEV_TIMEOUT __BIT(18) 868 #define OTG_OTG_INT_HOST_NEG_DETECT __BIT(17) 869 #define OTG_OTG_INT_HOST_NEG_STATUS __BIT(9) 870 #define OTG_OTG_INT_SESSION_REQ_STATUS __BIT(8) 871 #define OTG_OTG_INT_SESSION_END_STATUS __BIT(2) 872 #define OTG_AHB_CFG_TX_PFIFO_EMPTY_INT_EN __BIT(8) 873 #define OTG_AHB_CFG_TX_NPFIFO_EMPTY_INT_EN __BIT(7) 874 #define OTG_AHB_CFG_DMA_EN __BIT(5) 875 #define OTG_AHB_CFG_BURST(x) (((x) & 0xf) << 1) 876 #define OTG_AHB_CFG_BURST_SINGLE 0 877 #define OTG_AHB_CFG_BURST_INCR 1 878 #define OTG_AHB_CFG_BURST_INCR4 3 879 #define OTG_AHB_CFG_BURST_INCR8 5 880 #define OTG_AHB_CFG_BURST_INCR16 7 881 #define OTG_AHB_CFG_GLOBAL_INT_EN __BIT(0) 882 #define OTG_CFG_CORRUPT_TX __BIT(31) 883 #define OTG_CFG_FORCE_DEVICE __BIT(30) 884 #define OTG_CFG_FORCE_HOST __BIT(29) 885 #define OTG_CFG_ULPI_EXT_VBUS_IND_SEL __BIT(22) 886 #define OTG_CFG_ULPI_EXT_VBUS_IND __BIT(21) 887 #define OTG_CFG_ULPI_EXT_VBUS_DRV __BIT(20) 888 #define OTG_CFG_ULPI_CLOCK_SUSPEND __BIT(19) 889 #define OTG_CFG_ULPI_AUTO_RESUME __BIT(18) 890 #define OTG_CFG_ULPI_FS_LS_SEL __BIT(17) 891 #define OTG_CFG_UTMI_I2C_SEL __BIT(16) 892 #define OTG_CFG_TURNAROUND_TIME(x) (((x) & 0xf) << 10) 893 #define OTG_CFG_HNP_CAP __BIT(9) 894 #define OTG_CFG_SRP_CAP __BIT(8) 895 #define OTG_CFG_ULPI_DDR_SEL __BIT(7) 896 #define OTG_CFG_HS_PHY_SEL __BIT(6) 897 #define OTG_CFG_FS_IF_SEL __BIT(5) 898 #define OTG_CFG_ULPI_UTMI_SEL __BIT(4) 899 #define OTG_CFG_PHY_IF __BIT(3) 900 #define OTG_CFG_TIMEOUT(x) (((x) & 0x7) << 0) 901 #define OTG_RST_AHB_IDLE __BIT(31) 902 #define OTG_RST_DMA_ACTIVE __BIT(30) 903 #define OTG_RST_TXQ_TO_FLUSH(x) (((x) & 0x1f) << 6) 904 #define OTG_RST_TXQ_FLUSH_ALL 0x10 905 #define OTG_RST_TXQ_FLUSH __BIT(5) 906 #define OTG_RST_RXQ_FLUSH __BIT(4) 907 #define OTG_RST_INQ_FLUSH __BIT(3) 908 #define OTG_RST_HC_FRAME __BIT(2) 909 #define OTG_RST_AHB __BIT(1) 910 #define OTG_RST_CORE __BIT(0) 911 #define OTG_INT_RESUME __BIT(31) 912 #define OTG_INT_SESSION_REQ __BIT(30) 913 #define OTG_INT_DISCONNECT __BIT(29) 914 #define OTG_INT_CONNID_STATUS __BIT(28) 915 #define OTG_INT_PTX_EMPTY __BIT(26) 916 #define OTG_INT_HOST_CHANNEL __BIT(25) 917 #define OTG_INT_PORT_STATUS __BIT(24) 918 #define OTG_INT_DMA_FETCH_SUSPEND __BIT(22) 919 #define OTG_INT_INCOMPLETE_PERIODIC __BIT(21) 920 #define OTG_INT_INCOMPLETE_ISOC __BIT(20) 921 #define OTG_INT_DV_OUT_EP __BIT(19) 922 #define OTG_INT_DV_IN_EP __BIT(18) 923 #define OTG_INT_DV_EP_MISMATCH __BIT(17) 924 #define OTG_INT_DV_PERIODIC_END __BIT(15) 925 #define OTG_INT_DV_ISOC_OUT_DROP __BIT(14) 926 #define OTG_INT_DV_ENUM_COMPLETE __BIT(13) 927 #define OTG_INT_DV_USB_RESET __BIT(12) 928 #define OTG_INT_DV_USB_SUSPEND __BIT(11) 929 #define OTG_INT_DV_USB_EARLY_SUSPEND __BIT(10) 930 #define OTG_INT_I2C __BIT(9) 931 #define OTG_INT_ULPI_CARKIT __BIT(8) 932 #define OTG_INT_DV_OUT_NAK_EFFECTIVE __BIT(7) 933 #define OTG_INT_DV_IN_NAK_EFFECTIVE __BIT(6) 934 #define OTG_INT_NPTX_EMPTY __BIT(5) 935 #define OTG_INT_RX_FIFO __BIT(4) 936 #define OTG_INT_SOF __BIT(3) 937 #define OTG_INT_OTG __BIT(2) 938 #define OTG_INT_MODE_MISMATCH __BIT(1) 939 #define OTG_INT_MODE __BIT(0) 940 #define USB_OTG_SNPSID_CORE_REV_2_00 0x4F542000 941 #define OTG_HC_CFG_FORCE_NO_HS __BIT(2) 942 #define OTG_HC_CFG_FSLS_CLK_SEL(x) (((x) & 0x3) << 0) 943 #define OTG_HC_CFG_FS_CLK_3060 0 944 #define OTG_HC_CFG_FS_CLK_48 1 945 #define OTG_HC_CFG_LS_CLK_3060 0 946 #define OTG_HC_CFG_LS_CLK_48 1 947 #define OTG_HC_CFG_LS_CLK_6 2 948 #define USB_OTG_HC_FRM_NUM(x) (x & 0x3fff) 949 #define USB_OTG_HC_FRM_REM(x) (x >> 16) 950 #define USB_OTG_HC_PORT_SPEED(x) (((x) >> 17) & 0x3) 951 #define USB_OTG_HC_PORT_SPEED_HS 0 952 #define USB_OTG_HC_PORT_SPEED_FS 1 953 #define USB_OTG_HC_PORT_SPEED_LS 2 954 #define USB_OTG_HC_PORT_TEST(x) (((x) & 0xf) << 13) 955 #define USB_OTG_HC_PORT_TEST_DISABLED 0 956 #define USB_OTG_HC_PORT_TEST_J_MODE 1 957 #define USB_OTG_HC_PORT_TEST_K_MODE 2 958 #define USB_OTG_HC_PORT_TEST_NAK_MODE 3 959 #define USB_OTG_HC_PORT_TEST_PKT_MODE 4 960 #define USB_OTG_HC_PORT_TEST_FORCE_MODE 5 961 #define USB_OTG_HC_PORT_POWER __BIT(12) 962 #define USB_OTG_HC_PORT_LINE_STAT (((x) >> 10) & 0x3) 963 #define USB_OTG_HC_PORT_LINE_STAT_DP 1 964 #define USB_OTG_HC_PORT_LINE_STAT_DM 3 965 #define USB_OTG_HC_PORT_RESET __BIT(8) 966 #define USB_OTG_HC_PORT_SUSPEND __BIT(7) 967 #define USB_OTG_HC_PORT_RESUME __BIT(6) 968 #define USB_OTG_HC_PORT_OVCURR_CHANGE __BIT(5) 969 #define USB_OTG_HC_PORT_OVCURR __BIT(4) 970 #define USB_OTG_HC_PORT_ENABLE_CHANGE __BIT(3) 971 #define USB_OTG_HC_PORT_ENABLE __BIT(2) 972 #define USB_OTG_HC_PORT_CONNECT_CHANGE __BIT(1) 973 #define USB_OTG_HC_PORT_STATUS __BIT(0) 974 #define USB_OTG_HC_CH_CFG_ENABLE __BIT(31) 975 #define USB_OTG_HC_CH_CFG_DISABLE __BIT(30) 976 #define USB_OTG_HC_CH_CFG_ODD_FRAME __BIT(29) 977 #define USB_OTG_HC_CH_CFG_DEV_ADDR(x) (((x) & 0x7f) << 22) 978 #define USB_OTG_HC_CH_CFG_MULTI_CNT(x) (((x) & 0x3) << 20) 979 #define USB_OTG_HC_CH_CFG_EP_TYPE(x) (((x) & 0x3) << 18) 980 #define USB_OTG_HC_CH_CFG_EP_TYPE_CTRL 0 981 #define USB_OTG_HC_CH_CFG_EP_TYPE_ISOC 1 982 #define USB_OTG_HC_CH_CFG_EP_TYPE_BULK 2 983 #define USB_OTG_HC_CH_CFG_EP_TYPE_INTR 3 984 #define USB_OTG_HC_CH_CFG_LS __BIT(17) 985 #define USB_OTG_HC_CH_CFG_EP_DIR(x) (((x) & 0x1) << 15) 986 #define USB_OTG_HC_CH_CFG_EP_DIR_OUT 0 987 #define USB_OTG_HC_CH_CFG_EP_DIR_IN 1 988 #define USB_OTG_HC_CH_CFG_EP_NUM(x) (((x) & 0xf) << 11) 989 #define USB_OTG_HC_CH_CFG_MAX_PKT_SZ(x) (((x) & 0x7ff) << 0) 990 #define USB_OTG_HC_CH_SPLT_EN __BIT(31) 991 #define USB_OTG_HC_CH_SPLT_COMPLETE __BIT(16) 992 #define USB_OTG_HC_CH_SPLT_POS(x) (((x) & 0x3) << 14) 993 #define USB_OTG_HC_CH_SPLT_POS_MID 0 994 #define USB_OTG_HC_CH_SPLT_POS_END 1 995 #define USB_OTG_HC_CH_SPLT_POS_BEGIN 2 996 #define USB_OTG_HC_CH_SPLT_POS_ALL 3 997 #define USB_OTG_HC_CH_SPLT_HUB_ADDR(x) (((x) & 0x7f) << 7) 998 #define USB_OTG_HC_CH_SPLT_PORT_ADDR(x) (((x) & 0x7f) << 0) 999 #define USB_OTG_HC_CH_INT_ALL 0x7ff 1000 #define USB_OTG_HC_CH_INT_TOGGLE_ERROR __BIT(10) 1001 #define USB_OTG_HC_CH_INT_FRAME_OVERRUN __BIT(9) 1002 #define USB_OTG_HC_CH_INT_BABBLE_ERROR __BIT(8) 1003 #define USB_OTG_HC_CH_INT_XACT_ERROR __BIT(7) 1004 #define USB_OTG_HC_CH_INT_NYET __BIT(6) 1005 #define USB_OTG_HC_CH_INT_ACK __BIT(5) 1006 #define USB_OTG_HC_CH_INT_NAK __BIT(4) 1007 #define USB_OTG_HC_CH_INT_STALL __BIT(3) 1008 #define USB_OTG_HC_CH_INT_DMA_ERROR __BIT(2) 1009 #define USB_OTG_HC_CH_INT_HALTED __BIT(1) 1010 #define USB_OTG_HC_CH_INT_XFER_COMPLETE __BIT(0) 1011 #define USB_OTG_HC_CH_XFER_DO_PING __BIT(31) 1012 #define USB_OTG_HC_CH_WR_XFER_PID(x) (((x) & 0x3) << 29) 1013 #define USB_OTG_HC_CH_RD_XFER_PID(x) (((x) >> 29) & 0x3) 1014 #define USB_OTG_HC_CH_XFER_PID_DATA0 0 1015 #define USB_OTG_HC_CH_XFER_PID_DATA2 1 1016 #define USB_OTG_HC_CH_XFER_PID_DATA1 2 1017 #define USB_OTG_HC_CH_XFER_PID_SETUP 3 1018 #define USB_OTG_HC_CH_XFER_PID_MDATA 3 1019 #define USB_OTG_HC_CH_XFER_SET_PKT_CNT(x) (((x) & 0x3ff) << 19) 1020 #define USB_OTG_HC_CH_XFER_SET_BYTES(x) ((x) & 0x7ffff) 1021 #define USB_OTG_HC_CH_XFER_GET_PKT_CNT(x) (((x) >> 19) & 0x3ff) 1022 #define USB_OTG_HC_CH_XFER_GET_BYTES(x) ((x) & 0x7ffff) 1023 1024 /* PCIe Registers - 0x10140000 */ 1025 #define RA_PCI_PCICFG 0x0000 1026 #define PCICFG_P2P_BR_DEVNUM1 __BITS(23,20) 1027 #define PCICFG_P2P_BR_DEVNUM0 __BITS(19,16) 1028 #define PCICFG_PSIRST __BIT(1) 1029 #define RA_PCI_PCIINT 0x0008 1030 #define PCIINT_INT3 __BIT(21) // PCIe1 interrupt 1031 #define PCIINT_INT2 __BIT(20) // PCIe0 interrupt 1032 #define PCIINT_INT1 __BIT(19) 1033 #define PCIINT_INT0 __BIT(18) 1034 #define RA_PCI_PCIENA 0x000c 1035 #define RA_PCI_CFGADDR 0x0020 1036 #define CFGADDR_EXTREG __BITS(27,24) 1037 #define CFGADDR_BUS __BITS(23,16) 1038 #define CFGADDR_DEV __BITS(15,11) 1039 #define CFGADDR_FUN __BITS(10,8) 1040 #define CFGADDR_REG __BITS(7,0) 1041 #define RA_PCI_CFGDATA 0x0024 1042 #define RA_PCI_MEMBASE 0x0028 1043 #define MEMBASE_ADDR __BITS(31,16) 1044 #define RA_PCI_IOBASE 0x002c 1045 #define IOBASE_ADDR __BITS(31,16) 1046 #define RA_PCI_PHY0CFG 0x0090 1047 #define PHY0CFG_SPI_BUSY __BIT(31) 1048 #define PHY0CFG_SPI_WR __BIT(23) 1049 #define PHY0CFG_SPI_ADDR __BITS(15,8) 1050 #define PHY0CFG_SPI_DATA __BITS(7,0) 1051 1052 /* PCIe0 RC Control Registers - 0x10142000 */ 1053 #define RA_PCIE0_BAR0SETUP 0x0010 1054 #define BARSETUP_BARMSK __BITS(31,16) 1055 #define BARSETUP_BARENB __BIT(0) 1056 #define RA_PCIE0_BAR1SETUP 0x0014 1057 #define RA_PCIE0_IMBASEBAR0 0x0018 1058 #define IMBASEBAR0 __BITS(31,16) 1059 #define RA_PCIE0_ID 0x0010 1060 #define RA_PCIE0_CLASS 0x0014 1061 #define RA_PCIE0_SUBID 0x0018 1062 #define RA_PCIE0_STATUS 0x0018 1063 #define PCIE_STATUS_LINK_UP __BIT(0) 1064 1065 #endif /* _RALINK_REG_H_ */ 1066
Indexes created Wed Oct 01 12:09:54 GMT 2025