ralink_reg.h revision 1.7
1 /* $NetBSD: ralink_reg.h,v 1.7 2014/04/30 00:53:31 matt Exp $ */ 2 /*- 3 * Copyright (c) 2011 CradlePoint Technology, Inc. 4 * All rights reserved. 5 * 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY CRADLEPOINT TECHNOLOGY, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains the configuration parameters for the RT3052 board. 31 */ 32 33 #ifndef _RALINK_REG_H_ 34 #define _RALINK_REG_H_ 35 36 #ifdef _KERNEL_OPT 37 #include "opt_rasoc.h" 38 #endif 39 40 #include <mips/cpuregs.h> 41 42 #if defined(RT3050) 43 #define RA_CLOCK_RATE 320000000 44 #define RA_BUS_FREQ (RA_CLOCK_RATE / 3) 45 #define RA_UART_FREQ RA_BUS_FREQ 46 #elif defined(RT3052) 47 #define RA_CLOCK_RATE 384000000 48 #define RA_BUS_FREQ (RA_CLOCK_RATE / 3) 49 #define RA_UART_FREQ RA_BUS_FREQ 50 #elif defined(RT3883) 51 #if 0 52 #define RA_CLOCK_RATE 480000000 53 #else 54 #define RA_CLOCK_RATE 500000000 55 #endif 56 #define RA_BUS_FREQ 166000000 /* DDR speed */ 57 #define RA_UART_FREQ 40000000 58 #elif defined(MT7620) 59 #define RA_CLOCK_RATE 580000000 60 #define RA_BUS_FREQ (RA_CLOCK_RATE / 3) 61 #define RA_UART_FREQ 40000000 62 #else 63 /* Ralink dev board */ 64 #define RA_CLOCK_RATE 384000000 65 #define RA_BUS_FREQ (RA_CLOCK_RATE / 3) 66 #define RA_UART_FREQ RA_BUS_FREQ 67 #endif 68 69 #define RA_BAUDRATE CONSPEED 70 #define RA_SERIAL_CLKDIV 16 71 72 #define RA_SRAM_BASE 0x00000000 73 #define RA_SRAM_END 0x0FFFFFFF 74 #define RA_SYSCTL_BASE 0x10000000 75 #define RA_TIMER_BASE 0x10000100 76 #define RA_INTCTL_BASE 0x10000200 77 #define RA_MEMCTL_BASE 0x10000300 78 #if defined(RT3052) || defined(RT3050) 79 #define RA_PCM_BASE 0x10000400 80 #endif 81 #define RA_UART_BASE 0x10000500 82 #define RA_PIO_BASE 0x10000600 83 #if defined(RT3052) || defined(RT3050) 84 #define RA_GDMA_BASE 0x10000700 85 #elif defined(RT3883) 86 #define RA_FLASHCTL_BASE 0x10000700 87 #endif 88 #define RA_NANDCTL_BASE 0x10000800 89 #define RA_I2C_BASE 0x10000900 90 #define RA_I2S_BASE 0x10000A00 91 #define RA_SPI_BASE 0x10000B00 92 #define RA_UART_LITE_BASE 0x10000C00 93 #if defined(RT3883) 94 #define RA_PCM_BASE 0x10002000 95 #define RA_GDMA_BASE 0x10002800 96 #define RA_CODEC1_BASE 0x10003000 97 #define RA_CODEC2_BASE 0x10003800 98 #endif 99 #define RA_FRAME_ENGINE_BASE 0x10100000 100 #define RA_ETH_SW_BASE 0x10110000 101 #define RA_ROM_BASE 0x10118000 102 #if defined(RT3883) || defined(MT7620) 103 #define RA_USB_DEVICE_BASE 0x10120000 104 #if defined(MT7620) 105 #define RA_SDHC_BASE 0x10130000 106 #endif 107 #define RA_PCI_BASE 0x10140000 108 #define RA_PCIWIN_BASE 0x10150000 109 #endif 110 #define RA_11N_MAC_BASE 0x10180000 111 #define RA_USB_OTG_BASE 0x101C0000 112 #if defined(RT3883) || defined(MT7620) 113 #define RA_USB_HOST_BASE 0x101C0000 114 #define RA_USB_BLOCK_SIZE 0x1000 115 #define RA_USB_EHCI_BASE (RA_USB_HOST_BASE + 0x0000) 116 #define RA_USB_OHCI_BASE (RA_USB_EHCI_BASE + RA_USB_BLOCK_SIZE) 117 #endif 118 #if defined(RT3052) || defined(RT3050) 119 #define RA_FLASH_BASE 0x1F000000 120 #define RA_FLASH_END 0x1F7FFFFF 121 #elif defined(RT3883) || defined(MT7620) 122 #define RA_FLASH_BASE 0x1C000000 123 #define RA_FLASH_END 0x1DFFFFFF 124 #endif 125 126 #define RA_IOREG_VADDR(base, offset) \ 127 (volatile uint32_t *)MIPS_PHYS_TO_KSEG1((base) + (offset)) 128 129 #define FLD_GET(val,pos,mask) (((val) >> (pos)) & (mask)) 130 #define FLD_SET(val,pos,mask) (((val) & (mask)) << (pos)) 131 132 /* 133 * System Control Registers 134 */ 135 #define RA_SYSCTL_ID0 0x00 136 #define RA_SYSCTL_ID1 0x04 137 #define RA_SYSCTL_REVID 0x0c 138 #define RA_SYSCTL_CFG0 0x10 139 #define RA_SYSCTL_CFG1 0x14 140 #define RA_SYSCTL_CLKCFG0 0x2C 141 #define RA_SYSCTL_CLKCFG1 0x30 142 #define RA_SYSCTL_RST 0x34 143 #define RA_SYSCTL_RSTSTAT 0x38 144 #define RA_SYSCTL_GPIOMODE 0x60 145 146 #if defined(RT3050) || defined(RT3052) 147 #define SYSCTL_CFG0_INIC_EE_SDRAM __BIT(29) 148 #define SYSCTL_CFG0_INIC_8MB_SDRAM __BIT(28) 149 #define SYSCTL_CFG0_GE0_MODE __BITS(24,25) 150 #define SYSCTL_CFG0_BYPASS_PLL __BIT(21) 151 #define SYSCTL_CFG0_BE __BIT(20) 152 #define SYSCTL_CFG0_CPU_CLK_SEL __BIT(18) 153 #define SYSCTL_CFG0_BOOT_FROM __BITS(16,17) 154 #define SYSCTL_CFG0_TEST_CODE __BITS(8,15) 155 #define SYSCTL_CFG0_SRAM_CS_MODE __BITS(2,3) 156 #define SYSCTL_CFG0_SDRAM_CLK_DRV __BIT(0) 157 #elif defined(RT3883) 158 #define SYSCTL_CFG0_BE __BIT(19) 159 #define SYSCTL_CFG0_DRAM_SIZE __BITS(12,14) 160 #define SYSCTL_CFG0_DRAM_2MB 0 161 #define SYSCTL_CFG0_DRAM_8MB 1 162 #define SYSCTL_CFG0_DRAM_16MB 2 163 #define SYSCTL_CFG0_DRAM_32MB 3 164 #define SYSCTL_CFG0_DRAM_64MB 4 165 #define SYSCTL_CFG0_DRAM_128MB 5 166 #define SYSCTL_CFG0_DRAM_256MB 6 167 #elif defined(MT7620) 168 #define SYSCTL_CFG0_TEST_CODE __BITS(31,24) 169 #define SYSCTL_CFG0_BS_SHADOW __BITS(22,12) 170 #define SYSCTL_CFG0_DRAM_FROM_EE __BIT(8) 171 #define SYSCTL_CFG0_DBG_JTAG_MODE __BIT(7) 172 #define SYSCTL_CFG0_XTAL_FREQ_SEL __BIT(6) 173 #define SYSCTL_CFG0_DRAM_TYPE __BITS(5,4) 174 #define SYSCTL_CFG0_CHIP_MODE __BITS(3,0) 175 #endif 176 177 #if defined(RT3883) || defined(MT7620) 178 #define SYSCTL_CFG1_GE2_MODE __BITS(15,14) 179 #define SYSCTL_CFG1_GE1_MODE __BITS(13,12) 180 #define GE_MODE_RGMII 0 // RGMII mode (10/100/1000) 181 #define GE_MODE_MII 1 // MII mode (10/100) 182 #define GE_MODE_RMII 2 // Reverse MMI (10/100) 183 #define SYSCTL_CFG1_USB0_HOST_MODE __BIT(10) 184 #define SYSCTL_CFG1_PCIE_RC_MODE __BIT(8) 185 #endif 186 #if defined(RT3883) 187 #define SYSCTL_CFG1_PCI_HOST_MODE __BIT(7) 188 #define SYSCTL_CFG1_PCI_66M_MODE __BIT(6) 189 #endif 190 191 #if defined(RT3883) || defined(MT7620) 192 #define SYSCTL_CLKCFG0_REFCLK0_RATE __BITS(11,9) 193 #endif 194 #if defined(RT3883) 195 #define SYSCTL_CLKCFG0_OSC_1US_DIV_3883 __BITS(21,16) 196 #define SYSCTL_CLKCFG0_REFCLK1_RATE __BITS(15,13) 197 #define SYSCTL_CLKCFG0_REFCLK0_IS_OUT __BIT(8) 198 #define SYSCTL_CLKCFG0_CPU_FREQ_ADJ __BITS(3,0) 199 #endif 200 #if defined(MT7620) 201 #define SYSCTL_CLKCFG0_OSC_1US_DIV_7620 __BITS(29,24) 202 #define SYSCTL_CLKCFG0_INT_CLK_FDIV __BITS(22,18) 203 #define SYSCTL_CLKCFG0_INT_CLK_FFRAC __BITS(16,12) 204 #define SYSCTL_CLKCFG0_PERI_CLK_SEL __BIT(4) 205 #define SYSCTL_CLKCFG0_EPHY_USE_25M __BIT(3) 206 #endif 207 208 #if defined(RT3883) 209 #define SYSCTL_CLKCFG1_PBUS_DIV2 __BIT(30) 210 #define SYSCTL_CLKCFG1_SYS_TCK_EN __BIT(29) 211 #define SYSCTL_CLKCFG1_FE_GDMA_PCLK_EN __BIT(22) 212 #define SYSCTL_CLKCFG1_PCIE_CLK_EN_3883 __BIT(21) 213 #define SYSCTL_CLKCFG1_UPHY1_CLK_EN __BIT(20) 214 #define SYSCTL_CLKCFG1_PCI_CLK_EN __BIT(19) 215 #define SYSCTL_CLKCFG1_UPHY0_CLK_EN_3883 __BIT(18) 216 #define SYSCTL_CLKCFG1_GE2_CLK_EN_3883 __BIT(17) 217 #define SYSCTL_CLKCFG1_GE1_CLK_EN_3883 __BIT(16) 218 #endif 219 #if defined(MT7620) 220 #define SYSCTL_CLKCFG1_SDHC_CLK_EN __BIT(30) 221 #define SYSCTL_CLKCFG1_AUX_SYS_TCK_EN __BIT(28) 222 #define SYSCTL_CLKCFG1_PCIE_CLK_EN_7620 __BIT(26) 223 #define SYSCTL_CLKCFG1_UPHY0_CLK_EN_7620 __BIT(25) 224 #define SYSCTL_CLKCFG1_ESW_CLK_EN __BIT(23) 225 #define SYSCTL_CLKCFG1_FE_CLK_EN __BIT(21) 226 #define SYSCTL_CLKCFG1_UARTL_CLK_EN __BIT(19) 227 #define SYSCTL_CLKCFG1_SPI_CLK_EN __BIT(18) 228 #define SYSCTL_CLKCFG1_I2S_CLK_EN __BIT(17) 229 #define SYSCTL_CLKCFG1_I2C_CLK_EN __BIT(16) 230 #define SYSCTL_CLKCFG1_NAND_CLK_EN __BIT(15) 231 #define SYSCTL_CLKCFG1_GDMA_CLK_EN __BIT(14) 232 #define SYSCTL_CLKCFG1_GPIO_CLK_EN __BIT(13) 233 #define SYSCTL_CLKCFG1_UART_CLK_EN __BIT(12) 234 #define SYSCTL_CLKCFG1_PCM_CLK_EN __BIT(11) 235 #define SYSCTL_CLKCFG1_MC_CLK_EN __BIT(10) 236 #define SYSCTL_CLKCFG1_INTC_CLK_EN __BIT(9) 237 #define SYSCTL_CLKCFG1_TIMER_CLK_EN __BIT(8) 238 #define SYSCTL_CLKCFG1_GE2_CLK_EN_7620 __BIT(7) 239 #define SYSCTL_CLKCFG1_GE1_CLK_EN_7620 __BIT(6) 240 #endif 241 242 #if defined(RT3883) || defined(MT7620) 243 /* 3883 doesn't have memo regs, use teststat instead */ 244 #define RA_SYSCTL_MEMO0 0x18 245 #define RA_SYSCTL_MEMO1 0x1C 246 #else 247 #define RA_SYSCTL_MEMO0 0x68 248 #define RA_SYSCTL_MEMO1 0x6C 249 #endif 250 251 #define RST_PPE_7620 __BIT(31) 252 #define RST_SDHC_7620 __BIT(30) 253 #define RST_MIPS_CNT_7620 __BIT(28) 254 #define RST_PCIPCIE_3883 __BIT(27) 255 #define RST_FLASH_3883 __BIT(26) 256 #define RST_PCIE0_7620 __BIT(26) 257 #define RST_UDEV_3883 __BIT(25) 258 #define RST_UHST0_7620 __BIT(25) 259 #define RST_PCI_3883 __BIT(24) 260 #define RST_EPHY_7620 __BIT(24) 261 #define RST_PCIE_3883 __BIT(23) 262 #define RST_ESW_7620 __BIT(23) 263 #define RST_UHST __BIT(22) 264 #define RST_FE __BIT(21) 265 #define RST_WLAN __BIT(20) 266 #define RST_UARTL __BIT(19) 267 #define RST_SPI __BIT(18) 268 #define RST_I2S __BIT(17) 269 #define RST_I2C __BIT(16) 270 #define RST_NAND __BIT(15) 271 #define RST_DMA __BIT(14) 272 #define RST_PIO __BIT(13) 273 #define RST_UART __BIT(12) 274 #define RST_PCM __BIT(11) 275 #define RST_MC __BIT(10) 276 #define RST_INTC __BIT(9) 277 #define RST_TIMER __BIT(8) 278 #define RST_GE2 __BIT(7) 279 #define RST_GE1 __BIT(6) 280 #define RST_SYS __BIT(0) 281 282 #define GPIOMODE_RGMII __BIT(9) 283 #define GPIOMODE_SDRAM __BIT(8) 284 #define GPIOMODE_MDIO __BIT(7) 285 #define GPIOMODE_JTAG __BIT(6) 286 #define GPIOMODE_UARTL __BIT(5) 287 #define GPIOMODE_UARTF2 __BIT(4) 288 #define GPIOMODE_UARTF1 __BIT(3) 289 #define GPIOMODE_UARTF0 __BIT(2) 290 #define GPIOMODE_UARTF_0_2 \ 291 (GPIOMODE_UARTF0|GPIOMODE_UARTF1|GPIOMODE_UARTF2) 292 #define GPIOMODE_SPI __BIT(1) 293 #define GPIOMODE_I2C __BIT(0) 294 295 /* 296 * Timer Registers 297 */ 298 #define RA_TIMER_STAT 0x00 299 #define RA_TIMER_0_LOAD 0x10 300 #define RA_TIMER_0_VALUE 0x14 301 #define RA_TIMER_0_CNTRL 0x18 302 #define RA_TIMER_1_LOAD 0x20 303 #define RA_TIMER_1_VALUE 0x24 304 #define RA_TIMER_1_CNTRL 0x28 305 306 #define TIMER_1_RESET __BIT(5) 307 #define TIMER_0_RESET __BIT(4) 308 #define TIMER_1_INT_STATUS __BIT(1) 309 #define TIMER_0_INT_STATUS __BIT(0) 310 #define TIMER_TEST_EN __BIT(15) 311 #define TIMER_EN __BIT(7) 312 #define TIMER_MODE(x) (((x) & 0x3) << 4) 313 #define TIMER_MODE_FREE 0 314 #define TIMER_MODE_PERIODIC 1 315 #define TIMER_MODE_TIMEOUT 2 316 #define TIMER_MODE_WDOG 3 /* only valid for TIMER_1 */ 317 #define TIMER_PRESCALE(x) (((x) & 0xf) << 0) 318 #define TIMER_PRESCALE_DIV_1 0 319 #define TIMER_PRESCALE_DIV_4 1 320 #define TIMER_PRESCALE_DIV_8 2 321 #define TIMER_PRESCALE_DIV_16 3 322 #define TIMER_PRESCALE_DIV_32 4 323 #define TIMER_PRESCALE_DIV_64 5 324 #define TIMER_PRESCALE_DIV_128 6 325 #define TIMER_PRESCALE_DIV_256 7 326 #define TIMER_PRESCALE_DIV_512 8 327 #define TIMER_PRESCALE_DIV_1024 9 328 #define TIMER_PRESCALE_DIV_2048 10 329 #define TIMER_PRESCALE_DIV_4096 11 330 #define TIMER_PRESCALE_DIV_8192 12 331 #define TIMER_PRESCALE_DIV_16384 13 332 #define TIMER_PRESCALE_DIV_32768 14 333 #define TIMER_PRESCALE_DIV_65536 15 334 335 /* 336 * Interrupt Controller Registers 337 */ 338 #define RA_INTCTL_IRQ0STAT 0x00 339 #define RA_INTCTL_IRQ1STAT 0x04 340 #define RA_INTCTL_TYPE 0x20 341 #define RA_INTCTL_RAW 0x30 342 #define RA_INTCTL_ENABLE 0x34 343 #define RA_INTCTL_DISABLE 0x38 344 345 346 #define INT_GLOBAL __BIT(31) 347 #define INT_UDEV __BIT(19) 348 #define INT_USB __BIT(18) 349 #define INT_ETHSW __BIT(17) 350 #define INT_R2P __BIT(15) 351 #define INT_SDHC __BIT(14) 352 #define INT_UARTL __BIT(12) 353 #define INT_SPI __BIT(11) 354 #define INT_I2S __BIT(10) 355 #define INT_PERF __BIT(9) 356 #define INT_NAND __BIT(8) 357 #define INT_DMA __BIT(7) 358 #define INT_PIO __BIT(6) 359 #define INT_UARTF __BIT(5) 360 #define INT_PCM __BIT(4) 361 #define INT_ILLACC __BIT(3) 362 #define INT_WDOG __BIT(2) 363 #define INT_TIMER0 __BIT(1) 364 #define INT_SYSCTL __BIT(0) 365 366 /* 367 * Ralink Linear CPU Interrupt Mapping For Lists 368 */ 369 #define RA_IRQ_LOW 0 370 #define RA_IRQ_HIGH 1 371 #define RA_IRQ_PCI 2 372 #define RA_IRQ_FENGINE 3 373 #define RA_IRQ_WLAN 4 374 #define RA_IRQ_TIMER 5 375 #define RA_IRQ_SYSCTL 6 376 #define RA_IRQ_TIMER0 7 377 #define RA_IRQ_WDOG 8 378 #define RA_IRQ_ILLACC 9 379 #define RA_IRQ_PCM 10 380 #define RA_IRQ_UARTF 11 381 #define RA_IRQ_PIO 12 382 #define RA_IRQ_DMA 13 383 #define RA_IRQ_NAND 14 384 #define RA_IRQ_PERF 15 385 #define RA_IRQ_I2S 16 386 #define RA_IRQ_UARTL 17 387 #define RA_IRQ_ETHSW 18 388 #define RA_IRQ_USB 19 389 #define RA_IRQ_MAX 20 390 391 /* 392 * General Purpose I/O 393 */ 394 #define RA_PIO_00_23_INT 0x00 395 #define RA_PIO_00_23_EDGE_INT 0x04 396 #define RA_PIO_00_23_INT_RISE_EN 0x08 397 #define RA_PIO_00_23_INT_FALL_EN 0x0C 398 #define RA_PIO_00_23_DATA 0x20 399 #define RA_PIO_00_23_DIR 0x24 400 #define RA_PIO_00_23_POLARITY 0x28 401 #define RA_PIO_00_23_SET_BIT 0x2C 402 #define RA_PIO_00_23_CLR_BIT 0x30 403 #define RA_PIO_00_23_TGL_BIT 0x34 404 #define RA_PIO_24_39_INT 0x38 405 #define RA_PIO_24_39_EDGE_INT 0x3C 406 #define RA_PIO_24_39_INT_RISE_EN 0x40 407 #define RA_PIO_24_39_INT_FALL_EN 0x44 408 #define RA_PIO_24_39_DATA 0x48 409 #define RA_PIO_24_39_DIR 0x4C 410 #define RA_PIO_24_39_POLARITY 0x50 411 #define RA_PIO_24_39_SET_BIT 0x54 412 #define RA_PIO_24_39_CLR_BIT 0x58 413 #define RA_PIO_24_39_TGL_BIT 0x5C 414 #define RA_PIO_40_51_INT 0x60 415 #define RA_PIO_40_51_EDGE_INT 0x64 416 #define RA_PIO_40_51_INT_RISE_EN 0x68 417 #define RA_PIO_40_51_INT_FALL_EN 0x6C 418 #define RA_PIO_40_51_DATA 0x70 419 #define RA_PIO_40_51_DIR 0x74 420 #define RA_PIO_40_51_POLARITY 0x78 421 #define RA_PIO_40_51_SET_BIT 0x7C 422 #define RA_PIO_40_51_CLR_BIT 0x80 423 #define RA_PIO_40_51_TGL_BIT 0x84 424 #define RA_PIO_72_95_INT 0x88 425 #define RA_PIO_72_95_EDGE_INT 0x8c 426 #define RA_PIO_72_95_INT_RISE_EN 0x90 427 #define RA_PIO_72_95_INT_FALL_EN 0x94 428 #define RA_PIO_72_95_DATA 0x98 429 #define RA_PIO_72_95_DIR 0x9c 430 #define RA_PIO_72_95_POLARITY 0xa0 431 #define RA_PIO_72_95_SET_BIT 0xa4 432 #define RA_PIO_72_95_CLR_BIT 0xa8 433 #define RA_PIO_72_95_TGL_BIT 0xac 434 435 436 /* 437 * UART registers 438 */ 439 440 #define RA_UART_RBR 0x00 441 #define RA_UART_TBR 0x04 442 #define RA_UART_IER 0x08 443 #define RA_UART_IIR 0x0C 444 #define RA_UART_FCR 0x10 445 #define RA_UART_LCR 0x14 446 #define RA_UART_MCR 0x18 447 #define RA_UART_LSR 0x1C 448 #define RA_UART_MSR 0x20 449 #define RA_UART_DLL 0x28 450 451 452 #define UART_IER_ELSI __BIT(2) 453 /* Receiver Line Status Interrupt Enable */ 454 #define UART_IER_ETBEI __BIT(1) 455 /* Transmit Buffer Empty Interrupt Enable */ 456 #define UART_IER_ERBFI __BIT(0) 457 /* Data Ready or Character Time-Out Interrupt Enable */ 458 459 #define UART_IIR_FIFOES1 __BIT(7) /* FIFO Mode Enable Status */ 460 #define UART_IIR_FIFOES0 __BIT(6) /* FIFO Mode Enable Status */ 461 #define UART_IIR_IID3 __BIT(3) /* Interrupt Source Encoded */ 462 #define UART_IIR_IID2 __BIT(2) /* Interrupt Source Encoded */ 463 #define UART_IIR_IID1 __BIT(1) /* Interrupt Source Encoded */ 464 #define UART_IIR_IP __BIT(0) /* Interrupt Pending (active low) */ 465 466 #define UART_FCR_RXTRIG1 __BIT(7) /* Receiver Interrupt Trigger Level */ 467 #define UART_FCR_RXTRIG0 __BIT(6) /* Receiver Interrupt Trigger Level */ 468 #define UART_FCR_TXTRIG1 __BIT(5) /* Transmitter Interrupt Trigger Level */ 469 #define UART_FCR_TXTRIG0 __BIT(4) /* Transmitter Interrupt Trigger Level */ 470 #define UART_FCR_DMAMODE __BIT(3) /* Enable DMA transfers */ 471 #define UART_FCR_TXRST __BIT(2) /* Reset Transmitter FIFO */ 472 #define UART_FCR_RXRST __BIT(1) /* Reset Receiver FIFO */ 473 #define UART_FCR_FIFOE __BIT(0) /* Transmit and Receive FIFO Enable */ 474 475 #define UART_LCR_DLAB __BIT(7) /* Divisor Latch Access Bit */ 476 #define UART_LCR_SB __BIT(6) /* Set Break */ 477 #define UART_LCR_STKYP __BIT(5) /* Sticky Parity */ 478 #define UART_LCR_EPS __BIT(4) /* Even Parity Select */ 479 #define UART_LCR_PEN __BIT(3) /* Parity Enable */ 480 #define UART_LCR_STB __BIT(2) /* Stop Bit */ 481 #define UART_LCR_WLS1 __BIT(1) /* Word Length Select */ 482 #define UART_LCR_WLS0 __BIT(0) /* Word Length Select */ 483 484 #define UART_MCR_LOOP __BIT(4) /* Loop-back Mode Enable */ 485 486 #define UART_MSR_DCD __BIT(7) /* Data Carrier Detect */ 487 #define UART_MSR_RI __BIT(6) /* Ring Indicator */ 488 #define UART_MSR_DSR __BIT(5) /* Data Set Ready */ 489 #define UART_MSR_CTS __BIT(4) /* Clear To Send */ 490 #define UART_MSR_DDCD __BIT(3) /* Delta Data Carrier Detect */ 491 #define UART_MSR_TERI __BIT(2) /* Trailing Edge Ring Indicator */ 492 #define UART_MSR_DDSR __BIT(1) /* Delta Data Set Ready */ 493 #define UART_MSR_DCTS __BIT(0) /* Delta Clear To Send */ 494 495 #define UART_LSR_FIFOE __BIT(7) /* FIFO Error Status */ 496 #define UART_LSR_TEMT __BIT(6) /* Transmitter Empty */ 497 #define UART_LSR_TDRQ __BIT(5) /* Transmit Data Request */ 498 #define UART_LSR_BI __BIT(4) /* Break Interrupt */ 499 #define UART_LSR_FE __BIT(3) /* Framing Error */ 500 #define UART_LSR_PE __BIT(2) /* Parity Error */ 501 #define UART_LSR_OE __BIT(1) /* Overrun Error */ 502 #define UART_LSR_DR __BIT(0) /* Data Ready */ 503 504 /* 505 * I2C registers 506 */ 507 #define RA_I2C_CONFIG 0x00 508 #define RA_I2C_CLKDIV 0x04 509 #define RA_I2C_DEVADDR 0x08 510 #define RA_I2C_ADDR 0x0C 511 #define RA_I2C_DATAOUT 0x10 512 #define RA_I2C_DATAIN 0x14 513 #define RA_I2C_STATUS 0x18 514 #define RA_I2C_STARTXFR 0x1C 515 #define RA_I2C_BYTECNT 0x20 516 517 #define I2C_CONFIG_ADDRLEN(x) (((x) & 0x7) << 5) 518 #define I2C_CONFIG_ADDRLEN_7 6 519 #define I2C_CONFIG_ADDRLEN_8 7 520 #define I2C_CONFIG_DEVADLEN(x) (((x) & 0x7) << 2) 521 #define I2C_CONFIG_DEVADLEN_6 5 522 #define I2C_CONFIG_DEVADLEN_7 6 523 #define I2C_CONFIG_ADDRDIS __BIT(1) 524 #define I2C_CONFIG_DEVDIS __BIT(0) 525 #define I2C_STATUS_STARTERR __BIT(4) 526 #define I2C_STATUS_ACKERR __BIT(3) 527 #define I2C_STATUS_DATARDY __BIT(2) 528 #define I2C_STATUS_SDOEMPTY __BIT(1) 529 #define I2C_STATUS_BUSY __BIT(0) 530 531 /* 532 * SPI registers 533 */ 534 #define RA_SPI_STATUS 0x00 535 #define RA_SPI_CONFIG 0x10 536 #define RA_SPI_CONTROL 0x14 537 #define RA_SPI_DATA 0x20 538 539 #define SPI_STATUS_BUSY __BIT(0) 540 #define SPI_CONFIG_MSBFIRST __BIT(8) 541 #define SPI_CONFIG_CLK __BIT(6) 542 #define SPI_CONFIG_RXCLKEDGE_FALL __BIT(5) 543 #define SPI_CONFIG_TXCLKEDGE_FALL __BIT(4) 544 #define SPI_CONFIG_TRISTATE __BIT(3) 545 #define SPI_CONFIG_RATE(x) ((x) & 0x7) 546 #define SPI_CONFIG_RATE_DIV_2 0 547 #define SPI_CONFIG_RATE_DIV_4 1 548 #define SPI_CONFIG_RATE_DIV_8 2 549 #define SPI_CONFIG_RATE_DIV_16 3 550 #define SPI_CONFIG_RATE_DIV_32 4 551 #define SPI_CONFIG_RATE_DIV_64 5 552 #define SPI_CONFIG_RATE_DIV_128 6 553 #define SPI_CONFIG_RATE_DIV_NONE 7 554 #define SPI_CONTROL_TRISTATE __BIT(3) 555 #define SPI_CONTROL_STARTWR __BIT(2) 556 #define SPI_CONTROL_STARTRD __BIT(1) 557 #define SPI_CONTROL_ENABLE_LOW (0 << 0) 558 #define SPI_CONTROL_ENABLE_HIGH __BIT(0) 559 #define SPI_DATA_VAL(x) ((x) & 0xff) 560 561 /* 562 * Frame Engine registers 563 */ 564 #define RA_FE_MDIO_ACCESS 0x000 565 #define RA_FE_MDIO_CFG1 0x004 566 #define RA_FE_GLOBAL_CFG 0x008 567 #define RA_FE_GLOBAL_RESET 0x00C 568 #define RA_FE_INT_STATUS 0x010 569 #define RA_FE_INT_ENABLE 0x014 570 #define RA_FE_MDIO_CFG2 0x018 571 #define RA_FE_TIME_STAMP 0x01C 572 #define RA_FE_GDMA1_FWD_CFG 0x020 573 #define RA_FE_GDMA1_SCHED_CFG 0x024 574 #define RA_FE_GDMA1_SHAPE_CFG 0x028 575 #define RA_FE_GDMA1_MAC_LSB 0x02C 576 #define RA_FE_GDMA1_MAC_MSB 0x030 577 #define RA_FE_PSE_FQ_CFG 0x040 578 #define RA_FE_CDMA_FC_CFG 0x044 579 #define RA_FE_GDMA1_FC_CFG 0x048 580 #define RA_FE_GDMA2_FC_CFG 0x04C 581 #define RA_FE_CDMA_OQ_STA 0x050 582 #define RA_FE_GDMA1_OQ_STA 0x054 583 #define RA_FE_GDMA2_OQ_STA 0x058 584 #define RA_FE_PSE_IQ_STA 0x05C 585 #define RA_FE_GDMA2_FWD_CFG 0x060 586 #define RA_FE_GDMA2_SCHED_CFG 0x064 587 #define RA_FE_GDMA2_SHAPE_CFG 0x068 588 #define RA_FE_GDMA2_MAC_LSB 0x06C 589 #define RA_FE_GDMA2_MAC_MSB 0x070 590 #define RA_FE_CDMA_CSG_CFG 0x080 591 #define RA_FE_CDMA_SCHED_CFG 0x084 592 #define RA_FE_PPPOE_SID_0001 0x088 593 #define RA_FE_PPPOE_SID_0203 0x08C 594 #define RA_FE_PPPOE_SID_0405 0x090 595 #define RA_FE_PPPOE_SID_0607 0x094 596 #define RA_FE_PPPOE_SID_0809 0x098 597 #define RA_FE_PPPOE_SID_1011 0x09C 598 #define RA_FE_PPPOE_SID_1213 0x0A0 599 #define RA_FE_PPPOE_SID_1415 0x0A4 600 #define RA_FE_VLAN_ID_0001 0x0A8 601 #define RA_FE_VLAN_ID_0203 0x0AC 602 #define RA_FE_VLAN_ID_0405 0x0B0 603 #define RA_FE_VLAN_ID_0607 0x0B4 604 #define RA_FE_VLAN_ID_0809 0x0B8 605 #define RA_FE_VLAN_ID_1011 0x0BC 606 #define RA_FE_VLAN_ID_1213 0x0C0 607 #define RA_FE_VLAN_ID_1415 0x0C4 608 #define RA_FE_PDMA_GLOBAL_CFG 0x100 609 #define RA_FE_PDMA_RESET_IDX 0x104 610 #define RA_FE_PDMA_SCHED_CFG 0x108 611 #define RA_FE_PDMA_DLY_INT_CFG 0x10C 612 #define RA_FE_PDMA_TX0_PTR 0x110 613 #define RA_FE_PDMA_TX0_COUNT 0x114 614 #define RA_FE_PDMA_TX0_CPU_IDX 0x118 615 #define RA_FE_PDMA_TX0_DMA_IDX 0x11C 616 #define RA_FE_PDMA_TX1_PTR 0x120 617 #define RA_FE_PDMA_TX1_COUNT 0x124 618 #define RA_FE_PDMA_TX1_CPU_IDX 0x128 619 #define RA_FE_PDMA_TX1_DMA_IDX 0x12C 620 #define RA_FE_PDMA_RX0_PTR 0x130 621 #define RA_FE_PDMA_RX0_COUNT 0x134 622 #define RA_FE_PDMA_RX0_CPU_IDX 0x138 623 #define RA_FE_PDMA_RX0_DMA_IDX 0x13C 624 #define RA_FE_PDMA_TX2_PTR 0x140 625 #define RA_FE_PDMA_TX2_COUNT 0x144 626 #define RA_FE_PDMA_TX2_CPU_IDX 0x148 627 #define RA_FE_PDMA_TX2_DMA_IDX 0x14C 628 #define RA_FE_PDMA_TX3_PTR 0x150 629 #define RA_FE_PDMA_TX3_COUNT 0x154 630 #define RA_FE_PDMA_TX3_CPU_IDX 0x158 631 #define RA_FE_PDMA_TX3_DMA_IDX 0x15C 632 #define RA_FE_PDMA_FC_CFG 0x1F0 633 /* TODO: FE_COUNTERS */ 634 635 #define MDIO_ACCESS_TRG __BIT(31) 636 #define MDIO_ACCESS_WR __BIT(30) 637 #define MDIO_ACCESS_PHY_ADDR(x) (((x) & 0x1f) << 24) 638 #define MDIO_ACCESS_REG(x) (((x) & 0x1f) << 16) 639 #define MDIO_ACCESS_DATA(x) ((x) & 0xffff) 640 #define MDIO_CFG_AUTO_POLL __BIT(29) 641 #define MDIO_CFG_PHY_ADDR(x) (((x) & 0x1f) << 24) 642 #define MDIO_CFG_BP_EN __BIT(16) 643 #define MDIO_CFG_FORCE_CFG __BIT(15) 644 #define MDIO_CFG_SPEED(x) (((x) & 0x3) << 13) 645 #define MDIO_CFG_SPEED_1000M 2 646 #define MDIO_CFG_SPEED_100M 1 647 #define MDIO_CFG_SPEED_10M 0 648 #define MDIO_CFG_FULL_DUPLEX __BIT(12) 649 #define MDIO_CFG_FC_TX __BIT(11) 650 #define MDIO_CFG_FC_RX __BIT(10) 651 #define MDIO_CFG_LINK_DOWN __BIT(9) 652 #define MDIO_CFG_AUTO_DONE __BIT(8) 653 #define MDIO_CFG_MDC_CLKDIV(x) (((x) & 0x3) << 6) 654 #define MDIO_CFG_MDC_512KHZ 3 655 #define MDIO_CFG_MDC_1MHZ 2 656 #define MDIO_CFG_MDC_2MHZ 1 657 #define MDIO_CFG_MDC_4MHZ 0 658 #define MDIO_CFG_TURBO_50MHZ __BIT(5) 659 #define MDIO_CFG_TURBO_EN __BIT(4) 660 #define MDIO_CFG_RX_CLK_SKEW (((x) & 0x3) << 2) 661 #define MDIO_CFG_RX_SKEW_INV 3 662 #define MDIO_CFG_RX_SKEW_400PS 2 663 #define MDIO_CFG_RX_SKEW_200PS 1 664 #define MDIO_CFG_RX_SKEW_ZERO 0 665 #define MDIO_CFG_TX_CLK_MODE(x) (((x) & 0x1) << 0) 666 #define MDIO_CFG_TX_CLK_MODE_3COM 1 667 #define MDIO_CFG_TX_CLK_MODE_HP 0 668 #define FE_GLOBAL_CFG_EXT_VLAN(x) (((x) & 0xffff) << 16) 669 #define FE_GLOBAL_CFG_US_CLK(x) (((x) & 0xff) << 8) 670 #define FE_GLOBAL_CFG_L2_SPACE(x) (((x) & 0xf) << 4) 671 #define FE_GLOBAL_RESET_PSE __BIT(0) 672 #define FE_INT_PPE_COUNT_HIGH __BIT(31) 673 #define FE_INT_DMA_COUNT_HIGH __BIT(29) 674 #define FE_INT_PSE_P2_FC_ASSERT __BIT(26) 675 #define FE_INT_PSE_FC_DROP __BIT(24) 676 #define FE_INT_GDMA_DROP_OTHER __BIT(23) 677 #define FE_INT_PSE_P1_FC_ASSERT __BIT(22) 678 #define FE_INT_PSE_P0_FC_ASSERT __BIT(21) 679 #define FE_INT_PSE_FQ_EMPTY __BIT(20) 680 #define FE_INT_TX_COHERENT __BIT(17) 681 #define FE_INT_RX_COHERENT __BIT(16) 682 #define FE_INT_TX3 __BIT(11) 683 #define FE_INT_TX2 __BIT(10) 684 #define FE_INT_TX1 __BIT(9) 685 #define FE_INT_TX0 __BIT(8) 686 #define FE_INT_RX __BIT(2) 687 #define FE_INT_TX_DELAY __BIT(1) 688 #define FE_INT_RX_DELAY __BIT(0) 689 #define FE_GDMA_FWD_CFG_JUMBO_LEN(x) (((x) & 0xf) << 28) 690 #define FE_GDMA_FWD_CFG_DROP_256B __BIT(23) 691 #define FE_GDMA_FWD_CFG_IP4_CRC_EN __BIT(22) 692 #define FE_GDMA_FWD_CFG_TCP_CRC_EN __BIT(21) 693 #define FE_GDMA_FWD_CFG_UDP_CRC_EN __BIT(20) 694 #define FE_GDMA_FWD_CFG_JUMBO_EN __BIT(19) 695 #define FE_GDMA_FWD_CFG_DIS_TX_PAD __BIT(18) 696 #define FE_GDMA_FWD_CFG_DIS_TX_CRC __BIT(17) 697 #define FE_GDMA_FWD_CFG_STRIP_RX_CRC __BIT(16) 698 #define FE_GDMA_FWD_CFG_UNICA_PORT(x) (((x) & 0x3) << 12) 699 #define FE_GDMA_FWD_CFG_BROAD_PORT(x) (((x) & 0x3) << 8) 700 #define FE_GDMA_FWD_CFG_MULTI_PORT(x) (((x) & 0x3) << 6) 701 #define FE_GDMA_FWD_CFG_OTHER_PORT(x) (((x) & 0x3) << 0) 702 #define FE_GDMA_FWD_CFG_PORT_DROP 7 703 #define FE_GDMA_FWD_CFG_PORT_PPE 6 704 #define FE_GDMA_FWD_CFG_PORT_GDMA2 2 705 #define FE_GDMA_FWD_CFG_PORT_GDMA1 1 706 #define FE_GDMA_FWD_CFG_PORT_CPU 0 707 #define FE_PSE_FQ_MAX_COUNT(x) (((x) & 0xff) << 24) 708 #define FE_PSE_FQ_FC_RELEASE(x) (((x) & 0xff) << 16) 709 #define FE_PSE_FQ_FC_ASSERT(x) (((x) & 0xff) << 8) 710 #define FE_PSE_FQ_FC_DROP(x) (((x) & 0xff) << 0) 711 #define FE_CDMA_CSG_CFG_VLAN_TAG(x) (((x) & 0xffff) << 16) 712 #define FE_CDMA_CSG_CFG_IP4_CRC_EN __BIT(2) 713 #define FE_CDMA_CSG_CFG_UDP_CRC_EN __BIT(1) 714 #define FE_CDMA_CSG_CFG_TCP_CRC_EN __BIT(0) 715 #define FE_PDMA_GLOBAL_CFG_HDR_SEG_LEN __BIT(16) 716 #define FE_PDMA_GLOBAL_CFG_TX_WB_DDONE __BIT(6) 717 #define FE_PDMA_GLOBAL_CFG_BURST_SZ(x) (((x) & 0x3) << 4) 718 #define FE_PDMA_GLOBAL_CFG_BURST_SZ_4 (0 << 4) 719 #define FE_PDMA_GLOBAL_CFG_BURST_SZ_8 __BIT(4) 720 #define FE_PDMA_GLOBAL_CFG_BURST_SZ_16 (2 << 4) 721 #define FE_PDMA_GLOBAL_CFG_RX_DMA_BUSY __BIT(3) 722 #define FE_PDMA_GLOBAL_CFG_RX_DMA_EN __BIT(2) 723 #define FE_PDMA_GLOBAL_CFG_TX_DMA_BUSY __BIT(1) 724 #define FE_PDMA_GLOBAL_CFG_TX_DMA_EN __BIT(0) 725 #define PDMA_RST_RX0 __BIT(16) 726 #define PDMA_RST_TX3 __BIT(3) 727 #define PDMA_RST_TX2 __BIT(2) 728 #define PDMA_RST_TX1 __BIT(1) 729 #define PDMA_RST_TX0 __BIT(0) 730 731 /* 732 * 10/100 Switch registers 733 */ 734 735 #define RA_ETH_SW_ISR 0x00 736 #define RA_ETH_SW_IMR 0x04 737 #define RA_ETH_SW_FCT0 0x08 738 #define RA_ETH_SW_FCT1 0x0C 739 #define RA_ETH_SW_PFC0 0x10 740 #define RA_ETH_SW_PFC1 0x14 741 #define RA_ETH_SW_PFC2 0x18 742 #define RA_ETH_SW_QCS0 0x1C 743 #define RA_ETH_SW_QCS1 0x20 744 #define RA_ETH_SW_ATS 0x24 745 #define RA_ETH_SW_ATS0 0x28 746 #define RA_ETH_SW_ATS1 0x2C 747 #define RA_ETH_SW_ATS2 0x30 748 #define RA_ETH_SW_WMAD0 0x34 749 #define RA_ETH_SW_WMAD1 0x38 750 #define RA_ETH_SW_WMAD2 0x3C 751 #define RA_ETH_SW_PVIDC0 0x40 752 #define RA_ETH_SW_PVIDC1 0x44 753 #define RA_ETH_SW_PVIDC2 0x48 754 #define RA_ETH_SW_PVIDC3 0x4C 755 #define RA_ETH_SW_VLANI0 0x50 756 #define RA_ETH_SW_VLANI1 0x54 757 #define RA_ETH_SW_VLANI2 0x58 758 #define RA_ETH_SW_VLANI3 0x5C 759 #define RA_ETH_SW_VLANI4 0x60 760 #define RA_ETH_SW_VLANI5 0x64 761 #define RA_ETH_SW_VLANI6 0x68 762 #define RA_ETH_SW_VLANI7 0x6C 763 #define RA_ETH_SW_VMSC0 0x70 764 #define RA_ETH_SW_VMSC1 0x74 765 #define RA_ETH_SW_VMSC2 0x78 766 #define RA_ETH_SW_VMSC3 0x7C 767 #define RA_ETH_SW_POA 0x80 768 #define RA_ETH_SW_FPA 0x84 769 #define RA_ETH_SW_PTS 0x88 770 #define RA_ETH_SW_SOCPC 0x8C 771 #define RA_ETH_SW_POC0 0x90 772 #define RA_ETH_SW_POC1 0x94 773 #define RA_ETH_SW_POC2 0x98 774 #define RA_ETH_SW_SWGC 0x9C 775 #define RA_ETH_SW_RST 0xA0 776 #define RA_ETH_SW_LEDP0 0xA4 777 #define RA_ETH_SW_LEDP1 0xA8 778 #define RA_ETH_SW_LEDP2 0xAC 779 #define RA_ETH_SW_LEDP3 0xB0 780 #define RA_ETH_SW_LEDP4 0xB4 781 #define RA_ETH_SW_WDOG 0xB8 782 #define RA_ETH_SW_DBG 0xBC 783 #define RA_ETH_SW_PCTL0 0xC0 784 #define RA_ETH_SW_PCTL1 0xC4 785 #define RA_ETH_SW_FPORT 0xC8 786 #define RA_ETH_SW_FTC2 0xCC 787 #define RA_ETH_SW_QSS0 0xD0 788 #define RA_ETH_SW_QSS1 0xD4 789 #define RA_ETH_SW_DBGC 0xD8 790 #define RA_ETH_SW_MTI1 0xDC 791 #define RA_ETH_SW_PPC 0xE0 792 #define RA_ETH_SW_SGC2 0xE4 793 #define RA_ETH_SW_PCNT0 0xE8 794 #define RA_ETH_SW_PCNT1 0xEC 795 #define RA_ETH_SW_PCNT2 0xF0 796 #define RA_ETH_SW_PCNT3 0xF4 797 #define RA_ETH_SW_PCNT4 0xF8 798 #define RA_ETH_SW_PCNT5 0xFC 799 800 #define ISR_WDOG1_EXPIRED __BIT(29) 801 #define ISR_WDOG0_EXPIRED __BIT(28) 802 #define ISR_HAS_INTRUDER __BIT(27) 803 #define ISR_PORT_STS_CHNG __BIT(26) 804 #define ISR_BRDCAST_STORM __BIT(25) 805 #define ISR_MUST_DROP_LAN __BIT(24) 806 #define ISR_GLOB_QUE_FULL __BIT(23) 807 #define ISR_LAN_QUE6_FULL __BIT(20) 808 #define ISR_LAN_QUE5_FULL __BIT(19) 809 #define ISR_LAN_QUE4_FULL __BIT(18) 810 #define ISR_LAN_QUE3_FULL __BIT(17) 811 #define ISR_LAN_QUE2_FULL __BIT(16) 812 #define ISR_LAN_QUE1_FULL __BIT(15) 813 #define ISR_LAN_QUE0_FULL __BIT(14) 814 #define FTC0_REL_THR 24 815 #define FTC0_SET_THR 16 816 #define FTC0_DROP_REL_THR 8 817 #define FTC0_DROP_SET_THR 0 818 #define FTC1_PER_PORT_THR 0 819 #define PCTL0_WR_VAL(x) (((x) & 0xffff) << 16) 820 #define PCTL0_RD_CMD __BIT(14) 821 #define PCTL0_WR_CMD __BIT(13) 822 #define PCTL0_REG(x) (((x) & 0x1f) << 8) 823 #define PCTL0_ADDR(x) (((x) & 0x1f) << 0) 824 #define PCTL1_RD_VAL(x) (((x) >> 16) & 0xffff) 825 #define PCTL1_RD_DONE __BIT(1) /* read clear */ 826 #define PCTL1_WR_DONE __BIT(0) /* read clear */ 827 #define SGC2_WL_FC_EN __BIT(30) 828 #define SGC2_PORT5_IS_LAN __BIT(29) 829 #define SGC2_PORT4_IS_LAN __BIT(28) 830 #define SGC2_PORT3_IS_LAN __BIT(27) 831 #define SGC2_PORT2_IS_LAN __BIT(26) 832 #define SGC2_PORT1_IS_LAN __BIT(25) 833 #define SGC2_PORT0_IS_LAN __BIT(24) 834 #define SGC2_TX_CPU_TPID(x) ((x) << 16) 835 #define SGC2_ARBITER_LAN_EN __BIT(11) 836 #define SGC2_CPU_TPID_EN __BIT(10) 837 #define SGC2_DBL_TAG_EN5 __BIT(5) 838 #define SGC2_DBL_TAG_EN4 __BIT(4) 839 #define SGC2_DBL_TAG_EN3 __BIT(3) 840 #define SGC2_DBL_TAG_EN2 __BIT(2) 841 #define SGC2_DBL_TAG_EN1 __BIT(1) 842 #define SGC2_DBL_TAG_EN0 __BIT(0) 843 844 845 #define FTC_THR_MSK 0xff 846 847 #define PFC0_MTCC_LIMIT 24 848 #define PFC0_TURN_OFF_CF 16 849 #define PFC0_TURN_OFF_CF_MSK 0xff 850 #define PFC0_VO_NUM 12 851 #define PFC0_CL_NUM 8 852 #define PFC0_BE_NUM 4 853 #define PFC0_BK_NUM 0 854 #define PFC0_NUM_MSK 0xf 855 856 #define PFC1_P6_Q1_EN __BIT(31) 857 #define PFC1_P6_TOS_EN __BIT(30) 858 #define PFC1_P5_TOS_EN __BIT(29) 859 #define PFC1_P4_TOS_EN __BIT(28) 860 #define PFC1_P3_TOS_EN __BIT(27) 861 862 #define PFC1_P1_TOS_EN __BIT(25) 863 #define PFC1_P0_TOS_EN __BIT(24) 864 #define PFC1_PORT_PRI6 12 865 #define PFC1_PORT_PRI5 10 866 #define PFC1_PORT_PRI4 8 867 #define PFC1_PORT_PRI3 6 868 #define PFC1_PORT_PRI2 4 869 #define PFC1_PORT_PRI1 2 870 #define PFC1_PORT_PRI0 0 871 #define PFC1_PORT_MSK 0x3 872 873 #define PFC2_PRI_THR_VO 24 874 #define PFC2_PRI_THR_CL 16 875 #define PFC2_PRI_THR_BE 8 876 #define PFC2_PRI_THR_BK 0 877 #define PFC2_PRI_THR_MSK 0xff 878 879 #define GQC0_EMPTY_BLOCKS 0 880 #define GQC0_EMPTY_BLOCKS_MSK 0xff 881 882 /* 883 * USB OTG Registers 884 */ 885 #define RA_USB_OTG_OTG_CNTRL 0x000 886 #define RA_USB_OTG_OTG_INT 0x004 887 #define RA_USB_OTG_AHB_CFG 0x008 888 #define RA_USB_OTG_CFG 0x00C 889 #define RA_USB_OTG_RESET 0x010 890 #define RA_USB_OTG_INT 0x014 891 #define RA_USB_OTG_INT_MASK 0x018 892 #define RA_USB_OTG_RX_STAT 0x01C 893 #define RA_USB_OTG_RX_POP_STAT 0x020 894 #define RA_USB_OTG_RX_FIFO_SZ 0x024 895 #define RA_USB_OTG_TX_FIFO_SZ 0x028 896 #define RA_USB_OTG_TX_FIFO_STAT 0x02C 897 #define RA_USB_OTG_I2C_ACCESS 0x030 898 #define RA_USB_OTG_PHY_CTL 0x034 899 #define RA_USB_OTG_GPIO 0x038 900 #define RA_USB_OTG_GUID 0x03C 901 #define RA_USB_OTG_SNPSID 0x040 902 #define RA_USB_OTG_HWCFG1 0x044 903 #define RA_USB_OTG_HWCFG2 0x048 904 #define RA_USB_OTG_HWCFG3 0x04C 905 #define RA_USB_OTG_HWCFG4 0x050 906 #define RA_USB_OTG_HC_TX_FIFO_SZ 0x100 907 #define RA_USB_OTG_DV_TX_FIFO_SZ 0x104 908 #define RA_USB_OTG_HC_CFG 0x400 909 #define RA_USB_OTG_HC_FRM_INTRVL 0x404 910 #define RA_USB_OTG_HC_FRM_NUM 0x408 911 #define RA_USB_OTG_HC_TX_STAT 0x410 912 #define RA_USB_OTG_HC_INT 0x414 913 #define RA_USB_OTG_HC_INT_MASK 0x418 914 #define RA_USB_OTG_HC_PORT 0x440 915 #define RA_USB_OTG_HC_CH_CFG 0x500 916 #define RA_USB_OTG_HC_CH_SPLT 0x504 917 #define RA_USB_OTG_HC_CH_INT 0x508 918 #define RA_USB_OTG_HC_CH_INT_MASK 0x50C 919 #define RA_USB_OTG_HC_CH_XFER 0x510 920 #define RA_USB_OTG_HC_CH_DMA_ADDR 0x514 921 #define RA_USB_OTG_DV_CFG 0x800 922 #define RA_USB_OTG_DV_CTL 0x804 923 #define RA_USB_OTG_DV_STAT 0x808 924 #define RA_USB_OTG_DV_IN_INT_MASK 0x810 925 #define RA_USB_OTG_DV_OUT_INT_MASK 0x814 926 #define RA_USB_OTG_DV_ALL_INT 0x818 927 #define RA_USB_OTG_DV_EP_INT_MASK 0x81c 928 #define RA_USB_OTG_DV_IN_SEQ_RQ1 0x820 929 #define RA_USB_OTG_DV_IN_SEQ_RQ2 0x824 930 #define RA_USB_OTG_DV_IN_SEQ_RQ3 0x830 931 #define RA_USB_OTG_DV_IN_SEQ_RQ4 0x834 932 #define RA_USB_OTG_DV_VBUS_DISCH 0x828 933 #define RA_USB_OTG_DV_VBUS_PULSE 0x82c 934 #define RA_USB_OTG_DV_THRESH_CTL 0x830 935 #define RA_USB_OTG_DV_IN_FIFO_INT 0x834 936 #define RA_USB_OTG_DV_IN0_CTL 0x900 937 938 #define OTG_OTG_CNTRL_B_SESS_VALID __BIT(19) 939 #define OTG_OTG_CNTRL_A_SESS_VALID __BIT(18) 940 #define OTG_OTG_CNTRL_DEBOUNCE_SHORT __BIT(17) 941 #define OTG_OTG_CNTRL_CONNID_STATUS __BIT(16) 942 #define OTG_OTG_CNTRL_DV_HNP_EN __BIT(11) 943 #define OTG_OTG_CNTRL_HC_SET_HNP_EN __BIT(10) 944 #define OTG_OTG_CNTRL_HNP_REQ __BIT(9) 945 #define OTG_OTG_CNTRL_HNP_SUCCESS __BIT(8) 946 #define OTG_OTG_CNTRL_SESS_REQ __BIT(1) 947 #define OTG_OTG_CNTRL_SESS_REQ_SUCCESS __BIT(0) 948 #define OTG_OTG_INT_DEBOUNCE_DONE __BIT(19) 949 #define OTG_OTG_INT_ADEV_TIMEOUT __BIT(18) 950 #define OTG_OTG_INT_HOST_NEG_DETECT __BIT(17) 951 #define OTG_OTG_INT_HOST_NEG_STATUS __BIT(9) 952 #define OTG_OTG_INT_SESSION_REQ_STATUS __BIT(8) 953 #define OTG_OTG_INT_SESSION_END_STATUS __BIT(2) 954 #define OTG_AHB_CFG_TX_PFIFO_EMPTY_INT_EN __BIT(8) 955 #define OTG_AHB_CFG_TX_NPFIFO_EMPTY_INT_EN __BIT(7) 956 #define OTG_AHB_CFG_DMA_EN __BIT(5) 957 #define OTG_AHB_CFG_BURST(x) (((x) & 0xf) << 1) 958 #define OTG_AHB_CFG_BURST_SINGLE 0 959 #define OTG_AHB_CFG_BURST_INCR 1 960 #define OTG_AHB_CFG_BURST_INCR4 3 961 #define OTG_AHB_CFG_BURST_INCR8 5 962 #define OTG_AHB_CFG_BURST_INCR16 7 963 #define OTG_AHB_CFG_GLOBAL_INT_EN __BIT(0) 964 #define OTG_CFG_CORRUPT_TX __BIT(31) 965 #define OTG_CFG_FORCE_DEVICE __BIT(30) 966 #define OTG_CFG_FORCE_HOST __BIT(29) 967 #define OTG_CFG_ULPI_EXT_VBUS_IND_SEL __BIT(22) 968 #define OTG_CFG_ULPI_EXT_VBUS_IND __BIT(21) 969 #define OTG_CFG_ULPI_EXT_VBUS_DRV __BIT(20) 970 #define OTG_CFG_ULPI_CLOCK_SUSPEND __BIT(19) 971 #define OTG_CFG_ULPI_AUTO_RESUME __BIT(18) 972 #define OTG_CFG_ULPI_FS_LS_SEL __BIT(17) 973 #define OTG_CFG_UTMI_I2C_SEL __BIT(16) 974 #define OTG_CFG_TURNAROUND_TIME(x) (((x) & 0xf) << 10) 975 #define OTG_CFG_HNP_CAP __BIT(9) 976 #define OTG_CFG_SRP_CAP __BIT(8) 977 #define OTG_CFG_ULPI_DDR_SEL __BIT(7) 978 #define OTG_CFG_HS_PHY_SEL __BIT(6) 979 #define OTG_CFG_FS_IF_SEL __BIT(5) 980 #define OTG_CFG_ULPI_UTMI_SEL __BIT(4) 981 #define OTG_CFG_PHY_IF __BIT(3) 982 #define OTG_CFG_TIMEOUT(x) (((x) & 0x7) << 0) 983 #define OTG_RST_AHB_IDLE __BIT(31) 984 #define OTG_RST_DMA_ACTIVE __BIT(30) 985 #define OTG_RST_TXQ_TO_FLUSH(x) (((x) & 0x1f) << 6) 986 #define OTG_RST_TXQ_FLUSH_ALL 0x10 987 #define OTG_RST_TXQ_FLUSH __BIT(5) 988 #define OTG_RST_RXQ_FLUSH __BIT(4) 989 #define OTG_RST_INQ_FLUSH __BIT(3) 990 #define OTG_RST_HC_FRAME __BIT(2) 991 #define OTG_RST_AHB __BIT(1) 992 #define OTG_RST_CORE __BIT(0) 993 #define OTG_INT_RESUME __BIT(31) 994 #define OTG_INT_SESSION_REQ __BIT(30) 995 #define OTG_INT_DISCONNECT __BIT(29) 996 #define OTG_INT_CONNID_STATUS __BIT(28) 997 #define OTG_INT_PTX_EMPTY __BIT(26) 998 #define OTG_INT_HOST_CHANNEL __BIT(25) 999 #define OTG_INT_PORT_STATUS __BIT(24) 1000 #define OTG_INT_DMA_FETCH_SUSPEND __BIT(22) 1001 #define OTG_INT_INCOMPLETE_PERIODIC __BIT(21) 1002 #define OTG_INT_INCOMPLETE_ISOC __BIT(20) 1003 #define OTG_INT_DV_OUT_EP __BIT(19) 1004 #define OTG_INT_DV_IN_EP __BIT(18) 1005 #define OTG_INT_DV_EP_MISMATCH __BIT(17) 1006 #define OTG_INT_DV_PERIODIC_END __BIT(15) 1007 #define OTG_INT_DV_ISOC_OUT_DROP __BIT(14) 1008 #define OTG_INT_DV_ENUM_COMPLETE __BIT(13) 1009 #define OTG_INT_DV_USB_RESET __BIT(12) 1010 #define OTG_INT_DV_USB_SUSPEND __BIT(11) 1011 #define OTG_INT_DV_USB_EARLY_SUSPEND __BIT(10) 1012 #define OTG_INT_I2C __BIT(9) 1013 #define OTG_INT_ULPI_CARKIT __BIT(8) 1014 #define OTG_INT_DV_OUT_NAK_EFFECTIVE __BIT(7) 1015 #define OTG_INT_DV_IN_NAK_EFFECTIVE __BIT(6) 1016 #define OTG_INT_NPTX_EMPTY __BIT(5) 1017 #define OTG_INT_RX_FIFO __BIT(4) 1018 #define OTG_INT_SOF __BIT(3) 1019 #define OTG_INT_OTG __BIT(2) 1020 #define OTG_INT_MODE_MISMATCH __BIT(1) 1021 #define OTG_INT_MODE __BIT(0) 1022 #define USB_OTG_SNPSID_CORE_REV_2_00 0x4F542000 1023 #define OTG_HC_CFG_FORCE_NO_HS __BIT(2) 1024 #define OTG_HC_CFG_FSLS_CLK_SEL(x) (((x) & 0x3) << 0) 1025 #define OTG_HC_CFG_FS_CLK_3060 0 1026 #define OTG_HC_CFG_FS_CLK_48 1 1027 #define OTG_HC_CFG_LS_CLK_3060 0 1028 #define OTG_HC_CFG_LS_CLK_48 1 1029 #define OTG_HC_CFG_LS_CLK_6 2 1030 #define USB_OTG_HC_FRM_NUM(x) (x & 0x3fff) 1031 #define USB_OTG_HC_FRM_REM(x) (x >> 16) 1032 #define USB_OTG_HC_PORT_SPEED(x) (((x) >> 17) & 0x3) 1033 #define USB_OTG_HC_PORT_SPEED_HS 0 1034 #define USB_OTG_HC_PORT_SPEED_FS 1 1035 #define USB_OTG_HC_PORT_SPEED_LS 2 1036 #define USB_OTG_HC_PORT_TEST(x) (((x) & 0xf) << 13) 1037 #define USB_OTG_HC_PORT_TEST_DISABLED 0 1038 #define USB_OTG_HC_PORT_TEST_J_MODE 1 1039 #define USB_OTG_HC_PORT_TEST_K_MODE 2 1040 #define USB_OTG_HC_PORT_TEST_NAK_MODE 3 1041 #define USB_OTG_HC_PORT_TEST_PKT_MODE 4 1042 #define USB_OTG_HC_PORT_TEST_FORCE_MODE 5 1043 #define USB_OTG_HC_PORT_POWER __BIT(12) 1044 #define USB_OTG_HC_PORT_LINE_STAT (((x) >> 10) & 0x3) 1045 #define USB_OTG_HC_PORT_LINE_STAT_DP 1 1046 #define USB_OTG_HC_PORT_LINE_STAT_DM 3 1047 #define USB_OTG_HC_PORT_RESET __BIT(8) 1048 #define USB_OTG_HC_PORT_SUSPEND __BIT(7) 1049 #define USB_OTG_HC_PORT_RESUME __BIT(6) 1050 #define USB_OTG_HC_PORT_OVCURR_CHANGE __BIT(5) 1051 #define USB_OTG_HC_PORT_OVCURR __BIT(4) 1052 #define USB_OTG_HC_PORT_ENABLE_CHANGE __BIT(3) 1053 #define USB_OTG_HC_PORT_ENABLE __BIT(2) 1054 #define USB_OTG_HC_PORT_CONNECT_CHANGE __BIT(1) 1055 #define USB_OTG_HC_PORT_STATUS __BIT(0) 1056 #define USB_OTG_HC_CH_CFG_ENABLE __BIT(31) 1057 #define USB_OTG_HC_CH_CFG_DISABLE __BIT(30) 1058 #define USB_OTG_HC_CH_CFG_ODD_FRAME __BIT(29) 1059 #define USB_OTG_HC_CH_CFG_DEV_ADDR(x) (((x) & 0x7f) << 22) 1060 #define USB_OTG_HC_CH_CFG_MULTI_CNT(x) (((x) & 0x3) << 20) 1061 #define USB_OTG_HC_CH_CFG_EP_TYPE(x) (((x) & 0x3) << 18) 1062 #define USB_OTG_HC_CH_CFG_EP_TYPE_CTRL 0 1063 #define USB_OTG_HC_CH_CFG_EP_TYPE_ISOC 1 1064 #define USB_OTG_HC_CH_CFG_EP_TYPE_BULK 2 1065 #define USB_OTG_HC_CH_CFG_EP_TYPE_INTR 3 1066 #define USB_OTG_HC_CH_CFG_LS __BIT(17) 1067 #define USB_OTG_HC_CH_CFG_EP_DIR(x) (((x) & 0x1) << 15) 1068 #define USB_OTG_HC_CH_CFG_EP_DIR_OUT 0 1069 #define USB_OTG_HC_CH_CFG_EP_DIR_IN 1 1070 #define USB_OTG_HC_CH_CFG_EP_NUM(x) (((x) & 0xf) << 11) 1071 #define USB_OTG_HC_CH_CFG_MAX_PKT_SZ(x) (((x) & 0x7ff) << 0) 1072 #define USB_OTG_HC_CH_SPLT_EN __BIT(31) 1073 #define USB_OTG_HC_CH_SPLT_COMPLETE __BIT(16) 1074 #define USB_OTG_HC_CH_SPLT_POS(x) (((x) & 0x3) << 14) 1075 #define USB_OTG_HC_CH_SPLT_POS_MID 0 1076 #define USB_OTG_HC_CH_SPLT_POS_END 1 1077 #define USB_OTG_HC_CH_SPLT_POS_BEGIN 2 1078 #define USB_OTG_HC_CH_SPLT_POS_ALL 3 1079 #define USB_OTG_HC_CH_SPLT_HUB_ADDR(x) (((x) & 0x7f) << 7) 1080 #define USB_OTG_HC_CH_SPLT_PORT_ADDR(x) (((x) & 0x7f) << 0) 1081 #define USB_OTG_HC_CH_INT_ALL 0x7ff 1082 #define USB_OTG_HC_CH_INT_TOGGLE_ERROR __BIT(10) 1083 #define USB_OTG_HC_CH_INT_FRAME_OVERRUN __BIT(9) 1084 #define USB_OTG_HC_CH_INT_BABBLE_ERROR __BIT(8) 1085 #define USB_OTG_HC_CH_INT_XACT_ERROR __BIT(7) 1086 #define USB_OTG_HC_CH_INT_NYET __BIT(6) 1087 #define USB_OTG_HC_CH_INT_ACK __BIT(5) 1088 #define USB_OTG_HC_CH_INT_NAK __BIT(4) 1089 #define USB_OTG_HC_CH_INT_STALL __BIT(3) 1090 #define USB_OTG_HC_CH_INT_DMA_ERROR __BIT(2) 1091 #define USB_OTG_HC_CH_INT_HALTED __BIT(1) 1092 #define USB_OTG_HC_CH_INT_XFER_COMPLETE __BIT(0) 1093 #define USB_OTG_HC_CH_XFER_DO_PING __BIT(31) 1094 #define USB_OTG_HC_CH_WR_XFER_PID(x) (((x) & 0x3) << 29) 1095 #define USB_OTG_HC_CH_RD_XFER_PID(x) (((x) >> 29) & 0x3) 1096 #define USB_OTG_HC_CH_XFER_PID_DATA0 0 1097 #define USB_OTG_HC_CH_XFER_PID_DATA2 1 1098 #define USB_OTG_HC_CH_XFER_PID_DATA1 2 1099 #define USB_OTG_HC_CH_XFER_PID_SETUP 3 1100 #define USB_OTG_HC_CH_XFER_PID_MDATA 3 1101 #define USB_OTG_HC_CH_XFER_SET_PKT_CNT(x) (((x) & 0x3ff) << 19) 1102 #define USB_OTG_HC_CH_XFER_SET_BYTES(x) ((x) & 0x7ffff) 1103 #define USB_OTG_HC_CH_XFER_GET_PKT_CNT(x) (((x) >> 19) & 0x3ff) 1104 #define USB_OTG_HC_CH_XFER_GET_BYTES(x) ((x) & 0x7ffff) 1105 1106 /* PCIe Registers - 0x10140000 */ 1107 #define RA_PCI_PCICFG 0x0000 1108 #define PCICFG_P2P_BR_DEVNUM1 __BITS(23,20) 1109 #define PCICFG_P2P_BR_DEVNUM0 __BITS(19,16) 1110 #define PCICFG_PSIRST __BIT(1) 1111 #define RA_PCI_PCIINT 0x0008 1112 #define PCIINT_INT3 __BIT(21) // PCIe1 interrupt 1113 #define PCIINT_INT2 __BIT(20) // PCIe0 interrupt 1114 #define PCIINT_INT1 __BIT(19) 1115 #define PCIINT_INT0 __BIT(18) 1116 #define RA_PCI_PCIENA 0x000c 1117 #define RA_PCI_CFGADDR 0x0020 1118 #define CFGADDR_EXTREG __BITS(27,24) 1119 #define CFGADDR_BUS __BITS(23,16) 1120 #define CFGADDR_DEV __BITS(15,11) 1121 #define CFGADDR_FUN __BITS(10,8) 1122 #define CFGADDR_REG __BITS(7,0) 1123 #define RA_PCI_CFGDATA 0x0024 1124 #define RA_PCI_MEMBASE 0x0028 1125 #define MEMBASE_ADDR __BITS(31,16) 1126 #define RA_PCI_IOBASE 0x002c 1127 #define IOBASE_ADDR __BITS(31,16) 1128 #define RA_PCI_PHY0CFG 0x0090 1129 #define PHY0CFG_SPI_BUSY __BIT(31) 1130 #define PHY0CFG_SPI_WR __BIT(23) 1131 #define PHY0CFG_SPI_ADDR __BITS(15,8) 1132 #define PHY0CFG_SPI_DATA __BITS(7,0) 1133 1134 /* PCIe0 RC Control Registers - 0x10142000 */ 1135 #define RA_PCIE0_BAR0SETUP 0x0010 1136 #define BARSETUP_BARMSK __BITS(31,16) 1137 #define BARSETUP_BARENB __BIT(0) 1138 #define RA_PCIE0_BAR1SETUP 0x0014 1139 #define RA_PCIE0_IMBASEBAR0 0x0018 1140 #define IMBASEBAR0 __BITS(31,16) 1141 #define RA_PCIE0_ID 0x0010 1142 #define RA_PCIE0_CLASS 0x0014 1143 #define RA_PCIE0_SUBID 0x0018 1144 #define RA_PCIE0_STATUS 0x0018 1145 #define PCIE_STATUS_LINK_UP __BIT(0) 1146 1147 #endif /* _RALINK_REG_H_ */ 1148
Indexes created Tue Sep 30 20:09:53 GMT 2025