rmixl_pcie.c revision 1.1.2.10
1 /* $NetBSD: rmixl_pcie.c,v 1.1.2.10 2010/03/29 23:32:21 cliff Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * PCI configuration support for RMI XLS SoC 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: rmixl_pcie.c,v 1.1.2.10 2010/03/29 23:32:21 cliff Exp $"); 44 45 #include "opt_pci.h" 46 #include "pci.h" 47 48 #include <sys/cdefs.h> 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/device.h> 53 #include <sys/extent.h> 54 #include <sys/malloc.h> 55 56 #include <uvm/uvm_extern.h> 57 58 #include <machine/bus.h> 59 #include <machine/intr.h> 60 61 #include <mips/rmi/rmixlreg.h> 62 #include <mips/rmi/rmixlvar.h> 63 #include <mips/rmi/rmixl_intr.h> 64 #include <mips/rmi/rmixl_pcievar.h> 65 66 #include <mips/rmi/rmixl_obiovar.h> 67 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 #include <dev/pci/pciconf.h> 71 72 #ifdef PCI_NETBSD_CONFIGURE 73 #include <mips/cache.h> 74 #endif 75 76 #include <machine/pci_machdep.h> 77 78 #ifdef PCI_DEBUG 79 int rmixl_pcie_debug = PCI_DEBUG; 80 # define DPRINTF(x) do { if (rmixl_pcie_debug) printf x ; } while (0) 81 #else 82 # define DPRINTF(x) 83 #endif 84 85 #ifndef DDB 86 # define STATIC static 87 #else 88 # define STATIC 89 #endif 90 91 92 /* 93 * XLS PCIe Extended Configuration Registers 94 */ 95 #define RMIXL_PCIE_ECFG_UESR 0x104 /* Uncorrectable Error Status Reg */ 96 #define RMIXL_PCIE_ECFG_UEMR 0x108 /* Uncorrectable Error Mask Reg */ 97 #define RMIXL_PCIE_ECFG_UEVR 0x10c /* Uncorrectable Error seVerity Reg */ 98 #define PCIE_ECFG_UEVR_DFLT \ 99 (__BITS(18,17) | __BIT(31) | __BITS(5,4) | __BIT(0)) 100 #define PCIE_ECFG_UExR_RESV (__BITS(31,21) | __BITS(11,6) | __BITS(3,1)) 101 #define RMIXL_PCIE_ECFG_CESR 0x110 /* Correctable Error Status Reg */ 102 #define RMIXL_PCIE_ECFG_CEMR 0x114 /* Correctable Error Mask Reg */ 103 #define PCIE_ECFG_CExR_RESV (__BITS(31,14) | __BITS(11,9) | __BITS(5,1)) 104 #define RMIXL_PCIE_ECFG_ACCR 0x118 /* Adv. Capabilities Control Reg */ 105 #define RMIXL_PCIE_ECFG_HLRn(n) (0x11c + ((n) * 4)) /* Header Log Regs */ 106 #define RMIXL_PCIE_ECFG_RECR 0x12c /* Root Error Command Reg */ 107 #define PCIE_ECFG_RECR_RESV __BITS(31,3) 108 #define RMIXL_PCIE_ECFG_RESR 0x130 /* Root Error Status Reg */ 109 #define PCIE_ECFG_RESR_RESV __BITS(26,7) 110 #define RMIXL_PCIE_ECFG_ESI 0x134 /* Error Source Identification Reg */ 111 #define RMIXL_PCIE_ECFG_DSNCR 0x140 /* Dev Serial Number Capability Regs */ 112 113 static const struct { 114 u_int offset; 115 u_int32_t rw1c; 116 } pcie_ecfg_errs_tab[] = { 117 { RMIXL_PCIE_ECFG_UESR, (__BITS(20,12) | __BIT(4)) }, 118 { RMIXL_PCIE_ECFG_CESR, (__BITS(20,12) | __BIT(4)) }, 119 { RMIXL_PCIE_ECFG_HLRn(0), 0 }, 120 { RMIXL_PCIE_ECFG_HLRn(1), 0 }, 121 { RMIXL_PCIE_ECFG_HLRn(2), 0 }, 122 { RMIXL_PCIE_ECFG_HLRn(3), 0 }, 123 { RMIXL_PCIE_ECFG_RESR, __BITS(6,0) }, 124 { RMIXL_PCIE_ECFG_ESI, 0 }, 125 }; 126 #define PCIE_ECFG_ERRS_OFFTAB_NENTRIES \ 127 (sizeof(pcie_ecfg_errs_tab)/sizeof(pcie_ecfg_errs_tab[0])) 128 129 typedef struct rmixl_pcie_int_csr { 130 uint r0; 131 uint r1; 132 } rmixl_pcie_int_csr_t; 133 134 static const rmixl_pcie_int_csr_t int_enb_offset[4] = { 135 { RMIXL_PCIE_LINK0_INT_ENABLE0, RMIXL_PCIE_LINK0_INT_ENABLE1 }, 136 { RMIXL_PCIE_LINK1_INT_ENABLE0, RMIXL_PCIE_LINK1_INT_ENABLE1 }, 137 { RMIXL_PCIE_LINK2_INT_ENABLE0, RMIXL_PCIE_LINK2_INT_ENABLE1 }, 138 { RMIXL_PCIE_LINK3_INT_ENABLE0, RMIXL_PCIE_LINK3_INT_ENABLE1 }, 139 }; 140 141 static const rmixl_pcie_int_csr_t int_sts_offset[4] = { 142 { RMIXL_PCIE_LINK0_INT_STATUS0, RMIXL_PCIE_LINK0_INT_STATUS1 }, 143 { RMIXL_PCIE_LINK1_INT_STATUS0, RMIXL_PCIE_LINK1_INT_STATUS1 }, 144 { RMIXL_PCIE_LINK2_INT_STATUS0, RMIXL_PCIE_LINK2_INT_STATUS1 }, 145 { RMIXL_PCIE_LINK3_INT_STATUS0, RMIXL_PCIE_LINK3_INT_STATUS1 }, 146 }; 147 148 static const u_int msi_enb_offset[4] = { 149 RMIXL_PCIE_LINK0_MSI_ENABLE, 150 RMIXL_PCIE_LINK1_MSI_ENABLE, 151 RMIXL_PCIE_LINK2_MSI_ENABLE, 152 RMIXL_PCIE_LINK3_MSI_ENABLE 153 }; 154 155 #define RMIXL_PCIE_LINK_STATUS0_ERRORS __BITS(6,4) 156 #define RMIXL_PCIE_LINK_STATUS1_ERRORS __BITS(10,0) 157 #define RMIXL_PCIE_LINK_STATUS_ERRORS \ 158 ((((uint64_t)RMIXL_PCIE_LINK_STATUS1_ERRORS) << 32) | \ 159 (uint64_t)RMIXL_PCIE_LINK_STATUS0_ERRORS) 160 161 static int rmixl_pcie_match(device_t, cfdata_t, void *); 162 static void rmixl_pcie_attach(device_t, device_t, void *); 163 static void rmixl_pcie_init(struct rmixl_pcie_softc *); 164 static void rmixl_pcie_init_ecfg(struct rmixl_pcie_softc *); 165 static void rmixl_pcie_attach_hook(struct device *, struct device *, 166 struct pcibus_attach_args *); 167 static void rmixl_pcie_lnkcfg_4xx(rmixl_pcie_lnktab_t *, uint32_t); 168 static void rmixl_pcie_lnkcfg_408Lite(rmixl_pcie_lnktab_t *, uint32_t); 169 static void rmixl_pcie_lnkcfg_2xx(rmixl_pcie_lnktab_t *, uint32_t); 170 static void rmixl_pcie_lnkcfg_1xx(rmixl_pcie_lnktab_t *, uint32_t); 171 static void rmixl_pcie_lnkcfg(struct rmixl_pcie_softc *); 172 static void rmixl_pcie_intcfg(struct rmixl_pcie_softc *); 173 static void rmixl_pcie_errata(struct rmixl_pcie_softc *); 174 static void rmixl_conf_interrupt(void *, int, int, int, int, int *); 175 static int rmixl_pcie_bus_maxdevs(void *, int); 176 static pcitag_t rmixl_tag_to_ecfg(pcitag_t); 177 static pcitag_t rmixl_pcie_make_tag(void *, int, int, int); 178 static void rmixl_pcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 179 void rmixl_pcie_tag_print(const char *restrict, void *, pcitag_t, int, vaddr_t, u_long); 180 static int rmixl_pcie_conf_setup(struct rmixl_pcie_softc *, 181 pcitag_t, int *, bus_space_tag_t *, 182 bus_space_handle_t *); 183 static pcireg_t rmixl_pcie_conf_read(void *, pcitag_t, int); 184 static void rmixl_pcie_conf_write(void *, pcitag_t, int, pcireg_t); 185 186 static int rmixl_pcie_intr_map(struct pci_attach_args *, 187 pci_intr_handle_t *); 188 static const char * 189 rmixl_pcie_intr_string(void *, pci_intr_handle_t); 190 static const struct evcnt * 191 rmixl_pcie_intr_evcnt(void *, pci_intr_handle_t); 192 static pci_intr_handle_t 193 rmixl_pcie_make_pih(u_int, u_int, u_int); 194 static void rmixl_pcie_decompose_pih(pci_intr_handle_t, u_int *, u_int *, u_int *); 195 static void rmixl_pcie_intr_disestablish(void *, void *); 196 static void *rmixl_pcie_intr_establish(void *, pci_intr_handle_t, 197 int, int (*)(void *), void *); 198 static int rmixl_pcie_intr(void *); 199 static void rmixl_pcie_link_error_intr(u_int, uint32_t, uint32_t); 200 #if defined(DEBUG) || defined(DDB) 201 int rmixl_pcie_error_check(void); 202 #endif 203 static int _rmixl_pcie_error_check(void *); 204 static int rmixl_pcie_error_intr(void *); 205 206 /* 207 * XXX use locks 208 */ 209 #define PCI_CONF_LOCK(s) (s) = splhigh() 210 #define PCI_CONF_UNLOCK(s) splx((s)) 211 212 213 #define RMIXL_PCIE_CONCAT3(a,b,c) a ## b ## c 214 #define RMIXL_PCIE_BAR_INIT(reg, bar, size, align) { \ 215 struct extent *ext = rmixl_configuration.rc_phys_ex; \ 216 u_long region_start; \ 217 uint64_t ba; \ 218 int err; \ 219 \ 220 err = extent_alloc(ext, (size), (align), 0UL, EX_NOWAIT, \ 221 ®ion_start); \ 222 if (err != 0) \ 223 panic("%s: extent_alloc(%p, %#lx, %#lx, %#lx, %#x, %p)",\ 224 __func__, ext, size, align, 0UL, EX_NOWAIT, \ 225 ®ion_start); \ 226 ba = (uint64_t)region_start; \ 227 ba *= (1024 * 1024); \ 228 bar = RMIXL_PCIE_CONCAT3(RMIXL_PCIE_,reg,_BAR)(ba, 1); \ 229 DPRINTF(("PCIE %s BAR was not enabled by firmware\n" \ 230 "enabling %s at phys %#" PRIxBUSADDR ", size %lu MB\n", \ 231 __STRING(reg), __STRING(reg), ba, size)); \ 232 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_BRIDGE + \ 233 RMIXL_PCIE_CONCAT3(RMIXL_SBC_PCIE_,reg,_BAR), bar); \ 234 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + \ 235 RMIXL_PCIE_CONCAT3(RMIXL_SBC_PCIE_,reg,_BAR)); \ 236 DPRINTF(("%s: %s BAR %#x\n", __func__, __STRING(reg), bar)); \ 237 } 238 239 240 #if defined(DEBUG) || defined(DDB) 241 static void *rmixl_pcie_v; 242 #endif 243 244 CFATTACH_DECL_NEW(rmixl_pcie, sizeof(struct rmixl_pcie_softc), 245 rmixl_pcie_match, rmixl_pcie_attach, NULL, NULL); 246 247 static int rmixl_pcie_found; 248 249 static int 250 rmixl_pcie_match(device_t parent, cfdata_t cf, void *aux) 251 { 252 uint32_t r; 253 254 /* XXX 255 * for now there is only one PCIe Interface on chip 256 * this could change with furture RMI XL family designs 257 */ 258 if (rmixl_pcie_found) 259 return 0; 260 261 /* read GPIO Reset Configuration register */ 262 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET_CFG); 263 r >>= 26; 264 r &= 3; 265 if (r != 0) 266 return 0; /* strapped for SRIO */ 267 268 return 1; 269 } 270 271 static void 272 rmixl_pcie_attach(device_t parent, device_t self, void *aux) 273 { 274 struct rmixl_pcie_softc *sc = device_private(self); 275 struct obio_attach_args *obio = aux; 276 struct rmixl_config *rcp = &rmixl_configuration; 277 struct pcibus_attach_args pba; 278 uint32_t bar; 279 280 rmixl_pcie_found = 1; 281 sc->sc_dev = self; 282 283 aprint_normal(" RMI XLS PCIe Interface\n"); 284 285 rmixl_pcie_lnkcfg(sc); 286 287 rmixl_pcie_intcfg(sc); 288 289 rmixl_pcie_errata(sc); 290 291 sc->sc_29bit_dmat = obio->obio_29bit_dmat; 292 sc->sc_32bit_dmat = obio->obio_32bit_dmat; 293 sc->sc_64bit_dmat = obio->obio_64bit_dmat; 294 295 sc->sc_tmsk = obio->obio_tmsk; 296 297 /* 298 * get PCI config space base addr from SBC PCIe CFG BAR 299 * initialize it if necessary 300 */ 301 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXL_SBC_PCIE_CFG_BAR); 302 DPRINTF(("%s: PCIE_CFG_BAR %#x\n", __func__, bar)); 303 if ((bar & RMIXL_PCIE_CFG_BAR_ENB) == 0) { 304 u_long n = RMIXL_PCIE_CFG_SIZE / (1024 * 1024); 305 RMIXL_PCIE_BAR_INIT(CFG, bar, n, n); 306 } 307 rcp->rc_pcie_cfg_pbase = (bus_addr_t)RMIXL_PCIE_CFG_BAR_TO_BA(bar); 308 rcp->rc_pcie_cfg_size = (bus_size_t)RMIXL_PCIE_CFG_SIZE; 309 310 /* 311 * get PCIE Extended config space base addr from SBC PCIe ECFG BAR 312 * initialize it if necessary 313 */ 314 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXL_SBC_PCIE_ECFG_BAR); 315 DPRINTF(("%s: PCIE_ECFG_BAR %#x\n", __func__, bar)); 316 if ((bar & RMIXL_PCIE_ECFG_BAR_ENB) == 0) { 317 u_long n = RMIXL_PCIE_ECFG_SIZE / (1024 * 1024); 318 RMIXL_PCIE_BAR_INIT(ECFG, bar, n, n); 319 } 320 rcp->rc_pcie_ecfg_pbase = (bus_addr_t)RMIXL_PCIE_ECFG_BAR_TO_BA(bar); 321 rcp->rc_pcie_ecfg_size = (bus_size_t)RMIXL_PCIE_ECFG_SIZE; 322 323 /* 324 * get PCI MEM space base [addr, size] from SBC PCIe MEM BAR 325 * initialize it if necessary 326 */ 327 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXL_SBC_PCIE_MEM_BAR); 328 DPRINTF(("%s: PCIE_MEM_BAR %#x\n", __func__, bar)); 329 if ((bar & RMIXL_PCIE_MEM_BAR_ENB) == 0) { 330 u_long n = 256; /* 256 MB */ 331 RMIXL_PCIE_BAR_INIT(MEM, bar, n, n); 332 } 333 rcp->rc_pci_mem_pbase = (bus_addr_t)RMIXL_PCIE_MEM_BAR_TO_BA(bar); 334 rcp->rc_pci_mem_size = (bus_size_t)RMIXL_PCIE_MEM_BAR_TO_SIZE(bar); 335 336 /* 337 * get PCI IO space base [addr, size] from SBC PCIe IO BAR 338 * initialize it if necessary 339 */ 340 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXL_SBC_PCIE_IO_BAR); 341 DPRINTF(("%s: PCIE_IO_BAR %#x\n", __func__, bar)); 342 if ((bar & RMIXL_PCIE_IO_BAR_ENB) == 0) { 343 u_long n = 32; /* 32 MB */ 344 RMIXL_PCIE_BAR_INIT(IO, bar, n, n); 345 } 346 rcp->rc_pci_io_pbase = (bus_addr_t)RMIXL_PCIE_IO_BAR_TO_BA(bar); 347 rcp->rc_pci_io_size = (bus_size_t)RMIXL_PCIE_IO_BAR_TO_SIZE(bar); 348 349 /* 350 * initialize the PCI CFG, ECFG bus space tags 351 */ 352 rmixl_pcie_cfg_bus_mem_init(&rcp->rc_pcie_cfg_memt, rcp); 353 sc->sc_pcie_cfg_memt = &rcp->rc_pcie_cfg_memt; 354 355 rmixl_pcie_ecfg_bus_mem_init(&rcp->rc_pcie_ecfg_memt, rcp); 356 sc->sc_pcie_ecfg_memt = &rcp->rc_pcie_ecfg_memt; 357 358 /* 359 * initialize the PCI MEM and IO bus space tags 360 */ 361 rmixl_pcie_bus_mem_init(&rcp->rc_pci_memt, rcp); 362 rmixl_pcie_bus_io_init(&rcp->rc_pci_iot, rcp); 363 364 /* 365 * initialize the extended configuration regs 366 */ 367 rmixl_pcie_init_ecfg(sc); 368 369 /* 370 * initialize the PCI chipset tag 371 */ 372 rmixl_pcie_init(sc); 373 374 /* 375 * attach the PCI bus 376 */ 377 memset(&pba, 0, sizeof(pba)); 378 pba.pba_memt = &rcp->rc_pci_memt; 379 pba.pba_iot = &rcp->rc_pci_iot; 380 pba.pba_dmat = sc->sc_32bit_dmat; 381 pba.pba_dmat64 = sc->sc_64bit_dmat; 382 pba.pba_pc = &sc->sc_pci_chipset; 383 pba.pba_bus = 0; 384 pba.pba_bridgetag = NULL; 385 pba.pba_intrswiz = 0; 386 pba.pba_intrtag = 0; 387 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 388 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 389 390 (void) config_found_ia(self, "pcibus", &pba, pcibusprint); 391 } 392 393 /* 394 * rmixl_pcie_lnkcfg_4xx - link configs for XLS4xx and XLS6xx 395 * use IO_AD[11] and IO_AD[10], observable in 396 * Bits[21:20] of the GPIO Reset Configuration register 397 */ 398 static void 399 rmixl_pcie_lnkcfg_4xx(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 400 { 401 u_int index; 402 static const rmixl_pcie_lnkcfg_t lnktab_4xx[4][4] = { 403 {{ LCFG_EP, 4}, {LCFG_NO, 0}, {LCFG_NO, 0}, {LCFG_NO, 0}}, 404 {{ LCFG_RC, 4}, {LCFG_NO, 0}, {LCFG_NO, 0}, {LCFG_NO, 0}}, 405 {{ LCFG_EP, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}}, 406 {{ LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}}, 407 }; 408 static const char *lnkstr_4xx[4] = { 409 "1EPx4", 410 "1RCx4", 411 "1EPx1, 3RCx1", 412 "4RCx1" 413 }; 414 index = (grcr >> 20) & 3; 415 ltp->ncfgs = 4; 416 ltp->cfg = lnktab_4xx[index]; 417 ltp->str = lnkstr_4xx[index]; 418 } 419 420 /* 421 * rmixl_pcie_lnkcfg_408Lite - link configs for XLS408Lite and XLS04A 422 * use IO_AD[11] and IO_AD[10], observable in 423 * Bits[21:20] of the GPIO Reset Configuration register 424 */ 425 static void 426 rmixl_pcie_lnkcfg_408Lite(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 427 { 428 u_int index; 429 static const rmixl_pcie_lnkcfg_t lnktab_408Lite[4][2] = { 430 {{ LCFG_EP, 4}, {LCFG_NO, 0}}, 431 {{ LCFG_RC, 4}, {LCFG_NO, 0}}, 432 {{ LCFG_EP, 1}, {LCFG_RC, 1}}, 433 {{ LCFG_RC, 1}, {LCFG_RC, 1}}, 434 }; 435 static const char *lnkstr_408Lite[4] = { 436 "4EPx4", 437 "1RCx4", 438 "1EPx1, 1RCx1", 439 "2RCx1" 440 }; 441 442 index = (grcr >> 20) & 3; 443 ltp->ncfgs = 2; 444 ltp->cfg = lnktab_408Lite[index]; 445 ltp->str = lnkstr_408Lite[index]; 446 } 447 448 /* 449 * rmixl_pcie_lnkcfg_2xx - link configs for XLS2xx 450 * use IO_AD[10], observable in Bit[20] of the 451 * GPIO Reset Configuration register 452 */ 453 static void 454 rmixl_pcie_lnkcfg_2xx(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 455 { 456 u_int index; 457 static const rmixl_pcie_lnkcfg_t lnktab_2xx[2][4] = { 458 {{ LCFG_EP, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}}, 459 {{ LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}} 460 }; 461 static const char *lnkstr_2xx[2] = { 462 "1EPx1, 3RCx1", 463 "4RCx1", 464 }; 465 466 index = (grcr >> 20) & 1; 467 ltp->ncfgs = 4; 468 ltp->cfg = lnktab_2xx[index]; 469 ltp->str = lnkstr_2xx[index]; 470 } 471 472 /* 473 * rmixl_pcie_lnkcfg_1xx - link configs for XLS1xx 474 * use IO_AD[10], observable in Bit[20] of the 475 * GPIO Reset Configuration register 476 */ 477 static void 478 rmixl_pcie_lnkcfg_1xx(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 479 { 480 u_int index; 481 static const rmixl_pcie_lnkcfg_t lnktab_1xx[2][2] = { 482 {{ LCFG_EP, 1}, {LCFG_RC, 1}}, 483 {{ LCFG_RC, 1}, {LCFG_RC, 1}} 484 }; 485 static const char *lnkstr_1xx[2] = { 486 "1EPx1, 1RCx1", 487 "2RCx1", 488 }; 489 490 index = (grcr >> 20) & 1; 491 ltp->ncfgs = 2; 492 ltp->cfg = lnktab_1xx[index]; 493 ltp->str = lnkstr_1xx[index]; 494 } 495 496 /* 497 * rmixl_pcie_lnkcfg - determine PCI Express Link Configuration 498 */ 499 static void 500 rmixl_pcie_lnkcfg(struct rmixl_pcie_softc *sc) 501 { 502 uint32_t r; 503 504 /* read GPIO Reset Configuration register */ 505 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET_CFG); 506 DPRINTF(("%s: GPIO RCR %#x\n", __func__, r)); 507 508 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 509 case MIPS_XLS104: 510 case MIPS_XLS108: 511 rmixl_pcie_lnkcfg_1xx(&sc->sc_pcie_lnktab, r); 512 break; 513 case MIPS_XLS204: 514 case MIPS_XLS208: 515 rmixl_pcie_lnkcfg_2xx(&sc->sc_pcie_lnktab, r); 516 break; 517 case MIPS_XLS404LITE: 518 case MIPS_XLS408LITE: 519 rmixl_pcie_lnkcfg_408Lite(&sc->sc_pcie_lnktab, r); 520 break; 521 case MIPS_XLS404: 522 case MIPS_XLS408: 523 case MIPS_XLS416: 524 case MIPS_XLS608: 525 case MIPS_XLS616: 526 /* 6xx uses same table as 4xx */ 527 rmixl_pcie_lnkcfg_4xx(&sc->sc_pcie_lnktab, r); 528 break; 529 default: 530 panic("%s: unknown RMI PRID IMPL", __func__); 531 } 532 533 aprint_normal("%s: link config %s\n", 534 device_xname(sc->sc_dev), sc->sc_pcie_lnktab.str); 535 } 536 537 /* 538 * rmixl_pcie_intcfg - init PCIe Link interrupt enables 539 */ 540 static void 541 rmixl_pcie_intcfg(struct rmixl_pcie_softc *sc) 542 { 543 rmixl_pcie_link_intr_t *lip; 544 int link; 545 546 DPRINTF(("%s: disable all link interrupts\n", __func__)); 547 for (link=0; link < sc->sc_pcie_lnktab.ncfgs; link++) { 548 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + int_enb_offset[link].r0, 549 RMIXL_PCIE_LINK_STATUS0_ERRORS); 550 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + int_enb_offset[link].r1, 551 RMIXL_PCIE_LINK_STATUS1_ERRORS); 552 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + msi_enb_offset[link], 0); 553 lip = &sc->sc_link_intr[link]; 554 LIST_INIT(&lip->dispatch); 555 lip->ih = NULL; 556 lip->link = link; 557 lip->enabled = false; 558 } 559 } 560 561 static void 562 rmixl_pcie_errata(struct rmixl_pcie_softc *sc) 563 { 564 const mips_prid_t cpu_id = mips_options.mips_cpu_id; 565 u_int rev; 566 u_int lanes; 567 bool e391 = false; 568 569 /* 570 * 3.9.1 PCIe Link-0 Registers Reset to Incorrect Values 571 * check if it allies to this CPU implementation and revision 572 */ 573 rev = MIPS_PRID_REV(cpu_id); 574 switch (MIPS_PRID_IMPL(cpu_id)) { 575 case MIPS_XLS104: 576 case MIPS_XLS108: 577 break; 578 case MIPS_XLS204: 579 case MIPS_XLS208: 580 /* stepping A0 is affected */ 581 if (rev == 0) 582 e391 = true; 583 break; 584 case MIPS_XLS404LITE: 585 case MIPS_XLS408LITE: 586 break; 587 case MIPS_XLS404: 588 case MIPS_XLS408: 589 case MIPS_XLS416: 590 /* steppings A0 and A1 are affected */ 591 if ((rev == 0) || (rev == 1)) 592 e391 = true; 593 break; 594 case MIPS_XLS608: 595 case MIPS_XLS616: 596 break; 597 default: 598 panic("unknown RMI PRID IMPL"); 599 } 600 601 /* 602 * for XLS we only need to check entry #0 603 * this may need to change for later XL family chips 604 */ 605 lanes = sc->sc_pcie_lnktab.cfg[0].lanes; 606 607 if ((e391 != false) && ((lanes == 2) || (lanes == 4))) { 608 /* 609 * attempt work around for errata 3.9.1 610 * "PCIe Link-0 Registers Reset to Incorrect Values" 611 * the registers are write-once: if the firmware already wrote, 612 * then our writes are ignored; hope they did it right. 613 */ 614 uint32_t queuectrl; 615 uint32_t bufdepth; 616 #ifdef DIAGNOSTIC 617 uint32_t r; 618 #endif 619 620 aprint_normal("%s: attempt work around for errata 3.9.1", 621 device_xname(sc->sc_dev)); 622 if (lanes == 4) { 623 queuectrl = 0x00018074; 624 bufdepth = 0x001901D1; 625 } else { 626 queuectrl = 0x00018036; 627 bufdepth = 0x001900D9; 628 } 629 630 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_BE + 631 RMIXL_VC0_POSTED_RX_QUEUE_CTRL, queuectrl); 632 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_BE + 633 RMIXL_VC0_POSTED_BUFFER_DEPTH, bufdepth); 634 635 #ifdef DIAGNOSTIC 636 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_BE + 637 RMIXL_VC0_POSTED_RX_QUEUE_CTRL); 638 printf("\nVC0_POSTED_RX_QUEUE_CTRL %#x\n", r); 639 640 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_BE + 641 RMIXL_VC0_POSTED_BUFFER_DEPTH); 642 printf("VC0_POSTED_BUFFER_DEPTH %#x\n", r); 643 #endif 644 } 645 } 646 647 static void 648 rmixl_pcie_init(struct rmixl_pcie_softc *sc) 649 { 650 pci_chipset_tag_t pc = &sc->sc_pci_chipset; 651 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 652 struct extent *ioext, *memext; 653 #endif 654 655 pc->pc_conf_v = (void *)sc; 656 pc->pc_attach_hook = rmixl_pcie_attach_hook; 657 pc->pc_bus_maxdevs = rmixl_pcie_bus_maxdevs; 658 pc->pc_make_tag = rmixl_pcie_make_tag; 659 pc->pc_decompose_tag = rmixl_pcie_decompose_tag; 660 pc->pc_conf_read = rmixl_pcie_conf_read; 661 pc->pc_conf_write = rmixl_pcie_conf_write; 662 663 pc->pc_intr_v = (void *)sc; 664 pc->pc_intr_map = rmixl_pcie_intr_map; 665 pc->pc_intr_string = rmixl_pcie_intr_string; 666 pc->pc_intr_evcnt = rmixl_pcie_intr_evcnt; 667 pc->pc_intr_establish = rmixl_pcie_intr_establish; 668 pc->pc_intr_disestablish = rmixl_pcie_intr_disestablish; 669 pc->pc_conf_interrupt = rmixl_conf_interrupt; 670 671 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 672 /* 673 * Configure the PCI bus. 674 */ 675 struct rmixl_config *rcp = &rmixl_configuration; 676 677 aprint_normal("%s: configuring PCI bus\n", 678 device_xname(sc->sc_dev)); 679 680 ioext = extent_create("pciio", 681 rcp->rc_pci_io_pbase, 682 rcp->rc_pci_io_pbase + rcp->rc_pci_io_size - 1, 683 M_DEVBUF, NULL, 0, EX_NOWAIT); 684 685 memext = extent_create("pcimem", 686 rcp->rc_pci_mem_pbase, 687 rcp->rc_pci_mem_pbase + rcp->rc_pci_mem_size - 1, 688 M_DEVBUF, NULL, 0, EX_NOWAIT); 689 690 pci_configure_bus(pc, ioext, memext, NULL, 0, 691 mips_cache_info.mci_dcache_align); 692 693 extent_destroy(ioext); 694 extent_destroy(memext); 695 #endif 696 } 697 698 static void 699 rmixl_pcie_init_ecfg(struct rmixl_pcie_softc *sc) 700 { 701 void *v; 702 pcitag_t tag; 703 pcireg_t r; 704 705 v = sc; 706 tag = rmixl_pcie_make_tag(v, 0, 0, 0); 707 708 #ifdef PCI_DEBUG 709 int i, offset; 710 static const int offtab[] = 711 { 0, 4, 8, 0xc, 0x10, 0x14, 0x18, 0x1c, 712 0x2c, 0x30, 0x34 }; 713 for (i=0; i < sizeof(offtab)/sizeof(offtab[0]); i++) { 714 offset = 0x100 + offtab[i]; 715 r = rmixl_pcie_conf_read(v, tag, offset); 716 printf("%s: %#x: %#x\n", __func__, offset, r); 717 } 718 #endif 719 r = rmixl_pcie_conf_read(v, tag, 0x100); 720 if (r == -1) 721 return; /* cannot access */ 722 723 /* check pre-existing uncorrectable errs */ 724 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_UESR); 725 r &= ~PCIE_ECFG_UExR_RESV; 726 if (r != 0) 727 panic("%s: Uncorrectable Error Status: %#x\n", 728 __func__, r); 729 730 /* unmask all uncorrectable errs */ 731 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_UEMR); 732 r &= ~PCIE_ECFG_UExR_RESV; 733 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_UEMR, r); 734 735 /* ensure default uncorrectable err severity confniguration */ 736 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_UEVR); 737 r &= ~PCIE_ECFG_UExR_RESV; 738 r |= PCIE_ECFG_UEVR_DFLT; 739 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_UEVR, r); 740 741 /* check pre-existing correctable errs */ 742 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_CESR); 743 r &= ~PCIE_ECFG_CExR_RESV; 744 #ifdef DIAGNOSTIC 745 if (r != 0) 746 aprint_normal("%s: Correctable Error Status: %#x\n", 747 device_xname(sc->sc_dev), r); 748 #endif 749 750 /* unmask all correctable errs */ 751 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_CEMR); 752 r &= ~PCIE_ECFG_CExR_RESV; 753 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_UEMR, r); 754 755 /* check pre-existing Root Error Status */ 756 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_RESR); 757 r &= ~PCIE_ECFG_RESR_RESV; 758 if (r != 0) 759 panic("%s: Root Error Status: %#x\n", __func__, r); 760 /* XXX TMP FIXME */ 761 762 /* enable all Root errs */ 763 r = (pcireg_t)(~PCIE_ECFG_RECR_RESV); 764 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_RECR, r); 765 766 /* 767 * establish ISR for PCIE Fatal Error interrupt 768 * - for XLS4xxLite, XLS2xx, XLS1xx only 769 */ 770 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 771 case MIPS_XLS104: 772 case MIPS_XLS108: 773 case MIPS_XLS204: 774 case MIPS_XLS208: 775 case MIPS_XLS404LITE: 776 case MIPS_XLS408LITE: 777 sc->sc_fatal_ih = rmixl_intr_establish(29, sc->sc_tmsk, 778 IPL_HIGH, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH, 779 rmixl_pcie_error_intr, v); 780 break; 781 default: 782 break; 783 } 784 785 #if defined(DEBUG) || defined(DDB) 786 rmixl_pcie_v = v; 787 #endif 788 } 789 790 void 791 rmixl_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *iline) 792 { 793 DPRINTF(("%s: %p, %d, %d, %d, %d, %p\n", 794 __func__, v, bus, dev, ipin, swiz, iline)); 795 } 796 797 void 798 rmixl_pcie_attach_hook(struct device *parent, struct device *self, 799 struct pcibus_attach_args *pba) 800 { 801 DPRINTF(("%s: pba_bus %d, pba_bridgetag %p, pc_conf_v %p\n", 802 __func__, pba->pba_bus, pba->pba_bridgetag, 803 pba->pba_pc->pc_conf_v)); 804 } 805 806 int 807 rmixl_pcie_bus_maxdevs(void *v, int busno) 808 { 809 return (32); /* XXX depends on the family of XLS SoC */ 810 } 811 812 /* 813 * rmixl_tag_to_ecfg - convert cfg address (generic tag) to ecfg address 814 * 815 * 39:29 (reserved) 816 * 28 Swap (0=little, 1=big endian) 817 * 27:20 Bus number 818 * 19:15 Device number 819 * 14:12 Function number 820 * 11:8 Extended Register number 821 * 7:0 Register number 822 */ 823 static pcitag_t 824 rmixl_tag_to_ecfg(pcitag_t tag) 825 { 826 KASSERT((tag & __BITS(7,0)) == 0); 827 return (tag << 4); 828 } 829 830 /* 831 * XLS pci tag is a 40 bit address composed thusly: 832 * 39:25 (reserved) 833 * 24 Swap (0=little, 1=big endian) 834 * 23:16 Bus number 835 * 15:11 Device number 836 * 10:8 Function number 837 * 7:0 Register number 838 * 839 * Note: this is the "native" composition for addressing CFG space, but not for ECFG space. 840 */ 841 pcitag_t 842 rmixl_pcie_make_tag(void *v, int bus, int dev, int fun) 843 { 844 return ((bus << 16) | (dev << 11) | (fun << 8)); 845 } 846 847 void 848 rmixl_pcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 849 { 850 if (bp != NULL) 851 *bp = (tag >> 16) & 0xff; 852 if (dp != NULL) 853 *dp = (tag >> 11) & 0x1f; 854 if (fp != NULL) 855 *fp = (tag >> 8) & 0x7; 856 } 857 858 void 859 rmixl_pcie_tag_print(const char *restrict s, void *v, pcitag_t tag, int offset, 860 vaddr_t va, u_long r) 861 { 862 int bus, dev, fun; 863 864 rmixl_pcie_decompose_tag(v, tag, &bus, &dev, &fun); 865 printf("%s: %d/%d/%d/%d - %#" PRIxVADDR ":%#lx\n", 866 s, bus, dev, fun, offset, va, r); 867 } 868 869 static int 870 rmixl_pcie_conf_setup(struct rmixl_pcie_softc *sc, 871 pcitag_t tag, int *offp, bus_space_tag_t *bstp, 872 bus_space_handle_t *bshp) 873 { 874 struct rmixl_config *rcp = &rmixl_configuration; 875 bus_space_tag_t bst; 876 bus_space_handle_t bsh; 877 bus_size_t size; 878 pcitag_t mask; 879 bus_addr_t ba; 880 int err; 881 static bus_space_handle_t cfg_bsh; 882 static bus_addr_t cfg_oba = -1; 883 static bus_space_handle_t ecfg_bsh; 884 static bus_addr_t ecfg_oba = -1; 885 886 /* 887 * bus space depends on offset 888 */ 889 if ((*offp >= 0) && (*offp < 0x100)) { 890 mask = __BITS(15,0); 891 bst = sc->sc_pcie_cfg_memt; 892 ba = rcp->rc_pcie_cfg_pbase; 893 ba += (tag & ~mask); 894 *offp += (tag & mask); 895 if (ba != cfg_oba) { 896 size = (bus_size_t)(mask + 1); 897 if (cfg_oba != -1) 898 bus_space_unmap(bst, cfg_bsh, size); 899 err = bus_space_map(bst, ba, size, 0, &cfg_bsh); 900 if (err != 0) { 901 #ifdef DEBUG 902 panic("%s: bus_space_map err %d, CFG space", 903 __func__, err); /* XXX */ 904 #endif 905 return -1; 906 } 907 cfg_oba = ba; 908 } 909 bsh = cfg_bsh; 910 } else if ((*offp >= 0x100) && (*offp <= 0x700)) { 911 mask = __BITS(14,0); 912 tag = rmixl_tag_to_ecfg(tag); /* convert to ECFG format */ 913 bst = sc->sc_pcie_ecfg_memt; 914 ba = rcp->rc_pcie_ecfg_pbase; 915 ba += (tag & ~mask); 916 *offp += (tag & mask); 917 if (ba != ecfg_oba) { 918 size = (bus_size_t)(mask + 1); 919 if (ecfg_oba != -1) 920 bus_space_unmap(bst, ecfg_bsh, size); 921 err = bus_space_map(bst, ba, size, 0, &ecfg_bsh); 922 if (err != 0) { 923 #ifdef DEBUG 924 panic("%s: bus_space_map err %d, ECFG space", 925 __func__, err); /* XXX */ 926 #endif 927 return -1; 928 } 929 ecfg_oba = ba; 930 } 931 bsh = ecfg_bsh; 932 } else { 933 #ifdef DEBUG 934 panic("%s: offset %#x: unknown", __func__, *offp); 935 #endif 936 return -1; 937 } 938 939 *bstp = bst; 940 *bshp = bsh; 941 942 return 0; 943 } 944 945 pcireg_t 946 rmixl_pcie_conf_read(void *v, pcitag_t tag, int offset) 947 { 948 struct rmixl_pcie_softc *sc = v; 949 static bus_space_handle_t bsh; 950 bus_space_tag_t bst; 951 pcireg_t rv; 952 uint64_t cfg0; 953 u_int s; 954 955 PCI_CONF_LOCK(s); 956 957 if (rmixl_pcie_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) { 958 cfg0 = rmixl_cache_err_dis(); 959 rv = bus_space_read_4(bst, bsh, (bus_size_t)offset); 960 if (rmixl_cache_err_check() != 0) { 961 #ifdef DIAGNOSTIC 962 int bus, dev, fun; 963 964 rmixl_pcie_decompose_tag(v, tag, &bus, &dev, &fun); 965 printf("%s: %d/%d/%d, offset %#x: bad address\n", 966 __func__, bus, dev, fun, offset); 967 #endif 968 rv = (pcireg_t) -1; 969 } 970 rmixl_cache_err_restore(cfg0); 971 } else { 972 rv = -1; 973 } 974 975 PCI_CONF_UNLOCK(s); 976 return rv; 977 } 978 979 void 980 rmixl_pcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 981 { 982 struct rmixl_pcie_softc *sc = v; 983 static bus_space_handle_t bsh; 984 bus_space_tag_t bst; 985 uint64_t cfg0; 986 u_int s; 987 988 PCI_CONF_LOCK(s); 989 990 if (rmixl_pcie_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) { 991 cfg0 = rmixl_cache_err_dis(); 992 bus_space_write_4(bst, bsh, (bus_size_t)offset, val); 993 if (rmixl_cache_err_check() != 0) { 994 #ifdef DIAGNOSTIC 995 int bus, dev, fun; 996 997 rmixl_pcie_decompose_tag(v, tag, &bus, &dev, &fun); 998 printf("%s: %d/%d/%d, offset %#x: bad address\n", 999 __func__, bus, dev, fun, offset); 1000 #endif 1001 } 1002 rmixl_cache_err_restore(cfg0); 1003 } 1004 1005 PCI_CONF_UNLOCK(s); 1006 } 1007 1008 int 1009 rmixl_pcie_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *pih) 1010 { 1011 u_int link; 1012 u_int irq; 1013 1014 #ifdef DEBUG 1015 DPRINTF(("%s: ps_bus %d, pa_intrswiz %#x, pa_intrtag %#lx," 1016 " pa_intrpin %d, pa_intrline %d, pa_rawintrpin %d\n", 1017 __func__, pa->pa_bus, pa->pa_intrswiz, pa->pa_intrtag, 1018 pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 1019 #endif 1020 1021 /* 1022 * PCIe Link INT irq assignment is cpu implementation specific 1023 */ 1024 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 1025 case MIPS_XLS104: 1026 case MIPS_XLS108: 1027 case MIPS_XLS204: 1028 case MIPS_XLS208: 1029 case MIPS_XLS404LITE: 1030 case MIPS_XLS408LITE: 1031 switch (pa->pa_bus) { 1032 case 1: 1033 link = 0; 1034 irq = 26; 1035 break; 1036 case 2: 1037 link = 1; 1038 irq = 27; 1039 break; 1040 default: 1041 panic("%s: bad bus %d\n", __func__, pa->pa_bus); 1042 } 1043 break; 1044 case MIPS_XLS404: 1045 case MIPS_XLS408: 1046 case MIPS_XLS416: 1047 case MIPS_XLS608: 1048 case MIPS_XLS616: 1049 switch (pa->pa_bus) { 1050 case 1: 1051 link = 0; 1052 irq = 26; 1053 break; 1054 case 2: 1055 link = 1; 1056 irq = 27; 1057 break; 1058 case 3: 1059 link = 2; 1060 irq = 28; 1061 break; 1062 case 4: 1063 link = 3; 1064 irq = 29; 1065 break; 1066 default: 1067 panic("%s: bad bus %d\n", __func__, pa->pa_bus); 1068 } 1069 break; 1070 default: 1071 panic("%s: cpu IMPL %#x not supported\n", 1072 __func__, MIPS_PRID_IMPL(mips_options.mips_cpu_id)); 1073 } 1074 1075 if (pa->pa_intrpin != PCI_INTERRUPT_PIN_NONE) 1076 *pih = rmixl_pcie_make_pih(link, pa->pa_intrpin - 1, irq); 1077 else 1078 *pih = ~0; 1079 1080 return 0; 1081 } 1082 1083 const char * 1084 rmixl_pcie_intr_string(void *v, pci_intr_handle_t pih) 1085 { 1086 const char *name = "(illegal)"; 1087 int irq = (int)pih; 1088 1089 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 1090 case MIPS_XLS104: 1091 case MIPS_XLS108: 1092 case MIPS_XLS204: 1093 case MIPS_XLS208: 1094 case MIPS_XLS404LITE: 1095 case MIPS_XLS408LITE: 1096 switch (irq) { 1097 case 26: 1098 case 27: 1099 name = rmixl_intr_string(irq); 1100 break; 1101 } 1102 break; 1103 case MIPS_XLS404: 1104 case MIPS_XLS408: 1105 case MIPS_XLS416: 1106 case MIPS_XLS608: 1107 case MIPS_XLS616: 1108 switch (irq) { 1109 case 26: 1110 case 27: 1111 case 28: 1112 case 29: 1113 name = rmixl_intr_string(irq); 1114 break; 1115 } 1116 break; 1117 default: 1118 panic("%s: cpu IMPL %#x not supported\n", 1119 __func__, MIPS_PRID_IMPL(mips_options.mips_cpu_id)); 1120 } 1121 1122 return name; 1123 } 1124 1125 const struct evcnt * 1126 rmixl_pcie_intr_evcnt(void *v, pci_intr_handle_t pih) 1127 { 1128 return NULL; 1129 } 1130 1131 static pci_intr_handle_t 1132 rmixl_pcie_make_pih(u_int link, u_int bitno, u_int irq) 1133 { 1134 pci_intr_handle_t pih; 1135 1136 KASSERT((link >= 0) && (link < RMIXL_PCIE_NLINKS_MAX)); 1137 KASSERT((bitno >= 0) && (bitno < 64)); 1138 KASSERT((irq >= 0) && (irq < 31)); 1139 1140 pih = (irq << 10); 1141 pih |= (bitno << 4); 1142 pih |= link; 1143 1144 return pih; 1145 } 1146 1147 static void 1148 rmixl_pcie_decompose_pih(pci_intr_handle_t pih, u_int *link, u_int *bitno, u_int *irq) 1149 { 1150 *link = (u_int)(pih & 0xf); 1151 *bitno = (u_int)((pih >> 4) & 0x3f); 1152 *irq = (u_int)(pih >> 10); 1153 1154 KASSERT((*link >= 0) && (*link < RMIXL_PCIE_NLINKS_MAX)); 1155 KASSERT((*bitno >= 0) && (*bitno < 64)); 1156 KASSERT((*irq >= 0) && (*irq < 31)); 1157 } 1158 1159 static void 1160 rmixl_pcie_intr_disestablish(void *v, void *ih) 1161 { 1162 rmixl_pcie_softc_t *sc = v; 1163 rmixl_pcie_link_dispatch_t *dip = ih; 1164 rmixl_pcie_link_intr_t *lip = &sc->sc_link_intr[dip->link];; 1165 uint32_t r; 1166 uint32_t bit; 1167 u_int offset; 1168 u_int other; 1169 1170 DPRINTF(("%s: link=%d pin=%d irq=%d\n", 1171 __func__, dip->link, dip->bitno + 1, dip->irq)); 1172 LIST_REMOVE(dip, next); 1173 1174 rmixl_intr_disestablish(lip->ih); 1175 1176 if (dip->bitno < 32) { 1177 bit = 1 << dip->bitno; 1178 offset = int_enb_offset[dip->link].r0; 1179 other = int_enb_offset[dip->link].r1; 1180 } else { 1181 bit = 1 << (dip->bitno - 32); 1182 offset = int_enb_offset[dip->link].r1; 1183 other = int_enb_offset[dip->link].r1; 1184 } 1185 1186 /* disable this interrupt in the PCIe bridge */ 1187 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + offset); 1188 r &= ~bit; 1189 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + offset, r); 1190 1191 /* 1192 * if both STATUS0 and STATUS1 are 0 1193 * mark the link interrupt disabled 1194 */ 1195 if (r == 0) { 1196 /* check the other reg */ 1197 if (RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + other) == 0) { 1198 lip->enabled = false; 1199 DPRINTF(("%s: disabled link %d\n", __func__, lip->link)); 1200 } 1201 } 1202 1203 evcnt_detach(&dip->count); 1204 1205 free(dip, M_DEVBUF); 1206 1207 } 1208 1209 static void * 1210 rmixl_pcie_intr_establish(void *v, pci_intr_handle_t pih, int ipl, 1211 int (*func)(void *), void *arg) 1212 { 1213 rmixl_pcie_softc_t *sc = v; 1214 u_int link, bitno, irq; 1215 uint32_t r; 1216 rmixl_pcie_link_intr_t *lip; 1217 rmixl_pcie_link_dispatch_t *dip; 1218 uint32_t bit; 1219 u_int offset; 1220 int s; 1221 1222 if (pih == ~0) { 1223 DPRINTF(("%s: bad pih=%#lx, implies PCI_INTERRUPT_PIN_NONE\n", 1224 __func__, pih)); 1225 return NULL; 1226 } 1227 1228 rmixl_pcie_decompose_pih(pih, &link, &bitno, &irq); 1229 DPRINTF(("%s: link=%d pin=%d irq=%d\n", __func__, link, bitno + 1, irq)); 1230 1231 lip = &sc->sc_link_intr[link]; 1232 1233 s = splhigh(); 1234 1235 #ifdef DEBUG 1236 LIST_FOREACH(dip, &lip->dispatch, next) { 1237 if (dip->bitno == bitno) 1238 panic("%s: pin %d alread on dispatch list", 1239 __func__, bitno + 1); 1240 } 1241 #endif 1242 1243 /* 1244 * all intrs on a link get same ipl and sc 1245 * first intr established sets the standard 1246 */ 1247 if (lip->enabled == true) { 1248 KASSERT(sc = lip->sc); 1249 if (sc != lip->sc) { 1250 printf("%s: sc %p mismatch\n", __func__, sc); 1251 goto out; 1252 } 1253 KASSERT(ipl = lip->ipl); 1254 if (ipl != lip->ipl) { 1255 printf("%s: ipl %d mismatch\n", __func__, ipl); 1256 goto out; 1257 } 1258 } 1259 1260 /* 1261 * allocate and initialize a dispatch handle 1262 */ 1263 dip = malloc(sizeof(*dip), M_DEVBUF, M_NOWAIT); 1264 if (dip == NULL) { 1265 printf("%s: cannot malloc dispatch handle\n", __func__); 1266 goto out; 1267 } 1268 1269 dip->link = link; 1270 dip->bitno = bitno; 1271 dip->irq = irq; 1272 dip->func = func; 1273 dip->arg = arg; 1274 snprintf(dip->count_name, sizeof(dip->count_name), 1275 "link %d, pin %d", link, bitno + 1); 1276 evcnt_attach_dynamic(&dip->count, EVCNT_TYPE_INTR, NULL, 1277 "rmixl_pcie", dip->count_name); 1278 1279 if (bitno < 32) { 1280 offset = int_enb_offset[link].r0; 1281 bit = 1 << bitno; 1282 } else { 1283 offset = int_enb_offset[link].r1; 1284 bit = 1 << (bitno - 32); 1285 } 1286 1287 /* enable this interrupt in the PCIe bridge */ 1288 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + offset); 1289 r |= bit; 1290 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + offset, r); 1291 1292 if (lip->enabled == false) { 1293 lip->ih = rmixl_intr_establish(irq, sc->sc_tmsk, 1294 ipl, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH, 1295 rmixl_pcie_intr, lip); 1296 if (lip->ih == NULL) 1297 panic("%s: cannot establish irq %d", __func__, link); 1298 1299 lip->sc = sc; 1300 lip->ipl = ipl; 1301 lip->enabled = true; 1302 DPRINTF(("%s: enabled link %d\n", __func__, link)); 1303 } 1304 LIST_INSERT_HEAD(&lip->dispatch, dip, next); 1305 1306 out: 1307 splx(s); 1308 return dip; 1309 } 1310 1311 static int 1312 rmixl_pcie_intr(void *arg) 1313 { 1314 rmixl_pcie_link_intr_t *lip = arg; 1315 u_int link = lip->link; 1316 int rv = 0; 1317 1318 uint32_t status0 = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + int_sts_offset[link].r0); 1319 uint32_t status1 = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + int_sts_offset[link].r1); 1320 uint64_t status = ((uint64_t)status1 << 32) | status0; 1321 DPRINTF(("%s: %d:%#"PRIx64"\n", __func__, link, status)); 1322 1323 if (status != 0) { 1324 rmixl_pcie_link_dispatch_t *dip; 1325 1326 if (status & RMIXL_PCIE_LINK_STATUS_ERRORS) 1327 rmixl_pcie_link_error_intr(link, status0, status1); 1328 1329 LIST_FOREACH(dip, &lip->dispatch, next) { 1330 uint64_t bit = 1 << dip->bitno; 1331 if ((status & bit) != 0) { 1332 (void)(*dip->func)(dip->arg); 1333 dip->count.ev_count++; 1334 rv = 1; 1335 } 1336 } 1337 } 1338 1339 return rv; 1340 } 1341 1342 static void 1343 rmixl_pcie_link_error_intr(u_int link, uint32_t status0, uint32_t status1) 1344 { 1345 printf("%s: mask %#"PRIx64"\n", 1346 __func__, RMIXL_PCIE_LINK_STATUS_ERRORS); 1347 printf("%s: PCIe Link Error: link=%d status0=%#x status1=%#x\n", 1348 __func__, link, status0, status1); 1349 #if defined(DDB) && defined(DEBUG) 1350 Debugger(); 1351 #endif 1352 } 1353 1354 #if defined(DEBUG) || defined(DDB) 1355 /* this function exists to facilitate call from ddb */ 1356 int 1357 rmixl_pcie_error_check(void) 1358 { 1359 if (rmixl_pcie_v != 0) 1360 return _rmixl_pcie_error_check(rmixl_pcie_v); 1361 return -1; 1362 } 1363 #endif 1364 1365 STATIC int 1366 _rmixl_pcie_error_check(void *v) 1367 { 1368 int i, offset; 1369 pcireg_t r; 1370 pcitag_t tag; 1371 int err=0; 1372 #ifdef DIAGNOSTIC 1373 pcireg_t regs[PCIE_ECFG_ERRS_OFFTAB_NENTRIES]; 1374 #endif 1375 1376 tag = rmixl_pcie_make_tag(v, 0, 0, 0); /* XXX */ 1377 1378 for (i=0; i < PCIE_ECFG_ERRS_OFFTAB_NENTRIES; i++) { 1379 offset = pcie_ecfg_errs_tab[i].offset; 1380 r = rmixl_pcie_conf_read(v, tag, offset); 1381 #ifdef DIAGNOSTIC 1382 regs[i] = r; 1383 #endif 1384 if (r != 0) { 1385 pcireg_t rw1c = r & pcie_ecfg_errs_tab[i].rw1c; 1386 if (rw1c != 0) { 1387 /* attempt to clear the error */ 1388 rmixl_pcie_conf_write(v, tag, offset, rw1c); 1389 }; 1390 if (offset == RMIXL_PCIE_ECFG_CESR) 1391 err |= 1; /* correctable */ 1392 else 1393 err |= 2; /* uncorrectable */ 1394 } 1395 } 1396 #ifdef DIAGNOSTIC 1397 if (err != 0) { 1398 for (i=0; i < PCIE_ECFG_ERRS_OFFTAB_NENTRIES; i++) { 1399 offset = pcie_ecfg_errs_tab[i].offset; 1400 printf("%s: %#x: %#x\n", __func__, offset, regs[i]); 1401 } 1402 } 1403 #endif 1404 1405 return err; 1406 } 1407 1408 static int 1409 rmixl_pcie_error_intr(void *v) 1410 { 1411 if (_rmixl_pcie_error_check(v) < 2) 1412 return 0; /* correctable */ 1413 1414 /* uncorrectable */ 1415 #if DDB 1416 Debugger(); 1417 #endif 1418 1419 /* XXX reset and recover? */ 1420 1421 panic("%s\n", __func__); 1422 } 1423 1424 /* 1425 * rmixl_physaddr_init_pcie: 1426 * called from rmixl_physaddr_init to get region addrs & sizes 1427 * from PCIE CFG, ECFG, IO, MEM BARs 1428 */ 1429 void 1430 rmixl_physaddr_init_pcie(struct extent *ext) 1431 { 1432 u_long base; 1433 u_long size; 1434 uint32_t r; 1435 1436 r = RMIXL_IOREG_READ(RMIXL_SBC_PCIE_CFG_BAR); 1437 if ((r & RMIXL_PCIE_CFG_BAR_ENB) != 0) { 1438 base = (u_long)(RMIXL_PCIE_CFG_BAR_TO_BA((uint64_t)r) 1439 / (1024 * 1024)); 1440 size = (u_long)RMIXL_PCIE_CFG_SIZE / (1024 * 1024); 1441 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1442 __LINE__, "CFG", r, base * 1024 * 1024, size)); 1443 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1444 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1445 "failed", __func__, ext, base, size, EX_NOWAIT); 1446 } 1447 1448 r = RMIXL_IOREG_READ(RMIXL_SBC_PCIE_ECFG_BAR); 1449 if ((r & RMIXL_PCIE_ECFG_BAR_ENB) != 0) { 1450 base = (u_long)(RMIXL_PCIE_ECFG_BAR_TO_BA((uint64_t)r) 1451 / (1024 * 1024)); 1452 size = (u_long)RMIXL_PCIE_ECFG_SIZE / (1024 * 1024); 1453 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1454 __LINE__, "ECFG", r, base * 1024 * 1024, size)); 1455 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1456 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1457 "failed", __func__, ext, base, size, EX_NOWAIT); 1458 } 1459 1460 r = RMIXL_IOREG_READ(RMIXL_SBC_PCIE_MEM_BAR); 1461 if ((r & RMIXL_PCIE_MEM_BAR_ENB) != 0) { 1462 base = (u_long)(RMIXL_PCIE_MEM_BAR_TO_BA((uint64_t)r) 1463 / (1024 * 1024)); 1464 size = (u_long)(RMIXL_PCIE_MEM_BAR_TO_SIZE((uint64_t)r) 1465 / (1024 * 1024)); 1466 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1467 __LINE__, "MEM", r, base * 1024 * 1024, size)); 1468 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1469 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1470 "failed", __func__, ext, base, size, EX_NOWAIT); 1471 } 1472 1473 r = RMIXL_IOREG_READ(RMIXL_SBC_PCIE_IO_BAR); 1474 if ((r & RMIXL_PCIE_IO_BAR_ENB) != 0) { 1475 base = (u_long)(RMIXL_PCIE_IO_BAR_TO_BA((uint64_t)r) 1476 / (1024 * 1024)); 1477 size = (u_long)(RMIXL_PCIE_IO_BAR_TO_SIZE((uint64_t)r) 1478 / (1024 * 1024)); 1479 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1480 __LINE__, "IO", r, base * 1024 * 1024, size)); 1481 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1482 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1483 "failed", __func__, ext, base, size, EX_NOWAIT); 1484 } 1485 } 1486
Indexes created Tue Oct 21 16:10:11 GMT 2025