rmixl_pcie.c revision 1.1.2.11
1 /* $NetBSD: rmixl_pcie.c,v 1.1.2.11 2010/04/07 19:26:14 cliff Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * PCI configuration support for RMI XLS SoC 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: rmixl_pcie.c,v 1.1.2.11 2010/04/07 19:26:14 cliff Exp $"); 44 45 #include "opt_pci.h" 46 #include "pci.h" 47 48 #include <sys/cdefs.h> 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/device.h> 53 #include <sys/extent.h> 54 #include <sys/malloc.h> 55 56 #include <uvm/uvm_extern.h> 57 58 #include <machine/bus.h> 59 #include <machine/intr.h> 60 61 #include <mips/rmi/rmixlreg.h> 62 #include <mips/rmi/rmixlvar.h> 63 #include <mips/rmi/rmixl_intr.h> 64 #include <mips/rmi/rmixl_pcievar.h> 65 66 #include <mips/rmi/rmixl_obiovar.h> 67 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 #include <dev/pci/pciconf.h> 71 72 #ifdef PCI_NETBSD_CONFIGURE 73 #include <mips/cache.h> 74 #endif 75 76 #include <machine/pci_machdep.h> 77 78 #ifdef PCI_DEBUG 79 int rmixl_pcie_debug = PCI_DEBUG; 80 # define DPRINTF(x) do { if (rmixl_pcie_debug) printf x ; } while (0) 81 #else 82 # define DPRINTF(x) 83 #endif 84 85 #ifndef DDB 86 # define STATIC static 87 #else 88 # define STATIC 89 #endif 90 91 92 /* 93 * XLS PCIe Extended Configuration Registers 94 */ 95 #define RMIXL_PCIE_ECFG_UESR 0x104 /* Uncorrectable Error Status Reg */ 96 #define RMIXL_PCIE_ECFG_UEMR 0x108 /* Uncorrectable Error Mask Reg */ 97 #define RMIXL_PCIE_ECFG_UEVR 0x10c /* Uncorrectable Error seVerity Reg */ 98 #define PCIE_ECFG_UEVR_DFLT \ 99 (__BITS(18,17) | __BIT(31) | __BITS(5,4) | __BIT(0)) 100 #define PCIE_ECFG_UExR_RESV (__BITS(31,21) | __BITS(11,6) | __BITS(3,1)) 101 #define RMIXL_PCIE_ECFG_CESR 0x110 /* Correctable Error Status Reg */ 102 #define RMIXL_PCIE_ECFG_CEMR 0x114 /* Correctable Error Mask Reg */ 103 #define PCIE_ECFG_CExR_RESV (__BITS(31,14) | __BITS(11,9) | __BITS(5,1)) 104 #define RMIXL_PCIE_ECFG_ACCR 0x118 /* Adv. Capabilities Control Reg */ 105 #define RMIXL_PCIE_ECFG_HLRn(n) (0x11c + ((n) * 4)) /* Header Log Regs */ 106 #define RMIXL_PCIE_ECFG_RECR 0x12c /* Root Error Command Reg */ 107 #define PCIE_ECFG_RECR_RESV __BITS(31,3) 108 #define RMIXL_PCIE_ECFG_RESR 0x130 /* Root Error Status Reg */ 109 #define PCIE_ECFG_RESR_RESV __BITS(26,7) 110 #define RMIXL_PCIE_ECFG_ESI 0x134 /* Error Source Identification Reg */ 111 #define RMIXL_PCIE_ECFG_DSNCR 0x140 /* Dev Serial Number Capability Regs */ 112 113 static const struct { 114 u_int offset; 115 u_int32_t rw1c; 116 } pcie_ecfg_errs_tab[] = { 117 { RMIXL_PCIE_ECFG_UESR, (__BITS(20,12) | __BIT(4)) }, 118 { RMIXL_PCIE_ECFG_CESR, (__BITS(20,12) | __BIT(4)) }, 119 { RMIXL_PCIE_ECFG_HLRn(0), 0 }, 120 { RMIXL_PCIE_ECFG_HLRn(1), 0 }, 121 { RMIXL_PCIE_ECFG_HLRn(2), 0 }, 122 { RMIXL_PCIE_ECFG_HLRn(3), 0 }, 123 { RMIXL_PCIE_ECFG_RESR, __BITS(6,0) }, 124 { RMIXL_PCIE_ECFG_ESI, 0 }, 125 }; 126 #define PCIE_ECFG_ERRS_OFFTAB_NENTRIES \ 127 (sizeof(pcie_ecfg_errs_tab)/sizeof(pcie_ecfg_errs_tab[0])) 128 129 typedef struct rmixl_pcie_int_csr { 130 uint r0; 131 uint r1; 132 } rmixl_pcie_int_csr_t; 133 134 static const rmixl_pcie_int_csr_t int_enb_offset[4] = { 135 { RMIXL_PCIE_LINK0_INT_ENABLE0, RMIXL_PCIE_LINK0_INT_ENABLE1 }, 136 { RMIXL_PCIE_LINK1_INT_ENABLE0, RMIXL_PCIE_LINK1_INT_ENABLE1 }, 137 { RMIXL_PCIE_LINK2_INT_ENABLE0, RMIXL_PCIE_LINK2_INT_ENABLE1 }, 138 { RMIXL_PCIE_LINK3_INT_ENABLE0, RMIXL_PCIE_LINK3_INT_ENABLE1 }, 139 }; 140 141 static const rmixl_pcie_int_csr_t int_sts_offset[4] = { 142 { RMIXL_PCIE_LINK0_INT_STATUS0, RMIXL_PCIE_LINK0_INT_STATUS1 }, 143 { RMIXL_PCIE_LINK1_INT_STATUS0, RMIXL_PCIE_LINK1_INT_STATUS1 }, 144 { RMIXL_PCIE_LINK2_INT_STATUS0, RMIXL_PCIE_LINK2_INT_STATUS1 }, 145 { RMIXL_PCIE_LINK3_INT_STATUS0, RMIXL_PCIE_LINK3_INT_STATUS1 }, 146 }; 147 148 static const u_int msi_enb_offset[4] = { 149 RMIXL_PCIE_LINK0_MSI_ENABLE, 150 RMIXL_PCIE_LINK1_MSI_ENABLE, 151 RMIXL_PCIE_LINK2_MSI_ENABLE, 152 RMIXL_PCIE_LINK3_MSI_ENABLE 153 }; 154 155 #define RMIXL_PCIE_LINK_STATUS0_ERRORS __BITS(6,4) 156 #define RMIXL_PCIE_LINK_STATUS1_ERRORS __BITS(10,0) 157 #define RMIXL_PCIE_LINK_STATUS_ERRORS \ 158 ((((uint64_t)RMIXL_PCIE_LINK_STATUS1_ERRORS) << 32) | \ 159 (uint64_t)RMIXL_PCIE_LINK_STATUS0_ERRORS) 160 161 static int rmixl_pcie_match(device_t, cfdata_t, void *); 162 static void rmixl_pcie_attach(device_t, device_t, void *); 163 static void rmixl_pcie_init(struct rmixl_pcie_softc *); 164 static void rmixl_pcie_init_ecfg(struct rmixl_pcie_softc *); 165 static void rmixl_pcie_attach_hook(struct device *, struct device *, 166 struct pcibus_attach_args *); 167 static void rmixl_pcie_lnkcfg_4xx(rmixl_pcie_lnktab_t *, uint32_t); 168 static void rmixl_pcie_lnkcfg_408Lite(rmixl_pcie_lnktab_t *, uint32_t); 169 static void rmixl_pcie_lnkcfg_2xx(rmixl_pcie_lnktab_t *, uint32_t); 170 static void rmixl_pcie_lnkcfg_1xx(rmixl_pcie_lnktab_t *, uint32_t); 171 static void rmixl_pcie_lnkcfg(struct rmixl_pcie_softc *); 172 static void rmixl_pcie_intcfg(struct rmixl_pcie_softc *); 173 static void rmixl_pcie_errata(struct rmixl_pcie_softc *); 174 static void rmixl_conf_interrupt(void *, int, int, int, int, int *); 175 static int rmixl_pcie_bus_maxdevs(void *, int); 176 static pcitag_t rmixl_tag_to_ecfg(pcitag_t); 177 static pcitag_t rmixl_pcie_make_tag(void *, int, int, int); 178 static void rmixl_pcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 179 void rmixl_pcie_tag_print(const char *restrict, void *, pcitag_t, int, vaddr_t, u_long); 180 static int rmixl_pcie_conf_setup(struct rmixl_pcie_softc *, 181 pcitag_t, int *, bus_space_tag_t *, 182 bus_space_handle_t *); 183 static pcireg_t rmixl_pcie_conf_read(void *, pcitag_t, int); 184 static void rmixl_pcie_conf_write(void *, pcitag_t, int, pcireg_t); 185 186 static int rmixl_pcie_intr_map(struct pci_attach_args *, 187 pci_intr_handle_t *); 188 static const char * 189 rmixl_pcie_intr_string(void *, pci_intr_handle_t); 190 static const struct evcnt * 191 rmixl_pcie_intr_evcnt(void *, pci_intr_handle_t); 192 static pci_intr_handle_t 193 rmixl_pcie_make_pih(u_int, u_int, u_int); 194 static void rmixl_pcie_decompose_pih(pci_intr_handle_t, u_int *, u_int *, u_int *); 195 static void rmixl_pcie_intr_disestablish(void *, void *); 196 static void *rmixl_pcie_intr_establish(void *, pci_intr_handle_t, 197 int, int (*)(void *), void *); 198 static int rmixl_pcie_intr(void *); 199 static void rmixl_pcie_link_error_intr(u_int, uint32_t, uint32_t); 200 #if defined(DEBUG) || defined(DDB) 201 int rmixl_pcie_error_check(void); 202 #endif 203 static int _rmixl_pcie_error_check(void *); 204 static int rmixl_pcie_error_intr(void *); 205 206 /* 207 * XXX use locks 208 */ 209 #define PCI_CONF_LOCK(s) (s) = splhigh() 210 #define PCI_CONF_UNLOCK(s) splx((s)) 211 212 213 #define RMIXL_PCIE_CONCAT3(a,b,c) a ## b ## c 214 #define RMIXL_PCIE_BAR_INIT(reg, bar, size, align) { \ 215 struct extent *ext = rmixl_configuration.rc_phys_ex; \ 216 u_long region_start; \ 217 uint64_t ba; \ 218 int err; \ 219 \ 220 err = extent_alloc(ext, (size), (align), 0UL, EX_NOWAIT, \ 221 ®ion_start); \ 222 if (err != 0) \ 223 panic("%s: extent_alloc(%p, %#lx, %#lx, %#lx, %#x, %p)",\ 224 __func__, ext, size, align, 0UL, EX_NOWAIT, \ 225 ®ion_start); \ 226 ba = (uint64_t)region_start; \ 227 ba *= (1024 * 1024); \ 228 bar = RMIXL_PCIE_CONCAT3(RMIXL_PCIE_,reg,_BAR)(ba, 1); \ 229 DPRINTF(("PCIE %s BAR was not enabled by firmware\n" \ 230 "enabling %s at phys %#" PRIxBUSADDR ", size %lu MB\n", \ 231 __STRING(reg), __STRING(reg), ba, size)); \ 232 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_BRIDGE + \ 233 RMIXL_PCIE_CONCAT3(RMIXLS_SBC_PCIE_,reg,_BAR), bar); \ 234 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + \ 235 RMIXL_PCIE_CONCAT3(RMIXLS_SBC_PCIE_,reg,_BAR)); \ 236 DPRINTF(("%s: %s BAR %#x\n", __func__, __STRING(reg), bar)); \ 237 } 238 239 240 #if defined(DEBUG) || defined(DDB) 241 static void *rmixl_pcie_v; 242 #endif 243 244 CFATTACH_DECL_NEW(rmixl_pcie, sizeof(struct rmixl_pcie_softc), 245 rmixl_pcie_match, rmixl_pcie_attach, NULL, NULL); 246 247 static int rmixl_pcie_found; 248 249 static int 250 rmixl_pcie_match(device_t parent, cfdata_t cf, void *aux) 251 { 252 uint32_t r; 253 254 /* 255 * PCIe interface exists on XLS chips only 256 */ 257 if (! cpu_rmixls(mips_options.mips_cpu)) 258 return 0; 259 260 /* XXX 261 * for now there is only one PCIe Interface on chip 262 * this could change with furture RMI XL family designs 263 */ 264 if (rmixl_pcie_found) 265 return 0; 266 267 /* read GPIO Reset Configuration register */ 268 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET_CFG); 269 r >>= 26; 270 r &= 3; 271 if (r != 0) 272 return 0; /* strapped for SRIO */ 273 274 return 1; 275 } 276 277 static void 278 rmixl_pcie_attach(device_t parent, device_t self, void *aux) 279 { 280 struct rmixl_pcie_softc *sc = device_private(self); 281 struct obio_attach_args *obio = aux; 282 struct rmixl_config *rcp = &rmixl_configuration; 283 struct pcibus_attach_args pba; 284 uint32_t bar; 285 286 rmixl_pcie_found = 1; 287 sc->sc_dev = self; 288 289 aprint_normal(" RMI XLS PCIe Interface\n"); 290 291 rmixl_pcie_lnkcfg(sc); 292 293 rmixl_pcie_intcfg(sc); 294 295 rmixl_pcie_errata(sc); 296 297 sc->sc_29bit_dmat = obio->obio_29bit_dmat; 298 sc->sc_32bit_dmat = obio->obio_32bit_dmat; 299 sc->sc_64bit_dmat = obio->obio_64bit_dmat; 300 301 sc->sc_tmsk = obio->obio_tmsk; 302 303 /* 304 * get PCI config space base addr from SBC PCIe CFG BAR 305 * initialize it if necessary 306 */ 307 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLS_SBC_PCIE_CFG_BAR); 308 DPRINTF(("%s: PCIE_CFG_BAR %#x\n", __func__, bar)); 309 if ((bar & RMIXL_PCIE_CFG_BAR_ENB) == 0) { 310 u_long n = RMIXL_PCIE_CFG_SIZE / (1024 * 1024); 311 RMIXL_PCIE_BAR_INIT(CFG, bar, n, n); 312 } 313 rcp->rc_pci_cfg_pbase = (bus_addr_t)RMIXL_PCIE_CFG_BAR_TO_BA(bar); 314 rcp->rc_pci_cfg_size = (bus_size_t)RMIXL_PCIE_CFG_SIZE; 315 316 /* 317 * get PCIE Extended config space base addr from SBC PCIe ECFG BAR 318 * initialize it if necessary 319 */ 320 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLS_SBC_PCIE_ECFG_BAR); 321 DPRINTF(("%s: PCIE_ECFG_BAR %#x\n", __func__, bar)); 322 if ((bar & RMIXL_PCIE_ECFG_BAR_ENB) == 0) { 323 u_long n = RMIXL_PCIE_ECFG_SIZE / (1024 * 1024); 324 RMIXL_PCIE_BAR_INIT(ECFG, bar, n, n); 325 } 326 rcp->rc_pci_ecfg_pbase = (bus_addr_t)RMIXL_PCIE_ECFG_BAR_TO_BA(bar); 327 rcp->rc_pci_ecfg_size = (bus_size_t)RMIXL_PCIE_ECFG_SIZE; 328 329 /* 330 * get PCI MEM space base [addr, size] from SBC PCIe MEM BAR 331 * initialize it if necessary 332 */ 333 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLS_SBC_PCIE_MEM_BAR); 334 DPRINTF(("%s: PCIE_MEM_BAR %#x\n", __func__, bar)); 335 if ((bar & RMIXL_PCIE_MEM_BAR_ENB) == 0) { 336 u_long n = 256; /* 256 MB */ 337 RMIXL_PCIE_BAR_INIT(MEM, bar, n, n); 338 } 339 rcp->rc_pci_mem_pbase = (bus_addr_t)RMIXL_PCIE_MEM_BAR_TO_BA(bar); 340 rcp->rc_pci_mem_size = (bus_size_t)RMIXL_PCIE_MEM_BAR_TO_SIZE(bar); 341 342 /* 343 * get PCI IO space base [addr, size] from SBC PCIe IO BAR 344 * initialize it if necessary 345 */ 346 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLS_SBC_PCIE_IO_BAR); 347 DPRINTF(("%s: PCIE_IO_BAR %#x\n", __func__, bar)); 348 if ((bar & RMIXL_PCIE_IO_BAR_ENB) == 0) { 349 u_long n = 32; /* 32 MB */ 350 RMIXL_PCIE_BAR_INIT(IO, bar, n, n); 351 } 352 rcp->rc_pci_io_pbase = (bus_addr_t)RMIXL_PCIE_IO_BAR_TO_BA(bar); 353 rcp->rc_pci_io_size = (bus_size_t)RMIXL_PCIE_IO_BAR_TO_SIZE(bar); 354 355 /* 356 * initialize the PCI CFG, ECFG bus space tags 357 */ 358 rmixl_pci_cfg_bus_mem_init(&rcp->rc_pci_cfg_memt, rcp); 359 sc->sc_pci_cfg_memt = &rcp->rc_pci_cfg_memt; 360 361 rmixl_pci_ecfg_bus_mem_init(&rcp->rc_pci_ecfg_memt, rcp); 362 sc->sc_pci_ecfg_memt = &rcp->rc_pci_ecfg_memt; 363 364 /* 365 * initialize the PCI MEM and IO bus space tags 366 */ 367 rmixl_pci_bus_mem_init(&rcp->rc_pci_memt, rcp); 368 rmixl_pci_bus_io_init(&rcp->rc_pci_iot, rcp); 369 370 /* 371 * initialize the extended configuration regs 372 */ 373 rmixl_pcie_init_ecfg(sc); 374 375 /* 376 * initialize the PCI chipset tag 377 */ 378 rmixl_pcie_init(sc); 379 380 /* 381 * attach the PCI bus 382 */ 383 memset(&pba, 0, sizeof(pba)); 384 pba.pba_memt = &rcp->rc_pci_memt; 385 pba.pba_iot = &rcp->rc_pci_iot; 386 pba.pba_dmat = sc->sc_32bit_dmat; 387 pba.pba_dmat64 = sc->sc_64bit_dmat; 388 pba.pba_pc = &sc->sc_pci_chipset; 389 pba.pba_bus = 0; 390 pba.pba_bridgetag = NULL; 391 pba.pba_intrswiz = 0; 392 pba.pba_intrtag = 0; 393 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 394 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 395 396 (void) config_found_ia(self, "pcibus", &pba, pcibusprint); 397 } 398 399 /* 400 * rmixl_pcie_lnkcfg_4xx - link configs for XLS4xx and XLS6xx 401 * use IO_AD[11] and IO_AD[10], observable in 402 * Bits[21:20] of the GPIO Reset Configuration register 403 */ 404 static void 405 rmixl_pcie_lnkcfg_4xx(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 406 { 407 u_int index; 408 static const rmixl_pcie_lnkcfg_t lnktab_4xx[4][4] = { 409 {{ LCFG_EP, 4}, {LCFG_NO, 0}, {LCFG_NO, 0}, {LCFG_NO, 0}}, 410 {{ LCFG_RC, 4}, {LCFG_NO, 0}, {LCFG_NO, 0}, {LCFG_NO, 0}}, 411 {{ LCFG_EP, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}}, 412 {{ LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}}, 413 }; 414 static const char *lnkstr_4xx[4] = { 415 "1EPx4", 416 "1RCx4", 417 "1EPx1, 3RCx1", 418 "4RCx1" 419 }; 420 index = (grcr >> 20) & 3; 421 ltp->ncfgs = 4; 422 ltp->cfg = lnktab_4xx[index]; 423 ltp->str = lnkstr_4xx[index]; 424 } 425 426 /* 427 * rmixl_pcie_lnkcfg_408Lite - link configs for XLS408Lite and XLS04A 428 * use IO_AD[11] and IO_AD[10], observable in 429 * Bits[21:20] of the GPIO Reset Configuration register 430 */ 431 static void 432 rmixl_pcie_lnkcfg_408Lite(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 433 { 434 u_int index; 435 static const rmixl_pcie_lnkcfg_t lnktab_408Lite[4][2] = { 436 {{ LCFG_EP, 4}, {LCFG_NO, 0}}, 437 {{ LCFG_RC, 4}, {LCFG_NO, 0}}, 438 {{ LCFG_EP, 1}, {LCFG_RC, 1}}, 439 {{ LCFG_RC, 1}, {LCFG_RC, 1}}, 440 }; 441 static const char *lnkstr_408Lite[4] = { 442 "4EPx4", 443 "1RCx4", 444 "1EPx1, 1RCx1", 445 "2RCx1" 446 }; 447 448 index = (grcr >> 20) & 3; 449 ltp->ncfgs = 2; 450 ltp->cfg = lnktab_408Lite[index]; 451 ltp->str = lnkstr_408Lite[index]; 452 } 453 454 /* 455 * rmixl_pcie_lnkcfg_2xx - link configs for XLS2xx 456 * use IO_AD[10], observable in Bit[20] of the 457 * GPIO Reset Configuration register 458 */ 459 static void 460 rmixl_pcie_lnkcfg_2xx(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 461 { 462 u_int index; 463 static const rmixl_pcie_lnkcfg_t lnktab_2xx[2][4] = { 464 {{ LCFG_EP, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}}, 465 {{ LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}} 466 }; 467 static const char *lnkstr_2xx[2] = { 468 "1EPx1, 3RCx1", 469 "4RCx1", 470 }; 471 472 index = (grcr >> 20) & 1; 473 ltp->ncfgs = 4; 474 ltp->cfg = lnktab_2xx[index]; 475 ltp->str = lnkstr_2xx[index]; 476 } 477 478 /* 479 * rmixl_pcie_lnkcfg_1xx - link configs for XLS1xx 480 * use IO_AD[10], observable in Bit[20] of the 481 * GPIO Reset Configuration register 482 */ 483 static void 484 rmixl_pcie_lnkcfg_1xx(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 485 { 486 u_int index; 487 static const rmixl_pcie_lnkcfg_t lnktab_1xx[2][2] = { 488 {{ LCFG_EP, 1}, {LCFG_RC, 1}}, 489 {{ LCFG_RC, 1}, {LCFG_RC, 1}} 490 }; 491 static const char *lnkstr_1xx[2] = { 492 "1EPx1, 1RCx1", 493 "2RCx1", 494 }; 495 496 index = (grcr >> 20) & 1; 497 ltp->ncfgs = 2; 498 ltp->cfg = lnktab_1xx[index]; 499 ltp->str = lnkstr_1xx[index]; 500 } 501 502 /* 503 * rmixl_pcie_lnkcfg - determine PCI Express Link Configuration 504 */ 505 static void 506 rmixl_pcie_lnkcfg(struct rmixl_pcie_softc *sc) 507 { 508 uint32_t r; 509 510 /* read GPIO Reset Configuration register */ 511 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET_CFG); 512 DPRINTF(("%s: GPIO RCR %#x\n", __func__, r)); 513 514 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 515 case MIPS_XLS104: 516 case MIPS_XLS108: 517 rmixl_pcie_lnkcfg_1xx(&sc->sc_pcie_lnktab, r); 518 break; 519 case MIPS_XLS204: 520 case MIPS_XLS208: 521 rmixl_pcie_lnkcfg_2xx(&sc->sc_pcie_lnktab, r); 522 break; 523 case MIPS_XLS404LITE: 524 case MIPS_XLS408LITE: 525 rmixl_pcie_lnkcfg_408Lite(&sc->sc_pcie_lnktab, r); 526 break; 527 case MIPS_XLS404: 528 case MIPS_XLS408: 529 case MIPS_XLS416: 530 case MIPS_XLS608: 531 case MIPS_XLS616: 532 /* 6xx uses same table as 4xx */ 533 rmixl_pcie_lnkcfg_4xx(&sc->sc_pcie_lnktab, r); 534 break; 535 default: 536 panic("%s: unknown RMI PRID IMPL", __func__); 537 } 538 539 aprint_normal("%s: link config %s\n", 540 device_xname(sc->sc_dev), sc->sc_pcie_lnktab.str); 541 } 542 543 /* 544 * rmixl_pcie_intcfg - init PCIe Link interrupt enables 545 */ 546 static void 547 rmixl_pcie_intcfg(struct rmixl_pcie_softc *sc) 548 { 549 rmixl_pcie_link_intr_t *lip; 550 int link; 551 552 DPRINTF(("%s: disable all link interrupts\n", __func__)); 553 for (link=0; link < sc->sc_pcie_lnktab.ncfgs; link++) { 554 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + int_enb_offset[link].r0, 555 RMIXL_PCIE_LINK_STATUS0_ERRORS); 556 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + int_enb_offset[link].r1, 557 RMIXL_PCIE_LINK_STATUS1_ERRORS); 558 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + msi_enb_offset[link], 0); 559 lip = &sc->sc_link_intr[link]; 560 LIST_INIT(&lip->dispatch); 561 lip->ih = NULL; 562 lip->link = link; 563 lip->enabled = false; 564 } 565 } 566 567 static void 568 rmixl_pcie_errata(struct rmixl_pcie_softc *sc) 569 { 570 const mips_prid_t cpu_id = mips_options.mips_cpu_id; 571 u_int rev; 572 u_int lanes; 573 bool e391 = false; 574 575 /* 576 * 3.9.1 PCIe Link-0 Registers Reset to Incorrect Values 577 * check if it allies to this CPU implementation and revision 578 */ 579 rev = MIPS_PRID_REV(cpu_id); 580 switch (MIPS_PRID_IMPL(cpu_id)) { 581 case MIPS_XLS104: 582 case MIPS_XLS108: 583 break; 584 case MIPS_XLS204: 585 case MIPS_XLS208: 586 /* stepping A0 is affected */ 587 if (rev == 0) 588 e391 = true; 589 break; 590 case MIPS_XLS404LITE: 591 case MIPS_XLS408LITE: 592 break; 593 case MIPS_XLS404: 594 case MIPS_XLS408: 595 case MIPS_XLS416: 596 /* steppings A0 and A1 are affected */ 597 if ((rev == 0) || (rev == 1)) 598 e391 = true; 599 break; 600 case MIPS_XLS608: 601 case MIPS_XLS616: 602 break; 603 default: 604 panic("unknown RMI PRID IMPL"); 605 } 606 607 /* 608 * for XLS we only need to check entry #0 609 * this may need to change for later XL family chips 610 */ 611 lanes = sc->sc_pcie_lnktab.cfg[0].lanes; 612 613 if ((e391 != false) && ((lanes == 2) || (lanes == 4))) { 614 /* 615 * attempt work around for errata 3.9.1 616 * "PCIe Link-0 Registers Reset to Incorrect Values" 617 * the registers are write-once: if the firmware already wrote, 618 * then our writes are ignored; hope they did it right. 619 */ 620 uint32_t queuectrl; 621 uint32_t bufdepth; 622 #ifdef DIAGNOSTIC 623 uint32_t r; 624 #endif 625 626 aprint_normal("%s: attempt work around for errata 3.9.1", 627 device_xname(sc->sc_dev)); 628 if (lanes == 4) { 629 queuectrl = 0x00018074; 630 bufdepth = 0x001901D1; 631 } else { 632 queuectrl = 0x00018036; 633 bufdepth = 0x001900D9; 634 } 635 636 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_BE + 637 RMIXL_VC0_POSTED_RX_QUEUE_CTRL, queuectrl); 638 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_BE + 639 RMIXL_VC0_POSTED_BUFFER_DEPTH, bufdepth); 640 641 #ifdef DIAGNOSTIC 642 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_BE + 643 RMIXL_VC0_POSTED_RX_QUEUE_CTRL); 644 printf("\nVC0_POSTED_RX_QUEUE_CTRL %#x\n", r); 645 646 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_BE + 647 RMIXL_VC0_POSTED_BUFFER_DEPTH); 648 printf("VC0_POSTED_BUFFER_DEPTH %#x\n", r); 649 #endif 650 } 651 } 652 653 static void 654 rmixl_pcie_init(struct rmixl_pcie_softc *sc) 655 { 656 pci_chipset_tag_t pc = &sc->sc_pci_chipset; 657 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 658 struct extent *ioext, *memext; 659 #endif 660 661 pc->pc_conf_v = (void *)sc; 662 pc->pc_attach_hook = rmixl_pcie_attach_hook; 663 pc->pc_bus_maxdevs = rmixl_pcie_bus_maxdevs; 664 pc->pc_make_tag = rmixl_pcie_make_tag; 665 pc->pc_decompose_tag = rmixl_pcie_decompose_tag; 666 pc->pc_conf_read = rmixl_pcie_conf_read; 667 pc->pc_conf_write = rmixl_pcie_conf_write; 668 669 pc->pc_intr_v = (void *)sc; 670 pc->pc_intr_map = rmixl_pcie_intr_map; 671 pc->pc_intr_string = rmixl_pcie_intr_string; 672 pc->pc_intr_evcnt = rmixl_pcie_intr_evcnt; 673 pc->pc_intr_establish = rmixl_pcie_intr_establish; 674 pc->pc_intr_disestablish = rmixl_pcie_intr_disestablish; 675 pc->pc_conf_interrupt = rmixl_conf_interrupt; 676 677 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 678 /* 679 * Configure the PCI bus. 680 */ 681 struct rmixl_config *rcp = &rmixl_configuration; 682 683 aprint_normal("%s: configuring PCI bus\n", 684 device_xname(sc->sc_dev)); 685 686 ioext = extent_create("pciio", 687 rcp->rc_pci_io_pbase, 688 rcp->rc_pci_io_pbase + rcp->rc_pci_io_size - 1, 689 M_DEVBUF, NULL, 0, EX_NOWAIT); 690 691 memext = extent_create("pcimem", 692 rcp->rc_pci_mem_pbase, 693 rcp->rc_pci_mem_pbase + rcp->rc_pci_mem_size - 1, 694 M_DEVBUF, NULL, 0, EX_NOWAIT); 695 696 pci_configure_bus(pc, ioext, memext, NULL, 0, 697 mips_cache_info.mci_dcache_align); 698 699 extent_destroy(ioext); 700 extent_destroy(memext); 701 #endif 702 } 703 704 static void 705 rmixl_pcie_init_ecfg(struct rmixl_pcie_softc *sc) 706 { 707 void *v; 708 pcitag_t tag; 709 pcireg_t r; 710 711 v = sc; 712 tag = rmixl_pcie_make_tag(v, 0, 0, 0); 713 714 #ifdef PCI_DEBUG 715 int i, offset; 716 static const int offtab[] = 717 { 0, 4, 8, 0xc, 0x10, 0x14, 0x18, 0x1c, 718 0x2c, 0x30, 0x34 }; 719 for (i=0; i < sizeof(offtab)/sizeof(offtab[0]); i++) { 720 offset = 0x100 + offtab[i]; 721 r = rmixl_pcie_conf_read(v, tag, offset); 722 printf("%s: %#x: %#x\n", __func__, offset, r); 723 } 724 #endif 725 r = rmixl_pcie_conf_read(v, tag, 0x100); 726 if (r == -1) 727 return; /* cannot access */ 728 729 /* check pre-existing uncorrectable errs */ 730 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_UESR); 731 r &= ~PCIE_ECFG_UExR_RESV; 732 if (r != 0) 733 panic("%s: Uncorrectable Error Status: %#x\n", 734 __func__, r); 735 736 /* unmask all uncorrectable errs */ 737 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_UEMR); 738 r &= ~PCIE_ECFG_UExR_RESV; 739 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_UEMR, r); 740 741 /* ensure default uncorrectable err severity confniguration */ 742 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_UEVR); 743 r &= ~PCIE_ECFG_UExR_RESV; 744 r |= PCIE_ECFG_UEVR_DFLT; 745 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_UEVR, r); 746 747 /* check pre-existing correctable errs */ 748 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_CESR); 749 r &= ~PCIE_ECFG_CExR_RESV; 750 #ifdef DIAGNOSTIC 751 if (r != 0) 752 aprint_normal("%s: Correctable Error Status: %#x\n", 753 device_xname(sc->sc_dev), r); 754 #endif 755 756 /* unmask all correctable errs */ 757 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_CEMR); 758 r &= ~PCIE_ECFG_CExR_RESV; 759 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_UEMR, r); 760 761 /* check pre-existing Root Error Status */ 762 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_RESR); 763 r &= ~PCIE_ECFG_RESR_RESV; 764 if (r != 0) 765 panic("%s: Root Error Status: %#x\n", __func__, r); 766 /* XXX TMP FIXME */ 767 768 /* enable all Root errs */ 769 r = (pcireg_t)(~PCIE_ECFG_RECR_RESV); 770 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_RECR, r); 771 772 /* 773 * establish ISR for PCIE Fatal Error interrupt 774 * - for XLS4xxLite, XLS2xx, XLS1xx only 775 */ 776 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 777 case MIPS_XLS104: 778 case MIPS_XLS108: 779 case MIPS_XLS204: 780 case MIPS_XLS208: 781 case MIPS_XLS404LITE: 782 case MIPS_XLS408LITE: 783 sc->sc_fatal_ih = rmixl_intr_establish(29, sc->sc_tmsk, 784 IPL_HIGH, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH, 785 rmixl_pcie_error_intr, v); 786 break; 787 default: 788 break; 789 } 790 791 #if defined(DEBUG) || defined(DDB) 792 rmixl_pcie_v = v; 793 #endif 794 } 795 796 void 797 rmixl_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *iline) 798 { 799 DPRINTF(("%s: %p, %d, %d, %d, %d, %p\n", 800 __func__, v, bus, dev, ipin, swiz, iline)); 801 } 802 803 void 804 rmixl_pcie_attach_hook(struct device *parent, struct device *self, 805 struct pcibus_attach_args *pba) 806 { 807 DPRINTF(("%s: pba_bus %d, pba_bridgetag %p, pc_conf_v %p\n", 808 __func__, pba->pba_bus, pba->pba_bridgetag, 809 pba->pba_pc->pc_conf_v)); 810 } 811 812 int 813 rmixl_pcie_bus_maxdevs(void *v, int busno) 814 { 815 return (32); /* XXX depends on the family of XLS SoC */ 816 } 817 818 /* 819 * rmixl_tag_to_ecfg - convert cfg address (generic tag) to ecfg address 820 * 821 * 39:29 (reserved) 822 * 28 Swap (0=little, 1=big endian) 823 * 27:20 Bus number 824 * 19:15 Device number 825 * 14:12 Function number 826 * 11:8 Extended Register number 827 * 7:0 Register number 828 */ 829 static pcitag_t 830 rmixl_tag_to_ecfg(pcitag_t tag) 831 { 832 KASSERT((tag & __BITS(7,0)) == 0); 833 return (tag << 4); 834 } 835 836 /* 837 * XLS pci tag is a 40 bit address composed thusly: 838 * 39:25 (reserved) 839 * 24 Swap (0=little, 1=big endian) 840 * 23:16 Bus number 841 * 15:11 Device number 842 * 10:8 Function number 843 * 7:0 Register number 844 * 845 * Note: this is the "native" composition for addressing CFG space, but not for ECFG space. 846 */ 847 pcitag_t 848 rmixl_pcie_make_tag(void *v, int bus, int dev, int fun) 849 { 850 return ((bus << 16) | (dev << 11) | (fun << 8)); 851 } 852 853 void 854 rmixl_pcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 855 { 856 if (bp != NULL) 857 *bp = (tag >> 16) & 0xff; 858 if (dp != NULL) 859 *dp = (tag >> 11) & 0x1f; 860 if (fp != NULL) 861 *fp = (tag >> 8) & 0x7; 862 } 863 864 void 865 rmixl_pcie_tag_print(const char *restrict s, void *v, pcitag_t tag, int offset, 866 vaddr_t va, u_long r) 867 { 868 int bus, dev, fun; 869 870 rmixl_pcie_decompose_tag(v, tag, &bus, &dev, &fun); 871 printf("%s: %d/%d/%d/%d - %#" PRIxVADDR ":%#lx\n", 872 s, bus, dev, fun, offset, va, r); 873 } 874 875 static int 876 rmixl_pcie_conf_setup(struct rmixl_pcie_softc *sc, 877 pcitag_t tag, int *offp, bus_space_tag_t *bstp, 878 bus_space_handle_t *bshp) 879 { 880 struct rmixl_config *rcp = &rmixl_configuration; 881 bus_space_tag_t bst; 882 bus_space_handle_t bsh; 883 bus_size_t size; 884 pcitag_t mask; 885 bus_addr_t ba; 886 int err; 887 static bus_space_handle_t cfg_bsh; 888 static bus_addr_t cfg_oba = -1; 889 static bus_space_handle_t ecfg_bsh; 890 static bus_addr_t ecfg_oba = -1; 891 892 /* 893 * bus space depends on offset 894 */ 895 if ((*offp >= 0) && (*offp < 0x100)) { 896 mask = __BITS(15,0); 897 bst = sc->sc_pci_cfg_memt; 898 ba = rcp->rc_pci_cfg_pbase; 899 ba += (tag & ~mask); 900 *offp += (tag & mask); 901 if (ba != cfg_oba) { 902 size = (bus_size_t)(mask + 1); 903 if (cfg_oba != -1) 904 bus_space_unmap(bst, cfg_bsh, size); 905 err = bus_space_map(bst, ba, size, 0, &cfg_bsh); 906 if (err != 0) { 907 #ifdef DEBUG 908 panic("%s: bus_space_map err %d, CFG space", 909 __func__, err); /* XXX */ 910 #endif 911 return -1; 912 } 913 cfg_oba = ba; 914 } 915 bsh = cfg_bsh; 916 } else if ((*offp >= 0x100) && (*offp <= 0x700)) { 917 mask = __BITS(14,0); 918 tag = rmixl_tag_to_ecfg(tag); /* convert to ECFG format */ 919 bst = sc->sc_pci_ecfg_memt; 920 ba = rcp->rc_pci_ecfg_pbase; 921 ba += (tag & ~mask); 922 *offp += (tag & mask); 923 if (ba != ecfg_oba) { 924 size = (bus_size_t)(mask + 1); 925 if (ecfg_oba != -1) 926 bus_space_unmap(bst, ecfg_bsh, size); 927 err = bus_space_map(bst, ba, size, 0, &ecfg_bsh); 928 if (err != 0) { 929 #ifdef DEBUG 930 panic("%s: bus_space_map err %d, ECFG space", 931 __func__, err); /* XXX */ 932 #endif 933 return -1; 934 } 935 ecfg_oba = ba; 936 } 937 bsh = ecfg_bsh; 938 } else { 939 #ifdef DEBUG 940 panic("%s: offset %#x: unknown", __func__, *offp); 941 #endif 942 return -1; 943 } 944 945 *bstp = bst; 946 *bshp = bsh; 947 948 return 0; 949 } 950 951 pcireg_t 952 rmixl_pcie_conf_read(void *v, pcitag_t tag, int offset) 953 { 954 struct rmixl_pcie_softc *sc = v; 955 static bus_space_handle_t bsh; 956 bus_space_tag_t bst; 957 pcireg_t rv; 958 uint64_t cfg0; 959 u_int s; 960 961 PCI_CONF_LOCK(s); 962 963 if (rmixl_pcie_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) { 964 cfg0 = rmixl_cache_err_dis(); 965 rv = bus_space_read_4(bst, bsh, (bus_size_t)offset); 966 if (rmixl_cache_err_check() != 0) { 967 #ifdef DIAGNOSTIC 968 int bus, dev, fun; 969 970 rmixl_pcie_decompose_tag(v, tag, &bus, &dev, &fun); 971 printf("%s: %d/%d/%d, offset %#x: bad address\n", 972 __func__, bus, dev, fun, offset); 973 #endif 974 rv = (pcireg_t) -1; 975 } 976 rmixl_cache_err_restore(cfg0); 977 } else { 978 rv = -1; 979 } 980 981 PCI_CONF_UNLOCK(s); 982 return rv; 983 } 984 985 void 986 rmixl_pcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 987 { 988 struct rmixl_pcie_softc *sc = v; 989 static bus_space_handle_t bsh; 990 bus_space_tag_t bst; 991 uint64_t cfg0; 992 u_int s; 993 994 PCI_CONF_LOCK(s); 995 996 if (rmixl_pcie_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) { 997 cfg0 = rmixl_cache_err_dis(); 998 bus_space_write_4(bst, bsh, (bus_size_t)offset, val); 999 if (rmixl_cache_err_check() != 0) { 1000 #ifdef DIAGNOSTIC 1001 int bus, dev, fun; 1002 1003 rmixl_pcie_decompose_tag(v, tag, &bus, &dev, &fun); 1004 printf("%s: %d/%d/%d, offset %#x: bad address\n", 1005 __func__, bus, dev, fun, offset); 1006 #endif 1007 } 1008 rmixl_cache_err_restore(cfg0); 1009 } 1010 1011 PCI_CONF_UNLOCK(s); 1012 } 1013 1014 int 1015 rmixl_pcie_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *pih) 1016 { 1017 u_int link; 1018 u_int irq; 1019 1020 #ifdef DEBUG 1021 DPRINTF(("%s: ps_bus %d, pa_intrswiz %#x, pa_intrtag %#lx," 1022 " pa_intrpin %d, pa_intrline %d, pa_rawintrpin %d\n", 1023 __func__, pa->pa_bus, pa->pa_intrswiz, pa->pa_intrtag, 1024 pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 1025 #endif 1026 1027 /* 1028 * PCIe Link INT irq assignment is cpu implementation specific 1029 */ 1030 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 1031 case MIPS_XLS104: 1032 case MIPS_XLS108: 1033 case MIPS_XLS204: 1034 case MIPS_XLS208: 1035 case MIPS_XLS404LITE: 1036 case MIPS_XLS408LITE: 1037 switch (pa->pa_bus) { 1038 case 1: 1039 link = 0; 1040 irq = 26; 1041 break; 1042 case 2: 1043 link = 1; 1044 irq = 27; 1045 break; 1046 default: 1047 panic("%s: bad bus %d\n", __func__, pa->pa_bus); 1048 } 1049 break; 1050 case MIPS_XLS404: 1051 case MIPS_XLS408: 1052 case MIPS_XLS416: 1053 case MIPS_XLS608: 1054 case MIPS_XLS616: 1055 switch (pa->pa_bus) { 1056 case 1: 1057 link = 0; 1058 irq = 26; 1059 break; 1060 case 2: 1061 link = 1; 1062 irq = 27; 1063 break; 1064 case 3: 1065 link = 2; 1066 irq = 28; 1067 break; 1068 case 4: 1069 link = 3; 1070 irq = 29; 1071 break; 1072 default: 1073 panic("%s: bad bus %d\n", __func__, pa->pa_bus); 1074 } 1075 break; 1076 default: 1077 panic("%s: cpu IMPL %#x not supported\n", 1078 __func__, MIPS_PRID_IMPL(mips_options.mips_cpu_id)); 1079 } 1080 1081 if (pa->pa_intrpin != PCI_INTERRUPT_PIN_NONE) 1082 *pih = rmixl_pcie_make_pih(link, pa->pa_intrpin - 1, irq); 1083 else 1084 *pih = ~0; 1085 1086 return 0; 1087 } 1088 1089 const char * 1090 rmixl_pcie_intr_string(void *v, pci_intr_handle_t pih) 1091 { 1092 const char *name = "(illegal)"; 1093 u_int link, bitno, irq; 1094 1095 rmixl_pcie_decompose_pih(pih, &link, &bitno, &irq); 1096 1097 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 1098 case MIPS_XLS104: 1099 case MIPS_XLS108: 1100 case MIPS_XLS204: 1101 case MIPS_XLS208: 1102 case MIPS_XLS404LITE: 1103 case MIPS_XLS408LITE: 1104 switch (irq) { 1105 case 26: 1106 case 27: 1107 name = rmixl_intr_string(irq); 1108 break; 1109 } 1110 break; 1111 case MIPS_XLS404: 1112 case MIPS_XLS408: 1113 case MIPS_XLS416: 1114 case MIPS_XLS608: 1115 case MIPS_XLS616: 1116 switch (irq) { 1117 case 26: 1118 case 27: 1119 case 28: 1120 case 29: 1121 name = rmixl_intr_string(irq); 1122 break; 1123 } 1124 break; 1125 default: 1126 panic("%s: cpu IMPL %#x not supported\n", 1127 __func__, MIPS_PRID_IMPL(mips_options.mips_cpu_id)); 1128 } 1129 1130 return name; 1131 } 1132 1133 const struct evcnt * 1134 rmixl_pcie_intr_evcnt(void *v, pci_intr_handle_t pih) 1135 { 1136 return NULL; 1137 } 1138 1139 static pci_intr_handle_t 1140 rmixl_pcie_make_pih(u_int link, u_int bitno, u_int irq) 1141 { 1142 pci_intr_handle_t pih; 1143 1144 KASSERT(link < RMIXL_PCIE_NLINKS_MAX); 1145 KASSERT(bitno < 64); 1146 KASSERT(irq < 32); 1147 1148 pih = (irq << 10); 1149 pih |= (bitno << 4); 1150 pih |= link; 1151 1152 return pih; 1153 } 1154 1155 static void 1156 rmixl_pcie_decompose_pih(pci_intr_handle_t pih, u_int *link, u_int *bitno, u_int *irq) 1157 { 1158 *link = (u_int)(pih & 0xf); 1159 *bitno = (u_int)((pih >> 4) & 0x3f); 1160 *irq = (u_int)(pih >> 10); 1161 1162 KASSERT(*link < RMIXL_PCIE_NLINKS_MAX); 1163 KASSERT(*bitno < 64); 1164 KASSERT(*irq < 32); 1165 } 1166 1167 static void 1168 rmixl_pcie_intr_disestablish(void *v, void *ih) 1169 { 1170 rmixl_pcie_softc_t *sc = v; 1171 rmixl_pcie_link_dispatch_t *dip = ih; 1172 rmixl_pcie_link_intr_t *lip = &sc->sc_link_intr[dip->link];; 1173 uint32_t r; 1174 uint32_t bit; 1175 u_int offset; 1176 u_int other; 1177 1178 DPRINTF(("%s: link=%d pin=%d irq=%d\n", 1179 __func__, dip->link, dip->bitno + 1, dip->irq)); 1180 LIST_REMOVE(dip, next); 1181 1182 rmixl_intr_disestablish(lip->ih); 1183 1184 if (dip->bitno < 32) { 1185 bit = 1 << dip->bitno; 1186 offset = int_enb_offset[dip->link].r0; 1187 other = int_enb_offset[dip->link].r1; 1188 } else { 1189 bit = 1 << (dip->bitno - 32); 1190 offset = int_enb_offset[dip->link].r1; 1191 other = int_enb_offset[dip->link].r0; 1192 } 1193 1194 /* disable this interrupt in the PCIe bridge */ 1195 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + offset); 1196 r &= ~bit; 1197 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + offset, r); 1198 1199 /* 1200 * if both STATUS0 and STATUS1 are 0 1201 * mark the link interrupt disabled 1202 */ 1203 if (r == 0) { 1204 /* check the other reg */ 1205 if (RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + other) == 0) { 1206 lip->enabled = false; 1207 DPRINTF(("%s: disabled link %d\n", __func__, lip->link)); 1208 } 1209 } 1210 1211 evcnt_detach(&dip->count); 1212 1213 free(dip, M_DEVBUF); 1214 1215 } 1216 1217 static void * 1218 rmixl_pcie_intr_establish(void *v, pci_intr_handle_t pih, int ipl, 1219 int (*func)(void *), void *arg) 1220 { 1221 rmixl_pcie_softc_t *sc = v; 1222 u_int link, bitno, irq; 1223 uint32_t r; 1224 rmixl_pcie_link_intr_t *lip; 1225 rmixl_pcie_link_dispatch_t *dip; 1226 uint32_t bit; 1227 u_int offset; 1228 int s; 1229 1230 if (pih == ~0) { 1231 DPRINTF(("%s: bad pih=%#lx, implies PCI_INTERRUPT_PIN_NONE\n", 1232 __func__, pih)); 1233 return NULL; 1234 } 1235 1236 rmixl_pcie_decompose_pih(pih, &link, &bitno, &irq); 1237 DPRINTF(("%s: link=%d pin=%d irq=%d\n", __func__, link, bitno + 1, irq)); 1238 1239 lip = &sc->sc_link_intr[link]; 1240 1241 s = splhigh(); 1242 1243 #ifdef DEBUG 1244 LIST_FOREACH(dip, &lip->dispatch, next) { 1245 if (dip->bitno == bitno) 1246 panic("%s: pin %d alread on dispatch list", 1247 __func__, bitno + 1); 1248 } 1249 #endif 1250 1251 /* 1252 * all intrs on a link get same ipl and sc 1253 * first intr established sets the standard 1254 */ 1255 if (lip->enabled == true) { 1256 KASSERT(sc == lip->sc); 1257 if (sc != lip->sc) { 1258 printf("%s: sc %p mismatch\n", __func__, sc); 1259 goto out; 1260 } 1261 KASSERT(ipl == lip->ipl); 1262 if (ipl != lip->ipl) { 1263 printf("%s: ipl %d mismatch\n", __func__, ipl); 1264 goto out; 1265 } 1266 } 1267 1268 /* 1269 * allocate and initialize a dispatch handle 1270 */ 1271 dip = malloc(sizeof(*dip), M_DEVBUF, M_NOWAIT); 1272 if (dip == NULL) { 1273 printf("%s: cannot malloc dispatch handle\n", __func__); 1274 goto out; 1275 } 1276 1277 dip->link = link; 1278 dip->bitno = bitno; 1279 dip->irq = irq; 1280 dip->func = func; 1281 dip->arg = arg; 1282 snprintf(dip->count_name, sizeof(dip->count_name), 1283 "link %d, pin %d", link, bitno + 1); 1284 evcnt_attach_dynamic(&dip->count, EVCNT_TYPE_INTR, NULL, 1285 "rmixl_pcie", dip->count_name); 1286 1287 if (bitno < 32) { 1288 offset = int_enb_offset[link].r0; 1289 bit = 1 << bitno; 1290 } else { 1291 offset = int_enb_offset[link].r1; 1292 bit = 1 << (bitno - 32); 1293 } 1294 1295 /* enable this interrupt in the PCIe bridge */ 1296 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + offset); 1297 r |= bit; 1298 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + offset, r); 1299 1300 if (lip->enabled == false) { 1301 lip->ih = rmixl_intr_establish(irq, sc->sc_tmsk, 1302 ipl, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH, 1303 rmixl_pcie_intr, lip); 1304 if (lip->ih == NULL) 1305 panic("%s: cannot establish irq %d", __func__, irq); 1306 1307 lip->sc = sc; 1308 lip->ipl = ipl; 1309 lip->enabled = true; 1310 DPRINTF(("%s: enabled link %d\n", __func__, link)); 1311 } 1312 LIST_INSERT_HEAD(&lip->dispatch, dip, next); 1313 1314 out: 1315 splx(s); 1316 return dip; 1317 } 1318 1319 static int 1320 rmixl_pcie_intr(void *arg) 1321 { 1322 rmixl_pcie_link_intr_t *lip = arg; 1323 u_int link = lip->link; 1324 int rv = 0; 1325 1326 uint32_t status0 = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + int_sts_offset[link].r0); 1327 uint32_t status1 = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + int_sts_offset[link].r1); 1328 uint64_t status = ((uint64_t)status1 << 32) | status0; 1329 DPRINTF(("%s: %d:%#"PRIx64"\n", __func__, link, status)); 1330 1331 if (status != 0) { 1332 rmixl_pcie_link_dispatch_t *dip; 1333 1334 if (status & RMIXL_PCIE_LINK_STATUS_ERRORS) 1335 rmixl_pcie_link_error_intr(link, status0, status1); 1336 1337 LIST_FOREACH(dip, &lip->dispatch, next) { 1338 uint64_t bit = 1 << dip->bitno; 1339 if ((status & bit) != 0) { 1340 (void)(*dip->func)(dip->arg); 1341 dip->count.ev_count++; 1342 rv = 1; 1343 } 1344 } 1345 } 1346 1347 return rv; 1348 } 1349 1350 static void 1351 rmixl_pcie_link_error_intr(u_int link, uint32_t status0, uint32_t status1) 1352 { 1353 printf("%s: mask %#"PRIx64"\n", 1354 __func__, RMIXL_PCIE_LINK_STATUS_ERRORS); 1355 printf("%s: PCIe Link Error: link=%d status0=%#x status1=%#x\n", 1356 __func__, link, status0, status1); 1357 #if defined(DDB) && defined(DEBUG) 1358 Debugger(); 1359 #endif 1360 } 1361 1362 #if defined(DEBUG) || defined(DDB) 1363 /* this function exists to facilitate call from ddb */ 1364 int 1365 rmixl_pcie_error_check(void) 1366 { 1367 if (rmixl_pcie_v != 0) 1368 return _rmixl_pcie_error_check(rmixl_pcie_v); 1369 return -1; 1370 } 1371 #endif 1372 1373 STATIC int 1374 _rmixl_pcie_error_check(void *v) 1375 { 1376 int i, offset; 1377 pcireg_t r; 1378 pcitag_t tag; 1379 int err=0; 1380 #ifdef DIAGNOSTIC 1381 pcireg_t regs[PCIE_ECFG_ERRS_OFFTAB_NENTRIES]; 1382 #endif 1383 1384 tag = rmixl_pcie_make_tag(v, 0, 0, 0); /* XXX */ 1385 1386 for (i=0; i < PCIE_ECFG_ERRS_OFFTAB_NENTRIES; i++) { 1387 offset = pcie_ecfg_errs_tab[i].offset; 1388 r = rmixl_pcie_conf_read(v, tag, offset); 1389 #ifdef DIAGNOSTIC 1390 regs[i] = r; 1391 #endif 1392 if (r != 0) { 1393 pcireg_t rw1c = r & pcie_ecfg_errs_tab[i].rw1c; 1394 if (rw1c != 0) { 1395 /* attempt to clear the error */ 1396 rmixl_pcie_conf_write(v, tag, offset, rw1c); 1397 }; 1398 if (offset == RMIXL_PCIE_ECFG_CESR) 1399 err |= 1; /* correctable */ 1400 else 1401 err |= 2; /* uncorrectable */ 1402 } 1403 } 1404 #ifdef DIAGNOSTIC 1405 if (err != 0) { 1406 for (i=0; i < PCIE_ECFG_ERRS_OFFTAB_NENTRIES; i++) { 1407 offset = pcie_ecfg_errs_tab[i].offset; 1408 printf("%s: %#x: %#x\n", __func__, offset, regs[i]); 1409 } 1410 } 1411 #endif 1412 1413 return err; 1414 } 1415 1416 static int 1417 rmixl_pcie_error_intr(void *v) 1418 { 1419 if (_rmixl_pcie_error_check(v) < 2) 1420 return 0; /* correctable */ 1421 1422 /* uncorrectable */ 1423 #if DDB 1424 Debugger(); 1425 #endif 1426 1427 /* XXX reset and recover? */ 1428 1429 panic("%s\n", __func__); 1430 } 1431 1432 /* 1433 * rmixl_physaddr_init_pcie: 1434 * called from rmixl_physaddr_init to get region addrs & sizes 1435 * from PCIE CFG, ECFG, IO, MEM BARs 1436 */ 1437 void 1438 rmixl_physaddr_init_pcie(struct extent *ext) 1439 { 1440 u_long base; 1441 u_long size; 1442 uint32_t r; 1443 1444 r = RMIXL_IOREG_READ(RMIXLS_SBC_PCIE_CFG_BAR); 1445 if ((r & RMIXL_PCIE_CFG_BAR_ENB) != 0) { 1446 base = (u_long)(RMIXL_PCIE_CFG_BAR_TO_BA((uint64_t)r) 1447 / (1024 * 1024)); 1448 size = (u_long)RMIXL_PCIE_CFG_SIZE / (1024 * 1024); 1449 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1450 __LINE__, "CFG", r, base * 1024 * 1024, size)); 1451 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1452 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1453 "failed", __func__, ext, base, size, EX_NOWAIT); 1454 } 1455 1456 r = RMIXL_IOREG_READ(RMIXLS_SBC_PCIE_ECFG_BAR); 1457 if ((r & RMIXL_PCIE_ECFG_BAR_ENB) != 0) { 1458 base = (u_long)(RMIXL_PCIE_ECFG_BAR_TO_BA((uint64_t)r) 1459 / (1024 * 1024)); 1460 size = (u_long)RMIXL_PCIE_ECFG_SIZE / (1024 * 1024); 1461 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1462 __LINE__, "ECFG", r, base * 1024 * 1024, size)); 1463 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1464 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1465 "failed", __func__, ext, base, size, EX_NOWAIT); 1466 } 1467 1468 r = RMIXL_IOREG_READ(RMIXLS_SBC_PCIE_MEM_BAR); 1469 if ((r & RMIXL_PCIE_MEM_BAR_ENB) != 0) { 1470 base = (u_long)(RMIXL_PCIE_MEM_BAR_TO_BA((uint64_t)r) 1471 / (1024 * 1024)); 1472 size = (u_long)(RMIXL_PCIE_MEM_BAR_TO_SIZE((uint64_t)r) 1473 / (1024 * 1024)); 1474 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1475 __LINE__, "MEM", r, base * 1024 * 1024, size)); 1476 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1477 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1478 "failed", __func__, ext, base, size, EX_NOWAIT); 1479 } 1480 1481 r = RMIXL_IOREG_READ(RMIXLS_SBC_PCIE_IO_BAR); 1482 if ((r & RMIXL_PCIE_IO_BAR_ENB) != 0) { 1483 base = (u_long)(RMIXL_PCIE_IO_BAR_TO_BA((uint64_t)r) 1484 / (1024 * 1024)); 1485 size = (u_long)(RMIXL_PCIE_IO_BAR_TO_SIZE((uint64_t)r) 1486 / (1024 * 1024)); 1487 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1488 __LINE__, "IO", r, base * 1024 * 1024, size)); 1489 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1490 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1491 "failed", __func__, ext, base, size, EX_NOWAIT); 1492 } 1493 } 1494
Indexes created Mon Oct 20 16:09:52 GMT 2025