rmixl_pcie.c revision 1.1.2.18
1 /* $NetBSD: rmixl_pcie.c,v 1.1.2.18 2011/12/24 01:57:54 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * PCI configuration support for RMI XLS SoC 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: rmixl_pcie.c,v 1.1.2.18 2011/12/24 01:57:54 matt Exp $"); 44 45 #include "opt_pci.h" 46 #include "pci.h" 47 48 #include <sys/cdefs.h> 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/device.h> 53 #include <sys/extent.h> 54 #include <sys/malloc.h> 55 #include <sys/kernel.h> /* for 'hz' */ 56 #include <sys/cpu.h> 57 58 #include <uvm/uvm_extern.h> 59 60 #include <machine/bus.h> 61 #include <machine/intr.h> 62 63 #include <mips/rmi/rmixlreg.h> 64 #include <mips/rmi/rmixlvar.h> 65 #include <mips/rmi/rmixl_intr.h> 66 #include <mips/rmi/rmixl_pcievar.h> 67 68 #include <mips/rmi/rmixl_obiovar.h> 69 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcidevs.h> 72 #include <dev/pci/pciconf.h> 73 74 #ifdef PCI_NETBSD_CONFIGURE 75 #include <mips/cache.h> 76 #endif 77 78 #include <machine/pci_machdep.h> 79 80 #ifdef PCI_DEBUG 81 int rmixl_pcie_debug = PCI_DEBUG; 82 # define DPRINTF(x) do { if (rmixl_pcie_debug) printf x ; } while (0) 83 #else 84 # define DPRINTF(x) 85 #endif 86 87 #ifndef DDB 88 # define STATIC static 89 #else 90 # define STATIC 91 #endif 92 93 94 /* 95 * XLS PCIe Extended Configuration Registers 96 */ 97 #define RMIXL_PCIE_ECFG_UESR 0x104 /* Uncorrectable Error Status Reg */ 98 #define RMIXL_PCIE_ECFG_UEMR 0x108 /* Uncorrectable Error Mask Reg */ 99 #define RMIXL_PCIE_ECFG_UEVR 0x10c /* Uncorrectable Error seVerity Reg */ 100 #define PCIE_ECFG_UEVR_DFLT \ 101 (__BITS(18,17) | __BIT(31) | __BITS(5,4) | __BIT(0)) 102 #define PCIE_ECFG_UExR_RESV (__BITS(31,21) | __BITS(11,6) | __BITS(3,1)) 103 #define RMIXL_PCIE_ECFG_CESR 0x110 /* Correctable Error Status Reg */ 104 #define RMIXL_PCIE_ECFG_CEMR 0x114 /* Correctable Error Mask Reg */ 105 #define PCIE_ECFG_CExR_RESV (__BITS(31,14) | __BITS(11,9) | __BITS(5,1)) 106 #define RMIXL_PCIE_ECFG_ACCR 0x118 /* Adv. Capabilities Control Reg */ 107 #define RMIXL_PCIE_ECFG_HLRn(n) (0x11c + ((n) * 4)) /* Header Log Regs */ 108 #define RMIXL_PCIE_ECFG_RECR 0x12c /* Root Error Command Reg */ 109 #define PCIE_ECFG_RECR_RESV __BITS(31,3) 110 #define RMIXL_PCIE_ECFG_RESR 0x130 /* Root Error Status Reg */ 111 #define PCIE_ECFG_RESR_RESV __BITS(26,7) 112 #define RMIXL_PCIE_ECFG_ESI 0x134 /* Error Source Identification Reg */ 113 #define RMIXL_PCIE_ECFG_DSNCR 0x140 /* Dev Serial Number Capability Regs */ 114 115 static const struct { 116 u_int offset; 117 u_int32_t rw1c; 118 } pcie_ecfg_errs_tab[] = { 119 { RMIXL_PCIE_ECFG_UESR, (__BITS(20,12) | __BIT(4)) }, 120 { RMIXL_PCIE_ECFG_CESR, (__BITS(20,12) | __BIT(4)) }, 121 { RMIXL_PCIE_ECFG_HLRn(0), 0 }, 122 { RMIXL_PCIE_ECFG_HLRn(1), 0 }, 123 { RMIXL_PCIE_ECFG_HLRn(2), 0 }, 124 { RMIXL_PCIE_ECFG_HLRn(3), 0 }, 125 { RMIXL_PCIE_ECFG_RESR, __BITS(6,0) }, 126 { RMIXL_PCIE_ECFG_ESI, 0 }, 127 }; 128 #define PCIE_ECFG_ERRS_OFFTAB_NENTRIES \ 129 (sizeof(pcie_ecfg_errs_tab)/sizeof(pcie_ecfg_errs_tab[0])) 130 131 typedef struct rmixl_pcie_int_csr { 132 uint r0; 133 uint r1; 134 } rmixl_pcie_int_csr_t; 135 136 static const rmixl_pcie_int_csr_t int_enb_offset[4] = { 137 { RMIXL_PCIE_LINK0_INT_ENABLE0, RMIXL_PCIE_LINK0_INT_ENABLE1 }, 138 { RMIXL_PCIE_LINK1_INT_ENABLE0, RMIXL_PCIE_LINK1_INT_ENABLE1 }, 139 { RMIXL_PCIE_LINK2_INT_ENABLE0, RMIXL_PCIE_LINK2_INT_ENABLE1 }, 140 { RMIXL_PCIE_LINK3_INT_ENABLE0, RMIXL_PCIE_LINK3_INT_ENABLE1 }, 141 }; 142 143 static const rmixl_pcie_int_csr_t int_sts_offset[4] = { 144 { RMIXL_PCIE_LINK0_INT_STATUS0, RMIXL_PCIE_LINK0_INT_STATUS1 }, 145 { RMIXL_PCIE_LINK1_INT_STATUS0, RMIXL_PCIE_LINK1_INT_STATUS1 }, 146 { RMIXL_PCIE_LINK2_INT_STATUS0, RMIXL_PCIE_LINK2_INT_STATUS1 }, 147 { RMIXL_PCIE_LINK3_INT_STATUS0, RMIXL_PCIE_LINK3_INT_STATUS1 }, 148 }; 149 150 static const u_int msi_enb_offset[4] = { 151 RMIXL_PCIE_LINK0_MSI_ENABLE, 152 RMIXL_PCIE_LINK1_MSI_ENABLE, 153 RMIXL_PCIE_LINK2_MSI_ENABLE, 154 RMIXL_PCIE_LINK3_MSI_ENABLE 155 }; 156 157 #define RMIXL_PCIE_LINK_STATUS0_ERRORS __BITS(6,4) 158 #define RMIXL_PCIE_LINK_STATUS1_ERRORS __BITS(10,0) 159 #define RMIXL_PCIE_LINK_STATUS_ERRORS \ 160 ((((uint64_t)RMIXL_PCIE_LINK_STATUS1_ERRORS) << 32) | \ 161 (uint64_t)RMIXL_PCIE_LINK_STATUS0_ERRORS) 162 163 #define RMIXL_PCIE_EVCNT(sc, link, bitno, cpu) \ 164 &(sc)->sc_evcnts[link][(bitno) * (ncpu) + (cpu)] 165 166 static int rmixl_pcie_match(device_t, cfdata_t, void *); 167 static void rmixl_pcie_attach(device_t, device_t, void *); 168 static void rmixl_pcie_init(struct rmixl_pcie_softc *); 169 static void rmixl_pcie_init_ecfg(struct rmixl_pcie_softc *); 170 static void rmixl_pcie_attach_hook(struct device *, struct device *, 171 struct pcibus_attach_args *); 172 static void rmixl_pcie_lnkcfg_xls4xx(rmixl_pcie_lnktab_t *, uint32_t); 173 static void rmixl_pcie_lnkcfg_xls408Lite(rmixl_pcie_lnktab_t *, uint32_t); 174 static void rmixl_pcie_lnkcfg_xls2xx(rmixl_pcie_lnktab_t *, uint32_t); 175 static void rmixl_pcie_lnkcfg_xls1xx(rmixl_pcie_lnktab_t *, uint32_t); 176 static void rmixl_pcie_lnkcfg(struct rmixl_pcie_softc *); 177 static void rmixl_pcie_intcfg(struct rmixl_pcie_softc *); 178 static void rmixl_pcie_errata(struct rmixl_pcie_softc *); 179 static void rmixl_conf_interrupt(void *, int, int, int, int, int *); 180 static int rmixl_pcie_bus_maxdevs(void *, int); 181 static pcitag_t rmixl_tag_ecfg_to_cfg(pcitag_t); 182 static pcitag_t rmixl_pcie_make_tag(void *, int, int, int); 183 static void rmixl_pcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 184 void rmixl_pcie_tag_print(const char *restrict, void *, pcitag_t, int, vaddr_t, u_long); 185 static int rmixl_pcie_conf_setup(struct rmixl_pcie_softc *, 186 pcitag_t, int *, bus_space_tag_t *, 187 bus_space_handle_t *); 188 static pcireg_t rmixl_pcie_conf_read(void *, pcitag_t, int); 189 static void rmixl_pcie_conf_write(void *, pcitag_t, int, pcireg_t); 190 #ifdef __PCI_DEV_FUNCORDER 191 static bool rmixl_pcie_dev_funcorder(void *, int, int, int, char *); 192 #endif 193 194 static int rmixl_pcie_intr_map(struct pci_attach_args *, 195 pci_intr_handle_t *); 196 static const char * 197 rmixl_pcie_intr_string(void *, pci_intr_handle_t); 198 static const struct evcnt * 199 rmixl_pcie_intr_evcnt(void *, pci_intr_handle_t); 200 static pci_intr_handle_t 201 rmixl_pcie_make_pih(u_int, u_int, u_int); 202 static void rmixl_pcie_decompose_pih(pci_intr_handle_t, u_int *, u_int *, u_int *); 203 static void rmixl_pcie_intr_disestablish(void *, void *); 204 static void *rmixl_pcie_intr_establish(void *, pci_intr_handle_t, 205 int, int (*)(void *), void *); 206 static rmixl_pcie_link_intr_t * 207 rmixl_pcie_lip_add_1(rmixl_pcie_softc_t *, u_int, int, int); 208 static void rmixl_pcie_lip_free_callout(rmixl_pcie_link_intr_t *); 209 static void rmixl_pcie_lip_free(void *); 210 static int rmixl_pcie_intr(void *); 211 static void rmixl_pcie_link_error_intr(u_int, uint32_t, uint32_t); 212 #if defined(DEBUG) || defined(DDB) 213 int rmixl_pcie_error_check(void); 214 #endif 215 static int _rmixl_pcie_error_check(void *); 216 static int rmixl_pcie_error_intr(void *); 217 218 static void rmixl_physaddr_add(struct extent *, const char *, 219 struct rmixl_region *, bus_addr_t, bus_size_t); 220 221 #define RMIXL_PCIE_BAR_INIT(rp, reg, bar, size, align) { \ 222 struct extent *ext = rmixl_configuration.rc_phys_ex; \ 223 u_long region_start; \ 224 int err; \ 225 \ 226 err = extent_alloc(ext, (size), (align), 0UL, EX_NOWAIT, \ 227 ®ion_start); \ 228 if (err != 0) \ 229 panic("%s: extent_alloc(%p, %#lx, %#lx, %#lx, %#x, %p)",\ 230 __func__, ext, size, align, 0UL, EX_NOWAIT, \ 231 ®ion_start); \ 232 const uint64_t pbase = (uint64_t)region_start << 20; \ 233 bar = RMIXL_PCIE_##reg##_BAR(pbase, 1); \ 234 DPRINTF(("%s: PCIE_%s_BAR was not enabled by firmware\n" \ 235 "%s enabling PCIE_%s_BAR at phys %#" PRIxBUSADDR \ 236 ", size %luMB\n", \ 237 __func__, __STRING(reg), \ 238 __func__, __STRING(reg), pbase, size)); \ 239 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_BRIDGE \ 240 + RMIXLS_SBC_PCIE_##reg##_BAR, bar); \ 241 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE \ 242 + RMIXLS_SBC_PCIE_##reg##_BAR); \ 243 DPRINTF(("%s: %s BAR %#x\n", __func__, __STRING(reg), bar)); \ 244 (rp)->r_pbase = pbase; \ 245 (rp)->r_size = (size) << 20; \ 246 } 247 248 249 #if defined(DEBUG) || defined(DDB) 250 static void *rmixl_pcie_v; 251 #endif 252 253 CFATTACH_DECL_NEW(rmixl_pcie, sizeof(struct rmixl_pcie_softc), 254 rmixl_pcie_match, rmixl_pcie_attach, NULL, NULL); 255 256 static bool rmixl_pcie_found; 257 258 static int 259 rmixl_pcie_match(device_t parent, cfdata_t cf, void *aux) 260 { 261 uint32_t r; 262 263 /* 264 * A PCIe interface exists only on XLS chips. 265 */ 266 if (! cpu_rmixls(mips_options.mips_cpu)) 267 return 0; 268 269 /* 270 * There is only one PCIe Interface on chip 271 */ 272 if (rmixl_pcie_found) 273 return 0; 274 275 /* read GPIO Reset Configuration register */ 276 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET_CFG); 277 r >>= 26; 278 r &= 3; 279 if (r != 0) 280 return 0; /* strapped for SRIO */ 281 282 return 1; 283 } 284 285 static void 286 rmixl_pcie_attach(device_t parent, device_t self, void *aux) 287 { 288 struct rmixl_pcie_softc *sc = device_private(self); 289 struct obio_attach_args *obio = aux; 290 struct rmixl_config *rcp = &rmixl_configuration; 291 struct pcibus_attach_args pba; 292 uint32_t bar; 293 294 rmixl_pcie_found = true; 295 sc->sc_dev = self; 296 297 aprint_normal(": RMI XLS PCIe Interface\n"); 298 299 mutex_init(&sc->sc_mutex, MUTEX_DEFAULT, IPL_HIGH); 300 301 rmixl_pcie_lnkcfg(sc); 302 303 rmixl_pcie_intcfg(sc); 304 305 rmixl_pcie_errata(sc); 306 307 sc->sc_dmat29 = obio->obio_dmat29; 308 sc->sc_dmat32 = obio->obio_dmat32; 309 sc->sc_dmat64 = obio->obio_dmat64; 310 sc->sc_pc = &rcp->rc_pci_chipset; 311 312 /* 313 * get PCI config space base addr from SBC PCIe CFG BAR 314 * initialize it if necessary 315 */ 316 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLS_SBC_PCIE_CFG_BAR); 317 DPRINTF(("%s: PCIE_CFG_BAR %#x\n", __func__, bar)); 318 if ((bar & RMIXL_PCIE_CFG_BAR_ENB) == 0) { 319 u_long n = RMIXL_PCIE_CFG_SIZE / (1024 * 1024); 320 RMIXL_PCIE_BAR_INIT(&rcp->rc_pci_cfg, CFG, bar, n, n); 321 } 322 323 /* 324 * get PCIE Extended config space base addr from SBC PCIe ECFG BAR 325 * initialize it if necessary 326 */ 327 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLS_SBC_PCIE_ECFG_BAR); 328 DPRINTF(("%s: PCIE_ECFG_BAR %#x\n", __func__, bar)); 329 if ((bar & RMIXL_PCIE_ECFG_BAR_ENB) == 0) { 330 u_long n = RMIXL_PCIE_ECFG_SIZE / (1024 * 1024); 331 RMIXL_PCIE_BAR_INIT(&rcp->rc_pci_ecfg, ECFG, bar, n, n); 332 } 333 334 /* 335 * get PCI MEM space base [addr, size] from SBC PCIe MEM BAR 336 * initialize it if necessary 337 */ 338 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLS_SBC_PCIE_MEM_BAR); 339 DPRINTF(("%s: PCIE_MEM_BAR %#x\n", __func__, bar)); 340 if ((bar & RMIXL_PCIE_MEM_BAR_ENB) == 0) { 341 u_long n = 256; /* 256 MB */ 342 RMIXL_PCIE_BAR_INIT(&rcp->rc_pci_mem, MEM, bar, n, n); 343 } 344 345 /* 346 * get PCI IO space base [addr, size] from SBC PCIe IO BAR 347 * initialize it if necessary 348 */ 349 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLS_SBC_PCIE_IO_BAR); 350 DPRINTF(("%s: PCIE_IO_BAR %#x\n", __func__, bar)); 351 if ((bar & RMIXL_PCIE_IO_BAR_ENB) == 0) { 352 u_long n = 32; /* 32 MB */ 353 RMIXL_PCIE_BAR_INIT(&rcp->rc_pci_io, IO, bar, n, n); 354 } 355 356 /* 357 * initialize the PCI CFG, ECFG bus space tags 358 */ 359 sc->sc_pci_cfg_memt = &rcp->rc_pci_cfg_memt; 360 rmixl_pci_cfg_el_bus_mem_init(sc->sc_pci_cfg_memt, rcp); 361 362 /* 363 * This should be in KSEG1 and has no extent tracking. 364 * (bit 24 controls little (0) or big (1) endian access). 365 */ 366 if (bus_space_map(sc->sc_pci_cfg_memt, 0, rcp->rc_pci_cfg.r_size / 2, 367 0, &rcp->rc_pci_cfg_memh)) 368 panic("%s: failed to map pci CFG registers " 369 "(base=%#"PRIxBUSADDR" size=%#"PRIxBUSSIZE")", 370 __func__, rcp->rc_pci_cfg.r_pbase, 371 rcp->rc_pci_cfg.r_size / 2); 372 373 sc->sc_pci_cfg_memh = rcp->rc_pci_cfg_memh; 374 375 sc->sc_pci_ecfg_memt = &rcp->rc_pci_ecfg_el_memt; 376 rmixl_pci_ecfg_el_bus_mem_init(sc->sc_pci_ecfg_memt, rcp); 377 378 /* 379 * This is too big to in KSEG1 but is accessible via XKPHYS 380 * and has no extent tracking. 381 * (bit 28 controls little (0) or big (1) endian access). 382 */ 383 #ifdef _LP64 384 if (bus_space_map(sc->sc_pci_ecfg_memt, 0, rcp->rc_pci_ecfg.r_size / 2, 385 0, &rcp->rc_pci_ecfg_el_memh)) 386 panic("%s: failed to map pci ECFG LE registers " 387 "(base=%#"PRIxBUSADDR" size=%#"PRIxBUSSIZE")", 388 __func__, rcp->rc_pci_ecfg.r_pbase, 389 rcp->rc_pci_ecfg.r_size / 2); 390 391 sc->sc_pci_ecfg_memh = rcp->rc_pci_ecfg_memh; 392 #else 393 printf("%s: skipping mapping of pci ECFG LE registers " 394 "(base=%#"PRIxBUSADDR" size=%#"PRIxBUSSIZE")\n", 395 __func__, rcp->rc_pci_ecfg.r_pbase, 396 rcp->rc_pci_ecfg.r_size / 2); 397 #endif 398 399 /* 400 * initialize the PCI MEM and IO bus space tags 401 */ 402 rmixl_pci_bus_mem_init(&rcp->rc_pci_memt, rcp); 403 rmixl_pci_bus_io_init(&rcp->rc_pci_iot, rcp); 404 405 /* 406 * initialize the extended configuration regs 407 */ 408 rmixl_pcie_init_ecfg(sc); 409 410 /* 411 * initialize the PCI chipset tag 412 */ 413 rmixl_pcie_init(sc); 414 415 /* 416 * attach the PCI bus 417 */ 418 memset(&pba, 0, sizeof(pba)); 419 pba.pba_memt = &rcp->rc_pci_memt; 420 pba.pba_iot = &rcp->rc_pci_iot; 421 pba.pba_dmat = sc->sc_dmat32; 422 pba.pba_dmat64 = sc->sc_dmat64; 423 pba.pba_pc = sc->sc_pc; 424 pba.pba_bus = 0; 425 pba.pba_bridgetag = NULL; 426 pba.pba_intrswiz = 0; 427 pba.pba_intrtag = 0; 428 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 429 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 430 431 (void) config_found_ia(self, "pcibus", &pba, pcibusprint); 432 } 433 434 /* 435 * rmixl_pcie_lnkcfg_xls4xx - link configs for XLS4xx and XLS6xx 436 * use IO_AD[11] and IO_AD[10], observable in 437 * Bits[21:20] of the GPIO Reset Configuration register 438 */ 439 static void 440 rmixl_pcie_lnkcfg_xls4xx(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 441 { 442 u_int index; 443 static const rmixl_pcie_lnkcfg_t lnktab_xls4xx[4][4] = { 444 {{ LCFG_EP, 4}, {LCFG_NO, 0}, {LCFG_NO, 0}, {LCFG_NO, 0}}, 445 {{ LCFG_RC, 4}, {LCFG_NO, 0}, {LCFG_NO, 0}, {LCFG_NO, 0}}, 446 {{ LCFG_EP, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}}, 447 {{ LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}}, 448 }; 449 static const char * const lnkstr_xls4xx[4] = { 450 "1EPx4", 451 "1RCx4", 452 "1EPx1, 3RCx1", 453 "4RCx1" 454 }; 455 index = (grcr >> 20) & 3; 456 ltp->ncfgs = 4; 457 ltp->cfg = lnktab_xls4xx[index]; 458 ltp->str = lnkstr_xls4xx[index]; 459 } 460 461 /* 462 * rmixl_pcie_lnkcfg_xls408Lite - link configs for XLS408Lite and XLS04A 463 * use IO_AD[11] and IO_AD[10], observable in 464 * Bits[21:20] of the GPIO Reset Configuration register 465 */ 466 static void 467 rmixl_pcie_lnkcfg_xls408Lite(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 468 { 469 u_int index; 470 static const rmixl_pcie_lnkcfg_t lnktab_xls408Lite[4][2] = { 471 {{ LCFG_EP, 4}, {LCFG_NO, 0}}, 472 {{ LCFG_RC, 4}, {LCFG_NO, 0}}, 473 {{ LCFG_EP, 1}, {LCFG_RC, 1}}, 474 {{ LCFG_RC, 1}, {LCFG_RC, 1}}, 475 }; 476 static const char * const lnkstr_xls408Lite[4] = { 477 "4EPx4", 478 "1RCx4", 479 "1EPx1, 1RCx1", 480 "2RCx1" 481 }; 482 483 index = (grcr >> 20) & 3; 484 ltp->ncfgs = 2; 485 ltp->cfg = lnktab_xls408Lite[index]; 486 ltp->str = lnkstr_xls408Lite[index]; 487 } 488 489 /* 490 * rmixl_pcie_lnkcfg_xls2xx - link configs for XLS2xx 491 * use IO_AD[10], observable in Bit[20] of the 492 * GPIO Reset Configuration register 493 */ 494 static void 495 rmixl_pcie_lnkcfg_xls2xx(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 496 { 497 u_int index; 498 static const rmixl_pcie_lnkcfg_t lnktab_xls2xx[2][4] = { 499 {{ LCFG_EP, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}}, 500 {{ LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}} 501 }; 502 static const char * const lnkstr_xls2xx[2] = { 503 "1EPx1, 3RCx1", 504 "4RCx1", 505 }; 506 507 index = (grcr >> 20) & 1; 508 ltp->ncfgs = 4; 509 ltp->cfg = lnktab_xls2xx[index]; 510 ltp->str = lnkstr_xls2xx[index]; 511 } 512 513 /* 514 * rmixl_pcie_lnkcfg_xls1xx - link configs for XLS1xx 515 * use IO_AD[10], observable in Bit[20] of the 516 * GPIO Reset Configuration register 517 */ 518 static void 519 rmixl_pcie_lnkcfg_xls1xx(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 520 { 521 u_int index; 522 static const rmixl_pcie_lnkcfg_t lnktab_xls1xx[2][2] = { 523 {{ LCFG_EP, 1}, {LCFG_RC, 1}}, 524 {{ LCFG_RC, 1}, {LCFG_RC, 1}} 525 }; 526 static const char * const lnkstr_xls1xx[2] = { 527 "1EPx1, 1RCx1", 528 "2RCx1", 529 }; 530 531 index = (grcr >> 20) & 1; 532 ltp->ncfgs = 2; 533 ltp->cfg = lnktab_xls1xx[index]; 534 ltp->str = lnkstr_xls1xx[index]; 535 } 536 537 /* 538 * rmixl_pcie_lnkcfg - determine PCI Express Link Configuration 539 */ 540 static void 541 rmixl_pcie_lnkcfg(struct rmixl_pcie_softc *sc) 542 { 543 uint32_t r; 544 545 /* read GPIO Reset Configuration register */ 546 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET_CFG); 547 DPRINTF(("%s: GPIO RCR %#x\n", __func__, r)); 548 549 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 550 case MIPS_XLS104: 551 case MIPS_XLS108: 552 rmixl_pcie_lnkcfg_xls1xx(&sc->sc_pcie_lnktab, r); 553 break; 554 case MIPS_XLS204: 555 case MIPS_XLS208: 556 rmixl_pcie_lnkcfg_xls2xx(&sc->sc_pcie_lnktab, r); 557 break; 558 case MIPS_XLS404LITE: 559 case MIPS_XLS408LITE: 560 rmixl_pcie_lnkcfg_xls408Lite(&sc->sc_pcie_lnktab, r); 561 break; 562 case MIPS_XLS404: 563 case MIPS_XLS408: 564 case MIPS_XLS416: 565 case MIPS_XLS608: 566 case MIPS_XLS616: 567 /* 6xx uses same table as 4xx */ 568 rmixl_pcie_lnkcfg_xls4xx(&sc->sc_pcie_lnktab, r); 569 break; 570 default: 571 panic("%s: unknown RMI PRID IMPL", __func__); 572 } 573 574 aprint_normal_dev(sc->sc_dev, "link config %s\n", 575 sc->sc_pcie_lnktab.str); 576 } 577 578 /* 579 * rmixl_pcie_intcfg - init PCIe Link interrupt enables 580 */ 581 static void 582 rmixl_pcie_intcfg(struct rmixl_pcie_softc *sc) 583 { 584 int link; 585 size_t size; 586 rmixl_pcie_evcnt_t *ev; 587 588 DPRINTF(("%s: disable all link interrupts\n", __func__)); 589 for (link=0; link < sc->sc_pcie_lnktab.ncfgs; link++) { 590 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + int_enb_offset[link].r0, 591 RMIXL_PCIE_LINK_STATUS0_ERRORS); 592 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + int_enb_offset[link].r1, 593 RMIXL_PCIE_LINK_STATUS1_ERRORS); 594 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + msi_enb_offset[link], 0); 595 sc->sc_link_intr[link] = NULL; 596 597 /* 598 * allocate per-cpu, per-pin interrupt event counters 599 */ 600 size = ncpu * PCI_INTERRUPT_PIN_MAX * sizeof(rmixl_pcie_evcnt_t); 601 ev = malloc(size, M_DEVBUF, M_NOWAIT); 602 if (ev == NULL) 603 panic("%s: cannot malloc evcnts\n", __func__); 604 sc->sc_evcnts[link] = ev; 605 for (int pin=PCI_INTERRUPT_PIN_A; pin <= PCI_INTERRUPT_PIN_MAX; pin++) { 606 for (int cpu=0; cpu < ncpu; cpu++) { 607 ev = RMIXL_PCIE_EVCNT(sc, link, pin - 1, cpu); 608 snprintf(ev->name, sizeof(ev->name), 609 "cpu%d, link %d, pin %d", cpu, link, pin); 610 evcnt_attach_dynamic(&ev->evcnt, EVCNT_TYPE_INTR, 611 NULL, "rmixl_pcie", ev->name); 612 } 613 } 614 } 615 } 616 617 static void 618 rmixl_pcie_errata(struct rmixl_pcie_softc *sc) 619 { 620 const mips_prid_t cpu_id = mips_options.mips_cpu_id; 621 u_int rev; 622 u_int lanes; 623 bool e391 = false; 624 625 /* 626 * 3.9.1 PCIe Link-0 Registers Reset to Incorrect Values 627 * check if it allies to this CPU implementation and revision 628 */ 629 rev = MIPS_PRID_REV(cpu_id); 630 switch (MIPS_PRID_IMPL(cpu_id)) { 631 case MIPS_XLS104: 632 case MIPS_XLS108: 633 break; 634 case MIPS_XLS204: 635 case MIPS_XLS208: 636 /* stepping A0 is affected */ 637 if (rev == 0) 638 e391 = true; 639 break; 640 case MIPS_XLS404LITE: 641 case MIPS_XLS408LITE: 642 break; 643 case MIPS_XLS404: 644 case MIPS_XLS408: 645 case MIPS_XLS416: 646 /* steppings A0 and A1 are affected */ 647 if ((rev == 0) || (rev == 1)) 648 e391 = true; 649 break; 650 case MIPS_XLS608: 651 case MIPS_XLS616: 652 break; 653 default: 654 panic("unknown RMI PRID IMPL"); 655 } 656 657 /* 658 * for XLS we only need to check entry #0 659 * this may need to change for later XL family chips 660 */ 661 lanes = sc->sc_pcie_lnktab.cfg[0].lanes; 662 663 if ((e391 != false) && ((lanes == 2) || (lanes == 4))) { 664 /* 665 * attempt work around for errata 3.9.1 666 * "PCIe Link-0 Registers Reset to Incorrect Values" 667 * the registers are write-once: if the firmware already wrote, 668 * then our writes are ignored; hope they did it right. 669 */ 670 uint32_t queuectrl; 671 uint32_t bufdepth; 672 #ifdef DIAGNOSTIC 673 uint32_t r; 674 #endif 675 676 aprint_normal("%s: attempt work around for errata 3.9.1", 677 device_xname(sc->sc_dev)); 678 if (lanes == 4) { 679 queuectrl = 0x00018074; 680 bufdepth = 0x001901D1; 681 } else { 682 queuectrl = 0x00018036; 683 bufdepth = 0x001900D9; 684 } 685 686 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_BE + 687 RMIXL_VC0_POSTED_RX_QUEUE_CTRL, queuectrl); 688 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_BE + 689 RMIXL_VC0_POSTED_BUFFER_DEPTH, bufdepth); 690 691 #ifdef DIAGNOSTIC 692 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_BE + 693 RMIXL_VC0_POSTED_RX_QUEUE_CTRL); 694 printf("\nVC0_POSTED_RX_QUEUE_CTRL %#x\n", r); 695 696 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_BE + 697 RMIXL_VC0_POSTED_BUFFER_DEPTH); 698 printf("VC0_POSTED_BUFFER_DEPTH %#x\n", r); 699 #endif 700 } 701 } 702 703 static void 704 rmixl_pcie_init(struct rmixl_pcie_softc *sc) 705 { 706 pci_chipset_tag_t pc = sc->sc_pc; 707 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 708 struct extent *ioext, *memext; 709 #endif 710 711 pc->pc_conf_v = (void *)sc; 712 pc->pc_attach_hook = rmixl_pcie_attach_hook; 713 pc->pc_bus_maxdevs = rmixl_pcie_bus_maxdevs; 714 pc->pc_make_tag = rmixl_pcie_make_tag; 715 pc->pc_decompose_tag = rmixl_pcie_decompose_tag; 716 pc->pc_conf_read = rmixl_pcie_conf_read; 717 pc->pc_conf_write = rmixl_pcie_conf_write; 718 #ifdef __PCI_DEV_FUNCORDER 719 pc->pc_dev_funcorder = rmixl_pcie_dev_funcorder; 720 #endif 721 722 pc->pc_intr_v = (void *)sc; 723 pc->pc_intr_map = rmixl_pcie_intr_map; 724 pc->pc_intr_string = rmixl_pcie_intr_string; 725 pc->pc_intr_evcnt = rmixl_pcie_intr_evcnt; 726 pc->pc_intr_establish = rmixl_pcie_intr_establish; 727 pc->pc_intr_disestablish = rmixl_pcie_intr_disestablish; 728 pc->pc_conf_interrupt = rmixl_conf_interrupt; 729 730 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 731 /* 732 * Configure the PCI bus. 733 */ 734 struct rmixl_config *rcp = &rmixl_configuration; 735 736 aprint_normal_dev(sc->sc_dev, "configuring PCI bus\n"); 737 738 ioext = extent_create("pciio", 739 rcp->rc_pci_io.r_pbase, 740 rcp->rc_pci_io.r_pbase + rcp->rc_pci_io.r_size - 1, 741 M_DEVBUF, NULL, 0, EX_NOWAIT); 742 743 memext = extent_create("pcimem", 744 rcp->rc_pci_mem.r_pbase, 745 rcp->rc_pci_mem.r_pbase + rcp->rc_pci_mem.r_size - 1, 746 M_DEVBUF, NULL, 0, EX_NOWAIT); 747 748 pci_configure_bus(pc, ioext, memext, NULL, 0, 749 mips_cache_info.mci_dcache_align); 750 751 extent_destroy(ioext); 752 extent_destroy(memext); 753 #endif 754 } 755 756 static void 757 rmixl_pcie_init_ecfg(struct rmixl_pcie_softc *sc) 758 { 759 void *v; 760 pcitag_t tag; 761 pcireg_t r; 762 763 v = sc; 764 tag = rmixl_pcie_make_tag(v, 0, 0, 0); 765 766 #ifdef PCI_DEBUG 767 int i, offset; 768 static const int offtab[] = 769 { 0, 4, 8, 0xc, 0x10, 0x14, 0x18, 0x1c, 770 0x2c, 0x30, 0x34 }; 771 for (i=0; i < sizeof(offtab)/sizeof(offtab[0]); i++) { 772 offset = 0x100 + offtab[i]; 773 r = rmixl_pcie_conf_read(v, tag, offset); 774 printf("%s: %#x: %#x\n", __func__, offset, r); 775 } 776 #endif 777 r = rmixl_pcie_conf_read(v, tag, 0x100); 778 if (r == -1) 779 return; /* cannot access */ 780 781 /* check pre-existing uncorrectable errs */ 782 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_UESR); 783 r &= ~PCIE_ECFG_UExR_RESV; 784 if (r != 0) 785 panic("%s: Uncorrectable Error Status: %#x\n", 786 __func__, r); 787 788 /* unmask all uncorrectable errs */ 789 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_UEMR); 790 r &= ~PCIE_ECFG_UExR_RESV; 791 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_UEMR, r); 792 793 /* ensure default uncorrectable err severity confniguration */ 794 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_UEVR); 795 r &= ~PCIE_ECFG_UExR_RESV; 796 r |= PCIE_ECFG_UEVR_DFLT; 797 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_UEVR, r); 798 799 /* check pre-existing correctable errs */ 800 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_CESR); 801 r &= ~PCIE_ECFG_CExR_RESV; 802 #ifdef DIAGNOSTIC 803 if (r != 0) 804 aprint_normal("%s: Correctable Error Status: %#x\n", 805 device_xname(sc->sc_dev), r); 806 #endif 807 808 /* unmask all correctable errs */ 809 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_CEMR); 810 r &= ~PCIE_ECFG_CExR_RESV; 811 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_UEMR, r); 812 813 /* check pre-existing Root Error Status */ 814 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_RESR); 815 r &= ~PCIE_ECFG_RESR_RESV; 816 if (r != 0) 817 panic("%s: Root Error Status: %#x\n", __func__, r); 818 /* XXX TMP FIXME */ 819 820 /* enable all Root errs */ 821 r = (pcireg_t)(~PCIE_ECFG_RECR_RESV); 822 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_RECR, r); 823 824 /* 825 * establish ISR for PCIE Fatal Error interrupt 826 * - for XLS4xxLite, XLS2xx, XLS1xx only 827 */ 828 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 829 case MIPS_XLS104: 830 case MIPS_XLS108: 831 case MIPS_XLS204: 832 case MIPS_XLS208: 833 case MIPS_XLS404LITE: 834 case MIPS_XLS408LITE: 835 sc->sc_fatal_ih = rmixl_intr_establish(29, 836 IPL_HIGH, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH, 837 rmixl_pcie_error_intr, v, false); 838 break; 839 default: 840 break; 841 } 842 843 #if defined(DEBUG) || defined(DDB) 844 rmixl_pcie_v = v; 845 #endif 846 } 847 848 void 849 rmixl_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *iline) 850 { 851 DPRINTF(("%s: %p, %d, %d, %d, %d, %p\n", 852 __func__, v, bus, dev, ipin, swiz, iline)); 853 } 854 855 void 856 rmixl_pcie_attach_hook(struct device *parent, struct device *self, 857 struct pcibus_attach_args *pba) 858 { 859 DPRINTF(("%s: pba_bus %d, pba_bridgetag %p, pc_conf_v %p\n", 860 __func__, pba->pba_bus, pba->pba_bridgetag, 861 pba->pba_pc->pc_conf_v)); 862 } 863 864 int 865 rmixl_pcie_bus_maxdevs(void *v, int busno) 866 { 867 return (32); /* XXX depends on the family of XLS SoC */ 868 } 869 870 /* 871 * rmixl_tag_ecfg_to_cfg - convert ecfg address to cfg (generic tag) address 872 * 873 * ecfg cfg 874 * 39:29 39:25 (reserved) 875 * 28 24 Swap (0=little, 1=big endian) 876 * 27:20 23:16 Bus number 877 * 19:15 15:11 Device number 878 * 14:12 10:8 Function number 879 * 11:0 7:0 Register number 880 */ 881 static inline pcitag_t 882 rmixl_tag_ecfg_to_cfg(pcitag_t tag) 883 { 884 KASSERT(_RMIXL_PCITAG_OFFSET(tag) == 0); 885 return tag >> 4; 886 } 887 888 /* 889 * XLS pci (extended) tag is a 40 bit address composed thusly: 890 * 39:29 (reserved) 891 * 28 Swap (0=little, 1=big endian) 892 * 27:20 Bus number 893 * 19:15 Device number 894 * 14:12 Function number 895 * 11:0 Register number 896 * 897 * Note: this is the "native" composition for addressing CFG space, but not for ECFG space. 898 */ 899 pcitag_t 900 rmixl_pcie_make_tag(void *v, int bus, int dev, int fun) 901 { 902 return _RMIXL_PCITAG(bus, dev, fun); 903 } 904 905 void 906 rmixl_pcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 907 { 908 if (bp != NULL) 909 *bp = _RMIXL_PCITAG_BUS(tag); 910 if (dp != NULL) 911 *dp = _RMIXL_PCITAG_DEV(tag); 912 if (fp != NULL) 913 *fp = _RMIXL_PCITAG_FUNC(tag); 914 } 915 916 void 917 rmixl_pcie_tag_print(const char *restrict s, void *v, pcitag_t tag, int offset, 918 vaddr_t va, u_long r) 919 { 920 int bus, dev, fun; 921 922 rmixl_pcie_decompose_tag(v, tag, &bus, &dev, &fun); 923 printf("%s: %lx: %d/%d/%d/%d - %#" PRIxVADDR ":%#lx\n", 924 s, tag, bus, dev, fun, offset, va, r); 925 } 926 927 static int 928 rmixl_pcie_conf_setup(struct rmixl_pcie_softc *sc, 929 pcitag_t tag, int *offp, bus_space_tag_t *bstp, 930 bus_space_handle_t *bshp) 931 { 932 bus_space_tag_t bst; 933 bus_space_handle_t bsh; 934 935 #ifdef _LP64 936 bst = sc->sc_pci_ecfg_memt; 937 bus_space_subregion(bst, sc->sc_pci_ecfg_memh, tag, 0x1000, &bsh); 938 #else 939 /* 940 * bus space depends on offset 941 */ 942 if ((*offp >= 0) && (*offp < 0x100)) { 943 bst = sc->sc_pci_cfg_memt; 944 tag = rmixl_tag_ecfg_to_cfg(tag); /* convert to CFG format */ 945 bus_space_subregion(bst, sc->sc_pci_cfg_memh, tag, 0x100, &bsh); 946 } else if ((*offp >= 0x100) && (*offp <= 0x700)) { 947 static bus_space_handle_t ecfg_bsh; 948 static bus_addr_t ecfg_oba = -1; 949 const pcitag_t mask = __BITS(14,0); /* all fnctns of a device */ 950 bst = sc->sc_pci_ecfg_memt; 951 const bus_addr_t ba = (tag & ~mask); 952 *offp += (tag & mask); 953 if (ba != ecfg_oba) { 954 bus_size_t size = (bus_size_t)(mask + 1); 955 if (ecfg_oba != -1) 956 bus_space_unmap(bst, ecfg_bsh, size); 957 int err = bus_space_map(bst, ba, size, 0, &ecfg_bsh); 958 if (err != 0) { 959 ecfg_oba = -1; 960 #ifdef DEBUG 961 panic("%s: ECFG: " 962 "bus_space_map(%p, %#"PRIxBUSADDR 963 ", %#"PRIxBUSSIZE", 0, %p): %d", 964 __func__, bst, ba, size, &ecfg_bsh, err); 965 #endif 966 return -1; 967 } 968 ecfg_oba = ba; 969 } 970 bsh = ecfg_bsh; 971 } else { 972 #ifdef DEBUG 973 panic("%s: offset %#x: unknown", __func__, *offp); 974 #endif 975 return -1; 976 } 977 #endif /* _LP64 */ 978 979 *bstp = bst; 980 *bshp = bsh; 981 982 return 0; 983 } 984 985 pcireg_t 986 rmixl_pcie_conf_read(void *v, pcitag_t tag, int offset) 987 { 988 struct rmixl_pcie_softc *sc = v; 989 static bus_space_handle_t bsh; 990 bus_space_tag_t bst; 991 pcireg_t rv; 992 uint64_t cfg0; 993 994 mutex_enter(&sc->sc_mutex); 995 996 if (rmixl_pcie_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) { 997 cfg0 = rmixl_cache_err_dis(); 998 rv = bus_space_read_4(bst, bsh, (bus_size_t)offset); 999 if (rmixl_cache_err_check() != 0) { 1000 #ifdef DIAGNOSTIC 1001 int bus, dev, fun; 1002 1003 rmixl_pcie_decompose_tag(v, tag, &bus, &dev, &fun); 1004 printf("%s: %d/%d/%d, offset %#x: bad address\n", 1005 __func__, bus, dev, fun, offset); 1006 #endif 1007 rv = (pcireg_t) -1; 1008 } 1009 rmixl_cache_err_restore(cfg0); 1010 } else { 1011 rv = -1; 1012 } 1013 1014 mutex_exit(&sc->sc_mutex); 1015 1016 return rv; 1017 } 1018 1019 void 1020 rmixl_pcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 1021 { 1022 struct rmixl_pcie_softc *sc = v; 1023 static bus_space_handle_t bsh; 1024 bus_space_tag_t bst; 1025 uint64_t cfg0; 1026 1027 mutex_enter(&sc->sc_mutex); 1028 1029 if (rmixl_pcie_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) { 1030 cfg0 = rmixl_cache_err_dis(); 1031 bus_space_write_4(bst, bsh, (bus_size_t)offset, val); 1032 if (rmixl_cache_err_check() != 0) { 1033 #ifdef DIAGNOSTIC 1034 int bus, dev, fun; 1035 1036 rmixl_pcie_decompose_tag(v, tag, &bus, &dev, &fun); 1037 printf("%s: %d/%d/%d, offset %#x: bad address\n", 1038 __func__, bus, dev, fun, offset); 1039 #endif 1040 } 1041 rmixl_cache_err_restore(cfg0); 1042 } 1043 1044 mutex_exit(&sc->sc_mutex); 1045 } 1046 1047 #ifdef __PCI_DEV_FUNCORDER 1048 bool 1049 rmixl_pcie_dev_funcorder(void *v, int bus, int device, int nfunctions, 1050 char *funcs) 1051 { 1052 return false; 1053 } 1054 #endif 1055 1056 int 1057 rmixl_pcie_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *pih) 1058 { 1059 int device; 1060 u_int link; 1061 u_int irq; 1062 1063 /* 1064 * The bus is unimportant since it can change depending on the 1065 * configuration. We are tied to device # of PCIe bridge we are 1066 * ultimately attached to. 1067 */ 1068 pci_decompose_tag(pa->pa_pc, pa->pa_intrtag, 1069 NULL, &device, NULL); 1070 1071 #ifdef DEBUG 1072 DPRINTF(("%s: ps_bus %d, pa_intrswiz %#x, pa_intrtag %#lx," 1073 " pa_intrpin %d, pa_intrline %d, pa_rawintrpin %d\n", 1074 __func__, pa->pa_bus, pa->pa_intrswiz, pa->pa_intrtag, 1075 pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 1076 #endif 1077 1078 /* 1079 * PCIe Link INT irq assignment is cpu implementation specific 1080 */ 1081 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 1082 case MIPS_XLS104: 1083 case MIPS_XLS108: 1084 case MIPS_XLS404LITE: 1085 case MIPS_XLS408LITE: 1086 if (device > 1) 1087 panic("%s: bad bus %d", __func__, device); 1088 link = device; 1089 irq = device + 26; 1090 break; 1091 case MIPS_XLS204: 1092 case MIPS_XLS208: { 1093 if (device > 3) 1094 panic("%s: bad bus %d", __func__, device); 1095 link = device; 1096 irq = device + (device & 2 ? 21 : 26); 1097 break; 1098 } 1099 case MIPS_XLS404: 1100 case MIPS_XLS408: 1101 case MIPS_XLS416: 1102 case MIPS_XLS608: 1103 case MIPS_XLS616: 1104 if (device > 3) 1105 panic("%s: bad bus %d", __func__, device); 1106 link = device; 1107 irq = device + 26; 1108 break; 1109 default: 1110 panic("%s: cpu IMPL %#x not supported\n", 1111 __func__, MIPS_PRID_IMPL(mips_options.mips_cpu_id)); 1112 } 1113 1114 if (pa->pa_intrpin != PCI_INTERRUPT_PIN_NONE) 1115 *pih = rmixl_pcie_make_pih(link, pa->pa_intrpin - 1, irq); 1116 else 1117 *pih = ~0; 1118 1119 return 0; 1120 } 1121 1122 const char * 1123 rmixl_pcie_intr_string(void *v, pci_intr_handle_t pih) 1124 { 1125 const char *name = "(illegal)"; 1126 u_int link, bitno, irq; 1127 1128 rmixl_pcie_decompose_pih(pih, &link, &bitno, &irq); 1129 1130 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 1131 case MIPS_XLS104: 1132 case MIPS_XLS108: 1133 case MIPS_XLS404LITE: 1134 case MIPS_XLS408LITE: 1135 switch (irq) { 1136 case 26: 1137 case 27: 1138 name = rmixl_irt_string(irq); 1139 break; 1140 } 1141 break; 1142 case MIPS_XLS204: 1143 case MIPS_XLS208: 1144 switch (irq) { 1145 case 23: 1146 case 24: 1147 case 26: 1148 case 27: 1149 name = rmixl_irt_string(irq); 1150 break; 1151 } 1152 break; 1153 case MIPS_XLS404: 1154 case MIPS_XLS408: 1155 case MIPS_XLS416: 1156 case MIPS_XLS608: 1157 case MIPS_XLS616: 1158 switch (irq) { 1159 case 26: 1160 case 27: 1161 case 28: 1162 case 29: 1163 name = rmixl_irt_string(irq); 1164 break; 1165 } 1166 break; 1167 default: 1168 panic("%s: cpu IMPL %#x not supported\n", 1169 __func__, MIPS_PRID_IMPL(mips_options.mips_cpu_id)); 1170 } 1171 1172 return name; 1173 } 1174 1175 const struct evcnt * 1176 rmixl_pcie_intr_evcnt(void *v, pci_intr_handle_t pih) 1177 { 1178 return NULL; 1179 } 1180 1181 static pci_intr_handle_t 1182 rmixl_pcie_make_pih(u_int link, u_int bitno, u_int irq) 1183 { 1184 pci_intr_handle_t pih; 1185 1186 KASSERT(link < RMIXL_PCIE_NLINKS_MAX); 1187 KASSERT(bitno < 64); 1188 KASSERT(irq < 32); 1189 1190 pih = (irq << 10); 1191 pih |= (bitno << 4); 1192 pih |= link; 1193 1194 return pih; 1195 } 1196 1197 static void 1198 rmixl_pcie_decompose_pih(pci_intr_handle_t pih, u_int *link, u_int *bitno, u_int *irq) 1199 { 1200 *link = (u_int)(pih & 0xf); 1201 *bitno = (u_int)((pih >> 4) & 0x3f); 1202 *irq = (u_int)(pih >> 10); 1203 1204 KASSERT(*link < RMIXL_PCIE_NLINKS_MAX); 1205 KASSERT(*bitno < 64); 1206 KASSERT(*irq < 32); 1207 } 1208 1209 static void 1210 rmixl_pcie_intr_disestablish(void *v, void *ih) 1211 { 1212 rmixl_pcie_softc_t *sc = v; 1213 rmixl_pcie_link_dispatch_t *dip = ih; 1214 rmixl_pcie_link_intr_t *lip = sc->sc_link_intr[dip->link]; 1215 uint32_t r; 1216 uint32_t bit; 1217 u_int offset; 1218 u_int other; 1219 bool busy; 1220 1221 DPRINTF(("%s: link=%d pin=%d irq=%d\n", 1222 __func__, dip->link, dip->bitno + 1, dip->irq)); 1223 1224 mutex_enter(&sc->sc_mutex); 1225 1226 dip->func = NULL; /* mark unused, prevent further dispatch */ 1227 1228 /* 1229 * if no other dispatch handle is using this interrupt, 1230 * we can disable it 1231 */ 1232 busy = false; 1233 for (int i=0; i < lip->dispatch_count; i++) { 1234 rmixl_pcie_link_dispatch_t *d = &lip->dispatch_data[i]; 1235 if (d == dip) 1236 continue; 1237 if (d->bitno == dip->bitno) { 1238 busy = true; 1239 break; 1240 } 1241 } 1242 if (! busy) { 1243 if (dip->bitno < 32) { 1244 bit = 1 << dip->bitno; 1245 offset = int_enb_offset[dip->link].r0; 1246 other = int_enb_offset[dip->link].r1; 1247 } else { 1248 bit = 1 << (dip->bitno - 32); 1249 offset = int_enb_offset[dip->link].r1; 1250 other = int_enb_offset[dip->link].r0; 1251 } 1252 1253 /* disable this interrupt in the PCIe bridge */ 1254 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + offset); 1255 r &= ~bit; 1256 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + offset, r); 1257 1258 /* 1259 * if both ENABLE0 and ENABLE1 are 0 1260 * disable the link interrupt 1261 */ 1262 if (r == 0) { 1263 /* check the other reg */ 1264 if (RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + other) == 0) { 1265 DPRINTF(("%s: disable link %d\n", __func__, lip->link)); 1266 1267 /* tear down interrupt on this link */ 1268 rmixl_intr_disestablish(lip->ih); 1269 1270 /* commit NULL interrupt set */ 1271 sc->sc_link_intr[dip->link] = NULL; 1272 1273 /* schedule delayed free of the old link interrupt set */ 1274 rmixl_pcie_lip_free_callout(lip); 1275 } 1276 } 1277 } 1278 1279 mutex_exit(&sc->sc_mutex); 1280 } 1281 1282 static void * 1283 rmixl_pcie_intr_establish(void *v, pci_intr_handle_t pih, int ipl, 1284 int (*func)(void *), void *arg) 1285 { 1286 rmixl_pcie_softc_t *sc = v; 1287 u_int link, bitno, irq; 1288 uint32_t r; 1289 rmixl_pcie_link_intr_t *lip; 1290 rmixl_pcie_link_dispatch_t *dip = NULL; 1291 uint32_t bit; 1292 u_int offset; 1293 1294 if (pih == ~0) { 1295 DPRINTF(("%s: bad pih=%#lx, implies PCI_INTERRUPT_PIN_NONE\n", 1296 __func__, pih)); 1297 return NULL; 1298 } 1299 1300 rmixl_pcie_decompose_pih(pih, &link, &bitno, &irq); 1301 DPRINTF(("%s: link=%d pin=%d irq=%d\n", 1302 __func__, link, bitno + 1, irq)); 1303 1304 mutex_enter(&sc->sc_mutex); 1305 1306 lip = rmixl_pcie_lip_add_1(sc, link, irq, ipl); 1307 if (lip == NULL) 1308 return NULL; 1309 1310 /* 1311 * initializae our new interrupt, the last element in dispatch_data[] 1312 */ 1313 dip = &lip->dispatch_data[lip->dispatch_count - 1]; 1314 dip->link = link; 1315 dip->bitno = bitno; 1316 dip->irq = irq; 1317 dip->func = func; 1318 dip->arg = arg; 1319 dip->counts = RMIXL_PCIE_EVCNT(sc, link, bitno, 0); 1320 1321 if (bitno < 32) { 1322 offset = int_enb_offset[link].r0; 1323 bit = 1 << bitno; 1324 } else { 1325 offset = int_enb_offset[link].r1; 1326 bit = 1 << (bitno - 32); 1327 } 1328 1329 /* commit the new link interrupt set */ 1330 sc->sc_link_intr[link] = lip; 1331 1332 /* enable this interrupt in the PCIe bridge */ 1333 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + offset); 1334 r |= bit; 1335 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + offset, r); 1336 1337 mutex_exit(&sc->sc_mutex); 1338 return dip; 1339 } 1340 1341 rmixl_pcie_link_intr_t * 1342 rmixl_pcie_lip_add_1(rmixl_pcie_softc_t *sc, u_int link, int irq, int ipl) 1343 { 1344 rmixl_pcie_link_intr_t *lip_old = sc->sc_link_intr[link]; 1345 rmixl_pcie_link_intr_t *lip_new; 1346 u_int dispatch_count; 1347 size_t size; 1348 1349 dispatch_count = 1; 1350 size = sizeof(rmixl_pcie_link_intr_t); 1351 if (lip_old != NULL) { 1352 /* 1353 * count only those dispatch elements still in use 1354 * unused ones will be pruned during copy 1355 * i.e. we are "lazy" there is no rmixl_pcie_lip_sub_1 1356 */ 1357 for (int i=0; i < lip_old->dispatch_count; i++) { 1358 if (lip_old->dispatch_data[i].func != NULL) { 1359 dispatch_count++; 1360 size += sizeof(rmixl_pcie_link_intr_t); 1361 } 1362 } 1363 } 1364 1365 /* 1366 * allocate and initialize link intr struct 1367 * with one or more dispatch handles 1368 */ 1369 lip_new = malloc(size, M_DEVBUF, M_NOWAIT); 1370 if (lip_new == NULL) { 1371 #ifdef DIAGNOSTIC 1372 printf("%s: cannot malloc\n", __func__); 1373 #endif 1374 return NULL; 1375 } 1376 1377 if (lip_old == NULL) { 1378 /* initialize the link interrupt struct */ 1379 lip_new->sc = sc; 1380 lip_new->link = link; 1381 lip_new->ipl = ipl; 1382 lip_new->ih = rmixl_intr_establish(irq, 1383 ipl, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH, 1384 rmixl_pcie_intr, lip_new, false); 1385 if (lip_new->ih == NULL) 1386 panic("%s: cannot establish irq %d", __func__, irq); 1387 } else { 1388 /* 1389 * all intrs on a link get same ipl and sc 1390 * first intr established sets the standard 1391 */ 1392 KASSERT(sc == lip_old->sc); 1393 if (sc != lip_old->sc) { 1394 printf("%s: sc %p mismatch\n", __func__, sc); 1395 free(lip_new, M_DEVBUF); 1396 return NULL; 1397 } 1398 KASSERT (ipl == lip_old->ipl); 1399 if (ipl != lip_old->ipl) { 1400 printf("%s: ipl %d mismatch\n", __func__, ipl); 1401 free(lip_new, M_DEVBUF); 1402 return NULL; 1403 } 1404 /* 1405 * copy lip_old to lip_new, skipping unused dispatch elemets 1406 */ 1407 memcpy(lip_new, lip_old, sizeof(rmixl_pcie_link_intr_t)); 1408 for (int j=0, i=0; i < lip_old->dispatch_count; i++) { 1409 if (lip_old->dispatch_data[i].func != NULL) { 1410 memcpy(&lip_new->dispatch_data[j], 1411 &lip_old->dispatch_data[i], 1412 sizeof(rmixl_pcie_link_dispatch_t)); 1413 j++; 1414 } 1415 } 1416 1417 /* 1418 * schedule delayed free of old link interrupt set 1419 */ 1420 rmixl_pcie_lip_free_callout(lip_old); 1421 } 1422 lip_new->dispatch_count = dispatch_count; 1423 1424 return lip_new; 1425 } 1426 1427 /* 1428 * delay free of the old link interrupt set 1429 * to allow anyone still using it to do so safely 1430 * XXX 2 seconds should be plenty? 1431 */ 1432 static void 1433 rmixl_pcie_lip_free_callout(rmixl_pcie_link_intr_t *lip) 1434 { 1435 callout_init(&lip->callout, 0); 1436 callout_reset(&lip->callout, 2 * hz, rmixl_pcie_lip_free, lip); 1437 } 1438 1439 static void 1440 rmixl_pcie_lip_free(void *arg) 1441 { 1442 rmixl_pcie_link_intr_t *lip = arg; 1443 1444 callout_destroy(&lip->callout); 1445 free(lip, M_DEVBUF); 1446 } 1447 1448 static int 1449 rmixl_pcie_intr(void *arg) 1450 { 1451 rmixl_pcie_link_intr_t *lip = arg; 1452 u_int link = lip->link; 1453 int rv = 0; 1454 1455 uint32_t status0 = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + int_sts_offset[link].r0); 1456 uint32_t status1 = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + int_sts_offset[link].r1); 1457 uint64_t status = ((uint64_t)status1 << 32) | status0; 1458 DPRINTF(("%s: %d:%#"PRIx64"\n", __func__, link, status)); 1459 1460 if (status != 0) { 1461 rmixl_pcie_link_dispatch_t *dip; 1462 1463 if (status & RMIXL_PCIE_LINK_STATUS_ERRORS) 1464 rmixl_pcie_link_error_intr(link, status0, status1); 1465 1466 for (u_int i=0; i < lip->dispatch_count; i++) { 1467 dip = &lip->dispatch_data[i]; 1468 int (*func)(void *) = dip->func; 1469 if (func != NULL) { 1470 uint64_t bit = 1 << dip->bitno; 1471 if ((status & bit) != 0) { 1472 (void)(*func)(dip->arg); 1473 dip->counts[cpu_index(curcpu())].evcnt.ev_count++; 1474 rv = 1; 1475 } 1476 } 1477 } 1478 } 1479 1480 return rv; 1481 } 1482 1483 static void 1484 rmixl_pcie_link_error_intr(u_int link, uint32_t status0, uint32_t status1) 1485 { 1486 printf("%s: mask %#"PRIx64"\n", 1487 __func__, RMIXL_PCIE_LINK_STATUS_ERRORS); 1488 printf("%s: PCIe Link Error: link=%d status0=%#x status1=%#x\n", 1489 __func__, link, status0, status1); 1490 #if defined(DDB) && defined(DEBUG) 1491 Debugger(); 1492 #endif 1493 } 1494 1495 #if defined(DEBUG) || defined(DDB) 1496 /* this function exists to facilitate call from ddb */ 1497 int 1498 rmixl_pcie_error_check(void) 1499 { 1500 if (rmixl_pcie_v != 0) 1501 return _rmixl_pcie_error_check(rmixl_pcie_v); 1502 return -1; 1503 } 1504 #endif 1505 1506 STATIC int 1507 _rmixl_pcie_error_check(void *v) 1508 { 1509 int i, offset; 1510 pcireg_t r; 1511 pcitag_t tag; 1512 int err=0; 1513 #ifdef DIAGNOSTIC 1514 pcireg_t regs[PCIE_ECFG_ERRS_OFFTAB_NENTRIES]; 1515 #endif 1516 1517 tag = rmixl_pcie_make_tag(v, 0, 0, 0); /* XXX */ 1518 1519 for (i=0; i < PCIE_ECFG_ERRS_OFFTAB_NENTRIES; i++) { 1520 offset = pcie_ecfg_errs_tab[i].offset; 1521 r = rmixl_pcie_conf_read(v, tag, offset); 1522 #ifdef DIAGNOSTIC 1523 regs[i] = r; 1524 #endif 1525 if (r != 0) { 1526 pcireg_t rw1c = r & pcie_ecfg_errs_tab[i].rw1c; 1527 if (rw1c != 0) { 1528 /* attempt to clear the error */ 1529 rmixl_pcie_conf_write(v, tag, offset, rw1c); 1530 }; 1531 if (offset == RMIXL_PCIE_ECFG_CESR) 1532 err |= 1; /* correctable */ 1533 else 1534 err |= 2; /* uncorrectable */ 1535 } 1536 } 1537 #ifdef DIAGNOSTIC 1538 if (err != 0) { 1539 for (i=0; i < PCIE_ECFG_ERRS_OFFTAB_NENTRIES; i++) { 1540 offset = pcie_ecfg_errs_tab[i].offset; 1541 printf("%s: %#x: %#x\n", __func__, offset, regs[i]); 1542 } 1543 } 1544 #endif 1545 1546 return err; 1547 } 1548 1549 static int 1550 rmixl_pcie_error_intr(void *v) 1551 { 1552 if (_rmixl_pcie_error_check(v) < 2) 1553 return 0; /* correctable */ 1554 1555 /* uncorrectable */ 1556 #if DDB 1557 Debugger(); 1558 #endif 1559 1560 /* XXX reset and recover? */ 1561 1562 panic("%s\n", __func__); 1563 } 1564 1565 /* 1566 * rmixl_physaddr_init_pcie: 1567 * called from rmixl_physaddr_init to get region addrs & sizes 1568 * from PCIE CFG, ECFG, IO, MEM BARs 1569 */ 1570 void 1571 rmixl_physaddr_init_pcie(struct extent *ext) 1572 { 1573 struct rmixl_config * const rcp = &rmixl_configuration; 1574 uint32_t r; 1575 1576 r = RMIXL_IOREG_READ(RMIXLS_SBC_PCIE_CFG_BAR); 1577 if ((r & RMIXL_PCIE_CFG_BAR_ENB) != 0) { 1578 rmixl_physaddr_add(ext, "pcicfg", &rcp->rc_pci_cfg, 1579 (bus_addr_t)RMIXL_PCIE_CFG_BAR_TO_BA((uint64_t)r), 1580 (bus_size_t)RMIXL_PCIE_CFG_SIZE); 1581 DPRINTF(("%s: %s: %#"PRIx64":%"PRIu64" MB\n", __func__, 1582 "pci-cfg", rcp->rc_pci_cfg.r_pbase, 1583 rcp->rc_pci_cfg.r_size >> 20)); 1584 1585 } 1586 1587 r = RMIXL_IOREG_READ(RMIXLS_SBC_PCIE_ECFG_BAR); 1588 if ((r & RMIXL_PCIE_ECFG_BAR_ENB) != 0) { 1589 rmixl_physaddr_add(ext, "pciecfg", &rcp->rc_pci_ecfg, 1590 (bus_addr_t)RMIXL_PCIE_ECFG_BAR_TO_BA((uint64_t)r), 1591 (bus_size_t)RMIXL_PCIE_ECFG_SIZE); 1592 DPRINTF(("%s: %s: %#"PRIx64":%"PRIu64" MB\n", __func__, 1593 "pci-ecfg", rcp->rc_pci_ecfg.r_pbase, 1594 rcp->rc_pci_ecfg.r_size >> 20)); 1595 } 1596 1597 r = RMIXL_IOREG_READ(RMIXLS_SBC_PCIE_MEM_BAR); 1598 if ((r & RMIXL_PCIE_MEM_BAR_ENB) != 0) { 1599 rmixl_physaddr_add(ext, "pcimem", &rcp->rc_pci_mem, 1600 (bus_addr_t)RMIXL_PCIE_MEM_BAR_TO_BA((uint64_t)r), 1601 (bus_size_t)RMIXL_PCIE_MEM_BAR_TO_SIZE((uint64_t)r)); 1602 DPRINTF(("%s: %s: %#"PRIx64":%"PRIu64" MB\n", __func__, 1603 "pci-mem", rcp->rc_pci_mem.r_pbase, 1604 rcp->rc_pci_mem.r_size >> 20)); 1605 } 1606 1607 r = RMIXL_IOREG_READ(RMIXLS_SBC_PCIE_IO_BAR); 1608 if ((r & RMIXL_PCIE_IO_BAR_ENB) != 0) { 1609 rmixl_physaddr_add(ext, "pciio", &rcp->rc_pci_io, 1610 (bus_addr_t)RMIXL_PCIE_IO_BAR_TO_BA((uint64_t)r), 1611 (bus_size_t)RMIXL_PCIE_IO_BAR_TO_SIZE((uint64_t)r)); 1612 DPRINTF(("%s: %s: %#"PRIx64":%"PRIu64" MB\n", __func__, 1613 "pci-io", rcp->rc_pci_io.r_pbase, 1614 rcp->rc_pci_io.r_size >> 20)); 1615 } 1616 } 1617
Indexes created Wed Oct 22 13:09:56 GMT 2025