rmixl_pcie.c revision 1.12
1 /* $NetBSD: rmixl_pcie.c,v 1.12 2015/10/02 05:22:51 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * PCI configuration support for RMI XLS SoC 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: rmixl_pcie.c,v 1.12 2015/10/02 05:22:51 msaitoh Exp $"); 44 45 #include "opt_pci.h" 46 #include "pci.h" 47 48 #include <sys/cdefs.h> 49 50 #include <sys/param.h> 51 #include <sys/bus.h> 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/extent.h> 55 #include <sys/intr.h> 56 #include <sys/kernel.h> /* for 'hz' */ 57 #include <sys/malloc.h> 58 #include <sys/systm.h> 59 60 #include <uvm/uvm_extern.h> 61 62 #include <mips/rmi/rmixlreg.h> 63 #include <mips/rmi/rmixlvar.h> 64 #include <mips/rmi/rmixl_intr.h> 65 #include <mips/rmi/rmixl_pcievar.h> 66 67 #include <mips/rmi/rmixl_obiovar.h> 68 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pcidevs.h> 71 #include <dev/pci/pciconf.h> 72 73 #ifdef PCI_NETBSD_CONFIGURE 74 #include <mips/cache.h> 75 #endif 76 77 #ifdef PCI_DEBUG 78 int rmixl_pcie_debug = PCI_DEBUG; 79 # define DPRINTF(x) do { if (rmixl_pcie_debug) printf x ; } while (0) 80 #else 81 # define DPRINTF(x) 82 #endif 83 84 #ifndef DDB 85 # define STATIC static 86 #else 87 # define STATIC 88 #endif 89 90 91 /* 92 * XLS PCIe Extended Configuration Registers 93 */ 94 #define RMIXL_PCIE_ECFG_UESR 0x104 /* Uncorrectable Error Status Reg */ 95 #define RMIXL_PCIE_ECFG_UEMR 0x108 /* Uncorrectable Error Mask Reg */ 96 #define RMIXL_PCIE_ECFG_UEVR 0x10c /* Uncorrectable Error seVerity Reg */ 97 #define PCIE_ECFG_UEVR_DFLT \ 98 (__BITS(18,17) | __BIT(31) | __BITS(5,4) | __BIT(0)) 99 #define PCIE_ECFG_UExR_RESV (__BITS(31,21) | __BITS(11,6) | __BITS(3,1)) 100 #define RMIXL_PCIE_ECFG_CESR 0x110 /* Correctable Error Status Reg */ 101 #define RMIXL_PCIE_ECFG_CEMR 0x114 /* Correctable Error Mask Reg */ 102 #define PCIE_ECFG_CExR_RESV (__BITS(31,14) | __BITS(11,9) | __BITS(5,1)) 103 #define RMIXL_PCIE_ECFG_ACCR 0x118 /* Adv. Capabilities Control Reg */ 104 #define RMIXL_PCIE_ECFG_HLRn(n) (0x11c + ((n) * 4)) /* Header Log Regs */ 105 #define RMIXL_PCIE_ECFG_RECR 0x12c /* Root Error Command Reg */ 106 #define PCIE_ECFG_RECR_RESV __BITS(31,3) 107 #define RMIXL_PCIE_ECFG_RESR 0x130 /* Root Error Status Reg */ 108 #define PCIE_ECFG_RESR_RESV __BITS(26,7) 109 #define RMIXL_PCIE_ECFG_ESI 0x134 /* Error Source Identification Reg */ 110 #define RMIXL_PCIE_ECFG_DSNCR 0x140 /* Dev Serial Number Capability Regs */ 111 112 static const struct { 113 u_int offset; 114 u_int32_t rw1c; 115 } pcie_ecfg_errs_tab[] = { 116 { RMIXL_PCIE_ECFG_UESR, (__BITS(20,12) | __BIT(4)) }, 117 { RMIXL_PCIE_ECFG_CESR, (__BITS(20,12) | __BIT(4)) }, 118 { RMIXL_PCIE_ECFG_HLRn(0), 0 }, 119 { RMIXL_PCIE_ECFG_HLRn(1), 0 }, 120 { RMIXL_PCIE_ECFG_HLRn(2), 0 }, 121 { RMIXL_PCIE_ECFG_HLRn(3), 0 }, 122 { RMIXL_PCIE_ECFG_RESR, __BITS(6,0) }, 123 { RMIXL_PCIE_ECFG_ESI, 0 }, 124 }; 125 #define PCIE_ECFG_ERRS_OFFTAB_NENTRIES \ 126 (sizeof(pcie_ecfg_errs_tab)/sizeof(pcie_ecfg_errs_tab[0])) 127 128 typedef struct rmixl_pcie_int_csr { 129 uint r0; 130 uint r1; 131 } rmixl_pcie_int_csr_t; 132 133 static const rmixl_pcie_int_csr_t int_enb_offset[4] = { 134 { RMIXL_PCIE_LINK0_INT_ENABLE0, RMIXL_PCIE_LINK0_INT_ENABLE1 }, 135 { RMIXL_PCIE_LINK1_INT_ENABLE0, RMIXL_PCIE_LINK1_INT_ENABLE1 }, 136 { RMIXL_PCIE_LINK2_INT_ENABLE0, RMIXL_PCIE_LINK2_INT_ENABLE1 }, 137 { RMIXL_PCIE_LINK3_INT_ENABLE0, RMIXL_PCIE_LINK3_INT_ENABLE1 }, 138 }; 139 140 static const rmixl_pcie_int_csr_t int_sts_offset[4] = { 141 { RMIXL_PCIE_LINK0_INT_STATUS0, RMIXL_PCIE_LINK0_INT_STATUS1 }, 142 { RMIXL_PCIE_LINK1_INT_STATUS0, RMIXL_PCIE_LINK1_INT_STATUS1 }, 143 { RMIXL_PCIE_LINK2_INT_STATUS0, RMIXL_PCIE_LINK2_INT_STATUS1 }, 144 { RMIXL_PCIE_LINK3_INT_STATUS0, RMIXL_PCIE_LINK3_INT_STATUS1 }, 145 }; 146 147 static const u_int msi_enb_offset[4] = { 148 RMIXL_PCIE_LINK0_MSI_ENABLE, 149 RMIXL_PCIE_LINK1_MSI_ENABLE, 150 RMIXL_PCIE_LINK2_MSI_ENABLE, 151 RMIXL_PCIE_LINK3_MSI_ENABLE 152 }; 153 154 #define RMIXL_PCIE_LINK_STATUS0_ERRORS __BITS(6,4) 155 #define RMIXL_PCIE_LINK_STATUS1_ERRORS __BITS(10,0) 156 #define RMIXL_PCIE_LINK_STATUS_ERRORS \ 157 ((((uint64_t)RMIXL_PCIE_LINK_STATUS1_ERRORS) << 32) | \ 158 (uint64_t)RMIXL_PCIE_LINK_STATUS0_ERRORS) 159 160 #define RMIXL_PCIE_EVCNT(sc, link, bitno, cpu) \ 161 &(sc)->sc_evcnts[link][(bitno) * (ncpu) + (cpu)] 162 163 static int rmixl_pcie_match(device_t, cfdata_t, void *); 164 static void rmixl_pcie_attach(device_t, device_t, void *); 165 static void rmixl_pcie_init(struct rmixl_pcie_softc *); 166 static void rmixl_pcie_init_ecfg(struct rmixl_pcie_softc *); 167 static void rmixl_pcie_attach_hook(device_t, device_t, 168 struct pcibus_attach_args *); 169 static void rmixl_pcie_lnkcfg_4xx(rmixl_pcie_lnktab_t *, uint32_t); 170 static void rmixl_pcie_lnkcfg_408Lite(rmixl_pcie_lnktab_t *, uint32_t); 171 static void rmixl_pcie_lnkcfg_2xx(rmixl_pcie_lnktab_t *, uint32_t); 172 static void rmixl_pcie_lnkcfg_1xx(rmixl_pcie_lnktab_t *, uint32_t); 173 static void rmixl_pcie_lnkcfg(struct rmixl_pcie_softc *); 174 static void rmixl_pcie_intcfg(struct rmixl_pcie_softc *); 175 static void rmixl_pcie_errata(struct rmixl_pcie_softc *); 176 static void rmixl_conf_interrupt(void *, int, int, int, int, int *); 177 static int rmixl_pcie_bus_maxdevs(void *, int); 178 static pcitag_t rmixl_tag_to_ecfg(pcitag_t); 179 static pcitag_t rmixl_pcie_make_tag(void *, int, int, int); 180 static void rmixl_pcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 181 void rmixl_pcie_tag_print(const char *restrict, void *, pcitag_t, int, vaddr_t, u_long); 182 static int rmixl_pcie_conf_setup(struct rmixl_pcie_softc *, 183 pcitag_t, int *, bus_space_tag_t *, 184 bus_space_handle_t *); 185 static pcireg_t rmixl_pcie_conf_read(void *, pcitag_t, int); 186 static void rmixl_pcie_conf_write(void *, pcitag_t, int, pcireg_t); 187 188 static int rmixl_pcie_intr_map(const struct pci_attach_args *, 189 pci_intr_handle_t *); 190 static const char * 191 rmixl_pcie_intr_string(void *, pci_intr_handle_t, char *, 192 size_t); 193 static const struct evcnt * 194 rmixl_pcie_intr_evcnt(void *, pci_intr_handle_t); 195 static pci_intr_handle_t 196 rmixl_pcie_make_pih(u_int, u_int, u_int); 197 static void rmixl_pcie_decompose_pih(pci_intr_handle_t, u_int *, u_int *, u_int *); 198 static void rmixl_pcie_intr_disestablish(void *, void *); 199 static void *rmixl_pcie_intr_establish(void *, pci_intr_handle_t, 200 int, int (*)(void *), void *); 201 static rmixl_pcie_link_intr_t * 202 rmixl_pcie_lip_add_1(rmixl_pcie_softc_t *, u_int, int, int); 203 static void rmixl_pcie_lip_free_callout(rmixl_pcie_link_intr_t *); 204 static void rmixl_pcie_lip_free(void *); 205 static int rmixl_pcie_intr(void *); 206 static void rmixl_pcie_link_error_intr(u_int, uint32_t, uint32_t); 207 #if defined(DEBUG) || defined(DDB) 208 int rmixl_pcie_error_check(void); 209 #endif 210 static int _rmixl_pcie_error_check(void *); 211 static int rmixl_pcie_error_intr(void *); 212 213 214 #define RMIXL_PCIE_CONCAT3(a,b,c) a ## b ## c 215 #define RMIXL_PCIE_BAR_INIT(reg, bar, size, align) { \ 216 struct extent *ext = rmixl_configuration.rc_phys_ex; \ 217 u_long region_start; \ 218 uint64_t ba; \ 219 int err; \ 220 \ 221 err = extent_alloc(ext, (size), (align), 0UL, EX_NOWAIT, \ 222 ®ion_start); \ 223 if (err != 0) \ 224 panic("%s: extent_alloc(%p, %#lx, %#lx, %#lx, %#x, %p)",\ 225 __func__, ext, size, align, 0UL, EX_NOWAIT, \ 226 ®ion_start); \ 227 ba = (uint64_t)region_start; \ 228 ba *= (1024 * 1024); \ 229 bar = RMIXL_PCIE_CONCAT3(RMIXL_PCIE_,reg,_BAR)(ba, 1); \ 230 DPRINTF(("PCIE %s BAR was not enabled by firmware\n" \ 231 "enabling %s at phys %#" PRIxBUSADDR ", size %lu MB\n", \ 232 __STRING(reg), __STRING(reg), ba, size)); \ 233 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_BRIDGE + \ 234 RMIXL_PCIE_CONCAT3(RMIXLS_SBC_PCIE_,reg,_BAR), bar); \ 235 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + \ 236 RMIXL_PCIE_CONCAT3(RMIXLS_SBC_PCIE_,reg,_BAR)); \ 237 DPRINTF(("%s: %s BAR %#x\n", __func__, __STRING(reg), bar)); \ 238 } 239 240 241 #if defined(DEBUG) || defined(DDB) 242 static void *rmixl_pcie_v; 243 #endif 244 245 CFATTACH_DECL_NEW(rmixl_pcie, sizeof(struct rmixl_pcie_softc), 246 rmixl_pcie_match, rmixl_pcie_attach, NULL, NULL); 247 248 static int rmixl_pcie_found; 249 250 static int 251 rmixl_pcie_match(device_t parent, cfdata_t cf, void *aux) 252 { 253 uint32_t r; 254 255 /* 256 * PCIe interface exists on XLS chips only 257 */ 258 if (! cpu_rmixls(mips_options.mips_cpu)) 259 return 0; 260 261 /* XXX 262 * for now there is only one PCIe Interface on chip 263 * this could change with furture RMI XL family designs 264 */ 265 if (rmixl_pcie_found) 266 return 0; 267 268 /* read GPIO Reset Configuration register */ 269 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET_CFG); 270 r >>= 26; 271 r &= 3; 272 if (r != 0) 273 return 0; /* strapped for SRIO */ 274 275 return 1; 276 } 277 278 static void 279 rmixl_pcie_attach(device_t parent, device_t self, void *aux) 280 { 281 struct rmixl_pcie_softc *sc = device_private(self); 282 struct obio_attach_args *obio = aux; 283 struct rmixl_config *rcp = &rmixl_configuration; 284 struct pcibus_attach_args pba; 285 uint32_t bar; 286 287 rmixl_pcie_found = 1; 288 sc->sc_dev = self; 289 290 aprint_normal(" RMI XLS PCIe Interface\n"); 291 292 mutex_init(&sc->sc_mutex, MUTEX_DEFAULT, IPL_HIGH); 293 294 rmixl_pcie_lnkcfg(sc); 295 296 rmixl_pcie_intcfg(sc); 297 298 rmixl_pcie_errata(sc); 299 300 sc->sc_29bit_dmat = obio->obio_29bit_dmat; 301 sc->sc_32bit_dmat = obio->obio_32bit_dmat; 302 sc->sc_64bit_dmat = obio->obio_64bit_dmat; 303 304 sc->sc_tmsk = obio->obio_tmsk; 305 306 /* 307 * get PCI config space base addr from SBC PCIe CFG BAR 308 * initialize it if necessary 309 */ 310 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLS_SBC_PCIE_CFG_BAR); 311 DPRINTF(("%s: PCIE_CFG_BAR %#x\n", __func__, bar)); 312 if ((bar & RMIXL_PCIE_CFG_BAR_ENB) == 0) { 313 u_long n = RMIXL_PCIE_CFG_SIZE / (1024 * 1024); 314 RMIXL_PCIE_BAR_INIT(CFG, bar, n, n); 315 } 316 rcp->rc_pci_cfg_pbase = (bus_addr_t)RMIXL_PCIE_CFG_BAR_TO_BA(bar); 317 rcp->rc_pci_cfg_size = (bus_size_t)RMIXL_PCIE_CFG_SIZE; 318 319 /* 320 * get PCIE Extended config space base addr from SBC PCIe ECFG BAR 321 * initialize it if necessary 322 */ 323 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLS_SBC_PCIE_ECFG_BAR); 324 DPRINTF(("%s: PCIE_ECFG_BAR %#x\n", __func__, bar)); 325 if ((bar & RMIXL_PCIE_ECFG_BAR_ENB) == 0) { 326 u_long n = RMIXL_PCIE_ECFG_SIZE / (1024 * 1024); 327 RMIXL_PCIE_BAR_INIT(ECFG, bar, n, n); 328 } 329 rcp->rc_pci_ecfg_pbase = (bus_addr_t)RMIXL_PCIE_ECFG_BAR_TO_BA(bar); 330 rcp->rc_pci_ecfg_size = (bus_size_t)RMIXL_PCIE_ECFG_SIZE; 331 332 /* 333 * get PCI MEM space base [addr, size] from SBC PCIe MEM BAR 334 * initialize it if necessary 335 */ 336 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLS_SBC_PCIE_MEM_BAR); 337 DPRINTF(("%s: PCIE_MEM_BAR %#x\n", __func__, bar)); 338 if ((bar & RMIXL_PCIE_MEM_BAR_ENB) == 0) { 339 u_long n = 256; /* 256 MB */ 340 RMIXL_PCIE_BAR_INIT(MEM, bar, n, n); 341 } 342 rcp->rc_pci_mem_pbase = (bus_addr_t)RMIXL_PCIE_MEM_BAR_TO_BA(bar); 343 rcp->rc_pci_mem_size = (bus_size_t)RMIXL_PCIE_MEM_BAR_TO_SIZE(bar); 344 345 /* 346 * get PCI IO space base [addr, size] from SBC PCIe IO BAR 347 * initialize it if necessary 348 */ 349 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLS_SBC_PCIE_IO_BAR); 350 DPRINTF(("%s: PCIE_IO_BAR %#x\n", __func__, bar)); 351 if ((bar & RMIXL_PCIE_IO_BAR_ENB) == 0) { 352 u_long n = 32; /* 32 MB */ 353 RMIXL_PCIE_BAR_INIT(IO, bar, n, n); 354 } 355 rcp->rc_pci_io_pbase = (bus_addr_t)RMIXL_PCIE_IO_BAR_TO_BA(bar); 356 rcp->rc_pci_io_size = (bus_size_t)RMIXL_PCIE_IO_BAR_TO_SIZE(bar); 357 358 /* 359 * initialize the PCI CFG, ECFG bus space tags 360 */ 361 rmixl_pci_cfg_bus_mem_init(&rcp->rc_pci_cfg_memt, rcp); 362 sc->sc_pci_cfg_memt = &rcp->rc_pci_cfg_memt; 363 364 rmixl_pci_ecfg_bus_mem_init(&rcp->rc_pci_ecfg_memt, rcp); 365 sc->sc_pci_ecfg_memt = &rcp->rc_pci_ecfg_memt; 366 367 /* 368 * initialize the PCI MEM and IO bus space tags 369 */ 370 rmixl_pci_bus_mem_init(&rcp->rc_pci_memt, rcp); 371 rmixl_pci_bus_io_init(&rcp->rc_pci_iot, rcp); 372 373 /* 374 * initialize the extended configuration regs 375 */ 376 rmixl_pcie_init_ecfg(sc); 377 378 /* 379 * initialize the PCI chipset tag 380 */ 381 rmixl_pcie_init(sc); 382 383 /* 384 * attach the PCI bus 385 */ 386 memset(&pba, 0, sizeof(pba)); 387 pba.pba_memt = &rcp->rc_pci_memt; 388 pba.pba_iot = &rcp->rc_pci_iot; 389 pba.pba_dmat = sc->sc_32bit_dmat; 390 pba.pba_dmat64 = sc->sc_64bit_dmat; 391 pba.pba_pc = &sc->sc_pci_chipset; 392 pba.pba_bus = 0; 393 pba.pba_bridgetag = NULL; 394 pba.pba_intrswiz = 0; 395 pba.pba_intrtag = 0; 396 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY | 397 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 398 399 (void) config_found_ia(self, "pcibus", &pba, pcibusprint); 400 } 401 402 /* 403 * rmixl_pcie_lnkcfg_4xx - link configs for XLS4xx and XLS6xx 404 * use IO_AD[11] and IO_AD[10], observable in 405 * Bits[21:20] of the GPIO Reset Configuration register 406 */ 407 static void 408 rmixl_pcie_lnkcfg_4xx(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 409 { 410 u_int index; 411 static const rmixl_pcie_lnkcfg_t lnktab_4xx[4][4] = { 412 {{ LCFG_EP, 4}, {LCFG_NO, 0}, {LCFG_NO, 0}, {LCFG_NO, 0}}, 413 {{ LCFG_RC, 4}, {LCFG_NO, 0}, {LCFG_NO, 0}, {LCFG_NO, 0}}, 414 {{ LCFG_EP, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}}, 415 {{ LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}}, 416 }; 417 static const char *lnkstr_4xx[4] = { 418 "1EPx4", 419 "1RCx4", 420 "1EPx1, 3RCx1", 421 "4RCx1" 422 }; 423 index = (grcr >> 20) & 3; 424 ltp->ncfgs = 4; 425 ltp->cfg = lnktab_4xx[index]; 426 ltp->str = lnkstr_4xx[index]; 427 } 428 429 /* 430 * rmixl_pcie_lnkcfg_408Lite - link configs for XLS408Lite and XLS04A 431 * use IO_AD[11] and IO_AD[10], observable in 432 * Bits[21:20] of the GPIO Reset Configuration register 433 */ 434 static void 435 rmixl_pcie_lnkcfg_408Lite(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 436 { 437 u_int index; 438 static const rmixl_pcie_lnkcfg_t lnktab_408Lite[4][2] = { 439 {{ LCFG_EP, 4}, {LCFG_NO, 0}}, 440 {{ LCFG_RC, 4}, {LCFG_NO, 0}}, 441 {{ LCFG_EP, 1}, {LCFG_RC, 1}}, 442 {{ LCFG_RC, 1}, {LCFG_RC, 1}}, 443 }; 444 static const char *lnkstr_408Lite[4] = { 445 "4EPx4", 446 "1RCx4", 447 "1EPx1, 1RCx1", 448 "2RCx1" 449 }; 450 451 index = (grcr >> 20) & 3; 452 ltp->ncfgs = 2; 453 ltp->cfg = lnktab_408Lite[index]; 454 ltp->str = lnkstr_408Lite[index]; 455 } 456 457 /* 458 * rmixl_pcie_lnkcfg_2xx - link configs for XLS2xx 459 * use IO_AD[10], observable in Bit[20] of the 460 * GPIO Reset Configuration register 461 */ 462 static void 463 rmixl_pcie_lnkcfg_2xx(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 464 { 465 u_int index; 466 static const rmixl_pcie_lnkcfg_t lnktab_2xx[2][4] = { 467 {{ LCFG_EP, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}}, 468 {{ LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}} 469 }; 470 static const char *lnkstr_2xx[2] = { 471 "1EPx1, 3RCx1", 472 "4RCx1", 473 }; 474 475 index = (grcr >> 20) & 1; 476 ltp->ncfgs = 4; 477 ltp->cfg = lnktab_2xx[index]; 478 ltp->str = lnkstr_2xx[index]; 479 } 480 481 /* 482 * rmixl_pcie_lnkcfg_1xx - link configs for XLS1xx 483 * use IO_AD[10], observable in Bit[20] of the 484 * GPIO Reset Configuration register 485 */ 486 static void 487 rmixl_pcie_lnkcfg_1xx(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 488 { 489 u_int index; 490 static const rmixl_pcie_lnkcfg_t lnktab_1xx[2][2] = { 491 {{ LCFG_EP, 1}, {LCFG_RC, 1}}, 492 {{ LCFG_RC, 1}, {LCFG_RC, 1}} 493 }; 494 static const char *lnkstr_1xx[2] = { 495 "1EPx1, 1RCx1", 496 "2RCx1", 497 }; 498 499 index = (grcr >> 20) & 1; 500 ltp->ncfgs = 2; 501 ltp->cfg = lnktab_1xx[index]; 502 ltp->str = lnkstr_1xx[index]; 503 } 504 505 /* 506 * rmixl_pcie_lnkcfg - determine PCI Express Link Configuration 507 */ 508 static void 509 rmixl_pcie_lnkcfg(struct rmixl_pcie_softc *sc) 510 { 511 uint32_t r; 512 513 /* read GPIO Reset Configuration register */ 514 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET_CFG); 515 DPRINTF(("%s: GPIO RCR %#x\n", __func__, r)); 516 517 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 518 case MIPS_XLS104: 519 case MIPS_XLS108: 520 rmixl_pcie_lnkcfg_1xx(&sc->sc_pcie_lnktab, r); 521 break; 522 case MIPS_XLS204: 523 case MIPS_XLS208: 524 rmixl_pcie_lnkcfg_2xx(&sc->sc_pcie_lnktab, r); 525 break; 526 case MIPS_XLS404LITE: 527 case MIPS_XLS408LITE: 528 rmixl_pcie_lnkcfg_408Lite(&sc->sc_pcie_lnktab, r); 529 break; 530 case MIPS_XLS404: 531 case MIPS_XLS408: 532 case MIPS_XLS416: 533 case MIPS_XLS608: 534 case MIPS_XLS616: 535 /* 6xx uses same table as 4xx */ 536 rmixl_pcie_lnkcfg_4xx(&sc->sc_pcie_lnktab, r); 537 break; 538 default: 539 panic("%s: unknown RMI PRID IMPL", __func__); 540 } 541 542 aprint_normal("%s: link config %s\n", 543 device_xname(sc->sc_dev), sc->sc_pcie_lnktab.str); 544 } 545 546 /* 547 * rmixl_pcie_intcfg - init PCIe Link interrupt enables 548 */ 549 static void 550 rmixl_pcie_intcfg(struct rmixl_pcie_softc *sc) 551 { 552 int link; 553 size_t size; 554 rmixl_pcie_evcnt_t *ev; 555 556 DPRINTF(("%s: disable all link interrupts\n", __func__)); 557 for (link=0; link < sc->sc_pcie_lnktab.ncfgs; link++) { 558 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + int_enb_offset[link].r0, 559 RMIXL_PCIE_LINK_STATUS0_ERRORS); 560 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + int_enb_offset[link].r1, 561 RMIXL_PCIE_LINK_STATUS1_ERRORS); 562 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + msi_enb_offset[link], 0); 563 sc->sc_link_intr[link] = NULL; 564 565 /* 566 * allocate per-cpu, per-pin interrupt event counters 567 */ 568 size = ncpu * PCI_INTERRUPT_PIN_MAX * sizeof(rmixl_pcie_evcnt_t); 569 ev = malloc(size, M_DEVBUF, M_NOWAIT); 570 if (ev == NULL) 571 panic("%s: cannot malloc evcnts\n", __func__); 572 sc->sc_evcnts[link] = ev; 573 for (int pin=PCI_INTERRUPT_PIN_A; pin <= PCI_INTERRUPT_PIN_MAX; pin++) { 574 for (int cpu=0; cpu < ncpu; cpu++) { 575 ev = RMIXL_PCIE_EVCNT(sc, link, pin - 1, cpu); 576 snprintf(ev->name, sizeof(ev->name), 577 "cpu%d, link %d, pin %d", cpu, link, pin); 578 evcnt_attach_dynamic(&ev->evcnt, EVCNT_TYPE_INTR, 579 NULL, "rmixl_pcie", ev->name); 580 } 581 } 582 } 583 } 584 585 static void 586 rmixl_pcie_errata(struct rmixl_pcie_softc *sc) 587 { 588 const mips_prid_t cpu_id = mips_options.mips_cpu_id; 589 u_int rev; 590 u_int lanes; 591 bool e391 = false; 592 593 /* 594 * 3.9.1 PCIe Link-0 Registers Reset to Incorrect Values 595 * check if it allies to this CPU implementation and revision 596 */ 597 rev = MIPS_PRID_REV(cpu_id); 598 switch (MIPS_PRID_IMPL(cpu_id)) { 599 case MIPS_XLS104: 600 case MIPS_XLS108: 601 break; 602 case MIPS_XLS204: 603 case MIPS_XLS208: 604 /* stepping A0 is affected */ 605 if (rev == 0) 606 e391 = true; 607 break; 608 case MIPS_XLS404LITE: 609 case MIPS_XLS408LITE: 610 break; 611 case MIPS_XLS404: 612 case MIPS_XLS408: 613 case MIPS_XLS416: 614 /* steppings A0 and A1 are affected */ 615 if ((rev == 0) || (rev == 1)) 616 e391 = true; 617 break; 618 case MIPS_XLS608: 619 case MIPS_XLS616: 620 break; 621 default: 622 panic("unknown RMI PRID IMPL"); 623 } 624 625 /* 626 * for XLS we only need to check entry #0 627 * this may need to change for later XL family chips 628 */ 629 lanes = sc->sc_pcie_lnktab.cfg[0].lanes; 630 631 if ((e391 != false) && ((lanes == 2) || (lanes == 4))) { 632 /* 633 * attempt work around for errata 3.9.1 634 * "PCIe Link-0 Registers Reset to Incorrect Values" 635 * the registers are write-once: if the firmware already wrote, 636 * then our writes are ignored; hope they did it right. 637 */ 638 uint32_t queuectrl; 639 uint32_t bufdepth; 640 #ifdef DIAGNOSTIC 641 uint32_t r; 642 #endif 643 644 aprint_normal("%s: attempt work around for errata 3.9.1", 645 device_xname(sc->sc_dev)); 646 if (lanes == 4) { 647 queuectrl = 0x00018074; 648 bufdepth = 0x001901D1; 649 } else { 650 queuectrl = 0x00018036; 651 bufdepth = 0x001900D9; 652 } 653 654 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_BE + 655 RMIXL_VC0_POSTED_RX_QUEUE_CTRL, queuectrl); 656 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_BE + 657 RMIXL_VC0_POSTED_BUFFER_DEPTH, bufdepth); 658 659 #ifdef DIAGNOSTIC 660 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_BE + 661 RMIXL_VC0_POSTED_RX_QUEUE_CTRL); 662 printf("\nVC0_POSTED_RX_QUEUE_CTRL %#x\n", r); 663 664 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_BE + 665 RMIXL_VC0_POSTED_BUFFER_DEPTH); 666 printf("VC0_POSTED_BUFFER_DEPTH %#x\n", r); 667 #endif 668 } 669 } 670 671 static void 672 rmixl_pcie_init(struct rmixl_pcie_softc *sc) 673 { 674 pci_chipset_tag_t pc = &sc->sc_pci_chipset; 675 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 676 struct extent *ioext, *memext; 677 #endif 678 679 pc->pc_conf_v = (void *)sc; 680 pc->pc_attach_hook = rmixl_pcie_attach_hook; 681 pc->pc_bus_maxdevs = rmixl_pcie_bus_maxdevs; 682 pc->pc_make_tag = rmixl_pcie_make_tag; 683 pc->pc_decompose_tag = rmixl_pcie_decompose_tag; 684 pc->pc_conf_read = rmixl_pcie_conf_read; 685 pc->pc_conf_write = rmixl_pcie_conf_write; 686 687 pc->pc_intr_v = (void *)sc; 688 pc->pc_intr_map = rmixl_pcie_intr_map; 689 pc->pc_intr_string = rmixl_pcie_intr_string; 690 pc->pc_intr_evcnt = rmixl_pcie_intr_evcnt; 691 pc->pc_intr_establish = rmixl_pcie_intr_establish; 692 pc->pc_intr_disestablish = rmixl_pcie_intr_disestablish; 693 pc->pc_conf_interrupt = rmixl_conf_interrupt; 694 695 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 696 /* 697 * Configure the PCI bus. 698 */ 699 struct rmixl_config *rcp = &rmixl_configuration; 700 701 aprint_normal("%s: configuring PCI bus\n", 702 device_xname(sc->sc_dev)); 703 704 ioext = extent_create("pciio", 705 rcp->rc_pci_io_pbase, 706 rcp->rc_pci_io_pbase + rcp->rc_pci_io_size - 1, 707 NULL, 0, EX_NOWAIT); 708 709 memext = extent_create("pcimem", 710 rcp->rc_pci_mem_pbase, 711 rcp->rc_pci_mem_pbase + rcp->rc_pci_mem_size - 1, 712 NULL, 0, EX_NOWAIT); 713 714 pci_configure_bus(pc, ioext, memext, NULL, 0, 715 mips_cache_info.mci_dcache_align); 716 717 extent_destroy(ioext); 718 extent_destroy(memext); 719 #endif 720 } 721 722 static void 723 rmixl_pcie_init_ecfg(struct rmixl_pcie_softc *sc) 724 { 725 void *v; 726 pcitag_t tag; 727 pcireg_t r; 728 729 v = sc; 730 tag = rmixl_pcie_make_tag(v, 0, 0, 0); 731 732 #ifdef PCI_DEBUG 733 int i, offset; 734 static const int offtab[] = 735 { 0, 4, 8, 0xc, 0x10, 0x14, 0x18, 0x1c, 736 0x2c, 0x30, 0x34 }; 737 for (i=0; i < sizeof(offtab)/sizeof(offtab[0]); i++) { 738 offset = 0x100 + offtab[i]; 739 r = rmixl_pcie_conf_read(v, tag, offset); 740 printf("%s: %#x: %#x\n", __func__, offset, r); 741 } 742 #endif 743 r = rmixl_pcie_conf_read(v, tag, 0x100); 744 if (r == -1) 745 return; /* cannot access */ 746 747 /* check pre-existing uncorrectable errs */ 748 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_UESR); 749 r &= ~PCIE_ECFG_UExR_RESV; 750 if (r != 0) 751 panic("%s: Uncorrectable Error Status: %#x\n", 752 __func__, r); 753 754 /* unmask all uncorrectable errs */ 755 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_UEMR); 756 r &= ~PCIE_ECFG_UExR_RESV; 757 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_UEMR, r); 758 759 /* ensure default uncorrectable err severity confniguration */ 760 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_UEVR); 761 r &= ~PCIE_ECFG_UExR_RESV; 762 r |= PCIE_ECFG_UEVR_DFLT; 763 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_UEVR, r); 764 765 /* check pre-existing correctable errs */ 766 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_CESR); 767 r &= ~PCIE_ECFG_CExR_RESV; 768 #ifdef DIAGNOSTIC 769 if (r != 0) 770 aprint_normal("%s: Correctable Error Status: %#x\n", 771 device_xname(sc->sc_dev), r); 772 #endif 773 774 /* unmask all correctable errs */ 775 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_CEMR); 776 r &= ~PCIE_ECFG_CExR_RESV; 777 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_UEMR, r); 778 779 /* check pre-existing Root Error Status */ 780 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_RESR); 781 r &= ~PCIE_ECFG_RESR_RESV; 782 if (r != 0) 783 panic("%s: Root Error Status: %#x\n", __func__, r); 784 /* XXX TMP FIXME */ 785 786 /* enable all Root errs */ 787 r = (pcireg_t)(~PCIE_ECFG_RECR_RESV); 788 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_RECR, r); 789 790 /* 791 * establish ISR for PCIE Fatal Error interrupt 792 * - for XLS4xxLite, XLS2xx, XLS1xx only 793 */ 794 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 795 case MIPS_XLS104: 796 case MIPS_XLS108: 797 case MIPS_XLS204: 798 case MIPS_XLS208: 799 case MIPS_XLS404LITE: 800 case MIPS_XLS408LITE: 801 sc->sc_fatal_ih = rmixl_intr_establish(29, sc->sc_tmsk, 802 IPL_HIGH, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH, 803 rmixl_pcie_error_intr, v, false); 804 break; 805 default: 806 break; 807 } 808 809 #if defined(DEBUG) || defined(DDB) 810 rmixl_pcie_v = v; 811 #endif 812 } 813 814 void 815 rmixl_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *iline) 816 { 817 DPRINTF(("%s: %p, %d, %d, %d, %d, %p\n", 818 __func__, v, bus, dev, ipin, swiz, iline)); 819 } 820 821 void 822 rmixl_pcie_attach_hook(device_t parent, device_t self, 823 struct pcibus_attach_args *pba) 824 { 825 DPRINTF(("%s: pba_bus %d, pba_bridgetag %p, pc_conf_v %p\n", 826 __func__, pba->pba_bus, pba->pba_bridgetag, 827 pba->pba_pc->pc_conf_v)); 828 } 829 830 int 831 rmixl_pcie_bus_maxdevs(void *v, int busno) 832 { 833 return (32); /* XXX depends on the family of XLS SoC */ 834 } 835 836 /* 837 * rmixl_tag_to_ecfg - convert cfg address (generic tag) to ecfg address 838 * 839 * 39:29 (reserved) 840 * 28 Swap (0=little, 1=big endian) 841 * 27:20 Bus number 842 * 19:15 Device number 843 * 14:12 Function number 844 * 11:8 Extended Register number 845 * 7:0 Register number 846 */ 847 static pcitag_t 848 rmixl_tag_to_ecfg(pcitag_t tag) 849 { 850 KASSERT((tag & __BITS(7,0)) == 0); 851 return (tag << 4); 852 } 853 854 /* 855 * XLS pci tag is a 40 bit address composed thusly: 856 * 39:25 (reserved) 857 * 24 Swap (0=little, 1=big endian) 858 * 23:16 Bus number 859 * 15:11 Device number 860 * 10:8 Function number 861 * 7:0 Register number 862 * 863 * Note: this is the "native" composition for addressing CFG space, but not for ECFG space. 864 */ 865 pcitag_t 866 rmixl_pcie_make_tag(void *v, int bus, int dev, int fun) 867 { 868 return ((bus << 16) | (dev << 11) | (fun << 8)); 869 } 870 871 void 872 rmixl_pcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 873 { 874 if (bp != NULL) 875 *bp = (tag >> 16) & 0xff; 876 if (dp != NULL) 877 *dp = (tag >> 11) & 0x1f; 878 if (fp != NULL) 879 *fp = (tag >> 8) & 0x7; 880 } 881 882 void 883 rmixl_pcie_tag_print(const char *restrict s, void *v, pcitag_t tag, int offset, 884 vaddr_t va, u_long r) 885 { 886 int bus, dev, fun; 887 888 rmixl_pcie_decompose_tag(v, tag, &bus, &dev, &fun); 889 printf("%s: %d/%d/%d/%d - %#" PRIxVADDR ":%#lx\n", 890 s, bus, dev, fun, offset, va, r); 891 } 892 893 static int 894 rmixl_pcie_conf_setup(struct rmixl_pcie_softc *sc, 895 pcitag_t tag, int *offp, bus_space_tag_t *bstp, 896 bus_space_handle_t *bshp) 897 { 898 struct rmixl_config *rcp = &rmixl_configuration; 899 bus_space_tag_t bst; 900 bus_space_handle_t bsh; 901 bus_size_t size; 902 pcitag_t mask; 903 bus_addr_t ba; 904 int err; 905 static bus_space_handle_t cfg_bsh; 906 static bus_addr_t cfg_oba = -1; 907 static bus_space_handle_t ecfg_bsh; 908 static bus_addr_t ecfg_oba = -1; 909 910 /* 911 * bus space depends on offset 912 */ 913 if ((*offp >= 0) && (*offp < 0x100)) { 914 mask = __BITS(15,0); 915 bst = sc->sc_pci_cfg_memt; 916 ba = rcp->rc_pci_cfg_pbase; 917 ba += (tag & ~mask); 918 *offp += (tag & mask); 919 if (ba != cfg_oba) { 920 size = (bus_size_t)(mask + 1); 921 if (cfg_oba != -1) 922 bus_space_unmap(bst, cfg_bsh, size); 923 err = bus_space_map(bst, ba, size, 0, &cfg_bsh); 924 if (err != 0) { 925 #ifdef DEBUG 926 panic("%s: bus_space_map err %d, CFG space", 927 __func__, err); /* XXX */ 928 #endif 929 return -1; 930 } 931 cfg_oba = ba; 932 } 933 bsh = cfg_bsh; 934 } else if ((*offp >= 0x100) && (*offp <= 0x700)) { 935 mask = __BITS(14,0); 936 tag = rmixl_tag_to_ecfg(tag); /* convert to ECFG format */ 937 bst = sc->sc_pci_ecfg_memt; 938 ba = rcp->rc_pci_ecfg_pbase; 939 ba += (tag & ~mask); 940 *offp += (tag & mask); 941 if (ba != ecfg_oba) { 942 size = (bus_size_t)(mask + 1); 943 if (ecfg_oba != -1) 944 bus_space_unmap(bst, ecfg_bsh, size); 945 err = bus_space_map(bst, ba, size, 0, &ecfg_bsh); 946 if (err != 0) { 947 #ifdef DEBUG 948 panic("%s: bus_space_map err %d, ECFG space", 949 __func__, err); /* XXX */ 950 #endif 951 return -1; 952 } 953 ecfg_oba = ba; 954 } 955 bsh = ecfg_bsh; 956 } else if ((*offp > 0x700) && (*offp <= PCI_EXTCONF_SIZE)) { 957 return -1; 958 } else { 959 #ifdef DEBUG 960 panic("%s: offset %#x: unknown", __func__, *offp); 961 #endif 962 return -1; 963 } 964 965 *bstp = bst; 966 *bshp = bsh; 967 968 return 0; 969 } 970 971 pcireg_t 972 rmixl_pcie_conf_read(void *v, pcitag_t tag, int offset) 973 { 974 struct rmixl_pcie_softc *sc = v; 975 static bus_space_handle_t bsh; 976 bus_space_tag_t bst; 977 pcireg_t rv; 978 uint64_t cfg0; 979 980 mutex_enter(&sc->sc_mutex); 981 982 if (rmixl_pcie_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) { 983 cfg0 = rmixl_cache_err_dis(); 984 rv = bus_space_read_4(bst, bsh, (bus_size_t)offset); 985 if (rmixl_cache_err_check() != 0) { 986 #ifdef DIAGNOSTIC 987 int bus, dev, fun; 988 989 rmixl_pcie_decompose_tag(v, tag, &bus, &dev, &fun); 990 printf("%s: %d/%d/%d, offset %#x: bad address\n", 991 __func__, bus, dev, fun, offset); 992 #endif 993 rv = (pcireg_t) -1; 994 } 995 rmixl_cache_err_restore(cfg0); 996 } else { 997 rv = -1; 998 } 999 1000 mutex_exit(&sc->sc_mutex); 1001 1002 return rv; 1003 } 1004 1005 void 1006 rmixl_pcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 1007 { 1008 struct rmixl_pcie_softc *sc = v; 1009 static bus_space_handle_t bsh; 1010 bus_space_tag_t bst; 1011 uint64_t cfg0; 1012 1013 mutex_enter(&sc->sc_mutex); 1014 1015 if (rmixl_pcie_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) { 1016 cfg0 = rmixl_cache_err_dis(); 1017 bus_space_write_4(bst, bsh, (bus_size_t)offset, val); 1018 if (rmixl_cache_err_check() != 0) { 1019 #ifdef DIAGNOSTIC 1020 int bus, dev, fun; 1021 1022 rmixl_pcie_decompose_tag(v, tag, &bus, &dev, &fun); 1023 printf("%s: %d/%d/%d, offset %#x: bad address\n", 1024 __func__, bus, dev, fun, offset); 1025 #endif 1026 } 1027 rmixl_cache_err_restore(cfg0); 1028 } 1029 1030 mutex_exit(&sc->sc_mutex); 1031 } 1032 1033 int 1034 rmixl_pcie_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *pih) 1035 { 1036 int device; 1037 u_int link; 1038 u_int irq; 1039 1040 /* 1041 * The bus is unimportant since it can change depending on the 1042 * configuration. We are tied to device # of PCIe bridge we are 1043 * ultimately attached to. 1044 */ 1045 pci_decompose_tag(pa->pa_pc, pa->pa_intrtag, 1046 NULL, &device, NULL); 1047 1048 #ifdef DEBUG 1049 DPRINTF(("%s: ps_bus %d, pa_intrswiz %#x, pa_intrtag %#lx," 1050 " pa_intrpin %d, pa_intrline %d, pa_rawintrpin %d\n", 1051 __func__, pa->pa_bus, pa->pa_intrswiz, pa->pa_intrtag, 1052 pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 1053 #endif 1054 1055 /* 1056 * PCIe Link INT irq assignment is cpu implementation specific 1057 */ 1058 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 1059 case MIPS_XLS104: 1060 case MIPS_XLS108: 1061 case MIPS_XLS404LITE: 1062 case MIPS_XLS408LITE: 1063 if (device > 1) 1064 panic("%s: bad bus %d", __func__, device); 1065 link = device; 1066 irq = device + 26; 1067 break; 1068 case MIPS_XLS204: 1069 case MIPS_XLS208: { 1070 if (device > 3) 1071 panic("%s: bad bus %d", __func__, device); 1072 link = device; 1073 irq = device + (device & 2 ? 21 : 26); 1074 break; 1075 } 1076 case MIPS_XLS404: 1077 case MIPS_XLS408: 1078 case MIPS_XLS416: 1079 case MIPS_XLS608: 1080 case MIPS_XLS616: 1081 if (device > 3) 1082 panic("%s: bad bus %d", __func__, device); 1083 link = device; 1084 irq = device + 26; 1085 break; 1086 default: 1087 panic("%s: cpu IMPL %#x not supported\n", 1088 __func__, MIPS_PRID_IMPL(mips_options.mips_cpu_id)); 1089 } 1090 1091 if (pa->pa_intrpin != PCI_INTERRUPT_PIN_NONE) 1092 *pih = rmixl_pcie_make_pih(link, pa->pa_intrpin - 1, irq); 1093 else 1094 *pih = ~0; 1095 1096 return 0; 1097 } 1098 1099 const char * 1100 rmixl_pcie_intr_string(void *v, pci_intr_handle_t pih, char *buf, size_t len) 1101 { 1102 const char *name = "(illegal)"; 1103 u_int link, bitno, irq; 1104 1105 rmixl_pcie_decompose_pih(pih, &link, &bitno, &irq); 1106 1107 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 1108 case MIPS_XLS104: 1109 case MIPS_XLS108: 1110 case MIPS_XLS404LITE: 1111 case MIPS_XLS408LITE: 1112 switch (irq) { 1113 case 26: 1114 case 27: 1115 name = rmixl_intr_string(RMIXL_IRT_VECTOR(irq)); 1116 break; 1117 } 1118 break; 1119 case MIPS_XLS204: 1120 case MIPS_XLS208: 1121 switch (irq) { 1122 case 23: 1123 case 24: 1124 case 26: 1125 case 27: 1126 name = rmixl_intr_string(RMIXL_IRT_VECTOR(irq)); 1127 break; 1128 } 1129 break; 1130 case MIPS_XLS404: 1131 case MIPS_XLS408: 1132 case MIPS_XLS416: 1133 case MIPS_XLS608: 1134 case MIPS_XLS616: 1135 switch (irq) { 1136 case 26: 1137 case 27: 1138 case 28: 1139 case 29: 1140 name = rmixl_intr_string(RMIXL_IRT_VECTOR(irq)); 1141 break; 1142 } 1143 break; 1144 default: 1145 panic("%s: cpu IMPL %#x not supported\n", 1146 __func__, MIPS_PRID_IMPL(mips_options.mips_cpu_id)); 1147 } 1148 1149 strlcpy(buf, name, len); 1150 return buf; 1151 } 1152 1153 const struct evcnt * 1154 rmixl_pcie_intr_evcnt(void *v, pci_intr_handle_t pih) 1155 { 1156 return NULL; 1157 } 1158 1159 static pci_intr_handle_t 1160 rmixl_pcie_make_pih(u_int link, u_int bitno, u_int irq) 1161 { 1162 pci_intr_handle_t pih; 1163 1164 KASSERT(link < RMIXL_PCIE_NLINKS_MAX); 1165 KASSERT(bitno < 64); 1166 KASSERT(irq < 32); 1167 1168 pih = (irq << 10); 1169 pih |= (bitno << 4); 1170 pih |= link; 1171 1172 return pih; 1173 } 1174 1175 static void 1176 rmixl_pcie_decompose_pih(pci_intr_handle_t pih, u_int *link, u_int *bitno, u_int *irq) 1177 { 1178 *link = (u_int)(pih & 0xf); 1179 *bitno = (u_int)((pih >> 4) & 0x3f); 1180 *irq = (u_int)(pih >> 10); 1181 1182 KASSERT(*link < RMIXL_PCIE_NLINKS_MAX); 1183 KASSERT(*bitno < 64); 1184 KASSERT(*irq < 32); 1185 } 1186 1187 static void 1188 rmixl_pcie_intr_disestablish(void *v, void *ih) 1189 { 1190 rmixl_pcie_softc_t *sc = v; 1191 rmixl_pcie_link_dispatch_t *dip = ih; 1192 rmixl_pcie_link_intr_t *lip = sc->sc_link_intr[dip->link]; 1193 uint32_t r; 1194 uint32_t bit; 1195 u_int offset; 1196 u_int other; 1197 bool busy; 1198 1199 DPRINTF(("%s: link=%d pin=%d irq=%d\n", 1200 __func__, dip->link, dip->bitno + 1, dip->irq)); 1201 1202 mutex_enter(&sc->sc_mutex); 1203 1204 dip->func = NULL; /* mark unused, prevent further dispatch */ 1205 1206 /* 1207 * if no other dispatch handle is using this interrupt, 1208 * we can disable it 1209 */ 1210 busy = false; 1211 for (int i=0; i < lip->dispatch_count; i++) { 1212 rmixl_pcie_link_dispatch_t *d = &lip->dispatch_data[i]; 1213 if (d == dip) 1214 continue; 1215 if (d->bitno == dip->bitno) { 1216 busy = true; 1217 break; 1218 } 1219 } 1220 if (! busy) { 1221 if (dip->bitno < 32) { 1222 bit = 1 << dip->bitno; 1223 offset = int_enb_offset[dip->link].r0; 1224 other = int_enb_offset[dip->link].r1; 1225 } else { 1226 bit = 1 << (dip->bitno - 32); 1227 offset = int_enb_offset[dip->link].r1; 1228 other = int_enb_offset[dip->link].r0; 1229 } 1230 1231 /* disable this interrupt in the PCIe bridge */ 1232 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + offset); 1233 r &= ~bit; 1234 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + offset, r); 1235 1236 /* 1237 * if both ENABLE0 and ENABLE1 are 0 1238 * disable the link interrupt 1239 */ 1240 if (r == 0) { 1241 /* check the other reg */ 1242 if (RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + other) == 0) { 1243 DPRINTF(("%s: disable link %d\n", __func__, lip->link)); 1244 1245 /* tear down interrupt on this link */ 1246 rmixl_intr_disestablish(lip->ih); 1247 1248 /* commit NULL interrupt set */ 1249 sc->sc_link_intr[dip->link] = NULL; 1250 1251 /* schedule delayed free of the old link interrupt set */ 1252 rmixl_pcie_lip_free_callout(lip); 1253 } 1254 } 1255 } 1256 1257 mutex_exit(&sc->sc_mutex); 1258 } 1259 1260 static void * 1261 rmixl_pcie_intr_establish(void *v, pci_intr_handle_t pih, int ipl, 1262 int (*func)(void *), void *arg) 1263 { 1264 rmixl_pcie_softc_t *sc = v; 1265 u_int link, bitno, irq; 1266 uint32_t r; 1267 rmixl_pcie_link_intr_t *lip; 1268 rmixl_pcie_link_dispatch_t *dip = NULL; 1269 uint32_t bit; 1270 u_int offset; 1271 1272 if (pih == ~0) { 1273 DPRINTF(("%s: bad pih=%#lx, implies PCI_INTERRUPT_PIN_NONE\n", 1274 __func__, pih)); 1275 return NULL; 1276 } 1277 1278 rmixl_pcie_decompose_pih(pih, &link, &bitno, &irq); 1279 DPRINTF(("%s: link=%d pin=%d irq=%d\n", 1280 __func__, link, bitno + 1, irq)); 1281 1282 mutex_enter(&sc->sc_mutex); 1283 1284 lip = rmixl_pcie_lip_add_1(sc, link, irq, ipl); 1285 if (lip == NULL) 1286 return NULL; 1287 1288 /* 1289 * initializae our new interrupt, the last element in dispatch_data[] 1290 */ 1291 dip = &lip->dispatch_data[lip->dispatch_count - 1]; 1292 dip->link = link; 1293 dip->bitno = bitno; 1294 dip->irq = irq; 1295 dip->func = func; 1296 dip->arg = arg; 1297 dip->counts = RMIXL_PCIE_EVCNT(sc, link, bitno, 0); 1298 1299 if (bitno < 32) { 1300 offset = int_enb_offset[link].r0; 1301 bit = 1 << bitno; 1302 } else { 1303 offset = int_enb_offset[link].r1; 1304 bit = 1 << (bitno - 32); 1305 } 1306 1307 /* commit the new link interrupt set */ 1308 sc->sc_link_intr[link] = lip; 1309 1310 /* enable this interrupt in the PCIe bridge */ 1311 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + offset); 1312 r |= bit; 1313 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + offset, r); 1314 1315 mutex_exit(&sc->sc_mutex); 1316 return dip; 1317 } 1318 1319 rmixl_pcie_link_intr_t * 1320 rmixl_pcie_lip_add_1(rmixl_pcie_softc_t *sc, u_int link, int irq, int ipl) 1321 { 1322 rmixl_pcie_link_intr_t *lip_old = sc->sc_link_intr[link]; 1323 rmixl_pcie_link_intr_t *lip_new; 1324 u_int dispatch_count; 1325 size_t size; 1326 1327 dispatch_count = 1; 1328 size = sizeof(rmixl_pcie_link_intr_t); 1329 if (lip_old != NULL) { 1330 /* 1331 * count only those dispatch elements still in use 1332 * unused ones will be pruned during copy 1333 * i.e. we are "lazy" there is no rmixl_pcie_lip_sub_1 1334 */ 1335 for (int i=0; i < lip_old->dispatch_count; i++) { 1336 if (lip_old->dispatch_data[i].func != NULL) { 1337 dispatch_count++; 1338 size += sizeof(rmixl_pcie_link_intr_t); 1339 } 1340 } 1341 } 1342 1343 /* 1344 * allocate and initialize link intr struct 1345 * with one or more dispatch handles 1346 */ 1347 lip_new = malloc(size, M_DEVBUF, M_NOWAIT); 1348 if (lip_new == NULL) { 1349 #ifdef DIAGNOSTIC 1350 printf("%s: cannot malloc\n", __func__); 1351 #endif 1352 return NULL; 1353 } 1354 1355 if (lip_old == NULL) { 1356 /* initialize the link interrupt struct */ 1357 lip_new->sc = sc; 1358 lip_new->link = link; 1359 lip_new->ipl = ipl; 1360 lip_new->ih = rmixl_intr_establish(irq, sc->sc_tmsk, 1361 ipl, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH, 1362 rmixl_pcie_intr, lip_new, false); 1363 if (lip_new->ih == NULL) 1364 panic("%s: cannot establish irq %d", __func__, irq); 1365 } else { 1366 /* 1367 * all intrs on a link get same ipl and sc 1368 * first intr established sets the standard 1369 */ 1370 KASSERT(sc == lip_old->sc); 1371 if (sc != lip_old->sc) { 1372 printf("%s: sc %p mismatch\n", __func__, sc); 1373 free(lip_new, M_DEVBUF); 1374 return NULL; 1375 } 1376 KASSERT (ipl == lip_old->ipl); 1377 if (ipl != lip_old->ipl) { 1378 printf("%s: ipl %d mismatch\n", __func__, ipl); 1379 free(lip_new, M_DEVBUF); 1380 return NULL; 1381 } 1382 /* 1383 * copy lip_old to lip_new, skipping unused dispatch elemets 1384 */ 1385 memcpy(lip_new, lip_old, sizeof(rmixl_pcie_link_intr_t)); 1386 for (int j=0, i=0; i < lip_old->dispatch_count; i++) { 1387 if (lip_old->dispatch_data[i].func != NULL) { 1388 memcpy(&lip_new->dispatch_data[j], 1389 &lip_old->dispatch_data[i], 1390 sizeof(rmixl_pcie_link_dispatch_t)); 1391 j++; 1392 } 1393 } 1394 1395 /* 1396 * schedule delayed free of old link interrupt set 1397 */ 1398 rmixl_pcie_lip_free_callout(lip_old); 1399 } 1400 lip_new->dispatch_count = dispatch_count; 1401 1402 return lip_new; 1403 } 1404 1405 /* 1406 * delay free of the old link interrupt set 1407 * to allow anyone still using it to do so safely 1408 * XXX 2 seconds should be plenty? 1409 */ 1410 static void 1411 rmixl_pcie_lip_free_callout(rmixl_pcie_link_intr_t *lip) 1412 { 1413 callout_init(&lip->callout, 0); 1414 callout_reset(&lip->callout, 2 * hz, rmixl_pcie_lip_free, lip); 1415 } 1416 1417 static void 1418 rmixl_pcie_lip_free(void *arg) 1419 { 1420 rmixl_pcie_link_intr_t *lip = arg; 1421 1422 callout_destroy(&lip->callout); 1423 free(lip, M_DEVBUF); 1424 } 1425 1426 static int 1427 rmixl_pcie_intr(void *arg) 1428 { 1429 rmixl_pcie_link_intr_t *lip = arg; 1430 u_int link = lip->link; 1431 int rv = 0; 1432 1433 uint32_t status0 = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + int_sts_offset[link].r0); 1434 uint32_t status1 = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + int_sts_offset[link].r1); 1435 uint64_t status = ((uint64_t)status1 << 32) | status0; 1436 DPRINTF(("%s: %d:%#"PRIx64"\n", __func__, link, status)); 1437 1438 if (status != 0) { 1439 rmixl_pcie_link_dispatch_t *dip; 1440 1441 if (status & RMIXL_PCIE_LINK_STATUS_ERRORS) 1442 rmixl_pcie_link_error_intr(link, status0, status1); 1443 1444 for (u_int i=0; i < lip->dispatch_count; i++) { 1445 dip = &lip->dispatch_data[i]; 1446 int (*func)(void *) = dip->func; 1447 if (func != NULL) { 1448 uint64_t bit = 1 << dip->bitno; 1449 if ((status & bit) != 0) { 1450 (void)(*func)(dip->arg); 1451 dip->counts[cpu_index(curcpu())].evcnt.ev_count++; 1452 rv = 1; 1453 } 1454 } 1455 } 1456 } 1457 1458 return rv; 1459 } 1460 1461 static void 1462 rmixl_pcie_link_error_intr(u_int link, uint32_t status0, uint32_t status1) 1463 { 1464 printf("%s: mask %#"PRIx64"\n", 1465 __func__, RMIXL_PCIE_LINK_STATUS_ERRORS); 1466 printf("%s: PCIe Link Error: link=%d status0=%#x status1=%#x\n", 1467 __func__, link, status0, status1); 1468 #if defined(DDB) && defined(DEBUG) 1469 Debugger(); 1470 #endif 1471 } 1472 1473 #if defined(DEBUG) || defined(DDB) 1474 /* this function exists to facilitate call from ddb */ 1475 int 1476 rmixl_pcie_error_check(void) 1477 { 1478 if (rmixl_pcie_v != 0) 1479 return _rmixl_pcie_error_check(rmixl_pcie_v); 1480 return -1; 1481 } 1482 #endif 1483 1484 STATIC int 1485 _rmixl_pcie_error_check(void *v) 1486 { 1487 int i, offset; 1488 pcireg_t r; 1489 pcitag_t tag; 1490 int err=0; 1491 #ifdef DIAGNOSTIC 1492 pcireg_t regs[PCIE_ECFG_ERRS_OFFTAB_NENTRIES]; 1493 #endif 1494 1495 tag = rmixl_pcie_make_tag(v, 0, 0, 0); /* XXX */ 1496 1497 for (i=0; i < PCIE_ECFG_ERRS_OFFTAB_NENTRIES; i++) { 1498 offset = pcie_ecfg_errs_tab[i].offset; 1499 r = rmixl_pcie_conf_read(v, tag, offset); 1500 #ifdef DIAGNOSTIC 1501 regs[i] = r; 1502 #endif 1503 if (r != 0) { 1504 pcireg_t rw1c = r & pcie_ecfg_errs_tab[i].rw1c; 1505 if (rw1c != 0) { 1506 /* attempt to clear the error */ 1507 rmixl_pcie_conf_write(v, tag, offset, rw1c); 1508 }; 1509 if (offset == RMIXL_PCIE_ECFG_CESR) 1510 err |= 1; /* correctable */ 1511 else 1512 err |= 2; /* uncorrectable */ 1513 } 1514 } 1515 #ifdef DIAGNOSTIC 1516 if (err != 0) { 1517 for (i=0; i < PCIE_ECFG_ERRS_OFFTAB_NENTRIES; i++) { 1518 offset = pcie_ecfg_errs_tab[i].offset; 1519 printf("%s: %#x: %#x\n", __func__, offset, regs[i]); 1520 } 1521 } 1522 #endif 1523 1524 return err; 1525 } 1526 1527 static int 1528 rmixl_pcie_error_intr(void *v) 1529 { 1530 if (_rmixl_pcie_error_check(v) < 2) 1531 return 0; /* correctable */ 1532 1533 /* uncorrectable */ 1534 #if DDB 1535 Debugger(); 1536 #endif 1537 1538 /* XXX reset and recover? */ 1539 1540 panic("%s\n", __func__); 1541 } 1542 1543 /* 1544 * rmixl_physaddr_init_pcie: 1545 * called from rmixl_physaddr_init to get region addrs & sizes 1546 * from PCIE CFG, ECFG, IO, MEM BARs 1547 */ 1548 void 1549 rmixl_physaddr_init_pcie(struct extent *ext) 1550 { 1551 u_long base; 1552 u_long size; 1553 uint32_t r; 1554 1555 r = RMIXL_IOREG_READ(RMIXLS_SBC_PCIE_CFG_BAR); 1556 if ((r & RMIXL_PCIE_CFG_BAR_ENB) != 0) { 1557 base = (u_long)(RMIXL_PCIE_CFG_BAR_TO_BA((uint64_t)r) 1558 / (1024 * 1024)); 1559 size = (u_long)RMIXL_PCIE_CFG_SIZE / (1024 * 1024); 1560 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1561 __LINE__, "CFG", r, base * 1024 * 1024, size)); 1562 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1563 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1564 "failed", __func__, ext, base, size, EX_NOWAIT); 1565 } 1566 1567 r = RMIXL_IOREG_READ(RMIXLS_SBC_PCIE_ECFG_BAR); 1568 if ((r & RMIXL_PCIE_ECFG_BAR_ENB) != 0) { 1569 base = (u_long)(RMIXL_PCIE_ECFG_BAR_TO_BA((uint64_t)r) 1570 / (1024 * 1024)); 1571 size = (u_long)RMIXL_PCIE_ECFG_SIZE / (1024 * 1024); 1572 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1573 __LINE__, "ECFG", r, base * 1024 * 1024, size)); 1574 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1575 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1576 "failed", __func__, ext, base, size, EX_NOWAIT); 1577 } 1578 1579 r = RMIXL_IOREG_READ(RMIXLS_SBC_PCIE_MEM_BAR); 1580 if ((r & RMIXL_PCIE_MEM_BAR_ENB) != 0) { 1581 base = (u_long)(RMIXL_PCIE_MEM_BAR_TO_BA((uint64_t)r) 1582 / (1024 * 1024)); 1583 size = (u_long)(RMIXL_PCIE_MEM_BAR_TO_SIZE((uint64_t)r) 1584 / (1024 * 1024)); 1585 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1586 __LINE__, "MEM", r, base * 1024 * 1024, size)); 1587 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1588 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1589 "failed", __func__, ext, base, size, EX_NOWAIT); 1590 } 1591 1592 r = RMIXL_IOREG_READ(RMIXLS_SBC_PCIE_IO_BAR); 1593 if ((r & RMIXL_PCIE_IO_BAR_ENB) != 0) { 1594 base = (u_long)(RMIXL_PCIE_IO_BAR_TO_BA((uint64_t)r) 1595 / (1024 * 1024)); 1596 size = (u_long)(RMIXL_PCIE_IO_BAR_TO_SIZE((uint64_t)r) 1597 / (1024 * 1024)); 1598 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1599 __LINE__, "IO", r, base * 1024 * 1024, size)); 1600 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1601 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1602 "failed", __func__, ext, base, size, EX_NOWAIT); 1603 } 1604 } 1605
Indexes created Sun Sep 28 16:09:52 GMT 2025