rmixl_pcie.c revision 1.2
1 /* $NetBSD: rmixl_pcie.c,v 1.2 2009/12/14 00:46:07 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * PCI configuration support for RMI XLS SoC 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: rmixl_pcie.c,v 1.2 2009/12/14 00:46:07 matt Exp $"); 44 45 #include "opt_pci.h" 46 #include "pci.h" 47 48 #include <sys/cdefs.h> 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/device.h> 53 #include <sys/extent.h> 54 #include <sys/malloc.h> 55 56 #include <uvm/uvm_extern.h> 57 58 #include <machine/bus.h> 59 #include <machine/intr.h> 60 61 #include <mips/rmi/rmixlreg.h> 62 #include <mips/rmi/rmixlvar.h> 63 #include <mips/rmi/rmixl_pcievar.h> 64 65 #include <mips/rmi/rmixl_obiovar.h> 66 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pcidevs.h> 69 #include <dev/pci/pciconf.h> 70 71 #ifdef PCI_NETBSD_CONFIGURE 72 #include <mips/cache.h> 73 #endif 74 75 #include <machine/pci_machdep.h> 76 77 #ifdef PCI_DEBUG 78 int rmixl_pcie_debug = PCI_DEBUG; 79 # define DPRINTF(x) do { if (rmixl_pcie_debug) printf x ; } while (0) 80 #else 81 # define DPRINTF(x) 82 #endif 83 84 #ifndef DDB 85 # define STATIC static 86 #else 87 # define STATIC 88 #endif 89 90 91 /* 92 * XLS PCIe Extended Configuration Registers 93 */ 94 #define RMIXL_PCIE_ECFG_UESR 0x104 /* Uncorrectable Error Status Reg */ 95 #define RMIXL_PCIE_ECFG_UEMR 0x108 /* Uncorrectable Error Mask Reg */ 96 #define RMIXL_PCIE_ECFG_UEVR 0x10c /* Uncorrectable Error seVerity Reg */ 97 #define PCIE_ECFG_UEVR_DFLT \ 98 (__BITS(18,17) | __BIT(31) | __BITS(5,4) | __BIT(0)) 99 #define PCIE_ECFG_UExR_RESV (__BITS(31,21) | __BITS(11,6) | __BITS(3,1)) 100 #define RMIXL_PCIE_ECFG_CESR 0x110 /* Correctable Error Status Reg */ 101 #define RMIXL_PCIE_ECFG_CEMR 0x114 /* Correctable Error Mask Reg */ 102 #define PCIE_ECFG_CExR_RESV (__BITS(31,14) | __BITS(11,9) | __BITS(5,1)) 103 #define RMIXL_PCIE_ECFG_ACCR 0x118 /* Adv. Capabilities Control Reg */ 104 #define RMIXL_PCIE_ECFG_HLRn(n) (0x11c + ((n) * 4)) /* Header Log Regs */ 105 #define RMIXL_PCIE_ECFG_RECR 0x12c /* Root Error Command Reg */ 106 #define PCIE_ECFG_RECR_RESV __BITS(31,3) 107 #define RMIXL_PCIE_ECFG_RESR 0x130 /* Root Error Status Reg */ 108 #define PCIE_ECFG_RESR_RESV __BITS(26,7) 109 #define RMIXL_PCIE_ECFG_ESI 0x134 /* Error Source Identification Reg */ 110 #define RMIXL_PCIE_ECFG_DSNCR 0x140 /* Dev Serial Number Capability Regs */ 111 112 static const struct { 113 u_int offset; 114 u_int32_t rw1c; 115 } pcie_ecfg_errs_tab[] = { 116 { RMIXL_PCIE_ECFG_UESR, (__BITS(20,12) | __BIT(4)) }, 117 { RMIXL_PCIE_ECFG_CESR, (__BITS(20,12) | __BIT(4)) }, 118 { RMIXL_PCIE_ECFG_HLRn(0), 0 }, 119 { RMIXL_PCIE_ECFG_HLRn(1), 0 }, 120 { RMIXL_PCIE_ECFG_HLRn(2), 0 }, 121 { RMIXL_PCIE_ECFG_HLRn(3), 0 }, 122 { RMIXL_PCIE_ECFG_RESR, __BITS(6,0) }, 123 { RMIXL_PCIE_ECFG_ESI, 0 }, 124 }; 125 #define PCIE_ECFG_ERRS_OFFTAB_NENTRIES \ 126 (sizeof(pcie_ecfg_errs_tab)/sizeof(pcie_ecfg_errs_tab[0])) 127 128 static int rmixl_pcie_match(device_t, cfdata_t, void *); 129 static void rmixl_pcie_attach(device_t, device_t, void *); 130 static void rmixl_pcie_init(struct rmixl_pcie_softc *); 131 static void rmixl_pcie_init_ecfg(struct rmixl_pcie_softc *); 132 static void rmixl_pcie_attach_hook(struct device *, struct device *, 133 struct pcibus_attach_args *); 134 static void rmixl_pcie_lnkcfg_4xx(rmixl_pcie_lnktab_t *, uint32_t); 135 static void rmixl_pcie_lnkcfg_408Lite(rmixl_pcie_lnktab_t *, uint32_t); 136 static void rmixl_pcie_lnkcfg_2xx(rmixl_pcie_lnktab_t *, uint32_t); 137 static void rmixl_pcie_lnkcfg_1xx(rmixl_pcie_lnktab_t *, uint32_t); 138 static void rmixl_pcie_lnkcfg(struct rmixl_pcie_softc *); 139 static void rmixl_pcie_errata(struct rmixl_pcie_softc *); 140 static void rmixl_conf_interrupt(void *, int, int, int, int, int *); 141 static int rmixl_pcie_bus_maxdevs(void *, int); 142 static pcitag_t rmixl_tag_to_ecfg(pcitag_t); 143 static pcitag_t rmixl_pcie_make_tag(void *, int, int, int); 144 static void rmixl_pcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 145 void rmixl_pcie_tag_print(const char *restrict, void *, pcitag_t, int, vaddr_t, u_long); 146 static int rmixl_pcie_conf_setup(struct rmixl_pcie_softc *, 147 pcitag_t, int *, bus_space_tag_t *, 148 bus_space_handle_t *); 149 static pcireg_t rmixl_pcie_conf_read(void *, pcitag_t, int); 150 static void rmixl_pcie_conf_write(void *, pcitag_t, int, pcireg_t); 151 152 static int rmixl_pcie_intr_map(struct pci_attach_args *, 153 pci_intr_handle_t *); 154 static const char * 155 rmixl_pcie_intr_string(void *, pci_intr_handle_t); 156 static const struct evcnt * 157 rmixl_pcie_intr_evcnt(void *, pci_intr_handle_t); 158 static void *rmixl_pcie_intr_establish(void *, pci_intr_handle_t, 159 int, int (*)(void *), void *); 160 static void rmixl_pcie_intr_disestablish(void *, void *); 161 #if defined(DEBUG) || defined(DDB) 162 int rmixl_pcie_error_check(void); 163 #endif 164 static int _rmixl_pcie_error_check(void *); 165 static int rmixl_pcie_error_intr(void *); 166 167 /* 168 * XXX use locks 169 */ 170 #define PCI_CONF_LOCK(s) (s) = splhigh() 171 #define PCI_CONF_UNLOCK(s) splx((s)) 172 173 174 #define RMIXL_PCIE_CONCAT3(a,b,c) a ## b ## c 175 #define RMIXL_PCIE_BAR_INIT(reg, bar, size, align) { \ 176 struct extent *ext = rmixl_configuration.rc_phys_ex; \ 177 u_long region_start; \ 178 uint64_t ba; \ 179 int err; \ 180 \ 181 err = extent_alloc(ext, (size), (align), 0UL, EX_NOWAIT, \ 182 ®ion_start); \ 183 if (err != 0) \ 184 panic("%s: extent_alloc(%p, %#lx, %#lx, %#lx, %#x, %p)",\ 185 __func__, ext, size, align, 0UL, EX_NOWAIT, \ 186 ®ion_start); \ 187 ba = (uint64_t)region_start; \ 188 ba *= (1024 * 1024); \ 189 bar = RMIXL_PCIE_CONCAT3(RMIXL_PCIE_,reg,_BAR)(ba, 1); \ 190 DPRINTF(("PCIE %s BAR was not enabled by firmware\n" \ 191 "enabling %s at phys %#" PRIxBUSADDR ", size %lu MB\n", \ 192 __STRING(reg), __STRING(reg), ba, size)); \ 193 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_BRIDGE + \ 194 RMIXL_PCIE_CONCAT3(RMIXL_SBC_PCIE_,reg,_BAR), bar); \ 195 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + \ 196 RMIXL_PCIE_CONCAT3(RMIXL_SBC_PCIE_,reg,_BAR)); \ 197 DPRINTF(("%s: %s BAR %#x\n", __func__, __STRING(reg), bar)); \ 198 } 199 200 201 #if defined(DEBUG) || defined(DDB) 202 static void *rmixl_pcie_v; 203 #endif 204 205 CFATTACH_DECL_NEW(rmixl_pcie, sizeof(struct rmixl_pcie_softc), 206 rmixl_pcie_match, rmixl_pcie_attach, NULL, NULL); 207 208 static int rmixl_pcie_found; 209 210 /* 211 * rmixl_cache_err_dis: 212 * - disable Cache, Data ECC, Snoop Tag Parity, Tag Parity errors 213 * - clear the cache error log 214 * - return previous value from RMIXL_PCR_L1D_CONFIG0 215 */ 216 static inline uint64_t 217 rmixl_cache_err_dis(void) 218 { 219 uint64_t r; 220 221 r = rmixl_mfcr(RMIXL_PCR_L1D_CONFIG0); 222 rmixl_mtcr(RMIXL_PCR_L1D_CONFIG0, r & ~0x2e); 223 rmixl_mtcr(RMIXL_PCR_L1D_CACHE_ERROR_LOG, 0); 224 return r; 225 } 226 227 /* 228 * rmixl_cache_err_restore: 229 * - clear the cache error log, cache error overflow log, 230 * and cache interrupt registers 231 * - restore previous value to RMIXL_PCR_L1D_CONFIG0 232 */ 233 static inline void 234 rmixl_cache_err_restore(uint64_t r) 235 { 236 rmixl_mtcr(RMIXL_PCR_L1D_CACHE_ERROR_LOG, 0); 237 rmixl_mtcr(RMIXL_PCR_L1D_CACHE_ERROR_OVF_LO, 0); 238 rmixl_mtcr(RMIXL_PCR_L1D_CACHE_INTERRUPT, 0); 239 rmixl_mtcr(RMIXL_PCR_L1D_CONFIG0, r); 240 } 241 242 static inline uint64_t 243 rmixl_cache_err_check(void) 244 { 245 return rmixl_mfcr(RMIXL_PCR_L1D_CACHE_ERROR_LOG); 246 } 247 248 static int 249 rmixl_pcie_match(device_t parent, cfdata_t cf, void *aux) 250 { 251 uint32_t r; 252 253 /* XXX 254 * for now there is only one PCIe Interface on chip 255 * this could change with furture RMI XL family designs 256 */ 257 if (rmixl_pcie_found) 258 return 0; 259 260 /* read GPIO Reset Configuration register */ 261 /* XXX FIXME define the offset */ 262 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET_CFG); 263 r >>= 26; 264 r &= 3; 265 if (r != 0) 266 return 0; /* strapped for SRIO */ 267 268 return 1; 269 } 270 271 static void 272 rmixl_pcie_attach(device_t parent, device_t self, void *aux) 273 { 274 struct rmixl_pcie_softc *sc = device_private(self); 275 struct obio_attach_args *obio = aux; 276 struct rmixl_config *rcp = &rmixl_configuration; 277 struct pcibus_attach_args pba; 278 uint32_t bar; 279 280 rmixl_pcie_found = 1; 281 sc->sc_dev = self; 282 283 aprint_normal(" RMI XLS PCIe Interface\n"); 284 285 rmixl_pcie_lnkcfg(sc); 286 287 rmixl_pcie_errata(sc); 288 289 sc->sc_29bit_dmat = obio->obio_29bit_dmat; 290 sc->sc_32bit_dmat = obio->obio_32bit_dmat; 291 sc->sc_64bit_dmat = obio->obio_64bit_dmat; 292 293 /* 294 * get PCI config space base addr from SBC PCIe CFG BAR 295 * initialize it if necessary 296 */ 297 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXL_SBC_PCIE_CFG_BAR); 298 DPRINTF(("%s: PCIE_CFG_BAR %#x\n", __func__, bar)); 299 if ((bar & RMIXL_PCIE_CFG_BAR_ENB) == 0) { 300 u_long n = RMIXL_PCIE_CFG_SIZE / (1024 * 1024); 301 RMIXL_PCIE_BAR_INIT(CFG, bar, n, n); 302 } 303 rcp->rc_pcie_cfg_pbase = (bus_addr_t)RMIXL_PCIE_CFG_BAR_TO_BA(bar); 304 rcp->rc_pcie_cfg_size = (bus_size_t)RMIXL_PCIE_CFG_SIZE; 305 306 /* 307 * get PCIE Extended config space base addr from SBC PCIe ECFG BAR 308 * initialize it if necessary 309 */ 310 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXL_SBC_PCIE_ECFG_BAR); 311 DPRINTF(("%s: PCIE_ECFG_BAR %#x\n", __func__, bar)); 312 if ((bar & RMIXL_PCIE_ECFG_BAR_ENB) == 0) { 313 u_long n = RMIXL_PCIE_ECFG_SIZE / (1024 * 1024); 314 RMIXL_PCIE_BAR_INIT(ECFG, bar, n, n); 315 } 316 rcp->rc_pcie_ecfg_pbase = (bus_addr_t)RMIXL_PCIE_ECFG_BAR_TO_BA(bar); 317 rcp->rc_pcie_ecfg_size = (bus_size_t)RMIXL_PCIE_ECFG_SIZE; 318 319 /* 320 * get PCI MEM space base [addr, size] from SBC PCIe MEM BAR 321 * initialize it if necessary 322 */ 323 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXL_SBC_PCIE_MEM_BAR); 324 DPRINTF(("%s: PCIE_MEM_BAR %#x\n", __func__, bar)); 325 if ((bar & RMIXL_PCIE_MEM_BAR_ENB) == 0) { 326 u_long n = 256; /* 256 MB */ 327 RMIXL_PCIE_BAR_INIT(MEM, bar, n, n); 328 } 329 rcp->rc_pci_mem_pbase = (bus_addr_t)RMIXL_PCIE_MEM_BAR_TO_BA(bar); 330 rcp->rc_pci_mem_size = (bus_size_t)RMIXL_PCIE_MEM_BAR_TO_SIZE(bar); 331 332 /* 333 * get PCI IO space base [addr, size] from SBC PCIe IO BAR 334 * initialize it if necessary 335 */ 336 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXL_SBC_PCIE_IO_BAR); 337 DPRINTF(("%s: PCIE_IO_BAR %#x\n", __func__, bar)); 338 if ((bar & RMIXL_PCIE_IO_BAR_ENB) == 0) { 339 u_long n = 32; /* 32 MB */ 340 RMIXL_PCIE_BAR_INIT(IO, bar, n, n); 341 } 342 rcp->rc_pci_io_pbase = (bus_addr_t)RMIXL_PCIE_IO_BAR_TO_BA(bar); 343 rcp->rc_pci_io_size = (bus_size_t)RMIXL_PCIE_IO_BAR_TO_SIZE(bar); 344 345 /* 346 * initialize the PCI CFG, ECFG bus space tags 347 */ 348 rmixl_pcie_cfg_bus_mem_init(&rcp->rc_pcie_cfg_memt, rcp); 349 sc->sc_pcie_cfg_memt = &rcp->rc_pcie_cfg_memt; 350 351 rmixl_pcie_ecfg_bus_mem_init(&rcp->rc_pcie_ecfg_memt, rcp); 352 sc->sc_pcie_ecfg_memt = &rcp->rc_pcie_ecfg_memt; 353 354 /* 355 * initialize the PCI MEM and IO bus space tags 356 */ 357 rmixl_pcie_bus_mem_init(&rcp->rc_pci_memt, rcp); 358 rmixl_pcie_bus_io_init(&rcp->rc_pci_iot, rcp); 359 360 /* 361 * initialize the extended configuration regs 362 */ 363 rmixl_pcie_init_ecfg(sc); 364 365 /* 366 * initialize the PCI chipset tag 367 */ 368 rmixl_pcie_init(sc); 369 370 /* 371 * attach the PCI bus 372 */ 373 memset(&pba, 0, sizeof(pba)); 374 pba.pba_memt = &rcp->rc_pci_memt; 375 pba.pba_iot = &rcp->rc_pci_iot; 376 pba.pba_dmat = sc->sc_29bit_dmat; /* XXX */ 377 #ifdef NOTYET 378 pba.pba_dmat64 = NULL; 379 #endif 380 pba.pba_pc = &sc->sc_pci_chipset; 381 pba.pba_bus = 0; 382 pba.pba_bridgetag = NULL; 383 pba.pba_intrswiz = 0; 384 pba.pba_intrtag = 0; 385 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 386 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 387 388 (void) config_found_ia(self, "pcibus", &pba, pcibusprint); 389 } 390 391 /* 392 * rmixl_pcie_lnkcfg_4xx - link configs for XLS4xx and XLS6xx 393 * use IO_AD[11] and IO_AD[10], observable in 394 * Bits[21:20] of the GPIO Reset Configuration register 395 */ 396 static void 397 rmixl_pcie_lnkcfg_4xx(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 398 { 399 u_int index; 400 static const rmixl_pcie_lnkcfg_t lnktab_4xx[4][4] = { 401 {{ LCFG_EP, 4}, {LCFG_NO, 0}, {LCFG_NO, 0}, {LCFG_NO, 0}}, 402 {{ LCFG_RC, 4}, {LCFG_NO, 0}, {LCFG_NO, 0}, {LCFG_NO, 0}}, 403 {{ LCFG_EP, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}}, 404 {{ LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}}, 405 }; 406 static const char *lnkstr_4xx[4] = { 407 "EP 1x4", 408 "RC 1x4", 409 "EP 1x1, RC 4x1", 410 "RC 4x1" 411 }; 412 index = (grcr >> 20) & 3; 413 ltp->ncfgs = 4; 414 ltp->cfg = lnktab_4xx[index]; 415 ltp->str = lnkstr_4xx[index]; 416 } 417 418 /* 419 * rmixl_pcie_lnkcfg_408Lite - link configs for XLS408Lite and XLS04A 420 * use IO_AD[11] and IO_AD[10], observable in 421 * Bits[21:20] of the GPIO Reset Configuration register 422 */ 423 static void 424 rmixl_pcie_lnkcfg_408Lite(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 425 { 426 u_int index; 427 static const rmixl_pcie_lnkcfg_t lnktab_408Lite[4][2] = { 428 {{ LCFG_EP, 4}, {LCFG_NO, 0}}, 429 {{ LCFG_RC, 4}, {LCFG_NO, 0}}, 430 {{ LCFG_EP, 1}, {LCFG_RC, 1}}, 431 {{ LCFG_RC, 1}, {LCFG_RC, 1}}, 432 }; 433 static const char *lnkstr_408Lite[4] = { 434 "EP 1x4", 435 "RC 1x4", 436 "EP 1x1, RC 1x1", 437 "RC 2x1" 438 }; 439 440 index = (grcr >> 20) & 3; 441 ltp->ncfgs = 2; 442 ltp->cfg = lnktab_408Lite[index]; 443 ltp->str = lnkstr_408Lite[index]; 444 } 445 446 /* 447 * rmixl_pcie_lnkcfg_2xx - link configs for XLS2xx 448 * use IO_AD[10], observable in Bit[20] of the 449 * GPIO Reset Configuration register 450 */ 451 static void 452 rmixl_pcie_lnkcfg_2xx(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 453 { 454 u_int index; 455 static const rmixl_pcie_lnkcfg_t lnktab_2xx[2][4] = { 456 {{ LCFG_EP, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}}, 457 {{ LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}} 458 }; 459 static const char *lnkstr_2xx[2] = { 460 "EP 1x1, RC 3x1", 461 "RC 4x1", 462 }; 463 464 index = (grcr >> 20) & 1; 465 ltp->ncfgs = 4; 466 ltp->cfg = lnktab_2xx[index]; 467 ltp->str = lnkstr_2xx[index]; 468 } 469 470 /* 471 * rmixl_pcie_lnkcfg_1xx - link configs for XLS1xx 472 * use IO_AD[10], observable in Bit[20] of the 473 * GPIO Reset Configuration register 474 */ 475 static void 476 rmixl_pcie_lnkcfg_1xx(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 477 { 478 u_int index; 479 static const rmixl_pcie_lnkcfg_t lnktab_1xx[2][2] = { 480 {{ LCFG_EP, 1}, {LCFG_RC, 1}}, 481 {{ LCFG_RC, 1}, {LCFG_RC, 1}} 482 }; 483 static const char *lnkstr_1xx[2] = { 484 "EP 1x1, RC 1x1", 485 "RC 2x1", 486 }; 487 488 index = (grcr >> 20) & 1; 489 ltp->ncfgs = 2; 490 ltp->cfg = lnktab_1xx[index]; 491 ltp->str = lnkstr_1xx[index]; 492 } 493 494 /* 495 * rmixl_pcie_lnkcfg - determine PCI Express Link Configuration 496 */ 497 static void 498 rmixl_pcie_lnkcfg(struct rmixl_pcie_softc *sc) 499 { 500 uint32_t r; 501 502 /* read GPIO Reset Configuration register */ 503 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET_CFG); 504 DPRINTF(("%s: GPIO RCR %#x\n", __func__, r)); 505 506 switch (MIPS_PRID_IMPL(cpu_id)) { 507 case MIPS_XLS104: 508 case MIPS_XLS108: 509 rmixl_pcie_lnkcfg_1xx(&sc->sc_pcie_lnktab, r); 510 break; 511 case MIPS_XLS204: 512 case MIPS_XLS208: 513 rmixl_pcie_lnkcfg_2xx(&sc->sc_pcie_lnktab, r); 514 break; 515 case MIPS_XLS404LITE: 516 case MIPS_XLS408LITE: 517 rmixl_pcie_lnkcfg_408Lite(&sc->sc_pcie_lnktab, r); 518 break; 519 case MIPS_XLS404: 520 case MIPS_XLS408: 521 case MIPS_XLS416: 522 case MIPS_XLS608: 523 case MIPS_XLS616: 524 /* 6xx uses same table as 4xx */ 525 rmixl_pcie_lnkcfg_4xx(&sc->sc_pcie_lnktab, r); 526 break; 527 default: 528 panic("%s: unknown RMI PRID IMPL", __func__); 529 } 530 531 aprint_normal("%s: link config %s\n", 532 device_xname(sc->sc_dev), sc->sc_pcie_lnktab.str); 533 } 534 535 static void 536 rmixl_pcie_errata(struct rmixl_pcie_softc *sc) 537 { 538 u_int rev; 539 u_int lanes; 540 bool e391 = false; 541 542 /* 543 * 3.9.1 PCIe Link-0 Registers Reset to Incorrect Values 544 * check if it allies to this CPU implementation and revision 545 */ 546 rev = MIPS_PRID_REV(cpu_id); 547 switch (MIPS_PRID_IMPL(cpu_id)) { 548 case MIPS_XLS104: 549 case MIPS_XLS108: 550 break; 551 case MIPS_XLS204: 552 case MIPS_XLS208: 553 /* stepping A0 is affected */ 554 if (rev == 0) 555 e391 = true; 556 break; 557 case MIPS_XLS404LITE: 558 case MIPS_XLS408LITE: 559 break; 560 case MIPS_XLS404: 561 case MIPS_XLS408: 562 case MIPS_XLS416: 563 /* steppings A0 and A1 are affected */ 564 if ((rev == 0) || (rev == 1)) 565 e391 = true; 566 break; 567 case MIPS_XLS608: 568 case MIPS_XLS616: 569 break; 570 default: 571 panic("unknown RMI PRID IMPL"); 572 } 573 574 /* 575 * for XLS we only need to check entry #0 576 * this may need to change for later XL family chips 577 */ 578 lanes = sc->sc_pcie_lnktab.cfg[0].lanes; 579 580 if ((e391 != false) && ((lanes == 2) || (lanes == 4))) { 581 /* 582 * attempt work around for errata 3.9.1 583 * "PCIe Link-0 Registers Reset to Incorrect Values" 584 * the registers are write-once: if the firmware already wrote, 585 * then our writes are ignored; hope they did it right. 586 */ 587 uint32_t queuectrl; 588 uint32_t bufdepth; 589 #ifdef DIAGNOSTIC 590 uint32_t r; 591 #endif 592 593 aprint_normal("%s: attempt work around for errata 3.9.1", 594 device_xname(sc->sc_dev)); 595 if (lanes == 4) { 596 queuectrl = 0x00018074; 597 bufdepth = 0x001901D1; 598 } else { 599 queuectrl = 0x00018036; 600 bufdepth = 0x001900D9; 601 } 602 603 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_BE + 604 RMIXL_VC0_POSTED_RX_QUEUE_CTRL, queuectrl); 605 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_BE + 606 RMIXL_VC0_POSTED_BUFFER_DEPTH, bufdepth); 607 608 #ifdef DIAGNOSTIC 609 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_BE + 610 RMIXL_VC0_POSTED_RX_QUEUE_CTRL); 611 printf("\nVC0_POSTED_RX_QUEUE_CTRL %#x\n", r); 612 613 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_BE + 614 RMIXL_VC0_POSTED_BUFFER_DEPTH); 615 printf("VC0_POSTED_BUFFER_DEPTH %#x\n", r); 616 #endif 617 } 618 } 619 620 static void 621 rmixl_pcie_init(struct rmixl_pcie_softc *sc) 622 { 623 pci_chipset_tag_t pc = &sc->sc_pci_chipset; 624 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 625 struct extent *ioext, *memext; 626 #endif 627 628 pc->pc_conf_v = (void *)sc; 629 pc->pc_attach_hook = rmixl_pcie_attach_hook; 630 pc->pc_bus_maxdevs = rmixl_pcie_bus_maxdevs; 631 pc->pc_make_tag = rmixl_pcie_make_tag; 632 pc->pc_decompose_tag = rmixl_pcie_decompose_tag; 633 pc->pc_conf_read = rmixl_pcie_conf_read; 634 pc->pc_conf_write = rmixl_pcie_conf_write; 635 636 pc->pc_intr_v = (void *)sc; 637 pc->pc_intr_map = rmixl_pcie_intr_map; 638 pc->pc_intr_string = rmixl_pcie_intr_string; 639 pc->pc_intr_evcnt = rmixl_pcie_intr_evcnt; 640 pc->pc_intr_establish = rmixl_pcie_intr_establish; 641 pc->pc_intr_disestablish = rmixl_pcie_intr_disestablish; 642 pc->pc_conf_interrupt = rmixl_conf_interrupt; 643 644 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 645 /* 646 * Configure the PCI bus. 647 */ 648 struct rmixl_config *rcp = &rmixl_configuration; 649 650 aprint_normal("%s: configuring PCI bus\n", 651 device_xname(sc->sc_dev)); 652 653 ioext = extent_create("pciio", 654 rcp->rc_pci_io_pbase, 655 rcp->rc_pci_io_pbase + rcp->rc_pci_io_size - 1, 656 M_DEVBUF, NULL, 0, EX_NOWAIT); 657 658 memext = extent_create("pcimem", 659 rcp->rc_pci_mem_pbase, 660 rcp->rc_pci_mem_pbase + rcp->rc_pci_mem_size - 1, 661 M_DEVBUF, NULL, 0, EX_NOWAIT); 662 663 pci_configure_bus(pc, ioext, memext, NULL, 0, mips_dcache_align); 664 665 extent_destroy(ioext); 666 extent_destroy(memext); 667 #endif 668 } 669 670 static void 671 rmixl_pcie_init_ecfg(struct rmixl_pcie_softc *sc) 672 { 673 void *v; 674 pcitag_t tag; 675 pcireg_t r; 676 677 v = sc; 678 tag = rmixl_pcie_make_tag(v, 0, 0, 0); 679 680 #ifdef PCI_DEBUG 681 int i, offset; 682 static const int offtab[] = 683 { 0, 4, 8, 0xc, 0x10, 0x14, 0x18, 0x1c, 684 0x2c, 0x30, 0x34 }; 685 for (i=0; i < sizeof(offtab)/sizeof(offtab[0]); i++) { 686 offset = 0x100 + offtab[i]; 687 r = rmixl_pcie_conf_read(v, tag, offset); 688 printf("%s: %#x: %#x\n", __func__, offset, r); 689 } 690 #endif 691 r = rmixl_pcie_conf_read(v, tag, 0x100); 692 if (r == -1) 693 return; /* cannot access */ 694 695 /* check pre-existing uncorrectable errs */ 696 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_UESR); 697 r &= ~PCIE_ECFG_UExR_RESV; 698 if (r != 0) 699 panic("%s: Uncorrectable Error Status: %#x\n", 700 __func__, r); 701 702 /* unmask all uncorrectable errs */ 703 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_UEMR); 704 r &= ~PCIE_ECFG_UExR_RESV; 705 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_UEMR, r); 706 707 /* ensure default uncorrectable err severity confniguration */ 708 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_UEVR); 709 r &= ~PCIE_ECFG_UExR_RESV; 710 r |= PCIE_ECFG_UEVR_DFLT; 711 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_UEVR, r); 712 713 /* check pre-existing correctable errs */ 714 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_CESR); 715 r &= ~PCIE_ECFG_CExR_RESV; 716 #ifdef DIAGNOSTIC 717 if (r != 0) 718 aprint_normal("%s: Correctable Error Status: %#x\n", 719 device_xname(sc->sc_dev), r); 720 #endif 721 722 /* unmask all correctable errs */ 723 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_CEMR); 724 r &= ~PCIE_ECFG_CExR_RESV; 725 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_UEMR, r); 726 727 /* check pre-existing Root Error Status */ 728 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_RESR); 729 r &= ~PCIE_ECFG_RESR_RESV; 730 if (r != 0) 731 panic("%s: Root Error Status: %#x\n", __func__, r); 732 /* XXX TMP FIXME */ 733 734 /* enable all Root errs */ 735 r = (pcireg_t)(~PCIE_ECFG_RECR_RESV); 736 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_RECR, r); 737 738 739 if (MIPS_PRID_IMPL(cpu_id) == MIPS_XLS408LITE) { 740 /* 741 * establish ISR for PCIE Fatal Error interrupt 742 * XXX for XLS408Lite, XLS2xx, XLS1xx only 743 * tested on XLS408Lite only 744 */ 745 (void)rmixl_intr_establish(29, IPL_HIGH, 746 RMIXL_INTR_LEVEL, RMIXL_INTR_HIGH, 747 rmixl_pcie_error_intr, v); 748 } 749 #if defined(DEBUG) || defined(DDB) 750 rmixl_pcie_v = v; 751 #endif 752 } 753 754 void 755 rmixl_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *iline) 756 { 757 DPRINTF(("%s: %p, %d, %d, %d, %d, %p\n", 758 __func__, v, bus, dev, ipin, swiz, iline)); 759 } 760 761 void 762 rmixl_pcie_attach_hook(struct device *parent, struct device *self, 763 struct pcibus_attach_args *pba) 764 { 765 DPRINTF(("%s: pba_bus %d, pba_bridgetag %p, pc_conf_v %p\n", 766 __func__, pba->pba_bus, pba->pba_bridgetag, 767 pba->pba_pc->pc_conf_v)); 768 } 769 770 int 771 rmixl_pcie_bus_maxdevs(void *v, int busno) 772 { 773 return (32); /* XXX depends on the family of XLS SoC */ 774 } 775 776 /* 777 * rmixl_tag_to_ecfg - convert cfg address (generic tag) to ecfg address 778 * 779 * 39:29 (reserved) 780 * 28 Swap (0=little, 1=big endian) 781 * 27:20 Bus number 782 * 19:15 Device number 783 * 14:12 Function number 784 * 11:8 Extended Register number 785 * 7:0 Register number 786 */ 787 static pcitag_t 788 rmixl_tag_to_ecfg(pcitag_t tag) 789 { 790 KASSERT((tag & __BITS(7,0)) == 0); 791 return (tag << 4); 792 } 793 794 /* 795 * XLS pci tag is a 40 bit address composed thusly: 796 * 39:25 (reserved) 797 * 24 Swap (0=little, 1=big endian) 798 * 23:16 Bus number 799 * 15:11 Device number 800 * 10:8 Function number 801 * 7:0 Register number 802 * 803 * Note: this is the "native" composition for addressing CFG space, but not for ECFG space. 804 */ 805 pcitag_t 806 rmixl_pcie_make_tag(void *v, int bus, int dev, int fun) 807 { 808 return ((bus << 16) | (dev << 11) | (fun << 8)); 809 } 810 811 void 812 rmixl_pcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 813 { 814 if (bp != NULL) 815 *bp = (tag >> 16) & 0xff; 816 if (dp != NULL) 817 *dp = (tag >> 11) & 0x1f; 818 if (fp != NULL) 819 *fp = (tag >> 8) & 0x7; 820 } 821 822 void 823 rmixl_pcie_tag_print(const char *restrict s, void *v, pcitag_t tag, int offset, 824 vaddr_t va, u_long r) 825 { 826 int bus, dev, fun; 827 828 rmixl_pcie_decompose_tag(v, tag, &bus, &dev, &fun); 829 printf("%s: %d/%d/%d/%d - %#" PRIxVADDR ":%#lx\n", 830 s, bus, dev, fun, offset, va, r); 831 } 832 833 static int 834 rmixl_pcie_conf_setup(struct rmixl_pcie_softc *sc, 835 pcitag_t tag, int *offp, bus_space_tag_t *bstp, 836 bus_space_handle_t *bshp) 837 { 838 struct rmixl_config *rcp = &rmixl_configuration; 839 bus_space_tag_t bst; 840 bus_space_handle_t bsh; 841 bus_size_t size; 842 pcitag_t mask; 843 bus_addr_t ba; 844 int err; 845 static bus_space_handle_t cfg_bsh; 846 static bus_addr_t cfg_oba = -1; 847 static bus_space_handle_t ecfg_bsh; 848 static bus_addr_t ecfg_oba = -1; 849 850 /* 851 * bus space depends on offset 852 */ 853 if ((*offp >= 0) && (*offp < 0x100)) { 854 mask = __BITS(15,0); 855 bst = sc->sc_pcie_cfg_memt; 856 ba = rcp->rc_pcie_cfg_pbase; 857 ba += (tag & ~mask); 858 *offp += (tag & mask); 859 if (ba != cfg_oba) { 860 size = (bus_size_t)(mask + 1); 861 if (cfg_oba != -1) 862 bus_space_unmap(bst, cfg_bsh, size); 863 err = bus_space_map(bst, ba, size, 0, &cfg_bsh); 864 if (err != 0) { 865 #ifdef DEBUG 866 panic("%s: bus_space_map err %d, CFG space", 867 __func__, err); /* XXX */ 868 #endif 869 return -1; 870 } 871 cfg_oba = ba; 872 } 873 bsh = cfg_bsh; 874 } else if ((*offp >= 0x100) && (*offp <= 0x700)) { 875 mask = __BITS(14,0); 876 tag = rmixl_tag_to_ecfg(tag); /* convert to ECFG format */ 877 bst = sc->sc_pcie_ecfg_memt; 878 ba = rcp->rc_pcie_ecfg_pbase; 879 ba += (tag & ~mask); 880 *offp += (tag & mask); 881 if (ba != ecfg_oba) { 882 size = (bus_size_t)(mask + 1); 883 if (ecfg_oba != -1) 884 bus_space_unmap(bst, ecfg_bsh, size); 885 err = bus_space_map(bst, ba, size, 0, &ecfg_bsh); 886 if (err != 0) { 887 #ifdef DEBUH 888 panic("%s: bus_space_map err %d, ECFG space", 889 __func__, err); /* XXX */ 890 #endif 891 return -1; 892 } 893 ecfg_oba = ba; 894 } 895 bsh = ecfg_bsh; 896 } else { 897 #ifdef DEBUG 898 panic("%s: offset %#x: unknown", __func__, *offp); 899 #endif 900 return -1; 901 } 902 903 *bstp = bst; 904 *bshp = bsh; 905 906 return 0; 907 } 908 909 pcireg_t 910 rmixl_pcie_conf_read(void *v, pcitag_t tag, int offset) 911 { 912 struct rmixl_pcie_softc *sc = v; 913 static bus_space_handle_t bsh; 914 bus_space_tag_t bst; 915 pcireg_t rv; 916 uint64_t cfg0; 917 u_int s; 918 919 PCI_CONF_LOCK(s); 920 921 if (rmixl_pcie_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) { 922 cfg0 = rmixl_cache_err_dis(); 923 rv = bus_space_read_4(bst, bsh, (bus_size_t)offset); 924 if (rmixl_cache_err_check() != 0) { 925 #ifdef DIAGNOSTIC 926 int bus, dev, fun; 927 928 rmixl_pcie_decompose_tag(v, tag, &bus, &dev, &fun); 929 printf("%s: %d/%d/%d, offset %#x: bad address\n", 930 __func__, bus, dev, fun, offset); 931 #endif 932 rv = (pcireg_t) -1; 933 } 934 rmixl_cache_err_restore(cfg0); 935 } else { 936 rv = -1; 937 } 938 939 PCI_CONF_UNLOCK(s); 940 return rv; 941 } 942 943 void 944 rmixl_pcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 945 { 946 struct rmixl_pcie_softc *sc = v; 947 static bus_space_handle_t bsh; 948 bus_space_tag_t bst; 949 uint64_t cfg0; 950 u_int s; 951 952 PCI_CONF_LOCK(s); 953 954 if (rmixl_pcie_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) { 955 cfg0 = rmixl_cache_err_dis(); 956 bus_space_write_4(bst, bsh, (bus_size_t)offset, val); 957 if (rmixl_cache_err_check() != 0) { 958 #ifdef DIAGNOSTIC 959 int bus, dev, fun; 960 961 rmixl_pcie_decompose_tag(v, tag, &bus, &dev, &fun); 962 printf("%s: %d/%d/%d, offset %#x: bad address\n", 963 __func__, bus, dev, fun, offset); 964 #endif 965 } 966 rmixl_cache_err_restore(cfg0); 967 } 968 969 PCI_CONF_UNLOCK(s); 970 } 971 972 int 973 rmixl_pcie_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *pih) 974 { 975 u_int irq; 976 977 #ifdef DEBUG 978 DPRINTF(("%s: ps_bus %d, pa_intrswiz %#x, pa_intrtag %#lx," 979 " pa_intrpin %d, pa_intrline %d, pa_rawintrpin %d\n", 980 __func__, pa->pa_bus, pa->pa_intrswiz, pa->pa_intrtag, 981 pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 982 #endif 983 984 /* 985 * XXX cpu implementation specific 986 */ 987 switch (MIPS_PRID_IMPL(cpu_id)) { 988 case MIPS_XLS408LITE: 989 switch (pa->pa_bus) { 990 case 1: 991 irq = 26; 992 break; 993 case 2: 994 irq = 27; 995 break; 996 default: 997 panic("%s: bad bus %d\n", __func__, pa->pa_bus); 998 } 999 break; 1000 case MIPS_XLS416: 1001 case MIPS_XLS616: 1002 switch (pa->pa_bus) { 1003 case 1: 1004 irq = 26; 1005 break; 1006 case 2: 1007 irq = 27; 1008 break; 1009 case 3: 1010 irq = 28; 1011 break; 1012 case 4: 1013 irq = 29; 1014 break; 1015 default: 1016 panic("%s: bad bus %d\n", __func__, pa->pa_bus); 1017 } 1018 break; 1019 default: 1020 panic("%s: cpu IMPL %#x not supported\n", 1021 __func__, MIPS_PRID_IMPL(cpu_id)); 1022 } 1023 1024 *pih = irq; 1025 1026 return 0; 1027 } 1028 1029 const char * 1030 rmixl_pcie_intr_string(void *v, pci_intr_handle_t pih) 1031 { 1032 const char *name = "(illegal)"; 1033 int irq = (int)pih; 1034 1035 switch (MIPS_PRID_IMPL(cpu_id)) { 1036 case MIPS_XLS408LITE: 1037 switch (irq) { 1038 case 26: 1039 case 27: 1040 name = rmixl_intr_string(irq); 1041 break; 1042 } 1043 break; 1044 case MIPS_XLS616: 1045 switch (irq) { 1046 case 26: 1047 case 27: 1048 case 28: 1049 case 29: 1050 name = rmixl_intr_string(irq); 1051 break; 1052 } 1053 break; 1054 } 1055 1056 return name; 1057 } 1058 1059 const struct evcnt * 1060 rmixl_pcie_intr_evcnt(void *v, pci_intr_handle_t pih) 1061 { 1062 return NULL; 1063 } 1064 1065 static int 1066 rmixl_pcie_irq(pci_intr_handle_t pih) 1067 { 1068 return (int)pih; 1069 } 1070 1071 static void * 1072 rmixl_pcie_intr_establish(void *v, pci_intr_handle_t pih, int ipl, 1073 int (*func)(void *), void *arg) 1074 { 1075 return rmixl_intr_establish(rmixl_pcie_irq((int)pih), ipl, 1076 RMIXL_INTR_LEVEL, RMIXL_INTR_HIGH, func, arg); 1077 } 1078 1079 static void 1080 rmixl_pcie_intr_disestablish(void *v, void *ih) 1081 { 1082 rmixl_intr_disestablish(ih); 1083 } 1084 1085 #if defined(DEBUG) || defined(DDB) 1086 /* this function exists to facilitate call from ddb */ 1087 int 1088 rmixl_pcie_error_check(void) 1089 { 1090 if (rmixl_pcie_v != 0) 1091 return _rmixl_pcie_error_check(rmixl_pcie_v); 1092 return -1; 1093 } 1094 #endif 1095 1096 STATIC int 1097 _rmixl_pcie_error_check(void *v) 1098 { 1099 int i, offset; 1100 pcireg_t r; 1101 pcitag_t tag; 1102 int err=0; 1103 #ifdef DIAGNOSTIC 1104 pcireg_t regs[PCIE_ECFG_ERRS_OFFTAB_NENTRIES]; 1105 #endif 1106 1107 tag = rmixl_pcie_make_tag(v, 0, 0, 0); /* XXX */ 1108 1109 for (i=0; i < PCIE_ECFG_ERRS_OFFTAB_NENTRIES; i++) { 1110 offset = pcie_ecfg_errs_tab[i].offset; 1111 r = rmixl_pcie_conf_read(v, tag, offset); 1112 #ifdef DIAGNOSTIC 1113 regs[i] = r; 1114 #endif 1115 if (r != 0) { 1116 pcireg_t rw1c = r & pcie_ecfg_errs_tab[i].rw1c; 1117 if (rw1c != 0) { 1118 /* attempt to clear the error */ 1119 rmixl_pcie_conf_write(v, tag, offset, rw1c); 1120 }; 1121 if (offset == RMIXL_PCIE_ECFG_CESR) 1122 err |= 1; /* correctable */ 1123 else 1124 err |= 2; /* uncorrectable */ 1125 } 1126 } 1127 #ifdef DIAGNOSTIC 1128 if (err != 0) { 1129 for (i=0; i < PCIE_ECFG_ERRS_OFFTAB_NENTRIES; i++) { 1130 offset = pcie_ecfg_errs_tab[i].offset; 1131 printf("%s: %#x: %#x\n", __func__, offset, regs[i]); 1132 } 1133 } 1134 #endif 1135 1136 return err; 1137 } 1138 1139 static int 1140 rmixl_pcie_error_intr(void *v) 1141 { 1142 if (_rmixl_pcie_error_check(v) < 2) 1143 return 0; /* correctable */ 1144 1145 /* uncorrectable */ 1146 #if DDB 1147 Debugger(); 1148 #endif 1149 1150 /* XXX reset and recover? */ 1151 1152 panic("%s\n", __func__); 1153 } 1154
Indexes created Fri Sep 26 08:10:20 GMT 2025