rmixl_pcie.c revision 1.3
1 /* $NetBSD: rmixl_pcie.c,v 1.3 2011/02/20 07:48:37 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * PCI configuration support for RMI XLS SoC 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: rmixl_pcie.c,v 1.3 2011/02/20 07:48:37 matt Exp $"); 44 45 #include "opt_pci.h" 46 #include "pci.h" 47 48 #include <sys/cdefs.h> 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/device.h> 53 #include <sys/extent.h> 54 #include <sys/malloc.h> 55 #include <sys/kernel.h> /* for 'hz' */ 56 #include <sys/cpu.h> 57 58 #include <uvm/uvm_extern.h> 59 60 #include <machine/bus.h> 61 #include <machine/intr.h> 62 63 #include <mips/rmi/rmixlreg.h> 64 #include <mips/rmi/rmixlvar.h> 65 #include <mips/rmi/rmixl_intr.h> 66 #include <mips/rmi/rmixl_pcievar.h> 67 68 #include <mips/rmi/rmixl_obiovar.h> 69 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcidevs.h> 72 #include <dev/pci/pciconf.h> 73 74 #ifdef PCI_NETBSD_CONFIGURE 75 #include <mips/cache.h> 76 #endif 77 78 #include <machine/pci_machdep.h> 79 80 #ifdef PCI_DEBUG 81 int rmixl_pcie_debug = PCI_DEBUG; 82 # define DPRINTF(x) do { if (rmixl_pcie_debug) printf x ; } while (0) 83 #else 84 # define DPRINTF(x) 85 #endif 86 87 #ifndef DDB 88 # define STATIC static 89 #else 90 # define STATIC 91 #endif 92 93 94 /* 95 * XLS PCIe Extended Configuration Registers 96 */ 97 #define RMIXL_PCIE_ECFG_UESR 0x104 /* Uncorrectable Error Status Reg */ 98 #define RMIXL_PCIE_ECFG_UEMR 0x108 /* Uncorrectable Error Mask Reg */ 99 #define RMIXL_PCIE_ECFG_UEVR 0x10c /* Uncorrectable Error seVerity Reg */ 100 #define PCIE_ECFG_UEVR_DFLT \ 101 (__BITS(18,17) | __BIT(31) | __BITS(5,4) | __BIT(0)) 102 #define PCIE_ECFG_UExR_RESV (__BITS(31,21) | __BITS(11,6) | __BITS(3,1)) 103 #define RMIXL_PCIE_ECFG_CESR 0x110 /* Correctable Error Status Reg */ 104 #define RMIXL_PCIE_ECFG_CEMR 0x114 /* Correctable Error Mask Reg */ 105 #define PCIE_ECFG_CExR_RESV (__BITS(31,14) | __BITS(11,9) | __BITS(5,1)) 106 #define RMIXL_PCIE_ECFG_ACCR 0x118 /* Adv. Capabilities Control Reg */ 107 #define RMIXL_PCIE_ECFG_HLRn(n) (0x11c + ((n) * 4)) /* Header Log Regs */ 108 #define RMIXL_PCIE_ECFG_RECR 0x12c /* Root Error Command Reg */ 109 #define PCIE_ECFG_RECR_RESV __BITS(31,3) 110 #define RMIXL_PCIE_ECFG_RESR 0x130 /* Root Error Status Reg */ 111 #define PCIE_ECFG_RESR_RESV __BITS(26,7) 112 #define RMIXL_PCIE_ECFG_ESI 0x134 /* Error Source Identification Reg */ 113 #define RMIXL_PCIE_ECFG_DSNCR 0x140 /* Dev Serial Number Capability Regs */ 114 115 static const struct { 116 u_int offset; 117 u_int32_t rw1c; 118 } pcie_ecfg_errs_tab[] = { 119 { RMIXL_PCIE_ECFG_UESR, (__BITS(20,12) | __BIT(4)) }, 120 { RMIXL_PCIE_ECFG_CESR, (__BITS(20,12) | __BIT(4)) }, 121 { RMIXL_PCIE_ECFG_HLRn(0), 0 }, 122 { RMIXL_PCIE_ECFG_HLRn(1), 0 }, 123 { RMIXL_PCIE_ECFG_HLRn(2), 0 }, 124 { RMIXL_PCIE_ECFG_HLRn(3), 0 }, 125 { RMIXL_PCIE_ECFG_RESR, __BITS(6,0) }, 126 { RMIXL_PCIE_ECFG_ESI, 0 }, 127 }; 128 #define PCIE_ECFG_ERRS_OFFTAB_NENTRIES \ 129 (sizeof(pcie_ecfg_errs_tab)/sizeof(pcie_ecfg_errs_tab[0])) 130 131 typedef struct rmixl_pcie_int_csr { 132 uint r0; 133 uint r1; 134 } rmixl_pcie_int_csr_t; 135 136 static const rmixl_pcie_int_csr_t int_enb_offset[4] = { 137 { RMIXL_PCIE_LINK0_INT_ENABLE0, RMIXL_PCIE_LINK0_INT_ENABLE1 }, 138 { RMIXL_PCIE_LINK1_INT_ENABLE0, RMIXL_PCIE_LINK1_INT_ENABLE1 }, 139 { RMIXL_PCIE_LINK2_INT_ENABLE0, RMIXL_PCIE_LINK2_INT_ENABLE1 }, 140 { RMIXL_PCIE_LINK3_INT_ENABLE0, RMIXL_PCIE_LINK3_INT_ENABLE1 }, 141 }; 142 143 static const rmixl_pcie_int_csr_t int_sts_offset[4] = { 144 { RMIXL_PCIE_LINK0_INT_STATUS0, RMIXL_PCIE_LINK0_INT_STATUS1 }, 145 { RMIXL_PCIE_LINK1_INT_STATUS0, RMIXL_PCIE_LINK1_INT_STATUS1 }, 146 { RMIXL_PCIE_LINK2_INT_STATUS0, RMIXL_PCIE_LINK2_INT_STATUS1 }, 147 { RMIXL_PCIE_LINK3_INT_STATUS0, RMIXL_PCIE_LINK3_INT_STATUS1 }, 148 }; 149 150 static const u_int msi_enb_offset[4] = { 151 RMIXL_PCIE_LINK0_MSI_ENABLE, 152 RMIXL_PCIE_LINK1_MSI_ENABLE, 153 RMIXL_PCIE_LINK2_MSI_ENABLE, 154 RMIXL_PCIE_LINK3_MSI_ENABLE 155 }; 156 157 #define RMIXL_PCIE_LINK_STATUS0_ERRORS __BITS(6,4) 158 #define RMIXL_PCIE_LINK_STATUS1_ERRORS __BITS(10,0) 159 #define RMIXL_PCIE_LINK_STATUS_ERRORS \ 160 ((((uint64_t)RMIXL_PCIE_LINK_STATUS1_ERRORS) << 32) | \ 161 (uint64_t)RMIXL_PCIE_LINK_STATUS0_ERRORS) 162 163 #define RMIXL_PCIE_EVCNT(sc, link, bitno, cpu) \ 164 &(sc)->sc_evcnts[link][(bitno) * (ncpu) + (cpu)] 165 166 static int rmixl_pcie_match(device_t, cfdata_t, void *); 167 static void rmixl_pcie_attach(device_t, device_t, void *); 168 static void rmixl_pcie_init(struct rmixl_pcie_softc *); 169 static void rmixl_pcie_init_ecfg(struct rmixl_pcie_softc *); 170 static void rmixl_pcie_attach_hook(struct device *, struct device *, 171 struct pcibus_attach_args *); 172 static void rmixl_pcie_lnkcfg_4xx(rmixl_pcie_lnktab_t *, uint32_t); 173 static void rmixl_pcie_lnkcfg_408Lite(rmixl_pcie_lnktab_t *, uint32_t); 174 static void rmixl_pcie_lnkcfg_2xx(rmixl_pcie_lnktab_t *, uint32_t); 175 static void rmixl_pcie_lnkcfg_1xx(rmixl_pcie_lnktab_t *, uint32_t); 176 static void rmixl_pcie_lnkcfg(struct rmixl_pcie_softc *); 177 static void rmixl_pcie_intcfg(struct rmixl_pcie_softc *); 178 static void rmixl_pcie_errata(struct rmixl_pcie_softc *); 179 static void rmixl_conf_interrupt(void *, int, int, int, int, int *); 180 static int rmixl_pcie_bus_maxdevs(void *, int); 181 static pcitag_t rmixl_tag_to_ecfg(pcitag_t); 182 static pcitag_t rmixl_pcie_make_tag(void *, int, int, int); 183 static void rmixl_pcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 184 void rmixl_pcie_tag_print(const char *restrict, void *, pcitag_t, int, vaddr_t, u_long); 185 static int rmixl_pcie_conf_setup(struct rmixl_pcie_softc *, 186 pcitag_t, int *, bus_space_tag_t *, 187 bus_space_handle_t *); 188 static pcireg_t rmixl_pcie_conf_read(void *, pcitag_t, int); 189 static void rmixl_pcie_conf_write(void *, pcitag_t, int, pcireg_t); 190 191 static int rmixl_pcie_intr_map(struct pci_attach_args *, 192 pci_intr_handle_t *); 193 static const char * 194 rmixl_pcie_intr_string(void *, pci_intr_handle_t); 195 static const struct evcnt * 196 rmixl_pcie_intr_evcnt(void *, pci_intr_handle_t); 197 static pci_intr_handle_t 198 rmixl_pcie_make_pih(u_int, u_int, u_int); 199 static void rmixl_pcie_decompose_pih(pci_intr_handle_t, u_int *, u_int *, u_int *); 200 static void rmixl_pcie_intr_disestablish(void *, void *); 201 static void *rmixl_pcie_intr_establish(void *, pci_intr_handle_t, 202 int, int (*)(void *), void *); 203 static rmixl_pcie_link_intr_t * 204 rmixl_pcie_lip_add_1(rmixl_pcie_softc_t *, u_int, int, int); 205 static void rmixl_pcie_lip_free_callout(rmixl_pcie_link_intr_t *); 206 static void rmixl_pcie_lip_free(void *); 207 static int rmixl_pcie_intr(void *); 208 static void rmixl_pcie_link_error_intr(u_int, uint32_t, uint32_t); 209 #if defined(DEBUG) || defined(DDB) 210 int rmixl_pcie_error_check(void); 211 #endif 212 static int _rmixl_pcie_error_check(void *); 213 static int rmixl_pcie_error_intr(void *); 214 215 216 #define RMIXL_PCIE_CONCAT3(a,b,c) a ## b ## c 217 #define RMIXL_PCIE_BAR_INIT(reg, bar, size, align) { \ 218 struct extent *ext = rmixl_configuration.rc_phys_ex; \ 219 u_long region_start; \ 220 uint64_t ba; \ 221 int err; \ 222 \ 223 err = extent_alloc(ext, (size), (align), 0UL, EX_NOWAIT, \ 224 ®ion_start); \ 225 if (err != 0) \ 226 panic("%s: extent_alloc(%p, %#lx, %#lx, %#lx, %#x, %p)",\ 227 __func__, ext, size, align, 0UL, EX_NOWAIT, \ 228 ®ion_start); \ 229 ba = (uint64_t)region_start; \ 230 ba *= (1024 * 1024); \ 231 bar = RMIXL_PCIE_CONCAT3(RMIXL_PCIE_,reg,_BAR)(ba, 1); \ 232 DPRINTF(("PCIE %s BAR was not enabled by firmware\n" \ 233 "enabling %s at phys %#" PRIxBUSADDR ", size %lu MB\n", \ 234 __STRING(reg), __STRING(reg), ba, size)); \ 235 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_BRIDGE + \ 236 RMIXL_PCIE_CONCAT3(RMIXLS_SBC_PCIE_,reg,_BAR), bar); \ 237 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + \ 238 RMIXL_PCIE_CONCAT3(RMIXLS_SBC_PCIE_,reg,_BAR)); \ 239 DPRINTF(("%s: %s BAR %#x\n", __func__, __STRING(reg), bar)); \ 240 } 241 242 243 #if defined(DEBUG) || defined(DDB) 244 static void *rmixl_pcie_v; 245 #endif 246 247 CFATTACH_DECL_NEW(rmixl_pcie, sizeof(struct rmixl_pcie_softc), 248 rmixl_pcie_match, rmixl_pcie_attach, NULL, NULL); 249 250 static int rmixl_pcie_found; 251 252 static int 253 rmixl_pcie_match(device_t parent, cfdata_t cf, void *aux) 254 { 255 uint32_t r; 256 257 /* 258 * PCIe interface exists on XLS chips only 259 */ 260 if (! cpu_rmixls(mips_options.mips_cpu)) 261 return 0; 262 263 /* XXX 264 * for now there is only one PCIe Interface on chip 265 * this could change with furture RMI XL family designs 266 */ 267 if (rmixl_pcie_found) 268 return 0; 269 270 /* read GPIO Reset Configuration register */ 271 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET_CFG); 272 r >>= 26; 273 r &= 3; 274 if (r != 0) 275 return 0; /* strapped for SRIO */ 276 277 return 1; 278 } 279 280 static void 281 rmixl_pcie_attach(device_t parent, device_t self, void *aux) 282 { 283 struct rmixl_pcie_softc *sc = device_private(self); 284 struct obio_attach_args *obio = aux; 285 struct rmixl_config *rcp = &rmixl_configuration; 286 struct pcibus_attach_args pba; 287 uint32_t bar; 288 289 rmixl_pcie_found = 1; 290 sc->sc_dev = self; 291 292 aprint_normal(" RMI XLS PCIe Interface\n"); 293 294 mutex_init(&sc->sc_mutex, MUTEX_DEFAULT, IPL_HIGH); 295 296 rmixl_pcie_lnkcfg(sc); 297 298 rmixl_pcie_intcfg(sc); 299 300 rmixl_pcie_errata(sc); 301 302 sc->sc_29bit_dmat = obio->obio_29bit_dmat; 303 sc->sc_32bit_dmat = obio->obio_32bit_dmat; 304 sc->sc_64bit_dmat = obio->obio_64bit_dmat; 305 306 sc->sc_tmsk = obio->obio_tmsk; 307 308 /* 309 * get PCI config space base addr from SBC PCIe CFG BAR 310 * initialize it if necessary 311 */ 312 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLS_SBC_PCIE_CFG_BAR); 313 DPRINTF(("%s: PCIE_CFG_BAR %#x\n", __func__, bar)); 314 if ((bar & RMIXL_PCIE_CFG_BAR_ENB) == 0) { 315 u_long n = RMIXL_PCIE_CFG_SIZE / (1024 * 1024); 316 RMIXL_PCIE_BAR_INIT(CFG, bar, n, n); 317 } 318 rcp->rc_pci_cfg_pbase = (bus_addr_t)RMIXL_PCIE_CFG_BAR_TO_BA(bar); 319 rcp->rc_pci_cfg_size = (bus_size_t)RMIXL_PCIE_CFG_SIZE; 320 321 /* 322 * get PCIE Extended config space base addr from SBC PCIe ECFG BAR 323 * initialize it if necessary 324 */ 325 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLS_SBC_PCIE_ECFG_BAR); 326 DPRINTF(("%s: PCIE_ECFG_BAR %#x\n", __func__, bar)); 327 if ((bar & RMIXL_PCIE_ECFG_BAR_ENB) == 0) { 328 u_long n = RMIXL_PCIE_ECFG_SIZE / (1024 * 1024); 329 RMIXL_PCIE_BAR_INIT(ECFG, bar, n, n); 330 } 331 rcp->rc_pci_ecfg_pbase = (bus_addr_t)RMIXL_PCIE_ECFG_BAR_TO_BA(bar); 332 rcp->rc_pci_ecfg_size = (bus_size_t)RMIXL_PCIE_ECFG_SIZE; 333 334 /* 335 * get PCI MEM space base [addr, size] from SBC PCIe MEM BAR 336 * initialize it if necessary 337 */ 338 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLS_SBC_PCIE_MEM_BAR); 339 DPRINTF(("%s: PCIE_MEM_BAR %#x\n", __func__, bar)); 340 if ((bar & RMIXL_PCIE_MEM_BAR_ENB) == 0) { 341 u_long n = 256; /* 256 MB */ 342 RMIXL_PCIE_BAR_INIT(MEM, bar, n, n); 343 } 344 rcp->rc_pci_mem_pbase = (bus_addr_t)RMIXL_PCIE_MEM_BAR_TO_BA(bar); 345 rcp->rc_pci_mem_size = (bus_size_t)RMIXL_PCIE_MEM_BAR_TO_SIZE(bar); 346 347 /* 348 * get PCI IO space base [addr, size] from SBC PCIe IO BAR 349 * initialize it if necessary 350 */ 351 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLS_SBC_PCIE_IO_BAR); 352 DPRINTF(("%s: PCIE_IO_BAR %#x\n", __func__, bar)); 353 if ((bar & RMIXL_PCIE_IO_BAR_ENB) == 0) { 354 u_long n = 32; /* 32 MB */ 355 RMIXL_PCIE_BAR_INIT(IO, bar, n, n); 356 } 357 rcp->rc_pci_io_pbase = (bus_addr_t)RMIXL_PCIE_IO_BAR_TO_BA(bar); 358 rcp->rc_pci_io_size = (bus_size_t)RMIXL_PCIE_IO_BAR_TO_SIZE(bar); 359 360 /* 361 * initialize the PCI CFG, ECFG bus space tags 362 */ 363 rmixl_pci_cfg_bus_mem_init(&rcp->rc_pci_cfg_memt, rcp); 364 sc->sc_pci_cfg_memt = &rcp->rc_pci_cfg_memt; 365 366 rmixl_pci_ecfg_bus_mem_init(&rcp->rc_pci_ecfg_memt, rcp); 367 sc->sc_pci_ecfg_memt = &rcp->rc_pci_ecfg_memt; 368 369 /* 370 * initialize the PCI MEM and IO bus space tags 371 */ 372 rmixl_pci_bus_mem_init(&rcp->rc_pci_memt, rcp); 373 rmixl_pci_bus_io_init(&rcp->rc_pci_iot, rcp); 374 375 /* 376 * initialize the extended configuration regs 377 */ 378 rmixl_pcie_init_ecfg(sc); 379 380 /* 381 * initialize the PCI chipset tag 382 */ 383 rmixl_pcie_init(sc); 384 385 /* 386 * attach the PCI bus 387 */ 388 memset(&pba, 0, sizeof(pba)); 389 pba.pba_memt = &rcp->rc_pci_memt; 390 pba.pba_iot = &rcp->rc_pci_iot; 391 pba.pba_dmat = sc->sc_32bit_dmat; 392 pba.pba_dmat64 = sc->sc_64bit_dmat; 393 pba.pba_pc = &sc->sc_pci_chipset; 394 pba.pba_bus = 0; 395 pba.pba_bridgetag = NULL; 396 pba.pba_intrswiz = 0; 397 pba.pba_intrtag = 0; 398 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 399 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 400 401 (void) config_found_ia(self, "pcibus", &pba, pcibusprint); 402 } 403 404 /* 405 * rmixl_pcie_lnkcfg_4xx - link configs for XLS4xx and XLS6xx 406 * use IO_AD[11] and IO_AD[10], observable in 407 * Bits[21:20] of the GPIO Reset Configuration register 408 */ 409 static void 410 rmixl_pcie_lnkcfg_4xx(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 411 { 412 u_int index; 413 static const rmixl_pcie_lnkcfg_t lnktab_4xx[4][4] = { 414 {{ LCFG_EP, 4}, {LCFG_NO, 0}, {LCFG_NO, 0}, {LCFG_NO, 0}}, 415 {{ LCFG_RC, 4}, {LCFG_NO, 0}, {LCFG_NO, 0}, {LCFG_NO, 0}}, 416 {{ LCFG_EP, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}}, 417 {{ LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}}, 418 }; 419 static const char *lnkstr_4xx[4] = { 420 "1EPx4", 421 "1RCx4", 422 "1EPx1, 3RCx1", 423 "4RCx1" 424 }; 425 index = (grcr >> 20) & 3; 426 ltp->ncfgs = 4; 427 ltp->cfg = lnktab_4xx[index]; 428 ltp->str = lnkstr_4xx[index]; 429 } 430 431 /* 432 * rmixl_pcie_lnkcfg_408Lite - link configs for XLS408Lite and XLS04A 433 * use IO_AD[11] and IO_AD[10], observable in 434 * Bits[21:20] of the GPIO Reset Configuration register 435 */ 436 static void 437 rmixl_pcie_lnkcfg_408Lite(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 438 { 439 u_int index; 440 static const rmixl_pcie_lnkcfg_t lnktab_408Lite[4][2] = { 441 {{ LCFG_EP, 4}, {LCFG_NO, 0}}, 442 {{ LCFG_RC, 4}, {LCFG_NO, 0}}, 443 {{ LCFG_EP, 1}, {LCFG_RC, 1}}, 444 {{ LCFG_RC, 1}, {LCFG_RC, 1}}, 445 }; 446 static const char *lnkstr_408Lite[4] = { 447 "4EPx4", 448 "1RCx4", 449 "1EPx1, 1RCx1", 450 "2RCx1" 451 }; 452 453 index = (grcr >> 20) & 3; 454 ltp->ncfgs = 2; 455 ltp->cfg = lnktab_408Lite[index]; 456 ltp->str = lnkstr_408Lite[index]; 457 } 458 459 /* 460 * rmixl_pcie_lnkcfg_2xx - link configs for XLS2xx 461 * use IO_AD[10], observable in Bit[20] of the 462 * GPIO Reset Configuration register 463 */ 464 static void 465 rmixl_pcie_lnkcfg_2xx(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 466 { 467 u_int index; 468 static const rmixl_pcie_lnkcfg_t lnktab_2xx[2][4] = { 469 {{ LCFG_EP, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}}, 470 {{ LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}} 471 }; 472 static const char *lnkstr_2xx[2] = { 473 "1EPx1, 3RCx1", 474 "4RCx1", 475 }; 476 477 index = (grcr >> 20) & 1; 478 ltp->ncfgs = 4; 479 ltp->cfg = lnktab_2xx[index]; 480 ltp->str = lnkstr_2xx[index]; 481 } 482 483 /* 484 * rmixl_pcie_lnkcfg_1xx - link configs for XLS1xx 485 * use IO_AD[10], observable in Bit[20] of the 486 * GPIO Reset Configuration register 487 */ 488 static void 489 rmixl_pcie_lnkcfg_1xx(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 490 { 491 u_int index; 492 static const rmixl_pcie_lnkcfg_t lnktab_1xx[2][2] = { 493 {{ LCFG_EP, 1}, {LCFG_RC, 1}}, 494 {{ LCFG_RC, 1}, {LCFG_RC, 1}} 495 }; 496 static const char *lnkstr_1xx[2] = { 497 "1EPx1, 1RCx1", 498 "2RCx1", 499 }; 500 501 index = (grcr >> 20) & 1; 502 ltp->ncfgs = 2; 503 ltp->cfg = lnktab_1xx[index]; 504 ltp->str = lnkstr_1xx[index]; 505 } 506 507 /* 508 * rmixl_pcie_lnkcfg - determine PCI Express Link Configuration 509 */ 510 static void 511 rmixl_pcie_lnkcfg(struct rmixl_pcie_softc *sc) 512 { 513 uint32_t r; 514 515 /* read GPIO Reset Configuration register */ 516 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET_CFG); 517 DPRINTF(("%s: GPIO RCR %#x\n", __func__, r)); 518 519 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 520 case MIPS_XLS104: 521 case MIPS_XLS108: 522 rmixl_pcie_lnkcfg_1xx(&sc->sc_pcie_lnktab, r); 523 break; 524 case MIPS_XLS204: 525 case MIPS_XLS208: 526 rmixl_pcie_lnkcfg_2xx(&sc->sc_pcie_lnktab, r); 527 break; 528 case MIPS_XLS404LITE: 529 case MIPS_XLS408LITE: 530 rmixl_pcie_lnkcfg_408Lite(&sc->sc_pcie_lnktab, r); 531 break; 532 case MIPS_XLS404: 533 case MIPS_XLS408: 534 case MIPS_XLS416: 535 case MIPS_XLS608: 536 case MIPS_XLS616: 537 /* 6xx uses same table as 4xx */ 538 rmixl_pcie_lnkcfg_4xx(&sc->sc_pcie_lnktab, r); 539 break; 540 default: 541 panic("%s: unknown RMI PRID IMPL", __func__); 542 } 543 544 aprint_normal("%s: link config %s\n", 545 device_xname(sc->sc_dev), sc->sc_pcie_lnktab.str); 546 } 547 548 /* 549 * rmixl_pcie_intcfg - init PCIe Link interrupt enables 550 */ 551 static void 552 rmixl_pcie_intcfg(struct rmixl_pcie_softc *sc) 553 { 554 int link; 555 size_t size; 556 rmixl_pcie_evcnt_t *ev; 557 558 DPRINTF(("%s: disable all link interrupts\n", __func__)); 559 for (link=0; link < sc->sc_pcie_lnktab.ncfgs; link++) { 560 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + int_enb_offset[link].r0, 561 RMIXL_PCIE_LINK_STATUS0_ERRORS); 562 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + int_enb_offset[link].r1, 563 RMIXL_PCIE_LINK_STATUS1_ERRORS); 564 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + msi_enb_offset[link], 0); 565 sc->sc_link_intr[link] = NULL; 566 567 /* 568 * allocate per-cpu, per-pin interrupt event counters 569 */ 570 size = ncpu * PCI_INTERRUPT_PIN_MAX * sizeof(rmixl_pcie_evcnt_t); 571 ev = malloc(size, M_DEVBUF, M_NOWAIT); 572 if (ev == NULL) 573 panic("%s: cannot malloc evcnts\n", __func__); 574 sc->sc_evcnts[link] = ev; 575 for (int pin=PCI_INTERRUPT_PIN_A; pin <= PCI_INTERRUPT_PIN_MAX; pin++) { 576 for (int cpu=0; cpu < ncpu; cpu++) { 577 ev = RMIXL_PCIE_EVCNT(sc, link, pin - 1, cpu); 578 snprintf(ev->name, sizeof(ev->name), 579 "cpu%d, link %d, pin %d", cpu, link, pin); 580 evcnt_attach_dynamic(&ev->evcnt, EVCNT_TYPE_INTR, 581 NULL, "rmixl_pcie", ev->name); 582 } 583 } 584 } 585 } 586 587 static void 588 rmixl_pcie_errata(struct rmixl_pcie_softc *sc) 589 { 590 const mips_prid_t cpu_id = mips_options.mips_cpu_id; 591 u_int rev; 592 u_int lanes; 593 bool e391 = false; 594 595 /* 596 * 3.9.1 PCIe Link-0 Registers Reset to Incorrect Values 597 * check if it allies to this CPU implementation and revision 598 */ 599 rev = MIPS_PRID_REV(cpu_id); 600 switch (MIPS_PRID_IMPL(cpu_id)) { 601 case MIPS_XLS104: 602 case MIPS_XLS108: 603 break; 604 case MIPS_XLS204: 605 case MIPS_XLS208: 606 /* stepping A0 is affected */ 607 if (rev == 0) 608 e391 = true; 609 break; 610 case MIPS_XLS404LITE: 611 case MIPS_XLS408LITE: 612 break; 613 case MIPS_XLS404: 614 case MIPS_XLS408: 615 case MIPS_XLS416: 616 /* steppings A0 and A1 are affected */ 617 if ((rev == 0) || (rev == 1)) 618 e391 = true; 619 break; 620 case MIPS_XLS608: 621 case MIPS_XLS616: 622 break; 623 default: 624 panic("unknown RMI PRID IMPL"); 625 } 626 627 /* 628 * for XLS we only need to check entry #0 629 * this may need to change for later XL family chips 630 */ 631 lanes = sc->sc_pcie_lnktab.cfg[0].lanes; 632 633 if ((e391 != false) && ((lanes == 2) || (lanes == 4))) { 634 /* 635 * attempt work around for errata 3.9.1 636 * "PCIe Link-0 Registers Reset to Incorrect Values" 637 * the registers are write-once: if the firmware already wrote, 638 * then our writes are ignored; hope they did it right. 639 */ 640 uint32_t queuectrl; 641 uint32_t bufdepth; 642 #ifdef DIAGNOSTIC 643 uint32_t r; 644 #endif 645 646 aprint_normal("%s: attempt work around for errata 3.9.1", 647 device_xname(sc->sc_dev)); 648 if (lanes == 4) { 649 queuectrl = 0x00018074; 650 bufdepth = 0x001901D1; 651 } else { 652 queuectrl = 0x00018036; 653 bufdepth = 0x001900D9; 654 } 655 656 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_BE + 657 RMIXL_VC0_POSTED_RX_QUEUE_CTRL, queuectrl); 658 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_BE + 659 RMIXL_VC0_POSTED_BUFFER_DEPTH, bufdepth); 660 661 #ifdef DIAGNOSTIC 662 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_BE + 663 RMIXL_VC0_POSTED_RX_QUEUE_CTRL); 664 printf("\nVC0_POSTED_RX_QUEUE_CTRL %#x\n", r); 665 666 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_BE + 667 RMIXL_VC0_POSTED_BUFFER_DEPTH); 668 printf("VC0_POSTED_BUFFER_DEPTH %#x\n", r); 669 #endif 670 } 671 } 672 673 static void 674 rmixl_pcie_init(struct rmixl_pcie_softc *sc) 675 { 676 pci_chipset_tag_t pc = &sc->sc_pci_chipset; 677 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 678 struct extent *ioext, *memext; 679 #endif 680 681 pc->pc_conf_v = (void *)sc; 682 pc->pc_attach_hook = rmixl_pcie_attach_hook; 683 pc->pc_bus_maxdevs = rmixl_pcie_bus_maxdevs; 684 pc->pc_make_tag = rmixl_pcie_make_tag; 685 pc->pc_decompose_tag = rmixl_pcie_decompose_tag; 686 pc->pc_conf_read = rmixl_pcie_conf_read; 687 pc->pc_conf_write = rmixl_pcie_conf_write; 688 689 pc->pc_intr_v = (void *)sc; 690 pc->pc_intr_map = rmixl_pcie_intr_map; 691 pc->pc_intr_string = rmixl_pcie_intr_string; 692 pc->pc_intr_evcnt = rmixl_pcie_intr_evcnt; 693 pc->pc_intr_establish = rmixl_pcie_intr_establish; 694 pc->pc_intr_disestablish = rmixl_pcie_intr_disestablish; 695 pc->pc_conf_interrupt = rmixl_conf_interrupt; 696 697 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 698 /* 699 * Configure the PCI bus. 700 */ 701 struct rmixl_config *rcp = &rmixl_configuration; 702 703 aprint_normal("%s: configuring PCI bus\n", 704 device_xname(sc->sc_dev)); 705 706 ioext = extent_create("pciio", 707 rcp->rc_pci_io_pbase, 708 rcp->rc_pci_io_pbase + rcp->rc_pci_io_size - 1, 709 M_DEVBUF, NULL, 0, EX_NOWAIT); 710 711 memext = extent_create("pcimem", 712 rcp->rc_pci_mem_pbase, 713 rcp->rc_pci_mem_pbase + rcp->rc_pci_mem_size - 1, 714 M_DEVBUF, NULL, 0, EX_NOWAIT); 715 716 pci_configure_bus(pc, ioext, memext, NULL, 0, 717 mips_cache_info.mci_dcache_align); 718 719 extent_destroy(ioext); 720 extent_destroy(memext); 721 #endif 722 } 723 724 static void 725 rmixl_pcie_init_ecfg(struct rmixl_pcie_softc *sc) 726 { 727 void *v; 728 pcitag_t tag; 729 pcireg_t r; 730 731 v = sc; 732 tag = rmixl_pcie_make_tag(v, 0, 0, 0); 733 734 #ifdef PCI_DEBUG 735 int i, offset; 736 static const int offtab[] = 737 { 0, 4, 8, 0xc, 0x10, 0x14, 0x18, 0x1c, 738 0x2c, 0x30, 0x34 }; 739 for (i=0; i < sizeof(offtab)/sizeof(offtab[0]); i++) { 740 offset = 0x100 + offtab[i]; 741 r = rmixl_pcie_conf_read(v, tag, offset); 742 printf("%s: %#x: %#x\n", __func__, offset, r); 743 } 744 #endif 745 r = rmixl_pcie_conf_read(v, tag, 0x100); 746 if (r == -1) 747 return; /* cannot access */ 748 749 /* check pre-existing uncorrectable errs */ 750 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_UESR); 751 r &= ~PCIE_ECFG_UExR_RESV; 752 if (r != 0) 753 panic("%s: Uncorrectable Error Status: %#x\n", 754 __func__, r); 755 756 /* unmask all uncorrectable errs */ 757 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_UEMR); 758 r &= ~PCIE_ECFG_UExR_RESV; 759 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_UEMR, r); 760 761 /* ensure default uncorrectable err severity confniguration */ 762 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_UEVR); 763 r &= ~PCIE_ECFG_UExR_RESV; 764 r |= PCIE_ECFG_UEVR_DFLT; 765 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_UEVR, r); 766 767 /* check pre-existing correctable errs */ 768 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_CESR); 769 r &= ~PCIE_ECFG_CExR_RESV; 770 #ifdef DIAGNOSTIC 771 if (r != 0) 772 aprint_normal("%s: Correctable Error Status: %#x\n", 773 device_xname(sc->sc_dev), r); 774 #endif 775 776 /* unmask all correctable errs */ 777 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_CEMR); 778 r &= ~PCIE_ECFG_CExR_RESV; 779 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_UEMR, r); 780 781 /* check pre-existing Root Error Status */ 782 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_RESR); 783 r &= ~PCIE_ECFG_RESR_RESV; 784 if (r != 0) 785 panic("%s: Root Error Status: %#x\n", __func__, r); 786 /* XXX TMP FIXME */ 787 788 /* enable all Root errs */ 789 r = (pcireg_t)(~PCIE_ECFG_RECR_RESV); 790 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_RECR, r); 791 792 /* 793 * establish ISR for PCIE Fatal Error interrupt 794 * - for XLS4xxLite, XLS2xx, XLS1xx only 795 */ 796 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 797 case MIPS_XLS104: 798 case MIPS_XLS108: 799 case MIPS_XLS204: 800 case MIPS_XLS208: 801 case MIPS_XLS404LITE: 802 case MIPS_XLS408LITE: 803 sc->sc_fatal_ih = rmixl_intr_establish(29, sc->sc_tmsk, 804 IPL_HIGH, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH, 805 rmixl_pcie_error_intr, v, false); 806 break; 807 default: 808 break; 809 } 810 811 #if defined(DEBUG) || defined(DDB) 812 rmixl_pcie_v = v; 813 #endif 814 } 815 816 void 817 rmixl_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *iline) 818 { 819 DPRINTF(("%s: %p, %d, %d, %d, %d, %p\n", 820 __func__, v, bus, dev, ipin, swiz, iline)); 821 } 822 823 void 824 rmixl_pcie_attach_hook(struct device *parent, struct device *self, 825 struct pcibus_attach_args *pba) 826 { 827 DPRINTF(("%s: pba_bus %d, pba_bridgetag %p, pc_conf_v %p\n", 828 __func__, pba->pba_bus, pba->pba_bridgetag, 829 pba->pba_pc->pc_conf_v)); 830 } 831 832 int 833 rmixl_pcie_bus_maxdevs(void *v, int busno) 834 { 835 return (32); /* XXX depends on the family of XLS SoC */ 836 } 837 838 /* 839 * rmixl_tag_to_ecfg - convert cfg address (generic tag) to ecfg address 840 * 841 * 39:29 (reserved) 842 * 28 Swap (0=little, 1=big endian) 843 * 27:20 Bus number 844 * 19:15 Device number 845 * 14:12 Function number 846 * 11:8 Extended Register number 847 * 7:0 Register number 848 */ 849 static pcitag_t 850 rmixl_tag_to_ecfg(pcitag_t tag) 851 { 852 KASSERT((tag & __BITS(7,0)) == 0); 853 return (tag << 4); 854 } 855 856 /* 857 * XLS pci tag is a 40 bit address composed thusly: 858 * 39:25 (reserved) 859 * 24 Swap (0=little, 1=big endian) 860 * 23:16 Bus number 861 * 15:11 Device number 862 * 10:8 Function number 863 * 7:0 Register number 864 * 865 * Note: this is the "native" composition for addressing CFG space, but not for ECFG space. 866 */ 867 pcitag_t 868 rmixl_pcie_make_tag(void *v, int bus, int dev, int fun) 869 { 870 return ((bus << 16) | (dev << 11) | (fun << 8)); 871 } 872 873 void 874 rmixl_pcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 875 { 876 if (bp != NULL) 877 *bp = (tag >> 16) & 0xff; 878 if (dp != NULL) 879 *dp = (tag >> 11) & 0x1f; 880 if (fp != NULL) 881 *fp = (tag >> 8) & 0x7; 882 } 883 884 void 885 rmixl_pcie_tag_print(const char *restrict s, void *v, pcitag_t tag, int offset, 886 vaddr_t va, u_long r) 887 { 888 int bus, dev, fun; 889 890 rmixl_pcie_decompose_tag(v, tag, &bus, &dev, &fun); 891 printf("%s: %d/%d/%d/%d - %#" PRIxVADDR ":%#lx\n", 892 s, bus, dev, fun, offset, va, r); 893 } 894 895 static int 896 rmixl_pcie_conf_setup(struct rmixl_pcie_softc *sc, 897 pcitag_t tag, int *offp, bus_space_tag_t *bstp, 898 bus_space_handle_t *bshp) 899 { 900 struct rmixl_config *rcp = &rmixl_configuration; 901 bus_space_tag_t bst; 902 bus_space_handle_t bsh; 903 bus_size_t size; 904 pcitag_t mask; 905 bus_addr_t ba; 906 int err; 907 static bus_space_handle_t cfg_bsh; 908 static bus_addr_t cfg_oba = -1; 909 static bus_space_handle_t ecfg_bsh; 910 static bus_addr_t ecfg_oba = -1; 911 912 /* 913 * bus space depends on offset 914 */ 915 if ((*offp >= 0) && (*offp < 0x100)) { 916 mask = __BITS(15,0); 917 bst = sc->sc_pci_cfg_memt; 918 ba = rcp->rc_pci_cfg_pbase; 919 ba += (tag & ~mask); 920 *offp += (tag & mask); 921 if (ba != cfg_oba) { 922 size = (bus_size_t)(mask + 1); 923 if (cfg_oba != -1) 924 bus_space_unmap(bst, cfg_bsh, size); 925 err = bus_space_map(bst, ba, size, 0, &cfg_bsh); 926 if (err != 0) { 927 #ifdef DEBUG 928 panic("%s: bus_space_map err %d, CFG space", 929 __func__, err); /* XXX */ 930 #endif 931 return -1; 932 } 933 cfg_oba = ba; 934 } 935 bsh = cfg_bsh; 936 } else if ((*offp >= 0x100) && (*offp <= 0x700)) { 937 mask = __BITS(14,0); 938 tag = rmixl_tag_to_ecfg(tag); /* convert to ECFG format */ 939 bst = sc->sc_pci_ecfg_memt; 940 ba = rcp->rc_pci_ecfg_pbase; 941 ba += (tag & ~mask); 942 *offp += (tag & mask); 943 if (ba != ecfg_oba) { 944 size = (bus_size_t)(mask + 1); 945 if (ecfg_oba != -1) 946 bus_space_unmap(bst, ecfg_bsh, size); 947 err = bus_space_map(bst, ba, size, 0, &ecfg_bsh); 948 if (err != 0) { 949 #ifdef DEBUG 950 panic("%s: bus_space_map err %d, ECFG space", 951 __func__, err); /* XXX */ 952 #endif 953 return -1; 954 } 955 ecfg_oba = ba; 956 } 957 bsh = ecfg_bsh; 958 } else { 959 #ifdef DEBUG 960 panic("%s: offset %#x: unknown", __func__, *offp); 961 #endif 962 return -1; 963 } 964 965 *bstp = bst; 966 *bshp = bsh; 967 968 return 0; 969 } 970 971 pcireg_t 972 rmixl_pcie_conf_read(void *v, pcitag_t tag, int offset) 973 { 974 struct rmixl_pcie_softc *sc = v; 975 static bus_space_handle_t bsh; 976 bus_space_tag_t bst; 977 pcireg_t rv; 978 uint64_t cfg0; 979 980 mutex_enter(&sc->sc_mutex); 981 982 if (rmixl_pcie_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) { 983 cfg0 = rmixl_cache_err_dis(); 984 rv = bus_space_read_4(bst, bsh, (bus_size_t)offset); 985 if (rmixl_cache_err_check() != 0) { 986 #ifdef DIAGNOSTIC 987 int bus, dev, fun; 988 989 rmixl_pcie_decompose_tag(v, tag, &bus, &dev, &fun); 990 printf("%s: %d/%d/%d, offset %#x: bad address\n", 991 __func__, bus, dev, fun, offset); 992 #endif 993 rv = (pcireg_t) -1; 994 } 995 rmixl_cache_err_restore(cfg0); 996 } else { 997 rv = -1; 998 } 999 1000 mutex_exit(&sc->sc_mutex); 1001 1002 return rv; 1003 } 1004 1005 void 1006 rmixl_pcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 1007 { 1008 struct rmixl_pcie_softc *sc = v; 1009 static bus_space_handle_t bsh; 1010 bus_space_tag_t bst; 1011 uint64_t cfg0; 1012 1013 mutex_enter(&sc->sc_mutex); 1014 1015 if (rmixl_pcie_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) { 1016 cfg0 = rmixl_cache_err_dis(); 1017 bus_space_write_4(bst, bsh, (bus_size_t)offset, val); 1018 if (rmixl_cache_err_check() != 0) { 1019 #ifdef DIAGNOSTIC 1020 int bus, dev, fun; 1021 1022 rmixl_pcie_decompose_tag(v, tag, &bus, &dev, &fun); 1023 printf("%s: %d/%d/%d, offset %#x: bad address\n", 1024 __func__, bus, dev, fun, offset); 1025 #endif 1026 } 1027 rmixl_cache_err_restore(cfg0); 1028 } 1029 1030 mutex_exit(&sc->sc_mutex); 1031 } 1032 1033 int 1034 rmixl_pcie_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *pih) 1035 { 1036 int device; 1037 u_int link; 1038 u_int irq; 1039 1040 /* 1041 * The bus is unimportant since it can change depending on the 1042 * configuration. We are tied to device # of PCIe bridge we are 1043 * ultimately attached to. 1044 */ 1045 pci_decompose_tag(pa->pa_pc, pa->pa_intrtag, 1046 NULL, &device, NULL); 1047 1048 #ifdef DEBUG 1049 DPRINTF(("%s: ps_bus %d, pa_intrswiz %#x, pa_intrtag %#lx," 1050 " pa_intrpin %d, pa_intrline %d, pa_rawintrpin %d\n", 1051 __func__, pa->pa_bus, pa->pa_intrswiz, pa->pa_intrtag, 1052 pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 1053 #endif 1054 1055 /* 1056 * PCIe Link INT irq assignment is cpu implementation specific 1057 */ 1058 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 1059 case MIPS_XLS104: 1060 case MIPS_XLS108: 1061 case MIPS_XLS404LITE: 1062 case MIPS_XLS408LITE: 1063 if (device > 1) 1064 panic("%s: bad bus %d", __func__, device); 1065 link = device; 1066 irq = device + 26; 1067 break; 1068 case MIPS_XLS204: 1069 case MIPS_XLS208: { 1070 if (device > 3) 1071 panic("%s: bad bus %d", __func__, device); 1072 link = device; 1073 irq = device + (device & 2 ? 21 : 26); 1074 break; 1075 } 1076 case MIPS_XLS404: 1077 case MIPS_XLS408: 1078 case MIPS_XLS416: 1079 case MIPS_XLS608: 1080 case MIPS_XLS616: 1081 if (device > 3) 1082 panic("%s: bad bus %d", __func__, device); 1083 link = device; 1084 irq = device + 26; 1085 break; 1086 default: 1087 panic("%s: cpu IMPL %#x not supported\n", 1088 __func__, MIPS_PRID_IMPL(mips_options.mips_cpu_id)); 1089 } 1090 1091 if (pa->pa_intrpin != PCI_INTERRUPT_PIN_NONE) 1092 *pih = rmixl_pcie_make_pih(link, pa->pa_intrpin - 1, irq); 1093 else 1094 *pih = ~0; 1095 1096 return 0; 1097 } 1098 1099 const char * 1100 rmixl_pcie_intr_string(void *v, pci_intr_handle_t pih) 1101 { 1102 const char *name = "(illegal)"; 1103 u_int link, bitno, irq; 1104 1105 rmixl_pcie_decompose_pih(pih, &link, &bitno, &irq); 1106 1107 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 1108 case MIPS_XLS104: 1109 case MIPS_XLS108: 1110 case MIPS_XLS404LITE: 1111 case MIPS_XLS408LITE: 1112 switch (irq) { 1113 case 26: 1114 case 27: 1115 name = rmixl_intr_string(irq); 1116 break; 1117 } 1118 break; 1119 case MIPS_XLS204: 1120 case MIPS_XLS208: 1121 switch (irq) { 1122 case 23: 1123 case 24: 1124 case 26: 1125 case 27: 1126 name = rmixl_intr_string(irq); 1127 break; 1128 } 1129 break; 1130 case MIPS_XLS404: 1131 case MIPS_XLS408: 1132 case MIPS_XLS416: 1133 case MIPS_XLS608: 1134 case MIPS_XLS616: 1135 switch (irq) { 1136 case 26: 1137 case 27: 1138 case 28: 1139 case 29: 1140 name = rmixl_intr_string(irq); 1141 break; 1142 } 1143 break; 1144 default: 1145 panic("%s: cpu IMPL %#x not supported\n", 1146 __func__, MIPS_PRID_IMPL(mips_options.mips_cpu_id)); 1147 } 1148 1149 return name; 1150 } 1151 1152 const struct evcnt * 1153 rmixl_pcie_intr_evcnt(void *v, pci_intr_handle_t pih) 1154 { 1155 return NULL; 1156 } 1157 1158 static pci_intr_handle_t 1159 rmixl_pcie_make_pih(u_int link, u_int bitno, u_int irq) 1160 { 1161 pci_intr_handle_t pih; 1162 1163 KASSERT(link < RMIXL_PCIE_NLINKS_MAX); 1164 KASSERT(bitno < 64); 1165 KASSERT(irq < 32); 1166 1167 pih = (irq << 10); 1168 pih |= (bitno << 4); 1169 pih |= link; 1170 1171 return pih; 1172 } 1173 1174 static void 1175 rmixl_pcie_decompose_pih(pci_intr_handle_t pih, u_int *link, u_int *bitno, u_int *irq) 1176 { 1177 *link = (u_int)(pih & 0xf); 1178 *bitno = (u_int)((pih >> 4) & 0x3f); 1179 *irq = (u_int)(pih >> 10); 1180 1181 KASSERT(*link < RMIXL_PCIE_NLINKS_MAX); 1182 KASSERT(*bitno < 64); 1183 KASSERT(*irq < 32); 1184 } 1185 1186 static void 1187 rmixl_pcie_intr_disestablish(void *v, void *ih) 1188 { 1189 rmixl_pcie_softc_t *sc = v; 1190 rmixl_pcie_link_dispatch_t *dip = ih; 1191 rmixl_pcie_link_intr_t *lip = sc->sc_link_intr[dip->link]; 1192 uint32_t r; 1193 uint32_t bit; 1194 u_int offset; 1195 u_int other; 1196 bool busy; 1197 1198 DPRINTF(("%s: link=%d pin=%d irq=%d\n", 1199 __func__, dip->link, dip->bitno + 1, dip->irq)); 1200 1201 mutex_enter(&sc->sc_mutex); 1202 1203 dip->func = NULL; /* mark unused, prevent further dispatch */ 1204 1205 /* 1206 * if no other dispatch handle is using this interrupt, 1207 * we can disable it 1208 */ 1209 busy = false; 1210 for (int i=0; i < lip->dispatch_count; i++) { 1211 rmixl_pcie_link_dispatch_t *d = &lip->dispatch_data[i]; 1212 if (d == dip) 1213 continue; 1214 if (d->bitno == dip->bitno) { 1215 busy = true; 1216 break; 1217 } 1218 } 1219 if (! busy) { 1220 if (dip->bitno < 32) { 1221 bit = 1 << dip->bitno; 1222 offset = int_enb_offset[dip->link].r0; 1223 other = int_enb_offset[dip->link].r1; 1224 } else { 1225 bit = 1 << (dip->bitno - 32); 1226 offset = int_enb_offset[dip->link].r1; 1227 other = int_enb_offset[dip->link].r0; 1228 } 1229 1230 /* disable this interrupt in the PCIe bridge */ 1231 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + offset); 1232 r &= ~bit; 1233 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + offset, r); 1234 1235 /* 1236 * if both ENABLE0 and ENABLE1 are 0 1237 * disable the link interrupt 1238 */ 1239 if (r == 0) { 1240 /* check the other reg */ 1241 if (RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + other) == 0) { 1242 DPRINTF(("%s: disable link %d\n", __func__, lip->link)); 1243 1244 /* tear down interrupt on this link */ 1245 rmixl_intr_disestablish(lip->ih); 1246 1247 /* commit NULL interrupt set */ 1248 sc->sc_link_intr[dip->link] = NULL; 1249 1250 /* schedule delayed free of the old link interrupt set */ 1251 rmixl_pcie_lip_free_callout(lip); 1252 } 1253 } 1254 } 1255 1256 mutex_exit(&sc->sc_mutex); 1257 } 1258 1259 static void * 1260 rmixl_pcie_intr_establish(void *v, pci_intr_handle_t pih, int ipl, 1261 int (*func)(void *), void *arg) 1262 { 1263 rmixl_pcie_softc_t *sc = v; 1264 u_int link, bitno, irq; 1265 uint32_t r; 1266 rmixl_pcie_link_intr_t *lip; 1267 rmixl_pcie_link_dispatch_t *dip = NULL; 1268 uint32_t bit; 1269 u_int offset; 1270 1271 if (pih == ~0) { 1272 DPRINTF(("%s: bad pih=%#lx, implies PCI_INTERRUPT_PIN_NONE\n", 1273 __func__, pih)); 1274 return NULL; 1275 } 1276 1277 rmixl_pcie_decompose_pih(pih, &link, &bitno, &irq); 1278 DPRINTF(("%s: link=%d pin=%d irq=%d\n", 1279 __func__, link, bitno + 1, irq)); 1280 1281 mutex_enter(&sc->sc_mutex); 1282 1283 lip = rmixl_pcie_lip_add_1(sc, link, irq, ipl); 1284 if (lip == NULL) 1285 return NULL; 1286 1287 /* 1288 * initializae our new interrupt, the last element in dispatch_data[] 1289 */ 1290 dip = &lip->dispatch_data[lip->dispatch_count - 1]; 1291 dip->link = link; 1292 dip->bitno = bitno; 1293 dip->irq = irq; 1294 dip->func = func; 1295 dip->arg = arg; 1296 dip->counts = RMIXL_PCIE_EVCNT(sc, link, bitno, 0); 1297 1298 if (bitno < 32) { 1299 offset = int_enb_offset[link].r0; 1300 bit = 1 << bitno; 1301 } else { 1302 offset = int_enb_offset[link].r1; 1303 bit = 1 << (bitno - 32); 1304 } 1305 1306 /* commit the new link interrupt set */ 1307 sc->sc_link_intr[link] = lip; 1308 1309 /* enable this interrupt in the PCIe bridge */ 1310 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + offset); 1311 r |= bit; 1312 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + offset, r); 1313 1314 mutex_exit(&sc->sc_mutex); 1315 return dip; 1316 } 1317 1318 rmixl_pcie_link_intr_t * 1319 rmixl_pcie_lip_add_1(rmixl_pcie_softc_t *sc, u_int link, int irq, int ipl) 1320 { 1321 rmixl_pcie_link_intr_t *lip_old = sc->sc_link_intr[link]; 1322 rmixl_pcie_link_intr_t *lip_new; 1323 u_int dispatch_count; 1324 size_t size; 1325 1326 dispatch_count = 1; 1327 size = sizeof(rmixl_pcie_link_intr_t); 1328 if (lip_old != NULL) { 1329 /* 1330 * count only those dispatch elements still in use 1331 * unused ones will be pruned during copy 1332 * i.e. we are "lazy" there is no rmixl_pcie_lip_sub_1 1333 */ 1334 for (int i=0; i < lip_old->dispatch_count; i++) { 1335 if (lip_old->dispatch_data[i].func != NULL) { 1336 dispatch_count++; 1337 size += sizeof(rmixl_pcie_link_intr_t); 1338 } 1339 } 1340 } 1341 1342 /* 1343 * allocate and initialize link intr struct 1344 * with one or more dispatch handles 1345 */ 1346 lip_new = malloc(size, M_DEVBUF, M_NOWAIT); 1347 if (lip_new == NULL) { 1348 #ifdef DIAGNOSTIC 1349 printf("%s: cannot malloc\n", __func__); 1350 #endif 1351 return NULL; 1352 } 1353 1354 if (lip_old == NULL) { 1355 /* initialize the link interrupt struct */ 1356 lip_new->sc = sc; 1357 lip_new->link = link; 1358 lip_new->ipl = ipl; 1359 lip_new->ih = rmixl_intr_establish(irq, sc->sc_tmsk, 1360 ipl, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH, 1361 rmixl_pcie_intr, lip_new, false); 1362 if (lip_new->ih == NULL) 1363 panic("%s: cannot establish irq %d", __func__, irq); 1364 } else { 1365 /* 1366 * all intrs on a link get same ipl and sc 1367 * first intr established sets the standard 1368 */ 1369 KASSERT(sc == lip_old->sc); 1370 if (sc != lip_old->sc) { 1371 printf("%s: sc %p mismatch\n", __func__, sc); 1372 free(lip_new, M_DEVBUF); 1373 return NULL; 1374 } 1375 KASSERT (ipl == lip_old->ipl); 1376 if (ipl != lip_old->ipl) { 1377 printf("%s: ipl %d mismatch\n", __func__, ipl); 1378 free(lip_new, M_DEVBUF); 1379 return NULL; 1380 } 1381 /* 1382 * copy lip_old to lip_new, skipping unused dispatch elemets 1383 */ 1384 memcpy(lip_new, lip_old, sizeof(rmixl_pcie_link_intr_t)); 1385 for (int j=0, i=0; i < lip_old->dispatch_count; i++) { 1386 if (lip_old->dispatch_data[i].func != NULL) { 1387 memcpy(&lip_new->dispatch_data[j], 1388 &lip_old->dispatch_data[i], 1389 sizeof(rmixl_pcie_link_dispatch_t)); 1390 j++; 1391 } 1392 } 1393 1394 /* 1395 * schedule delayed free of old link interrupt set 1396 */ 1397 rmixl_pcie_lip_free_callout(lip_old); 1398 } 1399 lip_new->dispatch_count = dispatch_count; 1400 1401 return lip_new; 1402 } 1403 1404 /* 1405 * delay free of the old link interrupt set 1406 * to allow anyone still using it to do so safely 1407 * XXX 2 seconds should be plenty? 1408 */ 1409 static void 1410 rmixl_pcie_lip_free_callout(rmixl_pcie_link_intr_t *lip) 1411 { 1412 callout_init(&lip->callout, 0); 1413 callout_reset(&lip->callout, 2 * hz, rmixl_pcie_lip_free, lip); 1414 } 1415 1416 static void 1417 rmixl_pcie_lip_free(void *arg) 1418 { 1419 rmixl_pcie_link_intr_t *lip = arg; 1420 1421 callout_destroy(&lip->callout); 1422 free(lip, M_DEVBUF); 1423 } 1424 1425 static int 1426 rmixl_pcie_intr(void *arg) 1427 { 1428 rmixl_pcie_link_intr_t *lip = arg; 1429 u_int link = lip->link; 1430 int rv = 0; 1431 1432 uint32_t status0 = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + int_sts_offset[link].r0); 1433 uint32_t status1 = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + int_sts_offset[link].r1); 1434 uint64_t status = ((uint64_t)status1 << 32) | status0; 1435 DPRINTF(("%s: %d:%#"PRIx64"\n", __func__, link, status)); 1436 1437 if (status != 0) { 1438 rmixl_pcie_link_dispatch_t *dip; 1439 1440 if (status & RMIXL_PCIE_LINK_STATUS_ERRORS) 1441 rmixl_pcie_link_error_intr(link, status0, status1); 1442 1443 for (u_int i=0; i < lip->dispatch_count; i++) { 1444 dip = &lip->dispatch_data[i]; 1445 int (*func)(void *) = dip->func; 1446 if (func != NULL) { 1447 uint64_t bit = 1 << dip->bitno; 1448 if ((status & bit) != 0) { 1449 (void)(*func)(dip->arg); 1450 dip->counts[cpu_index(curcpu())].evcnt.ev_count++; 1451 rv = 1; 1452 } 1453 } 1454 } 1455 } 1456 1457 return rv; 1458 } 1459 1460 static void 1461 rmixl_pcie_link_error_intr(u_int link, uint32_t status0, uint32_t status1) 1462 { 1463 printf("%s: mask %#"PRIx64"\n", 1464 __func__, RMIXL_PCIE_LINK_STATUS_ERRORS); 1465 printf("%s: PCIe Link Error: link=%d status0=%#x status1=%#x\n", 1466 __func__, link, status0, status1); 1467 #if defined(DDB) && defined(DEBUG) 1468 Debugger(); 1469 #endif 1470 } 1471 1472 #if defined(DEBUG) || defined(DDB) 1473 /* this function exists to facilitate call from ddb */ 1474 int 1475 rmixl_pcie_error_check(void) 1476 { 1477 if (rmixl_pcie_v != 0) 1478 return _rmixl_pcie_error_check(rmixl_pcie_v); 1479 return -1; 1480 } 1481 #endif 1482 1483 STATIC int 1484 _rmixl_pcie_error_check(void *v) 1485 { 1486 int i, offset; 1487 pcireg_t r; 1488 pcitag_t tag; 1489 int err=0; 1490 #ifdef DIAGNOSTIC 1491 pcireg_t regs[PCIE_ECFG_ERRS_OFFTAB_NENTRIES]; 1492 #endif 1493 1494 tag = rmixl_pcie_make_tag(v, 0, 0, 0); /* XXX */ 1495 1496 for (i=0; i < PCIE_ECFG_ERRS_OFFTAB_NENTRIES; i++) { 1497 offset = pcie_ecfg_errs_tab[i].offset; 1498 r = rmixl_pcie_conf_read(v, tag, offset); 1499 #ifdef DIAGNOSTIC 1500 regs[i] = r; 1501 #endif 1502 if (r != 0) { 1503 pcireg_t rw1c = r & pcie_ecfg_errs_tab[i].rw1c; 1504 if (rw1c != 0) { 1505 /* attempt to clear the error */ 1506 rmixl_pcie_conf_write(v, tag, offset, rw1c); 1507 }; 1508 if (offset == RMIXL_PCIE_ECFG_CESR) 1509 err |= 1; /* correctable */ 1510 else 1511 err |= 2; /* uncorrectable */ 1512 } 1513 } 1514 #ifdef DIAGNOSTIC 1515 if (err != 0) { 1516 for (i=0; i < PCIE_ECFG_ERRS_OFFTAB_NENTRIES; i++) { 1517 offset = pcie_ecfg_errs_tab[i].offset; 1518 printf("%s: %#x: %#x\n", __func__, offset, regs[i]); 1519 } 1520 } 1521 #endif 1522 1523 return err; 1524 } 1525 1526 static int 1527 rmixl_pcie_error_intr(void *v) 1528 { 1529 if (_rmixl_pcie_error_check(v) < 2) 1530 return 0; /* correctable */ 1531 1532 /* uncorrectable */ 1533 #if DDB 1534 Debugger(); 1535 #endif 1536 1537 /* XXX reset and recover? */ 1538 1539 panic("%s\n", __func__); 1540 } 1541 1542 /* 1543 * rmixl_physaddr_init_pcie: 1544 * called from rmixl_physaddr_init to get region addrs & sizes 1545 * from PCIE CFG, ECFG, IO, MEM BARs 1546 */ 1547 void 1548 rmixl_physaddr_init_pcie(struct extent *ext) 1549 { 1550 u_long base; 1551 u_long size; 1552 uint32_t r; 1553 1554 r = RMIXL_IOREG_READ(RMIXLS_SBC_PCIE_CFG_BAR); 1555 if ((r & RMIXL_PCIE_CFG_BAR_ENB) != 0) { 1556 base = (u_long)(RMIXL_PCIE_CFG_BAR_TO_BA((uint64_t)r) 1557 / (1024 * 1024)); 1558 size = (u_long)RMIXL_PCIE_CFG_SIZE / (1024 * 1024); 1559 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1560 __LINE__, "CFG", r, base * 1024 * 1024, size)); 1561 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1562 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1563 "failed", __func__, ext, base, size, EX_NOWAIT); 1564 } 1565 1566 r = RMIXL_IOREG_READ(RMIXLS_SBC_PCIE_ECFG_BAR); 1567 if ((r & RMIXL_PCIE_ECFG_BAR_ENB) != 0) { 1568 base = (u_long)(RMIXL_PCIE_ECFG_BAR_TO_BA((uint64_t)r) 1569 / (1024 * 1024)); 1570 size = (u_long)RMIXL_PCIE_ECFG_SIZE / (1024 * 1024); 1571 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1572 __LINE__, "ECFG", r, base * 1024 * 1024, size)); 1573 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1574 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1575 "failed", __func__, ext, base, size, EX_NOWAIT); 1576 } 1577 1578 r = RMIXL_IOREG_READ(RMIXLS_SBC_PCIE_MEM_BAR); 1579 if ((r & RMIXL_PCIE_MEM_BAR_ENB) != 0) { 1580 base = (u_long)(RMIXL_PCIE_MEM_BAR_TO_BA((uint64_t)r) 1581 / (1024 * 1024)); 1582 size = (u_long)(RMIXL_PCIE_MEM_BAR_TO_SIZE((uint64_t)r) 1583 / (1024 * 1024)); 1584 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1585 __LINE__, "MEM", r, base * 1024 * 1024, size)); 1586 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1587 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1588 "failed", __func__, ext, base, size, EX_NOWAIT); 1589 } 1590 1591 r = RMIXL_IOREG_READ(RMIXLS_SBC_PCIE_IO_BAR); 1592 if ((r & RMIXL_PCIE_IO_BAR_ENB) != 0) { 1593 base = (u_long)(RMIXL_PCIE_IO_BAR_TO_BA((uint64_t)r) 1594 / (1024 * 1024)); 1595 size = (u_long)(RMIXL_PCIE_IO_BAR_TO_SIZE((uint64_t)r) 1596 / (1024 * 1024)); 1597 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1598 __LINE__, "IO", r, base * 1024 * 1024, size)); 1599 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1600 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1601 "failed", __func__, ext, base, size, EX_NOWAIT); 1602 } 1603 } 1604
Indexes created Fri Sep 26 08:10:20 GMT 2025