rmixl_pcie.c revision 1.8.2.3
1 /* $NetBSD: rmixl_pcie.c,v 1.8.2.3 2014/05/22 11:39:58 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * PCI configuration support for RMI XLS SoC 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: rmixl_pcie.c,v 1.8.2.3 2014/05/22 11:39:58 yamt Exp $"); 44 45 #include "opt_pci.h" 46 #include "pci.h" 47 48 #include <sys/cdefs.h> 49 50 #include <sys/param.h> 51 #include <sys/bus.h> 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/extent.h> 55 #include <sys/intr.h> 56 #include <sys/kernel.h> /* for 'hz' */ 57 #include <sys/malloc.h> 58 #include <sys/systm.h> 59 60 #include <uvm/uvm_extern.h> 61 62 #include <mips/rmi/rmixlreg.h> 63 #include <mips/rmi/rmixlvar.h> 64 #include <mips/rmi/rmixl_intr.h> 65 #include <mips/rmi/rmixl_pcievar.h> 66 67 #include <mips/rmi/rmixl_obiovar.h> 68 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pcidevs.h> 71 #include <dev/pci/pciconf.h> 72 73 #ifdef PCI_NETBSD_CONFIGURE 74 #include <mips/cache.h> 75 #endif 76 77 #ifdef PCI_DEBUG 78 int rmixl_pcie_debug = PCI_DEBUG; 79 # define DPRINTF(x) do { if (rmixl_pcie_debug) printf x ; } while (0) 80 #else 81 # define DPRINTF(x) 82 #endif 83 84 #ifndef DDB 85 # define STATIC static 86 #else 87 # define STATIC 88 #endif 89 90 91 /* 92 * XLS PCIe Extended Configuration Registers 93 */ 94 #define RMIXL_PCIE_ECFG_UESR 0x104 /* Uncorrectable Error Status Reg */ 95 #define RMIXL_PCIE_ECFG_UEMR 0x108 /* Uncorrectable Error Mask Reg */ 96 #define RMIXL_PCIE_ECFG_UEVR 0x10c /* Uncorrectable Error seVerity Reg */ 97 #define PCIE_ECFG_UEVR_DFLT \ 98 (__BITS(18,17) | __BIT(31) | __BITS(5,4) | __BIT(0)) 99 #define PCIE_ECFG_UExR_RESV (__BITS(31,21) | __BITS(11,6) | __BITS(3,1)) 100 #define RMIXL_PCIE_ECFG_CESR 0x110 /* Correctable Error Status Reg */ 101 #define RMIXL_PCIE_ECFG_CEMR 0x114 /* Correctable Error Mask Reg */ 102 #define PCIE_ECFG_CExR_RESV (__BITS(31,14) | __BITS(11,9) | __BITS(5,1)) 103 #define RMIXL_PCIE_ECFG_ACCR 0x118 /* Adv. Capabilities Control Reg */ 104 #define RMIXL_PCIE_ECFG_HLRn(n) (0x11c + ((n) * 4)) /* Header Log Regs */ 105 #define RMIXL_PCIE_ECFG_RECR 0x12c /* Root Error Command Reg */ 106 #define PCIE_ECFG_RECR_RESV __BITS(31,3) 107 #define RMIXL_PCIE_ECFG_RESR 0x130 /* Root Error Status Reg */ 108 #define PCIE_ECFG_RESR_RESV __BITS(26,7) 109 #define RMIXL_PCIE_ECFG_ESI 0x134 /* Error Source Identification Reg */ 110 #define RMIXL_PCIE_ECFG_DSNCR 0x140 /* Dev Serial Number Capability Regs */ 111 112 static const struct { 113 u_int offset; 114 u_int32_t rw1c; 115 } pcie_ecfg_errs_tab[] = { 116 { RMIXL_PCIE_ECFG_UESR, (__BITS(20,12) | __BIT(4)) }, 117 { RMIXL_PCIE_ECFG_CESR, (__BITS(20,12) | __BIT(4)) }, 118 { RMIXL_PCIE_ECFG_HLRn(0), 0 }, 119 { RMIXL_PCIE_ECFG_HLRn(1), 0 }, 120 { RMIXL_PCIE_ECFG_HLRn(2), 0 }, 121 { RMIXL_PCIE_ECFG_HLRn(3), 0 }, 122 { RMIXL_PCIE_ECFG_RESR, __BITS(6,0) }, 123 { RMIXL_PCIE_ECFG_ESI, 0 }, 124 }; 125 #define PCIE_ECFG_ERRS_OFFTAB_NENTRIES \ 126 (sizeof(pcie_ecfg_errs_tab)/sizeof(pcie_ecfg_errs_tab[0])) 127 128 typedef struct rmixl_pcie_int_csr { 129 uint r0; 130 uint r1; 131 } rmixl_pcie_int_csr_t; 132 133 static const rmixl_pcie_int_csr_t int_enb_offset[4] = { 134 { RMIXL_PCIE_LINK0_INT_ENABLE0, RMIXL_PCIE_LINK0_INT_ENABLE1 }, 135 { RMIXL_PCIE_LINK1_INT_ENABLE0, RMIXL_PCIE_LINK1_INT_ENABLE1 }, 136 { RMIXL_PCIE_LINK2_INT_ENABLE0, RMIXL_PCIE_LINK2_INT_ENABLE1 }, 137 { RMIXL_PCIE_LINK3_INT_ENABLE0, RMIXL_PCIE_LINK3_INT_ENABLE1 }, 138 }; 139 140 static const rmixl_pcie_int_csr_t int_sts_offset[4] = { 141 { RMIXL_PCIE_LINK0_INT_STATUS0, RMIXL_PCIE_LINK0_INT_STATUS1 }, 142 { RMIXL_PCIE_LINK1_INT_STATUS0, RMIXL_PCIE_LINK1_INT_STATUS1 }, 143 { RMIXL_PCIE_LINK2_INT_STATUS0, RMIXL_PCIE_LINK2_INT_STATUS1 }, 144 { RMIXL_PCIE_LINK3_INT_STATUS0, RMIXL_PCIE_LINK3_INT_STATUS1 }, 145 }; 146 147 static const u_int msi_enb_offset[4] = { 148 RMIXL_PCIE_LINK0_MSI_ENABLE, 149 RMIXL_PCIE_LINK1_MSI_ENABLE, 150 RMIXL_PCIE_LINK2_MSI_ENABLE, 151 RMIXL_PCIE_LINK3_MSI_ENABLE 152 }; 153 154 #define RMIXL_PCIE_LINK_STATUS0_ERRORS __BITS(6,4) 155 #define RMIXL_PCIE_LINK_STATUS1_ERRORS __BITS(10,0) 156 #define RMIXL_PCIE_LINK_STATUS_ERRORS \ 157 ((((uint64_t)RMIXL_PCIE_LINK_STATUS1_ERRORS) << 32) | \ 158 (uint64_t)RMIXL_PCIE_LINK_STATUS0_ERRORS) 159 160 #define RMIXL_PCIE_EVCNT(sc, link, bitno, cpu) \ 161 &(sc)->sc_evcnts[link][(bitno) * (ncpu) + (cpu)] 162 163 static int rmixl_pcie_match(device_t, cfdata_t, void *); 164 static void rmixl_pcie_attach(device_t, device_t, void *); 165 static void rmixl_pcie_init(struct rmixl_pcie_softc *); 166 static void rmixl_pcie_init_ecfg(struct rmixl_pcie_softc *); 167 static void rmixl_pcie_attach_hook(device_t, device_t, 168 struct pcibus_attach_args *); 169 static void rmixl_pcie_lnkcfg_4xx(rmixl_pcie_lnktab_t *, uint32_t); 170 static void rmixl_pcie_lnkcfg_408Lite(rmixl_pcie_lnktab_t *, uint32_t); 171 static void rmixl_pcie_lnkcfg_2xx(rmixl_pcie_lnktab_t *, uint32_t); 172 static void rmixl_pcie_lnkcfg_1xx(rmixl_pcie_lnktab_t *, uint32_t); 173 static void rmixl_pcie_lnkcfg(struct rmixl_pcie_softc *); 174 static void rmixl_pcie_intcfg(struct rmixl_pcie_softc *); 175 static void rmixl_pcie_errata(struct rmixl_pcie_softc *); 176 static void rmixl_conf_interrupt(void *, int, int, int, int, int *); 177 static int rmixl_pcie_bus_maxdevs(void *, int); 178 static pcitag_t rmixl_tag_to_ecfg(pcitag_t); 179 static pcitag_t rmixl_pcie_make_tag(void *, int, int, int); 180 static void rmixl_pcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 181 void rmixl_pcie_tag_print(const char *restrict, void *, pcitag_t, int, vaddr_t, u_long); 182 static int rmixl_pcie_conf_setup(struct rmixl_pcie_softc *, 183 pcitag_t, int *, bus_space_tag_t *, 184 bus_space_handle_t *); 185 static pcireg_t rmixl_pcie_conf_read(void *, pcitag_t, int); 186 static void rmixl_pcie_conf_write(void *, pcitag_t, int, pcireg_t); 187 188 static int rmixl_pcie_intr_map(const struct pci_attach_args *, 189 pci_intr_handle_t *); 190 static const char * 191 rmixl_pcie_intr_string(void *, pci_intr_handle_t, char *, 192 size_t); 193 static const struct evcnt * 194 rmixl_pcie_intr_evcnt(void *, pci_intr_handle_t); 195 static pci_intr_handle_t 196 rmixl_pcie_make_pih(u_int, u_int, u_int); 197 static void rmixl_pcie_decompose_pih(pci_intr_handle_t, u_int *, u_int *, u_int *); 198 static void rmixl_pcie_intr_disestablish(void *, void *); 199 static void *rmixl_pcie_intr_establish(void *, pci_intr_handle_t, 200 int, int (*)(void *), void *); 201 static rmixl_pcie_link_intr_t * 202 rmixl_pcie_lip_add_1(rmixl_pcie_softc_t *, u_int, int, int); 203 static void rmixl_pcie_lip_free_callout(rmixl_pcie_link_intr_t *); 204 static void rmixl_pcie_lip_free(void *); 205 static int rmixl_pcie_intr(void *); 206 static void rmixl_pcie_link_error_intr(u_int, uint32_t, uint32_t); 207 #if defined(DEBUG) || defined(DDB) 208 int rmixl_pcie_error_check(void); 209 #endif 210 static int _rmixl_pcie_error_check(void *); 211 static int rmixl_pcie_error_intr(void *); 212 213 214 #define RMIXL_PCIE_CONCAT3(a,b,c) a ## b ## c 215 #define RMIXL_PCIE_BAR_INIT(reg, bar, size, align) { \ 216 struct extent *ext = rmixl_configuration.rc_phys_ex; \ 217 u_long region_start; \ 218 uint64_t ba; \ 219 int err; \ 220 \ 221 err = extent_alloc(ext, (size), (align), 0UL, EX_NOWAIT, \ 222 ®ion_start); \ 223 if (err != 0) \ 224 panic("%s: extent_alloc(%p, %#lx, %#lx, %#lx, %#x, %p)",\ 225 __func__, ext, size, align, 0UL, EX_NOWAIT, \ 226 ®ion_start); \ 227 ba = (uint64_t)region_start; \ 228 ba *= (1024 * 1024); \ 229 bar = RMIXL_PCIE_CONCAT3(RMIXL_PCIE_,reg,_BAR)(ba, 1); \ 230 DPRINTF(("PCIE %s BAR was not enabled by firmware\n" \ 231 "enabling %s at phys %#" PRIxBUSADDR ", size %lu MB\n", \ 232 __STRING(reg), __STRING(reg), ba, size)); \ 233 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_BRIDGE + \ 234 RMIXL_PCIE_CONCAT3(RMIXLS_SBC_PCIE_,reg,_BAR), bar); \ 235 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + \ 236 RMIXL_PCIE_CONCAT3(RMIXLS_SBC_PCIE_,reg,_BAR)); \ 237 DPRINTF(("%s: %s BAR %#x\n", __func__, __STRING(reg), bar)); \ 238 } 239 240 241 #if defined(DEBUG) || defined(DDB) 242 static void *rmixl_pcie_v; 243 #endif 244 245 CFATTACH_DECL_NEW(rmixl_pcie, sizeof(struct rmixl_pcie_softc), 246 rmixl_pcie_match, rmixl_pcie_attach, NULL, NULL); 247 248 static int rmixl_pcie_found; 249 250 static int 251 rmixl_pcie_match(device_t parent, cfdata_t cf, void *aux) 252 { 253 uint32_t r; 254 255 /* 256 * PCIe interface exists on XLS chips only 257 */ 258 if (! cpu_rmixls(mips_options.mips_cpu)) 259 return 0; 260 261 /* XXX 262 * for now there is only one PCIe Interface on chip 263 * this could change with furture RMI XL family designs 264 */ 265 if (rmixl_pcie_found) 266 return 0; 267 268 /* read GPIO Reset Configuration register */ 269 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET_CFG); 270 r >>= 26; 271 r &= 3; 272 if (r != 0) 273 return 0; /* strapped for SRIO */ 274 275 return 1; 276 } 277 278 static void 279 rmixl_pcie_attach(device_t parent, device_t self, void *aux) 280 { 281 struct rmixl_pcie_softc *sc = device_private(self); 282 struct obio_attach_args *obio = aux; 283 struct rmixl_config *rcp = &rmixl_configuration; 284 struct pcibus_attach_args pba; 285 uint32_t bar; 286 287 rmixl_pcie_found = 1; 288 sc->sc_dev = self; 289 290 aprint_normal(" RMI XLS PCIe Interface\n"); 291 292 mutex_init(&sc->sc_mutex, MUTEX_DEFAULT, IPL_HIGH); 293 294 rmixl_pcie_lnkcfg(sc); 295 296 rmixl_pcie_intcfg(sc); 297 298 rmixl_pcie_errata(sc); 299 300 sc->sc_29bit_dmat = obio->obio_29bit_dmat; 301 sc->sc_32bit_dmat = obio->obio_32bit_dmat; 302 sc->sc_64bit_dmat = obio->obio_64bit_dmat; 303 304 sc->sc_tmsk = obio->obio_tmsk; 305 306 /* 307 * get PCI config space base addr from SBC PCIe CFG BAR 308 * initialize it if necessary 309 */ 310 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLS_SBC_PCIE_CFG_BAR); 311 DPRINTF(("%s: PCIE_CFG_BAR %#x\n", __func__, bar)); 312 if ((bar & RMIXL_PCIE_CFG_BAR_ENB) == 0) { 313 u_long n = RMIXL_PCIE_CFG_SIZE / (1024 * 1024); 314 RMIXL_PCIE_BAR_INIT(CFG, bar, n, n); 315 } 316 rcp->rc_pci_cfg_pbase = (bus_addr_t)RMIXL_PCIE_CFG_BAR_TO_BA(bar); 317 rcp->rc_pci_cfg_size = (bus_size_t)RMIXL_PCIE_CFG_SIZE; 318 319 /* 320 * get PCIE Extended config space base addr from SBC PCIe ECFG BAR 321 * initialize it if necessary 322 */ 323 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLS_SBC_PCIE_ECFG_BAR); 324 DPRINTF(("%s: PCIE_ECFG_BAR %#x\n", __func__, bar)); 325 if ((bar & RMIXL_PCIE_ECFG_BAR_ENB) == 0) { 326 u_long n = RMIXL_PCIE_ECFG_SIZE / (1024 * 1024); 327 RMIXL_PCIE_BAR_INIT(ECFG, bar, n, n); 328 } 329 rcp->rc_pci_ecfg_pbase = (bus_addr_t)RMIXL_PCIE_ECFG_BAR_TO_BA(bar); 330 rcp->rc_pci_ecfg_size = (bus_size_t)RMIXL_PCIE_ECFG_SIZE; 331 332 /* 333 * get PCI MEM space base [addr, size] from SBC PCIe MEM BAR 334 * initialize it if necessary 335 */ 336 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLS_SBC_PCIE_MEM_BAR); 337 DPRINTF(("%s: PCIE_MEM_BAR %#x\n", __func__, bar)); 338 if ((bar & RMIXL_PCIE_MEM_BAR_ENB) == 0) { 339 u_long n = 256; /* 256 MB */ 340 RMIXL_PCIE_BAR_INIT(MEM, bar, n, n); 341 } 342 rcp->rc_pci_mem_pbase = (bus_addr_t)RMIXL_PCIE_MEM_BAR_TO_BA(bar); 343 rcp->rc_pci_mem_size = (bus_size_t)RMIXL_PCIE_MEM_BAR_TO_SIZE(bar); 344 345 /* 346 * get PCI IO space base [addr, size] from SBC PCIe IO BAR 347 * initialize it if necessary 348 */ 349 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLS_SBC_PCIE_IO_BAR); 350 DPRINTF(("%s: PCIE_IO_BAR %#x\n", __func__, bar)); 351 if ((bar & RMIXL_PCIE_IO_BAR_ENB) == 0) { 352 u_long n = 32; /* 32 MB */ 353 RMIXL_PCIE_BAR_INIT(IO, bar, n, n); 354 } 355 rcp->rc_pci_io_pbase = (bus_addr_t)RMIXL_PCIE_IO_BAR_TO_BA(bar); 356 rcp->rc_pci_io_size = (bus_size_t)RMIXL_PCIE_IO_BAR_TO_SIZE(bar); 357 358 /* 359 * initialize the PCI CFG, ECFG bus space tags 360 */ 361 rmixl_pci_cfg_bus_mem_init(&rcp->rc_pci_cfg_memt, rcp); 362 sc->sc_pci_cfg_memt = &rcp->rc_pci_cfg_memt; 363 364 rmixl_pci_ecfg_bus_mem_init(&rcp->rc_pci_ecfg_memt, rcp); 365 sc->sc_pci_ecfg_memt = &rcp->rc_pci_ecfg_memt; 366 367 /* 368 * initialize the PCI MEM and IO bus space tags 369 */ 370 rmixl_pci_bus_mem_init(&rcp->rc_pci_memt, rcp); 371 rmixl_pci_bus_io_init(&rcp->rc_pci_iot, rcp); 372 373 /* 374 * initialize the extended configuration regs 375 */ 376 rmixl_pcie_init_ecfg(sc); 377 378 /* 379 * initialize the PCI chipset tag 380 */ 381 rmixl_pcie_init(sc); 382 383 /* 384 * attach the PCI bus 385 */ 386 memset(&pba, 0, sizeof(pba)); 387 pba.pba_memt = &rcp->rc_pci_memt; 388 pba.pba_iot = &rcp->rc_pci_iot; 389 pba.pba_dmat = sc->sc_32bit_dmat; 390 pba.pba_dmat64 = sc->sc_64bit_dmat; 391 pba.pba_pc = &sc->sc_pci_chipset; 392 pba.pba_bus = 0; 393 pba.pba_bridgetag = NULL; 394 pba.pba_intrswiz = 0; 395 pba.pba_intrtag = 0; 396 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY | 397 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 398 399 (void) config_found_ia(self, "pcibus", &pba, pcibusprint); 400 } 401 402 /* 403 * rmixl_pcie_lnkcfg_4xx - link configs for XLS4xx and XLS6xx 404 * use IO_AD[11] and IO_AD[10], observable in 405 * Bits[21:20] of the GPIO Reset Configuration register 406 */ 407 static void 408 rmixl_pcie_lnkcfg_4xx(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 409 { 410 u_int index; 411 static const rmixl_pcie_lnkcfg_t lnktab_4xx[4][4] = { 412 {{ LCFG_EP, 4}, {LCFG_NO, 0}, {LCFG_NO, 0}, {LCFG_NO, 0}}, 413 {{ LCFG_RC, 4}, {LCFG_NO, 0}, {LCFG_NO, 0}, {LCFG_NO, 0}}, 414 {{ LCFG_EP, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}}, 415 {{ LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}}, 416 }; 417 static const char *lnkstr_4xx[4] = { 418 "1EPx4", 419 "1RCx4", 420 "1EPx1, 3RCx1", 421 "4RCx1" 422 }; 423 index = (grcr >> 20) & 3; 424 ltp->ncfgs = 4; 425 ltp->cfg = lnktab_4xx[index]; 426 ltp->str = lnkstr_4xx[index]; 427 } 428 429 /* 430 * rmixl_pcie_lnkcfg_408Lite - link configs for XLS408Lite and XLS04A 431 * use IO_AD[11] and IO_AD[10], observable in 432 * Bits[21:20] of the GPIO Reset Configuration register 433 */ 434 static void 435 rmixl_pcie_lnkcfg_408Lite(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 436 { 437 u_int index; 438 static const rmixl_pcie_lnkcfg_t lnktab_408Lite[4][2] = { 439 {{ LCFG_EP, 4}, {LCFG_NO, 0}}, 440 {{ LCFG_RC, 4}, {LCFG_NO, 0}}, 441 {{ LCFG_EP, 1}, {LCFG_RC, 1}}, 442 {{ LCFG_RC, 1}, {LCFG_RC, 1}}, 443 }; 444 static const char *lnkstr_408Lite[4] = { 445 "4EPx4", 446 "1RCx4", 447 "1EPx1, 1RCx1", 448 "2RCx1" 449 }; 450 451 index = (grcr >> 20) & 3; 452 ltp->ncfgs = 2; 453 ltp->cfg = lnktab_408Lite[index]; 454 ltp->str = lnkstr_408Lite[index]; 455 } 456 457 /* 458 * rmixl_pcie_lnkcfg_2xx - link configs for XLS2xx 459 * use IO_AD[10], observable in Bit[20] of the 460 * GPIO Reset Configuration register 461 */ 462 static void 463 rmixl_pcie_lnkcfg_2xx(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 464 { 465 u_int index; 466 static const rmixl_pcie_lnkcfg_t lnktab_2xx[2][4] = { 467 {{ LCFG_EP, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}}, 468 {{ LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}} 469 }; 470 static const char *lnkstr_2xx[2] = { 471 "1EPx1, 3RCx1", 472 "4RCx1", 473 }; 474 475 index = (grcr >> 20) & 1; 476 ltp->ncfgs = 4; 477 ltp->cfg = lnktab_2xx[index]; 478 ltp->str = lnkstr_2xx[index]; 479 } 480 481 /* 482 * rmixl_pcie_lnkcfg_1xx - link configs for XLS1xx 483 * use IO_AD[10], observable in Bit[20] of the 484 * GPIO Reset Configuration register 485 */ 486 static void 487 rmixl_pcie_lnkcfg_1xx(rmixl_pcie_lnktab_t *ltp, uint32_t grcr) 488 { 489 u_int index; 490 static const rmixl_pcie_lnkcfg_t lnktab_1xx[2][2] = { 491 {{ LCFG_EP, 1}, {LCFG_RC, 1}}, 492 {{ LCFG_RC, 1}, {LCFG_RC, 1}} 493 }; 494 static const char *lnkstr_1xx[2] = { 495 "1EPx1, 1RCx1", 496 "2RCx1", 497 }; 498 499 index = (grcr >> 20) & 1; 500 ltp->ncfgs = 2; 501 ltp->cfg = lnktab_1xx[index]; 502 ltp->str = lnkstr_1xx[index]; 503 } 504 505 /* 506 * rmixl_pcie_lnkcfg - determine PCI Express Link Configuration 507 */ 508 static void 509 rmixl_pcie_lnkcfg(struct rmixl_pcie_softc *sc) 510 { 511 uint32_t r; 512 513 /* read GPIO Reset Configuration register */ 514 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET_CFG); 515 DPRINTF(("%s: GPIO RCR %#x\n", __func__, r)); 516 517 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 518 case MIPS_XLS104: 519 case MIPS_XLS108: 520 rmixl_pcie_lnkcfg_1xx(&sc->sc_pcie_lnktab, r); 521 break; 522 case MIPS_XLS204: 523 case MIPS_XLS208: 524 rmixl_pcie_lnkcfg_2xx(&sc->sc_pcie_lnktab, r); 525 break; 526 case MIPS_XLS404LITE: 527 case MIPS_XLS408LITE: 528 rmixl_pcie_lnkcfg_408Lite(&sc->sc_pcie_lnktab, r); 529 break; 530 case MIPS_XLS404: 531 case MIPS_XLS408: 532 case MIPS_XLS416: 533 case MIPS_XLS608: 534 case MIPS_XLS616: 535 /* 6xx uses same table as 4xx */ 536 rmixl_pcie_lnkcfg_4xx(&sc->sc_pcie_lnktab, r); 537 break; 538 default: 539 panic("%s: unknown RMI PRID IMPL", __func__); 540 } 541 542 aprint_normal("%s: link config %s\n", 543 device_xname(sc->sc_dev), sc->sc_pcie_lnktab.str); 544 } 545 546 /* 547 * rmixl_pcie_intcfg - init PCIe Link interrupt enables 548 */ 549 static void 550 rmixl_pcie_intcfg(struct rmixl_pcie_softc *sc) 551 { 552 int link; 553 size_t size; 554 rmixl_pcie_evcnt_t *ev; 555 556 DPRINTF(("%s: disable all link interrupts\n", __func__)); 557 for (link=0; link < sc->sc_pcie_lnktab.ncfgs; link++) { 558 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + int_enb_offset[link].r0, 559 RMIXL_PCIE_LINK_STATUS0_ERRORS); 560 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + int_enb_offset[link].r1, 561 RMIXL_PCIE_LINK_STATUS1_ERRORS); 562 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + msi_enb_offset[link], 0); 563 sc->sc_link_intr[link] = NULL; 564 565 /* 566 * allocate per-cpu, per-pin interrupt event counters 567 */ 568 size = ncpu * PCI_INTERRUPT_PIN_MAX * sizeof(rmixl_pcie_evcnt_t); 569 ev = malloc(size, M_DEVBUF, M_NOWAIT); 570 if (ev == NULL) 571 panic("%s: cannot malloc evcnts\n", __func__); 572 sc->sc_evcnts[link] = ev; 573 for (int pin=PCI_INTERRUPT_PIN_A; pin <= PCI_INTERRUPT_PIN_MAX; pin++) { 574 for (int cpu=0; cpu < ncpu; cpu++) { 575 ev = RMIXL_PCIE_EVCNT(sc, link, pin - 1, cpu); 576 snprintf(ev->name, sizeof(ev->name), 577 "cpu%d, link %d, pin %d", cpu, link, pin); 578 evcnt_attach_dynamic(&ev->evcnt, EVCNT_TYPE_INTR, 579 NULL, "rmixl_pcie", ev->name); 580 } 581 } 582 } 583 } 584 585 static void 586 rmixl_pcie_errata(struct rmixl_pcie_softc *sc) 587 { 588 const mips_prid_t cpu_id = mips_options.mips_cpu_id; 589 u_int rev; 590 u_int lanes; 591 bool e391 = false; 592 593 /* 594 * 3.9.1 PCIe Link-0 Registers Reset to Incorrect Values 595 * check if it allies to this CPU implementation and revision 596 */ 597 rev = MIPS_PRID_REV(cpu_id); 598 switch (MIPS_PRID_IMPL(cpu_id)) { 599 case MIPS_XLS104: 600 case MIPS_XLS108: 601 break; 602 case MIPS_XLS204: 603 case MIPS_XLS208: 604 /* stepping A0 is affected */ 605 if (rev == 0) 606 e391 = true; 607 break; 608 case MIPS_XLS404LITE: 609 case MIPS_XLS408LITE: 610 break; 611 case MIPS_XLS404: 612 case MIPS_XLS408: 613 case MIPS_XLS416: 614 /* steppings A0 and A1 are affected */ 615 if ((rev == 0) || (rev == 1)) 616 e391 = true; 617 break; 618 case MIPS_XLS608: 619 case MIPS_XLS616: 620 break; 621 default: 622 panic("unknown RMI PRID IMPL"); 623 } 624 625 /* 626 * for XLS we only need to check entry #0 627 * this may need to change for later XL family chips 628 */ 629 lanes = sc->sc_pcie_lnktab.cfg[0].lanes; 630 631 if ((e391 != false) && ((lanes == 2) || (lanes == 4))) { 632 /* 633 * attempt work around for errata 3.9.1 634 * "PCIe Link-0 Registers Reset to Incorrect Values" 635 * the registers are write-once: if the firmware already wrote, 636 * then our writes are ignored; hope they did it right. 637 */ 638 uint32_t queuectrl; 639 uint32_t bufdepth; 640 #ifdef DIAGNOSTIC 641 uint32_t r; 642 #endif 643 644 aprint_normal("%s: attempt work around for errata 3.9.1", 645 device_xname(sc->sc_dev)); 646 if (lanes == 4) { 647 queuectrl = 0x00018074; 648 bufdepth = 0x001901D1; 649 } else { 650 queuectrl = 0x00018036; 651 bufdepth = 0x001900D9; 652 } 653 654 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_BE + 655 RMIXL_VC0_POSTED_RX_QUEUE_CTRL, queuectrl); 656 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_BE + 657 RMIXL_VC0_POSTED_BUFFER_DEPTH, bufdepth); 658 659 #ifdef DIAGNOSTIC 660 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_BE + 661 RMIXL_VC0_POSTED_RX_QUEUE_CTRL); 662 printf("\nVC0_POSTED_RX_QUEUE_CTRL %#x\n", r); 663 664 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_BE + 665 RMIXL_VC0_POSTED_BUFFER_DEPTH); 666 printf("VC0_POSTED_BUFFER_DEPTH %#x\n", r); 667 #endif 668 } 669 } 670 671 static void 672 rmixl_pcie_init(struct rmixl_pcie_softc *sc) 673 { 674 pci_chipset_tag_t pc = &sc->sc_pci_chipset; 675 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 676 struct extent *ioext, *memext; 677 #endif 678 679 pc->pc_conf_v = (void *)sc; 680 pc->pc_attach_hook = rmixl_pcie_attach_hook; 681 pc->pc_bus_maxdevs = rmixl_pcie_bus_maxdevs; 682 pc->pc_make_tag = rmixl_pcie_make_tag; 683 pc->pc_decompose_tag = rmixl_pcie_decompose_tag; 684 pc->pc_conf_read = rmixl_pcie_conf_read; 685 pc->pc_conf_write = rmixl_pcie_conf_write; 686 687 pc->pc_intr_v = (void *)sc; 688 pc->pc_intr_map = rmixl_pcie_intr_map; 689 pc->pc_intr_string = rmixl_pcie_intr_string; 690 pc->pc_intr_evcnt = rmixl_pcie_intr_evcnt; 691 pc->pc_intr_establish = rmixl_pcie_intr_establish; 692 pc->pc_intr_disestablish = rmixl_pcie_intr_disestablish; 693 pc->pc_conf_interrupt = rmixl_conf_interrupt; 694 695 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 696 /* 697 * Configure the PCI bus. 698 */ 699 struct rmixl_config *rcp = &rmixl_configuration; 700 701 aprint_normal("%s: configuring PCI bus\n", 702 device_xname(sc->sc_dev)); 703 704 ioext = extent_create("pciio", 705 rcp->rc_pci_io_pbase, 706 rcp->rc_pci_io_pbase + rcp->rc_pci_io_size - 1, 707 NULL, 0, EX_NOWAIT); 708 709 memext = extent_create("pcimem", 710 rcp->rc_pci_mem_pbase, 711 rcp->rc_pci_mem_pbase + rcp->rc_pci_mem_size - 1, 712 NULL, 0, EX_NOWAIT); 713 714 pci_configure_bus(pc, ioext, memext, NULL, 0, 715 mips_cache_info.mci_dcache_align); 716 717 extent_destroy(ioext); 718 extent_destroy(memext); 719 #endif 720 } 721 722 static void 723 rmixl_pcie_init_ecfg(struct rmixl_pcie_softc *sc) 724 { 725 void *v; 726 pcitag_t tag; 727 pcireg_t r; 728 729 v = sc; 730 tag = rmixl_pcie_make_tag(v, 0, 0, 0); 731 732 #ifdef PCI_DEBUG 733 int i, offset; 734 static const int offtab[] = 735 { 0, 4, 8, 0xc, 0x10, 0x14, 0x18, 0x1c, 736 0x2c, 0x30, 0x34 }; 737 for (i=0; i < sizeof(offtab)/sizeof(offtab[0]); i++) { 738 offset = 0x100 + offtab[i]; 739 r = rmixl_pcie_conf_read(v, tag, offset); 740 printf("%s: %#x: %#x\n", __func__, offset, r); 741 } 742 #endif 743 r = rmixl_pcie_conf_read(v, tag, 0x100); 744 if (r == -1) 745 return; /* cannot access */ 746 747 /* check pre-existing uncorrectable errs */ 748 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_UESR); 749 r &= ~PCIE_ECFG_UExR_RESV; 750 if (r != 0) 751 panic("%s: Uncorrectable Error Status: %#x\n", 752 __func__, r); 753 754 /* unmask all uncorrectable errs */ 755 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_UEMR); 756 r &= ~PCIE_ECFG_UExR_RESV; 757 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_UEMR, r); 758 759 /* ensure default uncorrectable err severity confniguration */ 760 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_UEVR); 761 r &= ~PCIE_ECFG_UExR_RESV; 762 r |= PCIE_ECFG_UEVR_DFLT; 763 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_UEVR, r); 764 765 /* check pre-existing correctable errs */ 766 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_CESR); 767 r &= ~PCIE_ECFG_CExR_RESV; 768 #ifdef DIAGNOSTIC 769 if (r != 0) 770 aprint_normal("%s: Correctable Error Status: %#x\n", 771 device_xname(sc->sc_dev), r); 772 #endif 773 774 /* unmask all correctable errs */ 775 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_CEMR); 776 r &= ~PCIE_ECFG_CExR_RESV; 777 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_UEMR, r); 778 779 /* check pre-existing Root Error Status */ 780 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_RESR); 781 r &= ~PCIE_ECFG_RESR_RESV; 782 if (r != 0) 783 panic("%s: Root Error Status: %#x\n", __func__, r); 784 /* XXX TMP FIXME */ 785 786 /* enable all Root errs */ 787 r = (pcireg_t)(~PCIE_ECFG_RECR_RESV); 788 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_RECR, r); 789 790 /* 791 * establish ISR for PCIE Fatal Error interrupt 792 * - for XLS4xxLite, XLS2xx, XLS1xx only 793 */ 794 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 795 case MIPS_XLS104: 796 case MIPS_XLS108: 797 case MIPS_XLS204: 798 case MIPS_XLS208: 799 case MIPS_XLS404LITE: 800 case MIPS_XLS408LITE: 801 sc->sc_fatal_ih = rmixl_intr_establish(29, sc->sc_tmsk, 802 IPL_HIGH, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH, 803 rmixl_pcie_error_intr, v, false); 804 break; 805 default: 806 break; 807 } 808 809 #if defined(DEBUG) || defined(DDB) 810 rmixl_pcie_v = v; 811 #endif 812 } 813 814 void 815 rmixl_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *iline) 816 { 817 DPRINTF(("%s: %p, %d, %d, %d, %d, %p\n", 818 __func__, v, bus, dev, ipin, swiz, iline)); 819 } 820 821 void 822 rmixl_pcie_attach_hook(device_t parent, device_t self, 823 struct pcibus_attach_args *pba) 824 { 825 DPRINTF(("%s: pba_bus %d, pba_bridgetag %p, pc_conf_v %p\n", 826 __func__, pba->pba_bus, pba->pba_bridgetag, 827 pba->pba_pc->pc_conf_v)); 828 } 829 830 int 831 rmixl_pcie_bus_maxdevs(void *v, int busno) 832 { 833 return (32); /* XXX depends on the family of XLS SoC */ 834 } 835 836 /* 837 * rmixl_tag_to_ecfg - convert cfg address (generic tag) to ecfg address 838 * 839 * 39:29 (reserved) 840 * 28 Swap (0=little, 1=big endian) 841 * 27:20 Bus number 842 * 19:15 Device number 843 * 14:12 Function number 844 * 11:8 Extended Register number 845 * 7:0 Register number 846 */ 847 static pcitag_t 848 rmixl_tag_to_ecfg(pcitag_t tag) 849 { 850 KASSERT((tag & __BITS(7,0)) == 0); 851 return (tag << 4); 852 } 853 854 /* 855 * XLS pci tag is a 40 bit address composed thusly: 856 * 39:25 (reserved) 857 * 24 Swap (0=little, 1=big endian) 858 * 23:16 Bus number 859 * 15:11 Device number 860 * 10:8 Function number 861 * 7:0 Register number 862 * 863 * Note: this is the "native" composition for addressing CFG space, but not for ECFG space. 864 */ 865 pcitag_t 866 rmixl_pcie_make_tag(void *v, int bus, int dev, int fun) 867 { 868 return ((bus << 16) | (dev << 11) | (fun << 8)); 869 } 870 871 void 872 rmixl_pcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 873 { 874 if (bp != NULL) 875 *bp = (tag >> 16) & 0xff; 876 if (dp != NULL) 877 *dp = (tag >> 11) & 0x1f; 878 if (fp != NULL) 879 *fp = (tag >> 8) & 0x7; 880 } 881 882 void 883 rmixl_pcie_tag_print(const char *restrict s, void *v, pcitag_t tag, int offset, 884 vaddr_t va, u_long r) 885 { 886 int bus, dev, fun; 887 888 rmixl_pcie_decompose_tag(v, tag, &bus, &dev, &fun); 889 printf("%s: %d/%d/%d/%d - %#" PRIxVADDR ":%#lx\n", 890 s, bus, dev, fun, offset, va, r); 891 } 892 893 static int 894 rmixl_pcie_conf_setup(struct rmixl_pcie_softc *sc, 895 pcitag_t tag, int *offp, bus_space_tag_t *bstp, 896 bus_space_handle_t *bshp) 897 { 898 struct rmixl_config *rcp = &rmixl_configuration; 899 bus_space_tag_t bst; 900 bus_space_handle_t bsh; 901 bus_size_t size; 902 pcitag_t mask; 903 bus_addr_t ba; 904 int err; 905 static bus_space_handle_t cfg_bsh; 906 static bus_addr_t cfg_oba = -1; 907 static bus_space_handle_t ecfg_bsh; 908 static bus_addr_t ecfg_oba = -1; 909 910 /* 911 * bus space depends on offset 912 */ 913 if ((*offp >= 0) && (*offp < 0x100)) { 914 mask = __BITS(15,0); 915 bst = sc->sc_pci_cfg_memt; 916 ba = rcp->rc_pci_cfg_pbase; 917 ba += (tag & ~mask); 918 *offp += (tag & mask); 919 if (ba != cfg_oba) { 920 size = (bus_size_t)(mask + 1); 921 if (cfg_oba != -1) 922 bus_space_unmap(bst, cfg_bsh, size); 923 err = bus_space_map(bst, ba, size, 0, &cfg_bsh); 924 if (err != 0) { 925 #ifdef DEBUG 926 panic("%s: bus_space_map err %d, CFG space", 927 __func__, err); /* XXX */ 928 #endif 929 return -1; 930 } 931 cfg_oba = ba; 932 } 933 bsh = cfg_bsh; 934 } else if ((*offp >= 0x100) && (*offp <= 0x700)) { 935 mask = __BITS(14,0); 936 tag = rmixl_tag_to_ecfg(tag); /* convert to ECFG format */ 937 bst = sc->sc_pci_ecfg_memt; 938 ba = rcp->rc_pci_ecfg_pbase; 939 ba += (tag & ~mask); 940 *offp += (tag & mask); 941 if (ba != ecfg_oba) { 942 size = (bus_size_t)(mask + 1); 943 if (ecfg_oba != -1) 944 bus_space_unmap(bst, ecfg_bsh, size); 945 err = bus_space_map(bst, ba, size, 0, &ecfg_bsh); 946 if (err != 0) { 947 #ifdef DEBUG 948 panic("%s: bus_space_map err %d, ECFG space", 949 __func__, err); /* XXX */ 950 #endif 951 return -1; 952 } 953 ecfg_oba = ba; 954 } 955 bsh = ecfg_bsh; 956 } else { 957 #ifdef DEBUG 958 panic("%s: offset %#x: unknown", __func__, *offp); 959 #endif 960 return -1; 961 } 962 963 *bstp = bst; 964 *bshp = bsh; 965 966 return 0; 967 } 968 969 pcireg_t 970 rmixl_pcie_conf_read(void *v, pcitag_t tag, int offset) 971 { 972 struct rmixl_pcie_softc *sc = v; 973 static bus_space_handle_t bsh; 974 bus_space_tag_t bst; 975 pcireg_t rv; 976 uint64_t cfg0; 977 978 mutex_enter(&sc->sc_mutex); 979 980 if (rmixl_pcie_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) { 981 cfg0 = rmixl_cache_err_dis(); 982 rv = bus_space_read_4(bst, bsh, (bus_size_t)offset); 983 if (rmixl_cache_err_check() != 0) { 984 #ifdef DIAGNOSTIC 985 int bus, dev, fun; 986 987 rmixl_pcie_decompose_tag(v, tag, &bus, &dev, &fun); 988 printf("%s: %d/%d/%d, offset %#x: bad address\n", 989 __func__, bus, dev, fun, offset); 990 #endif 991 rv = (pcireg_t) -1; 992 } 993 rmixl_cache_err_restore(cfg0); 994 } else { 995 rv = -1; 996 } 997 998 mutex_exit(&sc->sc_mutex); 999 1000 return rv; 1001 } 1002 1003 void 1004 rmixl_pcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 1005 { 1006 struct rmixl_pcie_softc *sc = v; 1007 static bus_space_handle_t bsh; 1008 bus_space_tag_t bst; 1009 uint64_t cfg0; 1010 1011 mutex_enter(&sc->sc_mutex); 1012 1013 if (rmixl_pcie_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) { 1014 cfg0 = rmixl_cache_err_dis(); 1015 bus_space_write_4(bst, bsh, (bus_size_t)offset, val); 1016 if (rmixl_cache_err_check() != 0) { 1017 #ifdef DIAGNOSTIC 1018 int bus, dev, fun; 1019 1020 rmixl_pcie_decompose_tag(v, tag, &bus, &dev, &fun); 1021 printf("%s: %d/%d/%d, offset %#x: bad address\n", 1022 __func__, bus, dev, fun, offset); 1023 #endif 1024 } 1025 rmixl_cache_err_restore(cfg0); 1026 } 1027 1028 mutex_exit(&sc->sc_mutex); 1029 } 1030 1031 int 1032 rmixl_pcie_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *pih) 1033 { 1034 int device; 1035 u_int link; 1036 u_int irq; 1037 1038 /* 1039 * The bus is unimportant since it can change depending on the 1040 * configuration. We are tied to device # of PCIe bridge we are 1041 * ultimately attached to. 1042 */ 1043 pci_decompose_tag(pa->pa_pc, pa->pa_intrtag, 1044 NULL, &device, NULL); 1045 1046 #ifdef DEBUG 1047 DPRINTF(("%s: ps_bus %d, pa_intrswiz %#x, pa_intrtag %#lx," 1048 " pa_intrpin %d, pa_intrline %d, pa_rawintrpin %d\n", 1049 __func__, pa->pa_bus, pa->pa_intrswiz, pa->pa_intrtag, 1050 pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 1051 #endif 1052 1053 /* 1054 * PCIe Link INT irq assignment is cpu implementation specific 1055 */ 1056 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 1057 case MIPS_XLS104: 1058 case MIPS_XLS108: 1059 case MIPS_XLS404LITE: 1060 case MIPS_XLS408LITE: 1061 if (device > 1) 1062 panic("%s: bad bus %d", __func__, device); 1063 link = device; 1064 irq = device + 26; 1065 break; 1066 case MIPS_XLS204: 1067 case MIPS_XLS208: { 1068 if (device > 3) 1069 panic("%s: bad bus %d", __func__, device); 1070 link = device; 1071 irq = device + (device & 2 ? 21 : 26); 1072 break; 1073 } 1074 case MIPS_XLS404: 1075 case MIPS_XLS408: 1076 case MIPS_XLS416: 1077 case MIPS_XLS608: 1078 case MIPS_XLS616: 1079 if (device > 3) 1080 panic("%s: bad bus %d", __func__, device); 1081 link = device; 1082 irq = device + 26; 1083 break; 1084 default: 1085 panic("%s: cpu IMPL %#x not supported\n", 1086 __func__, MIPS_PRID_IMPL(mips_options.mips_cpu_id)); 1087 } 1088 1089 if (pa->pa_intrpin != PCI_INTERRUPT_PIN_NONE) 1090 *pih = rmixl_pcie_make_pih(link, pa->pa_intrpin - 1, irq); 1091 else 1092 *pih = ~0; 1093 1094 return 0; 1095 } 1096 1097 const char * 1098 rmixl_pcie_intr_string(void *v, pci_intr_handle_t pih, char *buf, size_t len) 1099 { 1100 const char *name = "(illegal)"; 1101 u_int link, bitno, irq; 1102 1103 rmixl_pcie_decompose_pih(pih, &link, &bitno, &irq); 1104 1105 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 1106 case MIPS_XLS104: 1107 case MIPS_XLS108: 1108 case MIPS_XLS404LITE: 1109 case MIPS_XLS408LITE: 1110 switch (irq) { 1111 case 26: 1112 case 27: 1113 name = rmixl_intr_string(RMIXL_IRT_VECTOR(irq)); 1114 break; 1115 } 1116 break; 1117 case MIPS_XLS204: 1118 case MIPS_XLS208: 1119 switch (irq) { 1120 case 23: 1121 case 24: 1122 case 26: 1123 case 27: 1124 name = rmixl_intr_string(RMIXL_IRT_VECTOR(irq)); 1125 break; 1126 } 1127 break; 1128 case MIPS_XLS404: 1129 case MIPS_XLS408: 1130 case MIPS_XLS416: 1131 case MIPS_XLS608: 1132 case MIPS_XLS616: 1133 switch (irq) { 1134 case 26: 1135 case 27: 1136 case 28: 1137 case 29: 1138 name = rmixl_intr_string(RMIXL_IRT_VECTOR(irq)); 1139 break; 1140 } 1141 break; 1142 default: 1143 panic("%s: cpu IMPL %#x not supported\n", 1144 __func__, MIPS_PRID_IMPL(mips_options.mips_cpu_id)); 1145 } 1146 1147 strlcpy(buf, name, len); 1148 return buf; 1149 } 1150 1151 const struct evcnt * 1152 rmixl_pcie_intr_evcnt(void *v, pci_intr_handle_t pih) 1153 { 1154 return NULL; 1155 } 1156 1157 static pci_intr_handle_t 1158 rmixl_pcie_make_pih(u_int link, u_int bitno, u_int irq) 1159 { 1160 pci_intr_handle_t pih; 1161 1162 KASSERT(link < RMIXL_PCIE_NLINKS_MAX); 1163 KASSERT(bitno < 64); 1164 KASSERT(irq < 32); 1165 1166 pih = (irq << 10); 1167 pih |= (bitno << 4); 1168 pih |= link; 1169 1170 return pih; 1171 } 1172 1173 static void 1174 rmixl_pcie_decompose_pih(pci_intr_handle_t pih, u_int *link, u_int *bitno, u_int *irq) 1175 { 1176 *link = (u_int)(pih & 0xf); 1177 *bitno = (u_int)((pih >> 4) & 0x3f); 1178 *irq = (u_int)(pih >> 10); 1179 1180 KASSERT(*link < RMIXL_PCIE_NLINKS_MAX); 1181 KASSERT(*bitno < 64); 1182 KASSERT(*irq < 32); 1183 } 1184 1185 static void 1186 rmixl_pcie_intr_disestablish(void *v, void *ih) 1187 { 1188 rmixl_pcie_softc_t *sc = v; 1189 rmixl_pcie_link_dispatch_t *dip = ih; 1190 rmixl_pcie_link_intr_t *lip = sc->sc_link_intr[dip->link]; 1191 uint32_t r; 1192 uint32_t bit; 1193 u_int offset; 1194 u_int other; 1195 bool busy; 1196 1197 DPRINTF(("%s: link=%d pin=%d irq=%d\n", 1198 __func__, dip->link, dip->bitno + 1, dip->irq)); 1199 1200 mutex_enter(&sc->sc_mutex); 1201 1202 dip->func = NULL; /* mark unused, prevent further dispatch */ 1203 1204 /* 1205 * if no other dispatch handle is using this interrupt, 1206 * we can disable it 1207 */ 1208 busy = false; 1209 for (int i=0; i < lip->dispatch_count; i++) { 1210 rmixl_pcie_link_dispatch_t *d = &lip->dispatch_data[i]; 1211 if (d == dip) 1212 continue; 1213 if (d->bitno == dip->bitno) { 1214 busy = true; 1215 break; 1216 } 1217 } 1218 if (! busy) { 1219 if (dip->bitno < 32) { 1220 bit = 1 << dip->bitno; 1221 offset = int_enb_offset[dip->link].r0; 1222 other = int_enb_offset[dip->link].r1; 1223 } else { 1224 bit = 1 << (dip->bitno - 32); 1225 offset = int_enb_offset[dip->link].r1; 1226 other = int_enb_offset[dip->link].r0; 1227 } 1228 1229 /* disable this interrupt in the PCIe bridge */ 1230 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + offset); 1231 r &= ~bit; 1232 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + offset, r); 1233 1234 /* 1235 * if both ENABLE0 and ENABLE1 are 0 1236 * disable the link interrupt 1237 */ 1238 if (r == 0) { 1239 /* check the other reg */ 1240 if (RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + other) == 0) { 1241 DPRINTF(("%s: disable link %d\n", __func__, lip->link)); 1242 1243 /* tear down interrupt on this link */ 1244 rmixl_intr_disestablish(lip->ih); 1245 1246 /* commit NULL interrupt set */ 1247 sc->sc_link_intr[dip->link] = NULL; 1248 1249 /* schedule delayed free of the old link interrupt set */ 1250 rmixl_pcie_lip_free_callout(lip); 1251 } 1252 } 1253 } 1254 1255 mutex_exit(&sc->sc_mutex); 1256 } 1257 1258 static void * 1259 rmixl_pcie_intr_establish(void *v, pci_intr_handle_t pih, int ipl, 1260 int (*func)(void *), void *arg) 1261 { 1262 rmixl_pcie_softc_t *sc = v; 1263 u_int link, bitno, irq; 1264 uint32_t r; 1265 rmixl_pcie_link_intr_t *lip; 1266 rmixl_pcie_link_dispatch_t *dip = NULL; 1267 uint32_t bit; 1268 u_int offset; 1269 1270 if (pih == ~0) { 1271 DPRINTF(("%s: bad pih=%#lx, implies PCI_INTERRUPT_PIN_NONE\n", 1272 __func__, pih)); 1273 return NULL; 1274 } 1275 1276 rmixl_pcie_decompose_pih(pih, &link, &bitno, &irq); 1277 DPRINTF(("%s: link=%d pin=%d irq=%d\n", 1278 __func__, link, bitno + 1, irq)); 1279 1280 mutex_enter(&sc->sc_mutex); 1281 1282 lip = rmixl_pcie_lip_add_1(sc, link, irq, ipl); 1283 if (lip == NULL) 1284 return NULL; 1285 1286 /* 1287 * initializae our new interrupt, the last element in dispatch_data[] 1288 */ 1289 dip = &lip->dispatch_data[lip->dispatch_count - 1]; 1290 dip->link = link; 1291 dip->bitno = bitno; 1292 dip->irq = irq; 1293 dip->func = func; 1294 dip->arg = arg; 1295 dip->counts = RMIXL_PCIE_EVCNT(sc, link, bitno, 0); 1296 1297 if (bitno < 32) { 1298 offset = int_enb_offset[link].r0; 1299 bit = 1 << bitno; 1300 } else { 1301 offset = int_enb_offset[link].r1; 1302 bit = 1 << (bitno - 32); 1303 } 1304 1305 /* commit the new link interrupt set */ 1306 sc->sc_link_intr[link] = lip; 1307 1308 /* enable this interrupt in the PCIe bridge */ 1309 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + offset); 1310 r |= bit; 1311 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + offset, r); 1312 1313 mutex_exit(&sc->sc_mutex); 1314 return dip; 1315 } 1316 1317 rmixl_pcie_link_intr_t * 1318 rmixl_pcie_lip_add_1(rmixl_pcie_softc_t *sc, u_int link, int irq, int ipl) 1319 { 1320 rmixl_pcie_link_intr_t *lip_old = sc->sc_link_intr[link]; 1321 rmixl_pcie_link_intr_t *lip_new; 1322 u_int dispatch_count; 1323 size_t size; 1324 1325 dispatch_count = 1; 1326 size = sizeof(rmixl_pcie_link_intr_t); 1327 if (lip_old != NULL) { 1328 /* 1329 * count only those dispatch elements still in use 1330 * unused ones will be pruned during copy 1331 * i.e. we are "lazy" there is no rmixl_pcie_lip_sub_1 1332 */ 1333 for (int i=0; i < lip_old->dispatch_count; i++) { 1334 if (lip_old->dispatch_data[i].func != NULL) { 1335 dispatch_count++; 1336 size += sizeof(rmixl_pcie_link_intr_t); 1337 } 1338 } 1339 } 1340 1341 /* 1342 * allocate and initialize link intr struct 1343 * with one or more dispatch handles 1344 */ 1345 lip_new = malloc(size, M_DEVBUF, M_NOWAIT); 1346 if (lip_new == NULL) { 1347 #ifdef DIAGNOSTIC 1348 printf("%s: cannot malloc\n", __func__); 1349 #endif 1350 return NULL; 1351 } 1352 1353 if (lip_old == NULL) { 1354 /* initialize the link interrupt struct */ 1355 lip_new->sc = sc; 1356 lip_new->link = link; 1357 lip_new->ipl = ipl; 1358 lip_new->ih = rmixl_intr_establish(irq, sc->sc_tmsk, 1359 ipl, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH, 1360 rmixl_pcie_intr, lip_new, false); 1361 if (lip_new->ih == NULL) 1362 panic("%s: cannot establish irq %d", __func__, irq); 1363 } else { 1364 /* 1365 * all intrs on a link get same ipl and sc 1366 * first intr established sets the standard 1367 */ 1368 KASSERT(sc == lip_old->sc); 1369 if (sc != lip_old->sc) { 1370 printf("%s: sc %p mismatch\n", __func__, sc); 1371 free(lip_new, M_DEVBUF); 1372 return NULL; 1373 } 1374 KASSERT (ipl == lip_old->ipl); 1375 if (ipl != lip_old->ipl) { 1376 printf("%s: ipl %d mismatch\n", __func__, ipl); 1377 free(lip_new, M_DEVBUF); 1378 return NULL; 1379 } 1380 /* 1381 * copy lip_old to lip_new, skipping unused dispatch elemets 1382 */ 1383 memcpy(lip_new, lip_old, sizeof(rmixl_pcie_link_intr_t)); 1384 for (int j=0, i=0; i < lip_old->dispatch_count; i++) { 1385 if (lip_old->dispatch_data[i].func != NULL) { 1386 memcpy(&lip_new->dispatch_data[j], 1387 &lip_old->dispatch_data[i], 1388 sizeof(rmixl_pcie_link_dispatch_t)); 1389 j++; 1390 } 1391 } 1392 1393 /* 1394 * schedule delayed free of old link interrupt set 1395 */ 1396 rmixl_pcie_lip_free_callout(lip_old); 1397 } 1398 lip_new->dispatch_count = dispatch_count; 1399 1400 return lip_new; 1401 } 1402 1403 /* 1404 * delay free of the old link interrupt set 1405 * to allow anyone still using it to do so safely 1406 * XXX 2 seconds should be plenty? 1407 */ 1408 static void 1409 rmixl_pcie_lip_free_callout(rmixl_pcie_link_intr_t *lip) 1410 { 1411 callout_init(&lip->callout, 0); 1412 callout_reset(&lip->callout, 2 * hz, rmixl_pcie_lip_free, lip); 1413 } 1414 1415 static void 1416 rmixl_pcie_lip_free(void *arg) 1417 { 1418 rmixl_pcie_link_intr_t *lip = arg; 1419 1420 callout_destroy(&lip->callout); 1421 free(lip, M_DEVBUF); 1422 } 1423 1424 static int 1425 rmixl_pcie_intr(void *arg) 1426 { 1427 rmixl_pcie_link_intr_t *lip = arg; 1428 u_int link = lip->link; 1429 int rv = 0; 1430 1431 uint32_t status0 = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + int_sts_offset[link].r0); 1432 uint32_t status1 = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + int_sts_offset[link].r1); 1433 uint64_t status = ((uint64_t)status1 << 32) | status0; 1434 DPRINTF(("%s: %d:%#"PRIx64"\n", __func__, link, status)); 1435 1436 if (status != 0) { 1437 rmixl_pcie_link_dispatch_t *dip; 1438 1439 if (status & RMIXL_PCIE_LINK_STATUS_ERRORS) 1440 rmixl_pcie_link_error_intr(link, status0, status1); 1441 1442 for (u_int i=0; i < lip->dispatch_count; i++) { 1443 dip = &lip->dispatch_data[i]; 1444 int (*func)(void *) = dip->func; 1445 if (func != NULL) { 1446 uint64_t bit = 1 << dip->bitno; 1447 if ((status & bit) != 0) { 1448 (void)(*func)(dip->arg); 1449 dip->counts[cpu_index(curcpu())].evcnt.ev_count++; 1450 rv = 1; 1451 } 1452 } 1453 } 1454 } 1455 1456 return rv; 1457 } 1458 1459 static void 1460 rmixl_pcie_link_error_intr(u_int link, uint32_t status0, uint32_t status1) 1461 { 1462 printf("%s: mask %#"PRIx64"\n", 1463 __func__, RMIXL_PCIE_LINK_STATUS_ERRORS); 1464 printf("%s: PCIe Link Error: link=%d status0=%#x status1=%#x\n", 1465 __func__, link, status0, status1); 1466 #if defined(DDB) && defined(DEBUG) 1467 Debugger(); 1468 #endif 1469 } 1470 1471 #if defined(DEBUG) || defined(DDB) 1472 /* this function exists to facilitate call from ddb */ 1473 int 1474 rmixl_pcie_error_check(void) 1475 { 1476 if (rmixl_pcie_v != 0) 1477 return _rmixl_pcie_error_check(rmixl_pcie_v); 1478 return -1; 1479 } 1480 #endif 1481 1482 STATIC int 1483 _rmixl_pcie_error_check(void *v) 1484 { 1485 int i, offset; 1486 pcireg_t r; 1487 pcitag_t tag; 1488 int err=0; 1489 #ifdef DIAGNOSTIC 1490 pcireg_t regs[PCIE_ECFG_ERRS_OFFTAB_NENTRIES]; 1491 #endif 1492 1493 tag = rmixl_pcie_make_tag(v, 0, 0, 0); /* XXX */ 1494 1495 for (i=0; i < PCIE_ECFG_ERRS_OFFTAB_NENTRIES; i++) { 1496 offset = pcie_ecfg_errs_tab[i].offset; 1497 r = rmixl_pcie_conf_read(v, tag, offset); 1498 #ifdef DIAGNOSTIC 1499 regs[i] = r; 1500 #endif 1501 if (r != 0) { 1502 pcireg_t rw1c = r & pcie_ecfg_errs_tab[i].rw1c; 1503 if (rw1c != 0) { 1504 /* attempt to clear the error */ 1505 rmixl_pcie_conf_write(v, tag, offset, rw1c); 1506 }; 1507 if (offset == RMIXL_PCIE_ECFG_CESR) 1508 err |= 1; /* correctable */ 1509 else 1510 err |= 2; /* uncorrectable */ 1511 } 1512 } 1513 #ifdef DIAGNOSTIC 1514 if (err != 0) { 1515 for (i=0; i < PCIE_ECFG_ERRS_OFFTAB_NENTRIES; i++) { 1516 offset = pcie_ecfg_errs_tab[i].offset; 1517 printf("%s: %#x: %#x\n", __func__, offset, regs[i]); 1518 } 1519 } 1520 #endif 1521 1522 return err; 1523 } 1524 1525 static int 1526 rmixl_pcie_error_intr(void *v) 1527 { 1528 if (_rmixl_pcie_error_check(v) < 2) 1529 return 0; /* correctable */ 1530 1531 /* uncorrectable */ 1532 #if DDB 1533 Debugger(); 1534 #endif 1535 1536 /* XXX reset and recover? */ 1537 1538 panic("%s\n", __func__); 1539 } 1540 1541 /* 1542 * rmixl_physaddr_init_pcie: 1543 * called from rmixl_physaddr_init to get region addrs & sizes 1544 * from PCIE CFG, ECFG, IO, MEM BARs 1545 */ 1546 void 1547 rmixl_physaddr_init_pcie(struct extent *ext) 1548 { 1549 u_long base; 1550 u_long size; 1551 uint32_t r; 1552 1553 r = RMIXL_IOREG_READ(RMIXLS_SBC_PCIE_CFG_BAR); 1554 if ((r & RMIXL_PCIE_CFG_BAR_ENB) != 0) { 1555 base = (u_long)(RMIXL_PCIE_CFG_BAR_TO_BA((uint64_t)r) 1556 / (1024 * 1024)); 1557 size = (u_long)RMIXL_PCIE_CFG_SIZE / (1024 * 1024); 1558 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1559 __LINE__, "CFG", r, base * 1024 * 1024, size)); 1560 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1561 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1562 "failed", __func__, ext, base, size, EX_NOWAIT); 1563 } 1564 1565 r = RMIXL_IOREG_READ(RMIXLS_SBC_PCIE_ECFG_BAR); 1566 if ((r & RMIXL_PCIE_ECFG_BAR_ENB) != 0) { 1567 base = (u_long)(RMIXL_PCIE_ECFG_BAR_TO_BA((uint64_t)r) 1568 / (1024 * 1024)); 1569 size = (u_long)RMIXL_PCIE_ECFG_SIZE / (1024 * 1024); 1570 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1571 __LINE__, "ECFG", r, base * 1024 * 1024, size)); 1572 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1573 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1574 "failed", __func__, ext, base, size, EX_NOWAIT); 1575 } 1576 1577 r = RMIXL_IOREG_READ(RMIXLS_SBC_PCIE_MEM_BAR); 1578 if ((r & RMIXL_PCIE_MEM_BAR_ENB) != 0) { 1579 base = (u_long)(RMIXL_PCIE_MEM_BAR_TO_BA((uint64_t)r) 1580 / (1024 * 1024)); 1581 size = (u_long)(RMIXL_PCIE_MEM_BAR_TO_SIZE((uint64_t)r) 1582 / (1024 * 1024)); 1583 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1584 __LINE__, "MEM", r, base * 1024 * 1024, size)); 1585 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1586 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1587 "failed", __func__, ext, base, size, EX_NOWAIT); 1588 } 1589 1590 r = RMIXL_IOREG_READ(RMIXLS_SBC_PCIE_IO_BAR); 1591 if ((r & RMIXL_PCIE_IO_BAR_ENB) != 0) { 1592 base = (u_long)(RMIXL_PCIE_IO_BAR_TO_BA((uint64_t)r) 1593 / (1024 * 1024)); 1594 size = (u_long)(RMIXL_PCIE_IO_BAR_TO_SIZE((uint64_t)r) 1595 / (1024 * 1024)); 1596 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1597 __LINE__, "IO", r, base * 1024 * 1024, size)); 1598 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1599 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1600 "failed", __func__, ext, base, size, EX_NOWAIT); 1601 } 1602 } 1603
Indexes created Mon Oct 20 16:09:52 GMT 2025