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rmixl_pcix.c revision 1.9.2.2
      1  1.9.2.2    yamt /*	$NetBSD: rmixl_pcix.c,v 1.9.2.2 2014/05/22 11:39:58 yamt Exp $	*/
      2      1.2    matt 
      3      1.2    matt /*
      4      1.2    matt  * Copyright (c) 2001 Wasabi Systems, Inc.
      5      1.2    matt  * All rights reserved.
      6      1.2    matt  *
      7      1.2    matt  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
      8      1.2    matt  *
      9      1.2    matt  * Redistribution and use in source and binary forms, with or without
     10      1.2    matt  * modification, are permitted provided that the following conditions
     11      1.2    matt  * are met:
     12      1.2    matt  * 1. Redistributions of source code must retain the above copyright
     13      1.2    matt  *    notice, this list of conditions and the following disclaimer.
     14      1.2    matt  * 2. Redistributions in binary form must reproduce the above copyright
     15      1.2    matt  *    notice, this list of conditions and the following disclaimer in the
     16      1.2    matt  *    documentation and/or other materials provided with the distribution.
     17      1.2    matt  * 3. All advertising materials mentioning features or use of this software
     18      1.2    matt  *    must display the following acknowledgement:
     19      1.2    matt  *	This product includes software developed for the NetBSD Project by
     20      1.2    matt  *	Wasabi Systems, Inc.
     21      1.2    matt  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
     22      1.2    matt  *    or promote products derived from this software without specific prior
     23      1.2    matt  *    written permission.
     24      1.2    matt  *
     25      1.2    matt  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
     26      1.2    matt  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     27      1.2    matt  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     28      1.2    matt  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
     29      1.2    matt  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     30      1.2    matt  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     31      1.2    matt  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     32      1.2    matt  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     33      1.2    matt  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     34      1.2    matt  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     35      1.2    matt  * POSSIBILITY OF SUCH DAMAGE.
     36      1.2    matt  */
     37      1.2    matt 
     38      1.2    matt /*
     39      1.2    matt  * PCI configuration support for RMI XLR SoC
     40      1.2    matt  */
     41      1.2    matt 
     42      1.2    matt #include <sys/cdefs.h>
     43  1.9.2.2    yamt __KERNEL_RCSID(0, "$NetBSD: rmixl_pcix.c,v 1.9.2.2 2014/05/22 11:39:58 yamt Exp $");
     44      1.2    matt 
     45      1.2    matt #include "opt_pci.h"
     46      1.2    matt #include "pci.h"
     47      1.2    matt 
     48      1.2    matt #include <sys/cdefs.h>
     49      1.2    matt 
     50      1.2    matt #include <sys/param.h>
     51      1.9    matt #include <sys/bus.h>
     52      1.9    matt #include <sys/cpu.h>
     53      1.2    matt #include <sys/device.h>
     54      1.2    matt #include <sys/extent.h>
     55      1.9    matt #include <sys/intr.h>
     56      1.2    matt #include <sys/malloc.h>
     57      1.2    matt #include <sys/kernel.h>		/* for 'hz' */
     58      1.9    matt #include <sys/systm.h>
     59      1.2    matt 
     60      1.2    matt #include <uvm/uvm_extern.h>
     61      1.2    matt 
     62      1.2    matt #include <mips/rmi/rmixlreg.h>
     63      1.2    matt #include <mips/rmi/rmixlvar.h>
     64      1.2    matt #include <mips/rmi/rmixl_intr.h>
     65      1.2    matt #include <mips/rmi/rmixl_pcixvar.h>
     66      1.2    matt 
     67      1.2    matt #include <mips/rmi/rmixl_obiovar.h>
     68      1.2    matt 
     69      1.2    matt #include <dev/pci/pcivar.h>
     70      1.2    matt #include <dev/pci/pcidevs.h>
     71      1.2    matt #include <dev/pci/pciconf.h>
     72      1.2    matt 
     73      1.2    matt #ifdef	PCI_NETBSD_CONFIGURE
     74      1.2    matt #include <mips/cache.h>
     75      1.2    matt #endif
     76      1.2    matt 
     77      1.2    matt #ifdef PCI_DEBUG
     78      1.2    matt int rmixl_pcix_debug = PCI_DEBUG;
     79      1.2    matt # define DPRINTF(x)	do { if (rmixl_pcix_debug) printf x ; } while (0)
     80      1.2    matt #else
     81      1.2    matt # define DPRINTF(x)
     82      1.2    matt #endif
     83      1.2    matt 
     84      1.2    matt #ifndef DDB
     85      1.2    matt # define STATIC static
     86      1.2    matt #else
     87      1.2    matt # define STATIC
     88      1.2    matt #endif
     89      1.2    matt 
     90      1.2    matt 
     91      1.2    matt /*
     92      1.2    matt  * XLR PCI-X Extended Configuration Registers
     93      1.2    matt  * Note:
     94      1.2    matt  * - MSI-related regs are omitted
     95      1.2    matt  * - Device mode regs are omitted
     96      1.2    matt  */
     97      1.2    matt #define RMIXL_PCIX_ECFG_HOST_BAR0_ADDR	0x100	/* Host BAR0 Address */
     98      1.2    matt #define RMIXL_PCIX_ECFG_HOST_BAR1_ADDR	0x104	/* Host BAR1 Address */
     99      1.2    matt #define RMIXL_PCIX_ECFG_HOST_BAR2_ADDR	0x108	/* Host BAR2 Address */
    100      1.2    matt #define RMIXL_PCIX_ECFG_HOST_BAR3_ADDR	0x10c	/* Host BAR3 Address */
    101      1.2    matt #define RMIXL_PCIX_ECFG_HOST_BAR4_ADDR	0x110	/* Host BAR4 Address */
    102      1.2    matt #define RMIXL_PCIX_ECFG_HOST_BAR5_ADDR	0x114	/* Host BAR5 Address */
    103      1.2    matt #define RMIXL_PCIX_ECFG_HOST_BAR0_SIZE	0x118	/* Host BAR0 Size */
    104      1.2    matt #define RMIXL_PCIX_ECFG_HOST_BAR1_SIZE	0x11c	/* Host BAR1 Size */
    105      1.2    matt #define RMIXL_PCIX_ECFG_HOST_BAR2_SIZE	0x120	/* Host BAR2 Size */
    106      1.2    matt #define RMIXL_PCIX_ECFG_HOST_BAR3_SIZE	0x124	/* Host BAR3 Size */
    107      1.2    matt #define RMIXL_PCIX_ECFG_HOST_BAR4_SIZE	0x128	/* Host BAR4 Size */
    108      1.2    matt #define RMIXL_PCIX_ECFG_HOST_BAR5_SIZE	0x12c	/* Host BAR5 Size */
    109      1.2    matt #define RMIXL_PCIX_ECFG_MATCH_BIT_ADDR	0x130	/* Match Bit Address BAR */
    110      1.2    matt #define RMIXL_PCIX_ECFG_MATCH_BIT_SIZE	0x134	/* Match Bit Size BAR */
    111      1.2    matt #define RMIXL_PCIX_ECFG_XLR_CONTROL	0x138	/* XLR Control reg */
    112      1.2    matt #define RMIXL_PCIX_ECFG_INTR_CONTROL	0x13c	/* Interrupt Control reg */
    113      1.2    matt #define RMIXL_PCIX_ECFG_INTR_STATUS	0x140	/* Interrupt Status reg */
    114      1.2    matt #define RMIXL_PCIX_ECFG_INTR_ERR_STATUS	0x144	/* Interrupt Error Status reg */
    115      1.2    matt #define RMIXL_PCIX_ECFG_HOST_MODE_STS	0x178	/* Host Mode Status */
    116      1.2    matt #define RMIXL_PCIX_ECFG_XLR_MBLE	0x17c	/* XLR Match Byte Lane Enable */
    117      1.2    matt #define RMIXL_PCIX_ECFG_HOST_XROM_ADDR	0x180	/* Host Expansion ROM Address */
    118      1.2    matt #define RMIXL_PCIX_ECFG_HOST_XROM_SIZE	0x184	/* Host Expansion ROM Size */
    119      1.2    matt #define RMIXL_PCIX_ECFG_HOST_MODE_CTL	0x18c	/* Host Mode Control */
    120      1.2    matt #define RMIXL_PCIX_ECFG_TXCAL_CTL	0x1a0	/* TX Calibration Preset Control */
    121      1.2    matt #define RMIXL_PCIX_ECFG_TXCAL_COUNT	0x1a4	/* TX Calibration Preset Count */
    122      1.2    matt 
    123      1.2    matt /*
    124      1.2    matt  * RMIXL_PCIX_ECFG_INTR_CONTROL bit defines
    125      1.2    matt  */
    126      1.2    matt #define PCIX_INTR_CONTROL_RESV		__BITS(31,8)
    127      1.2    matt #define PCIX_INTR_CONTROL_MSI1_MASK	__BIT(7)
    128      1.2    matt #define PCIX_INTR_CONTROL_MSI0_MASK	__BIT(6)
    129      1.2    matt #define PCIX_INTR_CONTROL_INTD_MASK	__BIT(5)
    130      1.2    matt #define PCIX_INTR_CONTROL_INTC_MASK	__BIT(4)
    131      1.2    matt #define PCIX_INTR_CONTROL_INTB_MASK	__BIT(3)
    132      1.2    matt #define PCIX_INTR_CONTROL_INTA_MASK	__BIT(2)
    133      1.2    matt #define PCIX_INTR_CONTROL_TMSI		__BIT(1)	/* Trigger MSI Interrupt */
    134      1.2    matt #define PCIX_INTR_CONTROL_DIA		__BIT(0)	/* Device Interrupt through INTA Pin */
    135      1.2    matt #define PCIX_INTR_CONTROL_MASK_ALL	\
    136      1.2    matt 		(PCIX_INTR_CONTROL_MSI1_MASK|PCIX_INTR_CONTROL_MSI0_MASK	\
    137      1.2    matt 		|PCIX_INTR_CONTROL_INTD_MASK|PCIX_INTR_CONTROL_INTC_MASK	\
    138      1.2    matt 		|PCIX_INTR_CONTROL_INTB_MASK|PCIX_INTR_CONTROL_INTA_MASK)
    139      1.2    matt 
    140      1.2    matt /*
    141      1.2    matt  * RMIXL_PCIX_ECFG_INTR_STATUS bit defines
    142      1.2    matt  */
    143      1.2    matt #define PCIX_INTR_STATUS_RESV		__BITS(31,6)
    144      1.2    matt #define PCIX_INTR_STATUS_MSI1		__BIT(5)
    145      1.2    matt #define PCIX_INTR_STATUS_MSI0		__BIT(4)
    146      1.2    matt #define PCIX_INTR_STATUS_INTD		__BIT(3)
    147      1.2    matt #define PCIX_INTR_STATUS_INTC		__BIT(2)
    148      1.2    matt #define PCIX_INTR_STATUS_INTB		__BIT(1)
    149      1.2    matt #define PCIX_INTR_STATUS_INTA		__BIT(0)
    150      1.2    matt 
    151      1.2    matt /*
    152      1.2    matt  * RMIXL_PCIX_ECFG_INTR_ERR_STATUS bit defines
    153      1.2    matt  */
    154      1.2    matt #define PCIX_INTR_ERR_STATUS_RESa	__BITS(31,5)
    155      1.2    matt #define PCIX_INTR_ERR_STATUS_SERR	__BIT(4)	/* System Error */
    156      1.2    matt #define PCIX_INTR_ERR_STATUS_RESb	__BIT(3)
    157      1.2    matt #define PCIX_INTR_ERR_STATUS_TE		__BIT(2)	/* Target Error */
    158      1.2    matt #define PCIX_INTR_ERR_STATUS_IE		__BIT(1)	/* Initiator Error */
    159      1.2    matt #define PCIX_INTR_ERR_STATUS_RCE	__BIT(0)	/* Retry Count Expired */
    160      1.2    matt #define PCIX_INTR_ERR_STATUS_RESV	\
    161      1.2    matt 		(PCIX_INTR_ERR_STATUS_RESa|PCIX_INTR_ERR_STATUS_RESb)
    162      1.2    matt 
    163      1.2    matt /*
    164      1.2    matt  * RMIXL_PCIX_ECFG_HOST_MODE_CTL bit defines
    165      1.2    matt  */
    166      1.2    matt #define PCIX_HOST_MODE_CTL_HDMSTAT	__BIT(1)	/* Host/Dev Mode status
    167      1.2    matt 							 *  read-only
    168      1.2    matt 							 *  1 = host
    169      1.2    matt 							 *  0 = device
    170      1.2    matt 							 */
    171      1.2    matt #define PCIX_HOST_MODE_CTL_HOSTSWRST	__BIT(0)	/* Host soft reset
    172      1.2    matt 							 *  set to 1 to reset
    173      1.2    matt 							 *  set to 0 to un-reset
    174      1.2    matt 							 */
    175      1.2    matt 
    176      1.2    matt 
    177      1.2    matt #if BYTE_ORDER == BIG_ENDIAN
    178      1.2    matt # define RMIXL_PCIXREG_BASE	RMIXL_IO_DEV_PCIX_EB
    179      1.2    matt #else
    180      1.2    matt # define RMIXL_PCIXREG_BASE	RMIXL_IO_DEV_PCIX_EL
    181      1.2    matt #endif
    182      1.2    matt 
    183      1.2    matt #define RMIXL_PCIXREG_VADDR(o)				\
    184      1.2    matt 	(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(	\
    185      1.2    matt 		rmixl_configuration.rc_io_pbase		\
    186      1.2    matt 		+ RMIXL_PCIXREG_BASE + (o))
    187      1.2    matt 
    188      1.2    matt #define RMIXL_PCIXREG_READ(o)     (*RMIXL_PCIXREG_VADDR(o))
    189      1.2    matt #define RMIXL_PCIXREG_WRITE(o,v)  *RMIXL_PCIXREG_VADDR(o) = (v)
    190      1.2    matt 
    191      1.2    matt 
    192      1.2    matt #define RMIXL_PCIX_CONCAT3(a,b,c) a ## b ## c
    193      1.2    matt #define RMIXL_PCIX_BAR_INIT(reg, bar, size, align) {			\
    194      1.2    matt 	struct extent *ext = rmixl_configuration.rc_phys_ex;		\
    195      1.2    matt 	u_long region_start;						\
    196      1.2    matt 	uint64_t ba;							\
    197      1.2    matt 	int err;							\
    198      1.2    matt 									\
    199      1.2    matt 	err = extent_alloc(ext, (size), (align), 0UL, EX_NOWAIT,	\
    200      1.2    matt 		&region_start);						\
    201      1.2    matt 	if (err != 0)							\
    202      1.2    matt 		panic("%s: extent_alloc(%p, %#lx, %#lx, %#lx, %#x, %p)",\
    203      1.2    matt 			__func__, ext, size, align, 0UL, EX_NOWAIT,	\
    204      1.2    matt 			&region_start);					\
    205      1.2    matt 	ba = (uint64_t)region_start;					\
    206      1.2    matt 	ba *= (1024 * 1024);						\
    207      1.2    matt 	bar = RMIXL_PCIX_CONCAT3(RMIXL_PCIX_,reg,_BAR)(ba, 1);		\
    208      1.2    matt 	DPRINTF(("PCIX %s BAR was not enabled by firmware\n"		\
    209      1.2    matt 		"enabling %s at phys %#" PRIxBUSADDR ", size %lu MB\n",	\
    210      1.2    matt 		__STRING(reg), __STRING(reg), ba, size));		\
    211      1.2    matt 	RMIXL_IOREG_WRITE(RMIXL_IO_DEV_BRIDGE + 			\
    212      1.2    matt 		RMIXL_PCIX_CONCAT3(RMIXLR_SBC_PCIX_,reg,_BAR), bar);	\
    213      1.2    matt 	bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE +			\
    214      1.2    matt 		RMIXL_PCIX_CONCAT3(RMIXLR_SBC_PCIX_,reg,_BAR));		\
    215      1.2    matt 	DPRINTF(("%s: %s BAR %#x\n", __func__, __STRING(reg), bar));	\
    216      1.2    matt }
    217      1.2    matt 
    218      1.2    matt 
    219      1.2    matt #define RMIXL_PCIX_EVCNT(sc, intrpin, cpu)	\
    220      1.2    matt 	&(sc)->sc_evcnts[(intrpin) * (ncpu) + (cpu)]
    221      1.2    matt 
    222      1.2    matt 
    223      1.2    matt static int	rmixl_pcix_match(device_t, cfdata_t, void *);
    224      1.2    matt static void	rmixl_pcix_attach(device_t, device_t, void *);
    225      1.2    matt static void	rmixl_pcix_init(rmixl_pcix_softc_t *);
    226      1.2    matt static void	rmixl_pcix_init_errors(rmixl_pcix_softc_t *);
    227  1.9.2.1    yamt static void	rmixl_pcix_attach_hook(device_t, device_t,
    228      1.2    matt 		    struct pcibus_attach_args *);
    229      1.2    matt static void	rmixl_pcix_intcfg(rmixl_pcix_softc_t *);
    230      1.2    matt static void	rmixl_pcix_errata(rmixl_pcix_softc_t *);
    231      1.2    matt static void	rmixl_conf_interrupt(void *, int, int, int, int, int *);
    232      1.2    matt static int	rmixl_pcix_bus_maxdevs(void *, int);
    233      1.2    matt static pcitag_t	rmixl_pcix_make_tag(void *, int, int, int);
    234      1.2    matt static void	rmixl_pcix_decompose_tag(void *, pcitag_t, int *, int *, int *);
    235      1.2    matt void		rmixl_pcix_tag_print(const char *restrict, void *, pcitag_t,				int, vaddr_t, u_long);
    236      1.2    matt static int	rmixl_pcix_conf_setup(rmixl_pcix_softc_t *,
    237      1.2    matt 			pcitag_t, int *, bus_space_tag_t *,
    238      1.2    matt 			bus_space_handle_t *);
    239      1.2    matt static pcireg_t	rmixl_pcix_conf_read(void *, pcitag_t, int);
    240      1.2    matt static void	rmixl_pcix_conf_write(void *, pcitag_t, int, pcireg_t);
    241      1.2    matt 
    242      1.3  dyoung static int	rmixl_pcix_intr_map(const struct pci_attach_args *,
    243      1.2    matt 		    pci_intr_handle_t *);
    244      1.2    matt static const char *
    245  1.9.2.2    yamt 		rmixl_pcix_intr_string(void *, pci_intr_handle_t,
    246  1.9.2.2    yamt 		    char *, size_t);
    247      1.2    matt static const struct evcnt *
    248      1.2    matt 		rmixl_pcix_intr_evcnt(void *, pci_intr_handle_t);
    249      1.2    matt static pci_intr_handle_t
    250      1.2    matt 		rmixl_pcix_make_pih(u_int, u_int);
    251      1.2    matt static void	rmixl_pcix_decompose_pih(pci_intr_handle_t, u_int *, u_int *);
    252      1.2    matt static void	rmixl_pcix_intr_disestablish(void *, void *);
    253      1.2    matt static void	*rmixl_pcix_intr_establish(void *, pci_intr_handle_t,
    254      1.2    matt 		    int, int (*)(void *), void *);
    255      1.2    matt static rmixl_pcix_intr_t *
    256      1.2    matt                 rmixl_pcix_pip_add_1(rmixl_pcix_softc_t *, int, int);
    257      1.2    matt static void     rmixl_pcix_pip_free_callout(rmixl_pcix_intr_t *);
    258      1.2    matt static void     rmixl_pcix_pip_free(void *);
    259      1.2    matt static int	rmixl_pcix_intr(void *);
    260      1.2    matt static int	rmixl_pcix_error_intr(void *);
    261      1.2    matt 
    262      1.2    matt 
    263      1.2    matt CFATTACH_DECL_NEW(rmixl_pcix, sizeof(rmixl_pcix_softc_t),
    264      1.2    matt     rmixl_pcix_match, rmixl_pcix_attach, NULL, NULL);
    265      1.2    matt 
    266      1.2    matt 
    267      1.2    matt static int rmixl_pcix_found;
    268      1.2    matt 
    269      1.2    matt 
    270      1.2    matt static int
    271      1.2    matt rmixl_pcix_match(device_t parent, cfdata_t cf, void *aux)
    272      1.2    matt {
    273      1.2    matt 	uint32_t r;
    274      1.2    matt 
    275      1.2    matt 	/*
    276      1.2    matt 	 * PCI-X interface exists on XLR chips only
    277      1.2    matt 	 */
    278      1.2    matt 	if (! cpu_rmixlr(mips_options.mips_cpu))
    279      1.2    matt 		return 0;
    280      1.2    matt 
    281      1.2    matt 	/* XXX
    282      1.2    matt 	 * for now there is only one PCI-X Interface on chip
    283      1.2    matt 	 * and only one chip in the system
    284      1.2    matt 	 * this could change with furture RMI XL family designs
    285      1.2    matt 	 * or when we have multi-chip systems.
    286      1.2    matt 	 */
    287      1.2    matt 	if (rmixl_pcix_found)
    288      1.2    matt 		return 0;
    289      1.2    matt 
    290      1.2    matt 	/* read Host Mode Control register */
    291      1.2    matt 	r = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_MODE_CTL);
    292      1.2    matt 	r &= PCIX_HOST_MODE_CTL_HDMSTAT;
    293      1.2    matt 	if (r == 0)
    294      1.2    matt 		return 0;	/* strapped for Device Mode */
    295      1.2    matt 
    296      1.2    matt 	return 1;
    297      1.2    matt }
    298      1.2    matt 
    299      1.2    matt static void
    300      1.2    matt rmixl_pcix_attach(device_t parent, device_t self, void *aux)
    301      1.2    matt {
    302      1.2    matt 	rmixl_pcix_softc_t *sc = device_private(self);
    303      1.2    matt 	struct obio_attach_args *obio = aux;
    304      1.2    matt 	struct rmixl_config *rcp = &rmixl_configuration;
    305      1.2    matt         struct pcibus_attach_args pba;
    306      1.2    matt 	uint32_t bar;
    307      1.2    matt 
    308      1.2    matt 	rmixl_pcix_found = 1;
    309      1.2    matt 	sc->sc_dev = self;
    310      1.2    matt 	sc->sc_29bit_dmat = obio->obio_29bit_dmat;
    311      1.2    matt 	sc->sc_32bit_dmat = obio->obio_32bit_dmat;
    312      1.2    matt 	sc->sc_64bit_dmat = obio->obio_64bit_dmat;
    313      1.2    matt 	sc->sc_tmsk = obio->obio_tmsk;
    314      1.2    matt 
    315      1.2    matt 	aprint_normal(": RMI XLR PCI-X Interface\n");
    316      1.2    matt 
    317      1.4   cliff 	mutex_init(&sc->sc_mutex, MUTEX_DEFAULT, IPL_HIGH);
    318      1.4   cliff 
    319      1.2    matt 	rmixl_pcix_intcfg(sc);
    320      1.2    matt 
    321      1.2    matt 	rmixl_pcix_errata(sc);
    322      1.2    matt 
    323      1.2    matt 	/*
    324      1.2    matt 	 * check XLR Control Register
    325      1.2    matt 	 */
    326      1.2    matt 	DPRINTF(("%s: XLR_CONTROL=%#x\n", __func__,
    327      1.2    matt 		RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_XLR_CONTROL)));
    328      1.2    matt 
    329      1.2    matt 	/*
    330      1.2    matt 	 * HBAR[0]   if a 32 bit BAR, or
    331      1.2    matt 	 * HBAR[0,1] if a 64 bit BAR pair
    332      1.2    matt 	 * must cover all RAM
    333      1.2    matt 	 */
    334      1.2    matt 	extern u_quad_t mem_cluster_maxaddr;
    335      1.2    matt 	uint64_t hbar_addr;
    336      1.2    matt 	uint64_t hbar_size;
    337      1.2    matt 	uint32_t hbar_size_lo, hbar_size_hi;
    338      1.2    matt 	uint32_t hbar_addr_lo, hbar_addr_hi;
    339      1.2    matt 
    340      1.2    matt 	hbar_addr_lo = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR0_ADDR);
    341      1.2    matt 	hbar_addr_hi = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR1_ADDR);
    342      1.2    matt 	hbar_size_lo = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR0_SIZE);
    343      1.2    matt 	hbar_size_hi = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR1_SIZE);
    344      1.2    matt 
    345      1.2    matt 	hbar_addr = (u_quad_t)(hbar_addr_lo & PCI_MAPREG_MEM_ADDR_MASK);
    346      1.2    matt 	hbar_size = hbar_size_lo;
    347      1.2    matt 	if ((hbar_size_lo & PCI_MAPREG_MEM_TYPE_64BIT) != 0) {
    348      1.2    matt 		hbar_addr |= (uint64_t)hbar_addr_hi << 32;
    349      1.2    matt 		hbar_size |= (uint64_t)hbar_size_hi << 32;
    350      1.2    matt 	}
    351      1.2    matt 	if ((hbar_addr != 0) || (hbar_size < mem_cluster_maxaddr)) {
    352      1.2    matt 		int error;
    353      1.2    matt 
    354      1.2    matt 		aprint_error_dev(self, "HostBAR0 addr %#x, size %#x\n",
    355      1.2    matt 			hbar_addr_lo, hbar_size_lo);
    356      1.2    matt 		if ((hbar_size_lo & PCI_MAPREG_MEM_TYPE_64BIT) != 0)
    357      1.2    matt 			aprint_error_dev(self, "HostBAR1 addr %#x, size %#x\n",
    358      1.2    matt 				hbar_addr_hi, hbar_size_hi);
    359      1.2    matt 		aprint_error_dev(self, "WARNING: firmware PCI-X setup error: "
    360      1.2    matt 			"RAM %#"PRIx64"..%#"PRIx64" not accessible by Host BAR, "
    361      1.2    matt 			"enabling DMA bounce buffers\n",
    362      1.2    matt 			hbar_size, mem_cluster_maxaddr-1);
    363      1.2    matt 
    364      1.2    matt 		/*
    365      1.2    matt 		 * force use of bouce buffers for inaccessible RAM addrs
    366      1.2    matt 		 */
    367      1.2    matt 		if (hbar_size < ((uint64_t)1 << 32)) {
    368      1.2    matt 			error = bus_dmatag_subregion(sc->sc_32bit_dmat,
    369      1.2    matt 				0, (bus_addr_t)hbar_size, &sc->sc_32bit_dmat,
    370      1.2    matt 				BUS_DMA_NOWAIT);
    371      1.2    matt 			if (error)
    372      1.2    matt 				panic("%s: failed to subregion 32-bit dma tag:"
    373      1.2    matt 					 " error %d", __func__, error);
    374      1.2    matt 			sc->sc_64bit_dmat = NULL;
    375      1.2    matt 		} else {
    376      1.2    matt 			error = bus_dmatag_subregion(sc->sc_64bit_dmat,
    377      1.2    matt 				0, (bus_addr_t)hbar_size, &sc->sc_64bit_dmat,
    378      1.2    matt 				BUS_DMA_NOWAIT);
    379      1.2    matt 			if (error)
    380      1.2    matt 				panic("%s: failed to subregion 64-bit dma tag:"
    381      1.2    matt 					" error %d", __func__, error);
    382      1.2    matt 		}
    383      1.2    matt 	}
    384      1.2    matt 
    385      1.2    matt 	/*
    386      1.2    matt 	 * check PCI-X interface byteswap setup
    387      1.2    matt 	 * ensure 'Match Byte Lane' is disabled
    388      1.2    matt 	 */
    389  1.9.2.2    yamt 	uint32_t mble;
    390      1.2    matt 	mble = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_XLR_MBLE);
    391  1.9.2.2    yamt #ifdef PCI_DEBUG
    392  1.9.2.2    yamt 	uint32_t mba, mbs;
    393      1.2    matt 	mba  = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_MATCH_BIT_ADDR);
    394      1.2    matt 	mbs  = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_MATCH_BIT_SIZE);
    395      1.2    matt 	DPRINTF(("%s: MBLE=%#x, MBA=%#x, MBS=%#x\n", __func__, mble, mba, mbs));
    396  1.9.2.2    yamt #endif
    397      1.2    matt 	if ((mble & __BIT(40)) != 0)
    398      1.2    matt 		RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_XLR_MBLE, 0);
    399      1.2    matt 
    400      1.2    matt 	/*
    401      1.2    matt 	 * get PCI config space base addr from SBC PCIe CFG BAR
    402      1.2    matt 	 * initialize it if necessary
    403      1.2    matt  	 */
    404      1.2    matt 	bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_CFG_BAR);
    405      1.2    matt 	DPRINTF(("%s: PCIX_CFG_BAR %#x\n", __func__, bar));
    406      1.2    matt 	if ((bar & RMIXL_PCIX_CFG_BAR_ENB) == 0) {
    407      1.2    matt 		u_long n = RMIXL_PCIX_CFG_SIZE / (1024 * 1024);
    408      1.2    matt 		RMIXL_PCIX_BAR_INIT(CFG, bar, n, n);
    409      1.2    matt 	}
    410      1.2    matt 	rcp->rc_pci_cfg_pbase = (bus_addr_t)RMIXL_PCIX_CFG_BAR_TO_BA(bar);
    411      1.2    matt 	rcp->rc_pci_cfg_size  = (bus_size_t)RMIXL_PCIX_CFG_SIZE;
    412      1.2    matt 
    413      1.2    matt 	/*
    414      1.2    matt 	 * get PCI MEM space base [addr, size] from SBC PCIe MEM BAR
    415      1.2    matt 	 * initialize it if necessary
    416      1.2    matt  	 */
    417      1.2    matt 	bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_MEM_BAR);
    418      1.2    matt 	DPRINTF(("%s: PCIX_MEM_BAR %#x\n", __func__, bar));
    419      1.2    matt 	if ((bar & RMIXL_PCIX_MEM_BAR_ENB) == 0) {
    420      1.2    matt 		u_long n = 256;				/* 256 MB */
    421      1.2    matt 		RMIXL_PCIX_BAR_INIT(MEM, bar, n, n);
    422      1.2    matt 	}
    423      1.2    matt 	rcp->rc_pci_mem_pbase = (bus_addr_t)RMIXL_PCIX_MEM_BAR_TO_BA(bar);
    424      1.2    matt 	rcp->rc_pci_mem_size  = (bus_size_t)RMIXL_PCIX_MEM_BAR_TO_SIZE(bar);
    425      1.2    matt 
    426      1.2    matt 	/*
    427      1.2    matt 	 * get PCI IO space base [addr, size] from SBC PCIe IO BAR
    428      1.2    matt 	 * initialize it if necessary
    429      1.2    matt  	 */
    430      1.2    matt 	bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_IO_BAR);
    431      1.2    matt 	DPRINTF(("%s: PCIX_IO_BAR %#x\n", __func__, bar));
    432      1.2    matt 	if ((bar & RMIXL_PCIX_IO_BAR_ENB) == 0) {
    433      1.2    matt 		u_long n = 32;				/* 32 MB */
    434      1.2    matt 		RMIXL_PCIX_BAR_INIT(IO, bar, n, n);
    435      1.2    matt 	}
    436      1.2    matt 	rcp->rc_pci_io_pbase = (bus_addr_t)RMIXL_PCIX_IO_BAR_TO_BA(bar);
    437      1.2    matt 	rcp->rc_pci_io_size  = (bus_size_t)RMIXL_PCIX_IO_BAR_TO_SIZE(bar);
    438      1.2    matt 
    439      1.2    matt 	/*
    440      1.2    matt 	 * initialize the PCI CFG bus space tag
    441      1.2    matt 	 */
    442      1.2    matt 	rmixl_pci_cfg_bus_mem_init(&rcp->rc_pci_cfg_memt, rcp);
    443      1.2    matt 	sc->sc_pci_cfg_memt = &rcp->rc_pci_cfg_memt;
    444      1.2    matt 
    445      1.2    matt 	/*
    446      1.2    matt 	 * initialize the PCI MEM and IO bus space tags
    447      1.2    matt 	 */
    448      1.2    matt 	rmixl_pci_bus_mem_init(&rcp->rc_pci_memt, rcp);
    449      1.2    matt 	rmixl_pci_bus_io_init(&rcp->rc_pci_iot, rcp);
    450      1.2    matt 
    451      1.2    matt 	/*
    452      1.2    matt 	 * initialize the extended configuration regs
    453      1.2    matt 	 */
    454      1.2    matt 	rmixl_pcix_init_errors(sc);
    455      1.2    matt 
    456      1.2    matt 	/*
    457      1.2    matt 	 * initialize the PCI chipset tag
    458      1.2    matt 	 */
    459      1.2    matt 	rmixl_pcix_init(sc);
    460      1.2    matt 
    461      1.2    matt 	/*
    462      1.2    matt 	 * attach the PCI bus
    463      1.2    matt 	 */
    464      1.2    matt 	memset(&pba, 0, sizeof(pba));
    465      1.2    matt 	pba.pba_memt = &rcp->rc_pci_memt;
    466      1.2    matt 	pba.pba_iot =  &rcp->rc_pci_iot;
    467      1.2    matt 	pba.pba_dmat = sc->sc_32bit_dmat;
    468      1.2    matt 	pba.pba_dmat64 = sc->sc_64bit_dmat;
    469      1.2    matt 	pba.pba_pc = &sc->sc_pci_chipset;
    470      1.2    matt 	pba.pba_bus = 0;
    471      1.2    matt 	pba.pba_bridgetag = NULL;
    472      1.2    matt 	pba.pba_intrswiz = 0;
    473      1.2    matt 	pba.pba_intrtag = 0;
    474      1.7  dyoung 	pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY |
    475      1.2    matt 		PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY;
    476      1.2    matt 
    477      1.2    matt 	(void) config_found_ia(self, "pcibus", &pba, pcibusprint);
    478      1.2    matt }
    479      1.2    matt 
    480      1.2    matt /*
    481      1.2    matt  * rmixl_pcix_intcfg - init PCI-X interrupt control
    482      1.2    matt  */
    483      1.2    matt static void
    484      1.2    matt rmixl_pcix_intcfg(rmixl_pcix_softc_t *sc)
    485      1.2    matt {
    486      1.2    matt 	size_t size;
    487      1.2    matt 	rmixl_pcix_evcnt_t *ev;
    488      1.2    matt 
    489      1.2    matt 	DPRINTF(("%s\n", __func__));
    490      1.2    matt 
    491      1.2    matt 	/* mask all interrupts until they are established */
    492      1.2    matt 	RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL,
    493      1.2    matt 		PCIX_INTR_CONTROL_MASK_ALL);
    494      1.2    matt 
    495      1.2    matt 	/*
    496      1.2    matt 	 * read-to-clear any pre-existing interrupts
    497      1.2    matt 	 * XXX MSI bits in STATUS are also documented as write 1 to clear in PRM
    498      1.2    matt 	 */
    499      1.2    matt 	(void)RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS);
    500      1.2    matt 	(void)RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS);
    501      1.2    matt 
    502      1.2    matt 	/* initialize the (non-error interrupt) dispatch handles */
    503      1.2    matt 	sc->sc_intr = NULL;
    504      1.2    matt 
    505      1.2    matt 	/*
    506      1.2    matt 	 * allocate per-cpu, per-pin interrupt event counters
    507      1.2    matt 	 */
    508      1.2    matt 	size = ncpu * PCI_INTERRUPT_PIN_MAX * sizeof(rmixl_pcix_evcnt_t);
    509      1.2    matt 	ev = malloc(size, M_DEVBUF, M_NOWAIT);
    510      1.2    matt 	if (ev == NULL)
    511      1.2    matt 		panic("%s: cannot malloc evcnts\n", __func__);
    512      1.2    matt 	sc->sc_evcnts = ev;
    513      1.2    matt 	for (int pin=PCI_INTERRUPT_PIN_A; pin <= PCI_INTERRUPT_PIN_MAX; pin++) {
    514      1.2    matt 		for (int cpu=0; cpu < ncpu; cpu++) {
    515      1.2    matt 			ev = RMIXL_PCIX_EVCNT(sc, pin - 1, cpu);
    516      1.2    matt 			snprintf(ev->name, sizeof(ev->name),
    517      1.2    matt 				"cpu%d, pin %d", cpu, pin);
    518      1.2    matt 			evcnt_attach_dynamic(&ev->evcnt, EVCNT_TYPE_INTR,
    519      1.2    matt 				NULL, "rmixl_pcix", ev->name);
    520      1.2    matt 		}
    521      1.2    matt 	}
    522      1.2    matt 
    523      1.2    matt 	/*
    524      1.2    matt 	 * establish PCIX error interrupt handler
    525      1.2    matt 	 */
    526      1.2    matt 	sc->sc_fatal_ih = rmixl_intr_establish(24, sc->sc_tmsk,
    527      1.2    matt 		IPL_VM, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH,
    528      1.2    matt 		rmixl_pcix_error_intr, sc, false);
    529      1.2    matt 	if (sc->sc_fatal_ih == NULL)
    530      1.2    matt 		panic("%s: cannot establish irq %d", __func__, 24);
    531      1.2    matt }
    532      1.2    matt 
    533      1.2    matt static void
    534      1.2    matt rmixl_pcix_errata(rmixl_pcix_softc_t *sc)
    535      1.2    matt {
    536      1.2    matt 	/* nothing */
    537      1.2    matt }
    538      1.2    matt 
    539      1.2    matt static void
    540      1.2    matt rmixl_pcix_init(rmixl_pcix_softc_t *sc)
    541      1.2    matt {
    542      1.2    matt 	pci_chipset_tag_t pc = &sc->sc_pci_chipset;
    543      1.2    matt #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
    544      1.2    matt 	struct extent *ioext, *memext;
    545      1.2    matt #endif
    546      1.2    matt 
    547      1.2    matt 	pc->pc_conf_v = (void *)sc;
    548      1.2    matt 	pc->pc_attach_hook = rmixl_pcix_attach_hook;
    549      1.2    matt 	pc->pc_bus_maxdevs = rmixl_pcix_bus_maxdevs;
    550      1.2    matt 	pc->pc_make_tag = rmixl_pcix_make_tag;
    551      1.2    matt 	pc->pc_decompose_tag = rmixl_pcix_decompose_tag;
    552      1.2    matt 	pc->pc_conf_read = rmixl_pcix_conf_read;
    553      1.2    matt 	pc->pc_conf_write = rmixl_pcix_conf_write;
    554      1.2    matt 
    555      1.2    matt 	pc->pc_intr_v = (void *)sc;
    556      1.2    matt 	pc->pc_intr_map = rmixl_pcix_intr_map;
    557      1.2    matt 	pc->pc_intr_string = rmixl_pcix_intr_string;
    558      1.2    matt 	pc->pc_intr_evcnt = rmixl_pcix_intr_evcnt;
    559      1.2    matt 	pc->pc_intr_establish = rmixl_pcix_intr_establish;
    560      1.2    matt 	pc->pc_intr_disestablish = rmixl_pcix_intr_disestablish;
    561      1.2    matt 	pc->pc_conf_interrupt = rmixl_conf_interrupt;
    562      1.2    matt 
    563      1.2    matt #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
    564      1.2    matt 	/*
    565      1.2    matt 	 * Configure the PCI bus.
    566      1.2    matt 	 */
    567      1.2    matt 	struct rmixl_config *rcp = &rmixl_configuration;
    568      1.2    matt 
    569      1.2    matt 	aprint_normal_dev(sc->sc_dev, "%s: configuring PCI bus\n");
    570      1.2    matt 
    571      1.2    matt 	ioext  = extent_create("pciio",
    572      1.2    matt 		rcp->rc_pci_io_pbase,
    573      1.2    matt 		rcp->rc_pci_io_pbase + rcp->rc_pci_io_size - 1,
    574      1.2    matt 		M_DEVBUF, NULL, 0, EX_NOWAIT);
    575      1.2    matt 
    576      1.2    matt 	memext = extent_create("pcimem",
    577      1.2    matt 		rcp->rc_pci_mem_pbase,
    578      1.2    matt 		rcp->rc_pci_mem_pbase + rcp->rc_pci_mem_size - 1,
    579      1.2    matt 		M_DEVBUF, NULL, 0, EX_NOWAIT);
    580      1.2    matt 
    581      1.2    matt 	pci_configure_bus(pc, ioext, memext, NULL, 0,
    582      1.2    matt 	    mips_cache_info.mci_dcache_align);
    583      1.2    matt 
    584      1.2    matt 	extent_destroy(ioext);
    585      1.2    matt 	extent_destroy(memext);
    586      1.2    matt #endif
    587      1.2    matt }
    588      1.2    matt 
    589      1.2    matt static void
    590      1.2    matt rmixl_pcix_init_errors(rmixl_pcix_softc_t *sc)
    591      1.2    matt {
    592      1.2    matt 	/* nothing */
    593      1.2    matt }
    594      1.2    matt 
    595      1.2    matt void
    596      1.2    matt rmixl_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *iline)
    597      1.2    matt {
    598      1.2    matt 	DPRINTF(("%s: %p, %d, %d, %d, %d, %p\n",
    599      1.2    matt 		__func__, v, bus, dev, ipin, swiz, iline));
    600      1.2    matt }
    601      1.2    matt 
    602      1.2    matt void
    603  1.9.2.1    yamt rmixl_pcix_attach_hook(device_t parent, device_t self,
    604      1.2    matt 	struct pcibus_attach_args *pba)
    605      1.2    matt {
    606      1.2    matt 	DPRINTF(("%s: pba_bus %d, pba_bridgetag %p, pc_conf_v %p\n",
    607      1.2    matt 		__func__, pba->pba_bus, pba->pba_bridgetag,
    608      1.2    matt 		pba->pba_pc->pc_conf_v));
    609      1.2    matt }
    610      1.2    matt 
    611      1.2    matt int
    612      1.2    matt rmixl_pcix_bus_maxdevs(void *v, int busno)
    613      1.2    matt {
    614      1.2    matt 	return (32);	/* XXX depends on the family of XLS SoC */
    615      1.2    matt }
    616      1.2    matt 
    617      1.2    matt /*
    618      1.2    matt  * XLS pci tag is a 40 bit address composed thusly:
    619      1.2    matt  *	39:25   (reserved)
    620      1.2    matt  *	24      Swap (0=little, 1=big endian)
    621      1.2    matt  *	23:16   Bus number
    622      1.2    matt  *	15:11   Device number
    623      1.2    matt  *	10:8    Function number
    624      1.2    matt  *	7:0     Register number
    625      1.2    matt  *
    626      1.2    matt  * Note: this is the "native" composition for addressing CFG space, but not for ECFG space.
    627      1.2    matt  */
    628      1.2    matt pcitag_t
    629      1.2    matt rmixl_pcix_make_tag(void *v, int bus, int dev, int fun)
    630      1.2    matt {
    631      1.2    matt 	return ((bus << 16) | (dev << 11) | (fun << 8));
    632      1.2    matt }
    633      1.2    matt 
    634      1.2    matt void
    635      1.2    matt rmixl_pcix_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
    636      1.2    matt {
    637      1.2    matt 	if (bp != NULL)
    638      1.2    matt 		*bp = (tag >> 16) & 0xff;
    639      1.2    matt 	if (dp != NULL)
    640      1.2    matt 		*dp = (tag >> 11) & 0x1f;
    641      1.2    matt 	if (fp != NULL)
    642      1.2    matt 		*fp = (tag >> 8) & 0x7;
    643      1.2    matt }
    644      1.2    matt 
    645      1.2    matt void
    646      1.2    matt rmixl_pcix_tag_print(const char *restrict s, void *v, pcitag_t tag, int offset,
    647      1.2    matt 	vaddr_t va, u_long r)
    648      1.2    matt {
    649      1.2    matt 	int bus, dev, fun;
    650      1.2    matt 
    651      1.2    matt 	rmixl_pcix_decompose_tag(v, tag, &bus, &dev, &fun);
    652      1.2    matt 	printf("%s: %d/%d/%d/%d - %#" PRIxVADDR ":%#lx\n",
    653      1.2    matt 		s, bus, dev, fun, offset, va, r);
    654      1.2    matt }
    655      1.2    matt 
    656      1.2    matt static int
    657      1.2    matt rmixl_pcix_conf_setup(rmixl_pcix_softc_t *sc,
    658      1.2    matt 	pcitag_t tag, int *offp, bus_space_tag_t *bstp,
    659      1.2    matt 	bus_space_handle_t *bshp)
    660      1.2    matt {
    661      1.2    matt 	struct rmixl_config *rcp = &rmixl_configuration;
    662      1.2    matt 	bus_space_tag_t bst;
    663      1.2    matt 	bus_space_handle_t bsh;
    664      1.2    matt 	bus_size_t size;
    665      1.2    matt 	pcitag_t mask;
    666      1.2    matt 	bus_addr_t ba;
    667      1.2    matt 	int err;
    668      1.2    matt 	static bus_space_handle_t cfg_bsh;
    669      1.2    matt 	static bus_addr_t cfg_oba = -1;
    670      1.2    matt 
    671      1.2    matt 	/*
    672      1.2    matt 	 * bus space depends on offset
    673      1.2    matt 	 */
    674      1.2    matt 	if ((*offp >= 0) && (*offp < 0x100)) {
    675      1.2    matt 		mask = __BITS(15,0);
    676      1.2    matt 		bst = sc->sc_pci_cfg_memt;
    677      1.2    matt 		ba = rcp->rc_pci_cfg_pbase;
    678      1.2    matt 		ba += (tag & ~mask);
    679      1.2    matt 		*offp += (tag & mask);
    680      1.2    matt 		if (ba != cfg_oba) {
    681      1.2    matt 			size = (bus_size_t)(mask + 1);
    682      1.2    matt 			if (cfg_oba != -1)
    683      1.2    matt 				bus_space_unmap(bst, cfg_bsh, size);
    684      1.2    matt 			err = bus_space_map(bst, ba, size, 0, &cfg_bsh);
    685      1.2    matt 			if (err != 0) {
    686      1.2    matt #ifdef DEBUG
    687      1.2    matt 				panic("%s: bus_space_map err %d, CFG space",
    688      1.2    matt 					__func__, err);	/* XXX */
    689      1.2    matt #endif
    690      1.2    matt 				return -1;
    691      1.2    matt 			}
    692      1.2    matt 			cfg_oba = ba;
    693      1.2    matt 		}
    694      1.2    matt 		bsh = cfg_bsh;
    695      1.2    matt 	} else  {
    696      1.2    matt #ifdef DEBUG
    697      1.2    matt 		panic("%s: offset %#x: unknown", __func__, *offp);
    698      1.2    matt #endif
    699      1.2    matt 		return -1;
    700      1.2    matt 	}
    701      1.2    matt 
    702      1.2    matt 	*bstp = bst;
    703      1.2    matt 	*bshp = bsh;
    704      1.2    matt 
    705      1.2    matt 	return 0;
    706      1.2    matt }
    707      1.2    matt 
    708      1.2    matt pcireg_t
    709      1.2    matt rmixl_pcix_conf_read(void *v, pcitag_t tag, int offset)
    710      1.2    matt {
    711      1.2    matt 	rmixl_pcix_softc_t *sc = v;
    712      1.2    matt 	static bus_space_handle_t bsh;
    713      1.2    matt 	bus_space_tag_t bst;
    714      1.2    matt 	pcireg_t rv;
    715      1.2    matt 	uint64_t cfg0;
    716      1.2    matt 
    717      1.2    matt 	mutex_enter(&sc->sc_mutex);
    718      1.2    matt 
    719      1.2    matt 	if (rmixl_pcix_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) {
    720      1.2    matt 		cfg0 = rmixl_cache_err_dis();
    721      1.2    matt 		rv = bus_space_read_4(bst, bsh, (bus_size_t)offset);
    722      1.2    matt 		if (rmixl_cache_err_check() != 0) {
    723      1.2    matt #ifdef DIAGNOSTIC
    724      1.2    matt 			int bus, dev, fun;
    725      1.2    matt 
    726      1.2    matt 			rmixl_pcix_decompose_tag(v, tag, &bus, &dev, &fun);
    727      1.2    matt 			printf("%s: %d/%d/%d, offset %#x: bad address\n",
    728      1.2    matt 				__func__, bus, dev, fun, offset);
    729      1.2    matt #endif
    730      1.2    matt 			rv = (pcireg_t) -1;
    731      1.2    matt 		}
    732      1.2    matt 		rmixl_cache_err_restore(cfg0);
    733      1.2    matt 	} else {
    734      1.2    matt 		rv = -1;
    735      1.2    matt 	}
    736      1.2    matt 
    737      1.2    matt 	mutex_exit(&sc->sc_mutex);
    738      1.2    matt 
    739      1.2    matt 	return rv;
    740      1.2    matt }
    741      1.2    matt 
    742      1.2    matt void
    743      1.2    matt rmixl_pcix_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val)
    744      1.2    matt {
    745      1.2    matt 	rmixl_pcix_softc_t *sc = v;
    746      1.2    matt 	static bus_space_handle_t bsh;
    747      1.2    matt 	bus_space_tag_t bst;
    748      1.2    matt 	uint64_t cfg0;
    749      1.2    matt 
    750      1.2    matt 	mutex_enter(&sc->sc_mutex);
    751      1.2    matt 
    752      1.2    matt 	if (rmixl_pcix_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) {
    753      1.2    matt 		cfg0 = rmixl_cache_err_dis();
    754      1.2    matt 		bus_space_write_4(bst, bsh, (bus_size_t)offset, val);
    755      1.2    matt 		if (rmixl_cache_err_check() != 0) {
    756      1.2    matt #ifdef DIAGNOSTIC
    757      1.2    matt 			int bus, dev, fun;
    758      1.2    matt 
    759      1.2    matt 			rmixl_pcix_decompose_tag(v, tag, &bus, &dev, &fun);
    760      1.2    matt 			printf("%s: %d/%d/%d, offset %#x: bad address\n",
    761      1.2    matt 				__func__, bus, dev, fun, offset);
    762      1.2    matt #endif
    763      1.2    matt 		}
    764      1.2    matt 		rmixl_cache_err_restore(cfg0);
    765      1.2    matt 	}
    766      1.2    matt 
    767      1.2    matt 	mutex_exit(&sc->sc_mutex);
    768      1.2    matt }
    769      1.2    matt 
    770      1.2    matt int
    771      1.3  dyoung rmixl_pcix_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *pih)
    772      1.2    matt {
    773      1.2    matt 	const u_int irq = 16;	/* PCIX index in IRT */
    774      1.2    matt 
    775      1.2    matt #ifdef DEBUG
    776      1.2    matt 	DPRINTF(("%s: ps_bus %d, pa_intrswiz %#x, pa_intrtag %#lx,"
    777      1.2    matt 		" pa_intrpin %d,  pa_intrline %d, pa_rawintrpin %d\n",
    778      1.2    matt 		__func__, pa->pa_bus, pa->pa_intrswiz, pa->pa_intrtag,
    779      1.2    matt 		pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin));
    780      1.2    matt #endif
    781      1.2    matt 
    782      1.2    matt 	if (pa->pa_intrpin != PCI_INTERRUPT_PIN_NONE)
    783      1.2    matt 		*pih = rmixl_pcix_make_pih(pa->pa_intrpin - 1, irq);
    784      1.2    matt 	else
    785      1.2    matt 		*pih = ~0;
    786      1.2    matt 
    787      1.2    matt 	return 0;
    788      1.2    matt }
    789      1.2    matt 
    790      1.2    matt const char *
    791  1.9.2.2    yamt rmixl_pcix_intr_string(void *v, pci_intr_handle_t pih, char *buf, size_t len)
    792      1.2    matt {
    793      1.2    matt 	u_int bitno, irq;
    794      1.2    matt 
    795      1.2    matt 	rmixl_pcix_decompose_pih(pih, &bitno, &irq);
    796      1.2    matt 
    797      1.2    matt 	if (! cpu_rmixlr(mips_options.mips_cpu))
    798      1.2    matt 		panic("%s: cpu %#x not supported\n",
    799      1.2    matt 			__func__, mips_options.mips_cpu_id);
    800      1.2    matt 
    801  1.9.2.2    yamt 	strlcpy(buf, rmixl_intr_string(RMIXL_IRT_VECTOR(irq)), len);
    802  1.9.2.2    yamt 	return buf;
    803      1.2    matt }
    804      1.2    matt 
    805      1.2    matt const struct evcnt *
    806      1.2    matt rmixl_pcix_intr_evcnt(void *v, pci_intr_handle_t pih)
    807      1.2    matt {
    808      1.2    matt 	return NULL;
    809      1.2    matt }
    810      1.2    matt 
    811      1.2    matt static pci_intr_handle_t
    812      1.2    matt rmixl_pcix_make_pih(u_int bitno, u_int irq)
    813      1.2    matt {
    814      1.2    matt 	pci_intr_handle_t pih;
    815      1.2    matt 
    816      1.2    matt 	KASSERT(bitno < 64);
    817      1.2    matt 	KASSERT(irq < 32);
    818      1.2    matt 
    819      1.2    matt 	pih  = (irq << 6);
    820      1.2    matt 	pih |= bitno;
    821      1.2    matt 
    822      1.2    matt 	return pih;
    823      1.2    matt }
    824      1.2    matt 
    825      1.2    matt static void
    826      1.2    matt rmixl_pcix_decompose_pih(pci_intr_handle_t pih, u_int *bitno, u_int *irq)
    827      1.2    matt {
    828      1.2    matt 	*bitno = (u_int)(pih & 0x3f);
    829      1.2    matt 	*irq = (u_int)(pih >> 6);
    830      1.2    matt 
    831      1.2    matt 	KASSERT(*bitno < 64);
    832      1.2    matt 	KASSERT(*irq < 31);
    833      1.2    matt }
    834      1.2    matt 
    835      1.2    matt static void
    836      1.2    matt rmixl_pcix_intr_disestablish(void *v, void *ih)
    837      1.2    matt {
    838      1.2    matt 	rmixl_pcix_softc_t *sc = v;
    839      1.2    matt 	rmixl_pcix_dispatch_t *dip = ih;
    840      1.2    matt 	rmixl_pcix_intr_t *pip = sc->sc_intr;
    841      1.2    matt 	bool busy;
    842      1.2    matt 
    843      1.2    matt 	DPRINTF(("%s: pin=%d irq=%d\n",
    844      1.2    matt 		__func__, dip->bitno + 1, dip->irq));
    845      1.2    matt 	KASSERT(dip->bitno < RMIXL_PCIX_NINTR);
    846      1.2    matt 
    847      1.2    matt 	mutex_enter(&sc->sc_mutex);
    848      1.2    matt 
    849      1.2    matt 	dip->func = NULL;	/* prevent further dispatch */
    850      1.2    matt 
    851      1.2    matt 	/*
    852      1.2    matt 	 * if no other dispatch handle is using this interrupt,
    853      1.2    matt 	 * we can disable it
    854      1.2    matt 	 */
    855      1.2    matt 	busy = false;
    856      1.2    matt 	for (int i=0; i < pip->dispatch_count; i++) {
    857      1.2    matt 		rmixl_pcix_dispatch_t *d = &pip->dispatch_data[i];
    858      1.2    matt 		if (d == dip)
    859      1.2    matt 			continue;
    860      1.2    matt 		if (d->bitno == dip->bitno) {
    861      1.2    matt 			busy = true;
    862      1.2    matt 			break;
    863      1.2    matt 		}
    864      1.2    matt 	}
    865      1.2    matt 	if (! busy) {
    866      1.2    matt 		uint32_t bit = 1 << (dip->bitno + 2);
    867      1.2    matt 		uint32_t r;
    868      1.2    matt 
    869      1.2    matt 		r = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL);
    870      1.2    matt 		r |= bit;		/* set mask */
    871      1.2    matt 		RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, r);
    872      1.2    matt 		DPRINTF(("%s: disabled pin %d\n", __func__, dip->bitno + 1));
    873      1.2    matt 
    874      1.2    matt 		pip->intenb &= ~(1 << dip->bitno);
    875      1.2    matt 
    876      1.2    matt 		if ((r & PCIX_INTR_CONTROL_MASK_ALL) == 0) {
    877      1.2    matt 			/* tear down interrupt for this pcix */
    878      1.2    matt 			rmixl_intr_disestablish(pip->ih);
    879      1.2    matt 
    880      1.2    matt 			/* commit NULL interrupt set */
    881      1.2    matt 			sc->sc_intr = NULL;
    882      1.2    matt 
    883      1.2    matt 			/* schedule delayed free of the old interrupt set */
    884      1.2    matt 			rmixl_pcix_pip_free_callout(pip);
    885      1.2    matt 		}
    886      1.2    matt 	}
    887      1.2    matt 
    888      1.2    matt 	mutex_exit(&sc->sc_mutex);
    889      1.2    matt }
    890      1.2    matt 
    891      1.2    matt static void *
    892      1.2    matt rmixl_pcix_intr_establish(void *v, pci_intr_handle_t pih, int ipl,
    893      1.2    matt         int (*func)(void *), void *arg)
    894      1.2    matt {
    895      1.2    matt 	rmixl_pcix_softc_t *sc = v;
    896      1.2    matt 	u_int bitno, irq;
    897      1.2    matt 	rmixl_pcix_intr_t *pip;
    898      1.2    matt 	rmixl_pcix_dispatch_t *dip = NULL;
    899      1.2    matt 
    900      1.2    matt 	if (pih == ~0) {
    901      1.2    matt 		DPRINTF(("%s: bad pih=%#lx, implies PCI_INTERRUPT_PIN_NONE\n",
    902      1.2    matt 			__func__, pih));
    903      1.2    matt 		return NULL;
    904      1.2    matt 	}
    905      1.2    matt 
    906      1.2    matt 	rmixl_pcix_decompose_pih(pih, &bitno, &irq);
    907      1.2    matt 	DPRINTF(("%s: pin=%d irq=%d\n", __func__, bitno + 1, irq));
    908      1.2    matt 
    909      1.2    matt 	KASSERT(bitno < RMIXL_PCIX_NINTR);
    910      1.2    matt 
    911      1.2    matt 	/*
    912      1.2    matt 	 * all PCI-X device intrs get same ipl
    913      1.2    matt 	 */
    914      1.2    matt 	KASSERT(ipl == IPL_VM);
    915      1.2    matt 
    916      1.2    matt 	mutex_enter(&sc->sc_mutex);
    917      1.2    matt 
    918      1.2    matt 	pip = rmixl_pcix_pip_add_1(sc, irq, ipl);
    919      1.2    matt 	if (pip == NULL)
    920      1.2    matt 		return NULL;
    921      1.2    matt 
    922      1.2    matt 	/*
    923      1.2    matt 	 * initializae our new interrupt, the last element in dispatch_data[]
    924      1.2    matt 	 */
    925      1.2    matt 	dip = &pip->dispatch_data[pip->dispatch_count - 1];
    926      1.2    matt 	dip->bitno = bitno;
    927      1.2    matt 	dip->irq = irq;
    928      1.2    matt 	dip->func = func;
    929      1.2    matt 	dip->arg = arg;
    930      1.5   cliff 	dip->counts = RMIXL_PCIX_EVCNT(sc, bitno, 0);
    931      1.2    matt #if NEVER
    932      1.2    matt 	snprintf(dip->count_name, sizeof(dip->count_name),
    933      1.2    matt 		"pin %d", bitno + 1);
    934      1.2    matt 	evcnt_attach_dynamic(&dip->count, EVCNT_TYPE_INTR, NULL,
    935      1.2    matt 		"rmixl_pcix", dip->count_name);
    936      1.2    matt #endif
    937      1.2    matt 
    938      1.2    matt 	/* commit the new interrupt set */
    939      1.2    matt 	sc->sc_intr = pip;
    940      1.2    matt 
    941      1.2    matt 	/* enable this interrupt in the PCIX controller, if necessary */
    942      1.2    matt 	if ((pip->intenb & (1 << bitno)) == 0) {
    943      1.2    matt 		uint32_t bit = 1 << (bitno + 2);
    944      1.2    matt 		uint32_t r;
    945      1.2    matt 
    946      1.2    matt 		r = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL);
    947      1.2    matt 		r &= ~bit;	/* clear mask */
    948      1.2    matt 		RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, r);
    949      1.2    matt 
    950      1.2    matt 		pip->sc = sc;
    951      1.2    matt 		pip->ipl = ipl;
    952      1.2    matt 		pip->intenb |= 1 << bitno;
    953      1.2    matt 		DPRINTF(("%s: enabled pin %d\n", __func__, bitno + 1));
    954      1.2    matt 	}
    955      1.2    matt 
    956      1.2    matt 	mutex_exit(&sc->sc_mutex);
    957      1.2    matt 	return dip;
    958      1.2    matt }
    959      1.2    matt 
    960      1.2    matt rmixl_pcix_intr_t *
    961      1.2    matt rmixl_pcix_pip_add_1(rmixl_pcix_softc_t *sc, int irq, int ipl)
    962      1.2    matt {
    963      1.2    matt 	rmixl_pcix_intr_t *pip_old = sc->sc_intr;
    964      1.2    matt 	rmixl_pcix_intr_t *pip_new;
    965      1.2    matt 	u_int dispatch_count;
    966      1.2    matt 	size_t size;
    967      1.2    matt 
    968      1.2    matt 	dispatch_count = 1;
    969      1.2    matt 	size = sizeof(rmixl_pcix_intr_t);
    970      1.2    matt 	if (pip_old != NULL) {
    971      1.2    matt 		/*
    972      1.2    matt 		 * count only those dispatch elements still in use
    973      1.2    matt 		 * unused ones will be pruned during copy
    974      1.2    matt 		 * i.e. we are "lazy" there is no rmixl_pcix_pip_sub_1
    975      1.2    matt 		 */
    976      1.2    matt 		for (int i=0; i < pip_old->dispatch_count; i++) {
    977      1.2    matt 			if (pip_old->dispatch_data[i].func != NULL) {
    978      1.2    matt 				dispatch_count++;
    979      1.2    matt 				size += sizeof(rmixl_pcix_intr_t);
    980      1.2    matt 			}
    981      1.2    matt 		}
    982      1.2    matt 	}
    983      1.2    matt 
    984      1.2    matt 	/*
    985      1.2    matt 	 * allocate and initialize softc intr struct
    986      1.2    matt 	 * with one or more dispatch handles
    987      1.2    matt 	 */
    988      1.6    matt 	pip_new = malloc(size, M_DEVBUF, M_NOWAIT|M_ZERO);
    989      1.2    matt 	if (pip_new == NULL) {
    990      1.2    matt #ifdef DIAGNOSTIC
    991      1.2    matt 		printf("%s: cannot malloc\n", __func__);
    992      1.2    matt #endif
    993      1.2    matt 		return NULL;
    994      1.2    matt 	}
    995      1.2    matt 
    996      1.2    matt 	if (pip_old == NULL) {
    997      1.2    matt 		/* initialize the interrupt struct */
    998      1.2    matt 		pip_new->sc = sc;
    999      1.2    matt 		pip_new->ipl = ipl;
   1000      1.2    matt 		pip_new->ih = rmixl_intr_establish(irq, sc->sc_tmsk,
   1001      1.2    matt 			ipl, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH,
   1002      1.2    matt 			rmixl_pcix_intr, pip_new, false);
   1003      1.2    matt 		if (pip_new->ih == NULL)
   1004      1.2    matt 			panic("%s: cannot establish irq %d", __func__, irq);
   1005      1.2    matt 	} else {
   1006      1.2    matt 		/*
   1007      1.2    matt 		 * all intrs on a softc get same ipl and sc
   1008      1.2    matt 		 * first intr established sets the standard
   1009      1.2    matt 		 */
   1010      1.2    matt 		KASSERT(sc == pip_old->sc);
   1011      1.2    matt 		if (sc != pip_old->sc) {
   1012      1.2    matt 			printf("%s: sc %p mismatch\n", __func__, sc);
   1013      1.2    matt 			free(pip_new, M_DEVBUF);
   1014      1.2    matt 			return NULL;
   1015      1.2    matt 		}
   1016      1.2    matt 		KASSERT (ipl == pip_old->ipl);
   1017      1.2    matt 		if (ipl != pip_old->ipl) {
   1018      1.2    matt 			printf("%s: ipl %d mismatch\n", __func__, ipl);
   1019      1.2    matt 			free(pip_new, M_DEVBUF);
   1020      1.2    matt 			return NULL;
   1021      1.2    matt 		}
   1022      1.2    matt 		/*
   1023      1.2    matt 		 * copy pip_old to pip_new, skipping unused dispatch elemets
   1024      1.2    matt 		 */
   1025      1.2    matt 		memcpy(pip_new, pip_old, sizeof(rmixl_pcix_intr_t));
   1026      1.2    matt 		for (int j=0, i=0; i < pip_old->dispatch_count; i++) {
   1027      1.2    matt 			if (pip_old->dispatch_data[i].func != NULL) {
   1028      1.2    matt 				memcpy(&pip_new->dispatch_data[j],
   1029      1.2    matt 					&pip_old->dispatch_data[i],
   1030      1.2    matt 					sizeof(rmixl_pcix_dispatch_t));
   1031      1.2    matt 				j++;
   1032      1.2    matt 			}
   1033      1.2    matt 		}
   1034      1.2    matt 
   1035      1.2    matt 		/*
   1036      1.2    matt 		 * schedule delayed free of old interrupt set
   1037      1.2    matt 		 */
   1038      1.2    matt 		rmixl_pcix_pip_free_callout(pip_old);
   1039      1.2    matt 	}
   1040      1.2    matt 	pip_new->dispatch_count = dispatch_count;
   1041      1.2    matt 
   1042      1.2    matt 	return pip_new;
   1043      1.2    matt }
   1044      1.2    matt 
   1045      1.2    matt /*
   1046      1.2    matt  * delay free of the old interrupt set
   1047      1.2    matt  * to allow anyone still using it to do so safely
   1048      1.2    matt  * XXX 2 seconds should be plenty?
   1049      1.2    matt  */
   1050      1.2    matt static void
   1051      1.2    matt rmixl_pcix_pip_free_callout(rmixl_pcix_intr_t *pip)
   1052      1.2    matt {
   1053      1.2    matt 	callout_init(&pip->callout, 0);
   1054      1.2    matt 	callout_reset(&pip->callout, 2 * hz, rmixl_pcix_pip_free, pip);
   1055      1.2    matt }
   1056      1.2    matt 
   1057      1.2    matt static void
   1058      1.2    matt rmixl_pcix_pip_free(void *arg)
   1059      1.2    matt {
   1060      1.2    matt 	rmixl_pcix_intr_t *pip = arg;
   1061      1.2    matt 
   1062      1.2    matt 	callout_destroy(&pip->callout);
   1063      1.2    matt 	free(pip, M_DEVBUF);
   1064      1.2    matt }
   1065      1.2    matt 
   1066      1.2    matt static int
   1067      1.2    matt rmixl_pcix_intr(void *arg)
   1068      1.2    matt {
   1069      1.2    matt 	rmixl_pcix_intr_t *pip = arg;
   1070      1.2    matt 	int rv = 0;
   1071      1.2    matt 
   1072      1.2    matt 	uint32_t status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS);
   1073      1.2    matt 	DPRINTF(("%s: %#x\n", __func__, status));
   1074      1.2    matt 
   1075      1.2    matt 	if (status != 0) {
   1076      1.2    matt 		for (int i=0; i < pip->dispatch_count; i++) {
   1077      1.2    matt 			rmixl_pcix_dispatch_t *dip = &pip->dispatch_data[i];
   1078      1.2    matt 			uint32_t bit = 1 << dip->bitno;
   1079      1.2    matt 			int (*func)(void *) = dip->func;
   1080      1.2    matt 			if ((func != NULL) && (status & bit) != 0) {
   1081      1.2    matt 				(void)(*func)(dip->arg);
   1082      1.2    matt 				dip->counts[cpu_index(curcpu())].evcnt.ev_count++;
   1083      1.2    matt 				rv = 1;
   1084      1.2    matt 			}
   1085      1.2    matt 		}
   1086      1.2    matt 	}
   1087      1.2    matt 	return rv;
   1088      1.2    matt }
   1089      1.2    matt 
   1090      1.2    matt static int
   1091      1.2    matt rmixl_pcix_error_intr(void *arg)
   1092      1.2    matt {
   1093      1.2    matt 	rmixl_pcix_softc_t *sc = arg;
   1094      1.2    matt 	uint32_t error_status;
   1095      1.2    matt 
   1096      1.2    matt 	error_status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS);
   1097      1.2    matt 
   1098      1.2    matt #ifdef DIAGNOSTIC
   1099      1.2    matt 	printf("%s: error status %#x\n", __func__, error_status);
   1100      1.2    matt #endif
   1101      1.2    matt 
   1102      1.2    matt #if DDB
   1103      1.2    matt 	Debugger();
   1104      1.2    matt #endif
   1105      1.2    matt 
   1106      1.2    matt 	/* XXX reset and recover? */
   1107      1.2    matt 
   1108      1.2    matt 	panic("%s: error %#x\n", device_xname(sc->sc_dev), error_status);
   1109      1.2    matt }
   1110      1.2    matt 
   1111      1.2    matt /*
   1112      1.2    matt  * rmixl_physaddr_init_pcix:
   1113      1.2    matt  *	called from rmixl_physaddr_init to get region addrs & sizes
   1114      1.2    matt  *	from PCIX CFG, ECFG, IO, MEM BARs
   1115      1.2    matt  */
   1116      1.2    matt void
   1117      1.2    matt rmixl_physaddr_init_pcix(struct extent *ext)
   1118      1.2    matt {
   1119      1.2    matt 	u_long base;
   1120      1.2    matt 	u_long size;
   1121      1.2    matt 	uint32_t r;
   1122      1.2    matt 
   1123      1.2    matt 	r = RMIXL_PCIXREG_READ(RMIXLR_SBC_PCIX_CFG_BAR);
   1124      1.2    matt 	if ((r & RMIXL_PCIX_CFG_BAR_ENB) != 0) {
   1125      1.2    matt 		base = (u_long)(RMIXL_PCIX_CFG_BAR_TO_BA((uint64_t)r)
   1126      1.2    matt 			/ (1024 * 1024));
   1127      1.2    matt 		size = (u_long)RMIXL_PCIX_CFG_SIZE / (1024 * 1024);
   1128      1.2    matt 		DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__,
   1129      1.2    matt 			__LINE__, "CFG", r, base * 1024 * 1024, size));
   1130      1.2    matt 		if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0)
   1131      1.2    matt 			panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) "
   1132      1.2    matt 				"failed", __func__, ext, base, size, EX_NOWAIT);
   1133      1.2    matt 	}
   1134      1.2    matt 
   1135      1.2    matt 	r = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_MEM_BAR);
   1136      1.2    matt 	if ((r & RMIXL_PCIX_MEM_BAR_ENB) != 0) {
   1137      1.2    matt 		base = (u_long)(RMIXL_PCIX_MEM_BAR_TO_BA((uint64_t)r)
   1138      1.2    matt 			/ (1024 * 1024));
   1139      1.2    matt 		size = (u_long)(RMIXL_PCIX_MEM_BAR_TO_SIZE((uint64_t)r)
   1140      1.2    matt 			/ (1024 * 1024));
   1141      1.2    matt 		DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__,
   1142      1.2    matt 			__LINE__, "MEM", r, base * 1024 * 1024, size));
   1143      1.2    matt 		if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0)
   1144      1.2    matt 			panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) "
   1145      1.2    matt 				"failed", __func__, ext, base, size, EX_NOWAIT);
   1146      1.2    matt 	}
   1147      1.2    matt 
   1148      1.2    matt 	r = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_IO_BAR);
   1149      1.2    matt 	if ((r & RMIXL_PCIX_IO_BAR_ENB) != 0) {
   1150      1.2    matt 		base = (u_long)(RMIXL_PCIX_IO_BAR_TO_BA((uint64_t)r)
   1151      1.2    matt 			/ (1024 * 1024));
   1152      1.2    matt 		size = (u_long)(RMIXL_PCIX_IO_BAR_TO_SIZE((uint64_t)r)
   1153      1.2    matt 			/ (1024 * 1024));
   1154      1.2    matt 		DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__,
   1155      1.2    matt 			__LINE__, "IO", r, base * 1024 * 1024, size));
   1156      1.2    matt 		if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0)
   1157      1.2    matt 			panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) "
   1158      1.2    matt 				"failed", __func__, ext, base, size, EX_NOWAIT);
   1159      1.2    matt 	}
   1160      1.2    matt }
   1161      1.2    matt 
   1162      1.2    matt #ifdef DDB
   1163      1.2    matt int rmixl_pcix_intr_chk(void);
   1164      1.2    matt int
   1165      1.2    matt rmixl_pcix_intr_chk(void)
   1166      1.2    matt {
   1167      1.2    matt 	uint32_t control, status, error_status;
   1168      1.2    matt 
   1169      1.2    matt 	control = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL);
   1170      1.2    matt 	status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS);
   1171      1.2    matt 	error_status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS);
   1172      1.2    matt 
   1173      1.2    matt 	printf("%s: %#x, %#x, %#x\n", __func__, control, status, error_status);
   1174      1.2    matt 
   1175      1.2    matt 	control |= PCIX_INTR_CONTROL_DIA;
   1176      1.2    matt 	RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, control);
   1177      1.2    matt 
   1178      1.2    matt 	control = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL);
   1179      1.2    matt 	status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS);
   1180      1.2    matt 	error_status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS);
   1181      1.2    matt 
   1182      1.2    matt 	printf("%s: %#x, %#x, %#x\n", __func__, control, status, error_status);
   1183      1.2    matt 
   1184      1.2    matt 	return 0;
   1185      1.2    matt }
   1186      1.2    matt #endif
   1187