rmixl_pcix.c revision 1.1.2.1
1 /* $NetBSD: rmixl_pcix.c,v 1.1.2.1 2010/04/07 19:25:48 cliff Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * PCI configuration support for RMI XLR SoC 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: rmixl_pcix.c,v 1.1.2.1 2010/04/07 19:25:48 cliff Exp $"); 44 45 #include "opt_pci.h" 46 #include "pci.h" 47 48 #include <sys/cdefs.h> 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/device.h> 53 #include <sys/extent.h> 54 #include <sys/malloc.h> 55 56 #include <uvm/uvm_extern.h> 57 58 #include <machine/bus.h> 59 #include <machine/intr.h> 60 61 #include <mips/rmi/rmixlreg.h> 62 #include <mips/rmi/rmixlvar.h> 63 #include <mips/rmi/rmixl_intr.h> 64 #include <mips/rmi/rmixl_pcixvar.h> 65 66 #include <mips/rmi/rmixl_obiovar.h> 67 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 #include <dev/pci/pciconf.h> 71 72 #ifdef PCI_NETBSD_CONFIGURE 73 #include <mips/cache.h> 74 #endif 75 76 #include <machine/pci_machdep.h> 77 78 #ifdef PCI_DEBUG 79 int rmixl_pcix_debug = PCI_DEBUG; 80 # define DPRINTF(x) do { if (rmixl_pcix_debug) printf x ; } while (0) 81 #else 82 # define DPRINTF(x) 83 #endif 84 85 #ifndef DDB 86 # define STATIC static 87 #else 88 # define STATIC 89 #endif 90 91 92 /* 93 * XLR PCI-X Extended Configuration Registers 94 * Note: 95 * - MSI-related regs are omitted 96 * - Device mode regs are omitted 97 */ 98 #define RMIXL_PCIX_ECFG_HOST_BAR0_ADDR 0x100 /* Host BAR0 Address */ 99 #define RMIXL_PCIX_ECFG_HOST_BAR1_ADDR 0x104 /* Host BAR1 Address */ 100 #define RMIXL_PCIX_ECFG_HOST_BAR2_ADDR 0x108 /* Host BAR2 Address */ 101 #define RMIXL_PCIX_ECFG_HOST_BAR3_ADDR 0x10c /* Host BAR3 Address */ 102 #define RMIXL_PCIX_ECFG_HOST_BAR4_ADDR 0x110 /* Host BAR4 Address */ 103 #define RMIXL_PCIX_ECFG_HOST_BAR5_ADDR 0x114 /* Host BAR5 Address */ 104 #define RMIXL_PCIX_ECFG_HOST_BAR0_SIZE 0x118 /* Host BAR0 Size */ 105 #define RMIXL_PCIX_ECFG_HOST_BAR1_SIZE 0x11c /* Host BAR1 Size */ 106 #define RMIXL_PCIX_ECFG_HOST_BAR2_SIZE 0x120 /* Host BAR2 Size */ 107 #define RMIXL_PCIX_ECFG_HOST_BAR3_SIZE 0x124 /* Host BAR3 Size */ 108 #define RMIXL_PCIX_ECFG_HOST_BAR4_SIZE 0x128 /* Host BAR4 Size */ 109 #define RMIXL_PCIX_ECFG_HOST_BAR5_SIZE 0x12c /* Host BAR5 Size */ 110 #define RMIXL_PCIX_ECFG_MATCH_BIT_ADDR 0x130 /* Match Bit Address BAR */ 111 #define RMIXL_PCIX_ECFG_MATCH_BIT_SIZE 0x134 /* Match Bit Size BAR */ 112 #define RMIXL_PCIX_ECFG_XLR_CONTROL 0x138 /* XLR Control reg */ 113 #define RMIXL_PCIX_ECFG_INTR_CONTROL 0x13c /* Interrupt Control reg */ 114 #define RMIXL_PCIX_ECFG_INTR_STATUS 0x140 /* Interrupt Status reg */ 115 #define RMIXL_PCIX_ECFG_INTR_ERR_STATUS 0x144 /* Interrupt Error Status reg */ 116 #define RMIXL_PCIX_ECFG_HOST_MODE_STS 0x178 /* Host Mode Status */ 117 #define RMIXL_PCIX_ECFG_XLR_MBLE 0x17c /* XLR Match Byte Lane Enable */ 118 #define RMIXL_PCIX_ECFG_HOST_XROM_ADDR 0x180 /* Host Expansion ROM Address */ 119 #define RMIXL_PCIX_ECFG_HOST_XROM_SIZE 0x184 /* Host Expansion ROM Size */ 120 #define RMIXL_PCIX_ECFG_HOST_MODE_CTL 0x18c /* Host Mode Control */ 121 #define RMIXL_PCIX_ECFG_TXCAL_CTL 0x1a0 /* TX Calibration Preset Control */ 122 #define RMIXL_PCIX_ECFG_TXCAL_COUNT 0x1a4 /* TX Calibration Preset Count */ 123 124 /* 125 * RMIXL_PCIX_ECFG_INTR_CONTROL bit defines 126 */ 127 #define PCIX_INTR_CONTROL_RESV __BITS(31,8) 128 #define PCIX_INTR_CONTROL_MSI1_MASK __BIT(7) 129 #define PCIX_INTR_CONTROL_MSI0_MASK __BIT(6) 130 #define PCIX_INTR_CONTROL_INTD_MASK __BIT(5) 131 #define PCIX_INTR_CONTROL_INTC_MASK __BIT(4) 132 #define PCIX_INTR_CONTROL_INTB_MASK __BIT(3) 133 #define PCIX_INTR_CONTROL_INTA_MASK __BIT(2) 134 #define PCIX_INTR_CONTROL_TMSI __BIT(1) /* Trigger MSI Interrupt */ 135 #define PCIX_INTR_CONTROL_DIA __BIT(0) /* Device Interrupt through INTA Pin */ 136 #define PCIX_INTR_CONTROL_MASK_ALL \ 137 (PCIX_INTR_CONTROL_MSI1_MASK|PCIX_INTR_CONTROL_MSI0_MASK \ 138 |PCIX_INTR_CONTROL_INTD_MASK|PCIX_INTR_CONTROL_INTC_MASK \ 139 |PCIX_INTR_CONTROL_INTB_MASK|PCIX_INTR_CONTROL_INTA_MASK) 140 141 /* 142 * RMIXL_PCIX_ECFG_INTR_STATUS bit defines 143 */ 144 #define PCIX_INTR_STATUS_RESV __BITS(31,6) 145 #define PCIX_INTR_STATUS_MSI1 __BIT(5) 146 #define PCIX_INTR_STATUS_MSI0 __BIT(4) 147 #define PCIX_INTR_STATUS_INTD __BIT(3) 148 #define PCIX_INTR_STATUS_INTC __BIT(2) 149 #define PCIX_INTR_STATUS_INTB __BIT(1) 150 #define PCIX_INTR_STATUS_INTA __BIT(0) 151 152 /* 153 * RMIXL_PCIX_ECFG_INTR_ERR_STATUS bit defines 154 */ 155 #define PCIX_INTR_ERR_STATUS_RESa __BITS(31,5) 156 #define PCIX_INTR_ERR_STATUS_SERR __BIT(4) /* System Error */ 157 #define PCIX_INTR_ERR_STATUS_RESb __BIT(3) 158 #define PCIX_INTR_ERR_STATUS_TE __BIT(2) /* Target Error */ 159 #define PCIX_INTR_ERR_STATUS_IE __BIT(1) /* Initiator Error */ 160 #define PCIX_INTR_ERR_STATUS_RCE __BIT(0) /* Retry Count Expired */ 161 #define PCIX_INTR_ERR_STATUS_RESV \ 162 (PCIX_INTR_ERR_STATUS_RESa|PCIX_INTR_ERR_STATUS_RESb) 163 164 165 166 #if BYTE_ORDER == BIG_ENDIAN 167 # define RMIXL_PCIXREG_BASE RMIXL_IO_DEV_PCIX_EB 168 #else 169 # define RMIXL_PCIXREG_BASE RMIXL_IO_DEV_PCIX_EL 170 #endif 171 172 #define RMIXL_PCIXREG_VADDR(o) \ 173 (volatile uint32_t *)MIPS_PHYS_TO_KSEG1( \ 174 rmixl_configuration.rc_io_pbase \ 175 + RMIXL_PCIXREG_BASE + (o)) 176 177 #define RMIXL_PCIXREG_READ(o) (*RMIXL_PCIXREG_VADDR(o)) 178 #define RMIXL_PCIXREG_WRITE(o,v) *RMIXL_PCIXREG_VADDR(o) = (v) 179 180 /* 181 * XXX use locks 182 */ 183 #define PCI_CONF_LOCK(s) (s) = splhigh() 184 #define PCI_CONF_UNLOCK(s) splx((s)) 185 186 187 #define RMIXL_PCIX_CONCAT3(a,b,c) a ## b ## c 188 #define RMIXL_PCIX_BAR_INIT(reg, bar, size, align) { \ 189 struct extent *ext = rmixl_configuration.rc_phys_ex; \ 190 u_long region_start; \ 191 uint64_t ba; \ 192 int err; \ 193 \ 194 err = extent_alloc(ext, (size), (align), 0UL, EX_NOWAIT, \ 195 ®ion_start); \ 196 if (err != 0) \ 197 panic("%s: extent_alloc(%p, %#lx, %#lx, %#lx, %#x, %p)",\ 198 __func__, ext, size, align, 0UL, EX_NOWAIT, \ 199 ®ion_start); \ 200 ba = (uint64_t)region_start; \ 201 ba *= (1024 * 1024); \ 202 bar = RMIXL_PCIX_CONCAT3(RMIXL_PCIX_,reg,_BAR)(ba, 1); \ 203 DPRINTF(("PCIX %s BAR was not enabled by firmware\n" \ 204 "enabling %s at phys %#" PRIxBUSADDR ", size %lu MB\n", \ 205 __STRING(reg), __STRING(reg), ba, size)); \ 206 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_BRIDGE + \ 207 RMIXL_PCIX_CONCAT3(RMIXLR_SBC_PCIX_,reg,_BAR), bar); \ 208 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + \ 209 RMIXL_PCIX_CONCAT3(RMIXLR_SBC_PCIX_,reg,_BAR)); \ 210 DPRINTF(("%s: %s BAR %#x\n", __func__, __STRING(reg), bar)); \ 211 } 212 213 static int rmixl_pcix_match(device_t, cfdata_t, void *); 214 static void rmixl_pcix_attach(device_t, device_t, void *); 215 static void rmixl_pcix_init(rmixl_pcix_softc_t *); 216 static void rmixl_pcix_init_errors(rmixl_pcix_softc_t *); 217 static void rmixl_pcix_attach_hook(struct device *, struct device *, 218 struct pcibus_attach_args *); 219 static void rmixl_pcix_intcfg(rmixl_pcix_softc_t *); 220 static void rmixl_pcix_errata(rmixl_pcix_softc_t *); 221 static void rmixl_conf_interrupt(void *, int, int, int, int, int *); 222 static int rmixl_pcix_bus_maxdevs(void *, int); 223 static pcitag_t rmixl_pcix_make_tag(void *, int, int, int); 224 static void rmixl_pcix_decompose_tag(void *, pcitag_t, int *, int *, int *); 225 void rmixl_pcix_tag_print(const char *restrict, void *, pcitag_t, int, vaddr_t, u_long); 226 static int rmixl_pcix_conf_setup(rmixl_pcix_softc_t *, 227 pcitag_t, int *, bus_space_tag_t *, 228 bus_space_handle_t *); 229 static pcireg_t rmixl_pcix_conf_read(void *, pcitag_t, int); 230 static void rmixl_pcix_conf_write(void *, pcitag_t, int, pcireg_t); 231 232 static int rmixl_pcix_intr_map(struct pci_attach_args *, 233 pci_intr_handle_t *); 234 static const char * 235 rmixl_pcix_intr_string(void *, pci_intr_handle_t); 236 static const struct evcnt * 237 rmixl_pcix_intr_evcnt(void *, pci_intr_handle_t); 238 static pci_intr_handle_t 239 rmixl_pcix_make_pih(u_int, u_int); 240 static void rmixl_pcix_decompose_pih(pci_intr_handle_t, u_int *, u_int *); 241 static void rmixl_pcix_intr_disestablish(void *, void *); 242 static void *rmixl_pcix_intr_establish(void *, pci_intr_handle_t, 243 int, int (*)(void *), void *); 244 static int rmixl_pcix_intr(void *); 245 static int rmixl_pcix_error_intr(void *); 246 247 248 CFATTACH_DECL_NEW(rmixl_pcix, sizeof(rmixl_pcix_softc_t), 249 rmixl_pcix_match, rmixl_pcix_attach, NULL, NULL); 250 251 252 static int rmixl_pcix_found; 253 254 #if defined(DIAGNOSTIC) || defined(DEBUG) || defined(DDB) 255 static rmixl_pcix_softc_t *rmixl_pcix_sc; 256 #endif 257 258 259 static int 260 rmixl_pcix_match(device_t parent, cfdata_t cf, void *aux) 261 { 262 uint32_t r; 263 264 /* 265 * PCI-X interface exists on XLR chips only 266 */ 267 if (! cpu_rmixlr(mips_options.mips_cpu)) 268 return 0; 269 270 /* XXX 271 * for now there is only one PCI-X Interface on chip 272 * and only one chip in the system 273 * this could change with furture RMI XL family designs 274 * or when we have multi-chip systems. 275 */ 276 if (rmixl_pcix_found) 277 return 0; 278 279 /* read Host Mode Control register */ 280 r = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_MODE_CTL); 281 r &= __BIT(1); /* XXX HDMStat */ 282 if (r == 0) 283 return 0; /* strapped for Device Mode */ 284 285 return 1; 286 } 287 288 static void 289 rmixl_pcix_attach(device_t parent, device_t self, void *aux) 290 { 291 rmixl_pcix_softc_t *sc = device_private(self); 292 struct obio_attach_args *obio = aux; 293 struct rmixl_config *rcp = &rmixl_configuration; 294 struct pcibus_attach_args pba; 295 uint32_t bar; 296 297 rmixl_pcix_found = 1; 298 #ifdef DIAGNOSTIC 299 rmixl_pcix_sc = sc; 300 #endif 301 sc->sc_dev = self; 302 sc->sc_29bit_dmat = obio->obio_29bit_dmat; 303 sc->sc_32bit_dmat = obio->obio_32bit_dmat; 304 sc->sc_64bit_dmat = obio->obio_64bit_dmat; 305 sc->sc_tmsk = obio->obio_tmsk; 306 307 aprint_normal(" RMI XLR PCI-X Interface\n"); 308 309 rmixl_pcix_intcfg(sc); 310 311 rmixl_pcix_errata(sc); 312 313 /* 314 * check XLR Control Register 315 */ 316 uint32_t xlr_control; 317 xlr_control = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_XLR_CONTROL); 318 printf("%s: XLR_CONTROL=%#x\n", __func__, xlr_control); 319 320 /* 321 * check HBAR[0..7] 322 */ 323 uint32_t hbar_addr, hbar_size; 324 u_int addr_off = RMIXL_PCIX_ECFG_HOST_BAR0_ADDR; 325 u_int size_off = RMIXL_PCIX_ECFG_HOST_BAR0_SIZE; 326 for (int i=0; i < 7; i++) { 327 hbar_addr = RMIXL_PCIXREG_READ(addr_off); 328 hbar_size = RMIXL_PCIXREG_READ(size_off); 329 addr_off += 4; 330 size_off += 4; 331 printf("%s: HBAR[%d]=%#x @ %#x\n", __func__, i, hbar_size, hbar_addr); 332 } 333 334 /* 335 * check PCI-X interface byteswap setup 336 * ensure 'Match Byte Lane' is disabled 337 */ 338 uint32_t mble, mba, mbs; 339 mble = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_XLR_MBLE); 340 mba = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_MATCH_BIT_ADDR); 341 mbs = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_MATCH_BIT_SIZE); 342 printf("%s: MBLE=%#x, MBA=%#x, MBS=%#x\n", __func__, mble, mba, mbs); 343 if ((mble & __BIT(40)) != 0) 344 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_XLR_MBLE, 0); 345 346 /* 347 * get PCI config space base addr from SBC PCIe CFG BAR 348 * initialize it if necessary 349 */ 350 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_CFG_BAR); 351 DPRINTF(("%s: PCIX_CFG_BAR %#x\n", __func__, bar)); 352 if ((bar & RMIXL_PCIX_CFG_BAR_ENB) == 0) { 353 u_long n = RMIXL_PCIX_CFG_SIZE / (1024 * 1024); 354 RMIXL_PCIX_BAR_INIT(CFG, bar, n, n); 355 } 356 rcp->rc_pci_cfg_pbase = (bus_addr_t)RMIXL_PCIX_CFG_BAR_TO_BA(bar); 357 rcp->rc_pci_cfg_size = (bus_size_t)RMIXL_PCIX_CFG_SIZE; 358 359 /* 360 * get PCI MEM space base [addr, size] from SBC PCIe MEM BAR 361 * initialize it if necessary 362 */ 363 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_MEM_BAR); 364 DPRINTF(("%s: PCIX_MEM_BAR %#x\n", __func__, bar)); 365 if ((bar & RMIXL_PCIX_MEM_BAR_ENB) == 0) { 366 u_long n = 256; /* 256 MB */ 367 RMIXL_PCIX_BAR_INIT(MEM, bar, n, n); 368 } 369 rcp->rc_pci_mem_pbase = (bus_addr_t)RMIXL_PCIX_MEM_BAR_TO_BA(bar); 370 rcp->rc_pci_mem_size = (bus_size_t)RMIXL_PCIX_MEM_BAR_TO_SIZE(bar); 371 printf("%s: rc_pci_mem_pbase %#"PRIxBUSADDR", rc_pci_mem_size %#"PRIxBUSSIZE"\n", 372 __func__, rcp->rc_pci_mem_pbase, rcp->rc_pci_mem_size); 373 374 /* 375 * get PCI IO space base [addr, size] from SBC PCIe IO BAR 376 * initialize it if necessary 377 */ 378 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_IO_BAR); 379 DPRINTF(("%s: PCIX_IO_BAR %#x\n", __func__, bar)); 380 if ((bar & RMIXL_PCIX_IO_BAR_ENB) == 0) { 381 u_long n = 32; /* 32 MB */ 382 RMIXL_PCIX_BAR_INIT(IO, bar, n, n); 383 } 384 rcp->rc_pci_io_pbase = (bus_addr_t)RMIXL_PCIX_IO_BAR_TO_BA(bar); 385 rcp->rc_pci_io_size = (bus_size_t)RMIXL_PCIX_IO_BAR_TO_SIZE(bar); 386 387 /* 388 * initialize the PCI CFG bus space tag 389 */ 390 rmixl_pci_cfg_bus_mem_init(&rcp->rc_pci_cfg_memt, rcp); 391 sc->sc_pci_cfg_memt = &rcp->rc_pci_cfg_memt; 392 393 /* 394 * initialize the PCI MEM and IO bus space tags 395 */ 396 rmixl_pci_bus_mem_init(&rcp->rc_pci_memt, rcp); 397 rmixl_pci_bus_io_init(&rcp->rc_pci_iot, rcp); 398 399 /* 400 * initialize the extended configuration regs 401 */ 402 rmixl_pcix_init_errors(sc); 403 404 /* 405 * initialize the PCI chipset tag 406 */ 407 rmixl_pcix_init(sc); 408 409 /* 410 * attach the PCI bus 411 */ 412 memset(&pba, 0, sizeof(pba)); 413 pba.pba_memt = &rcp->rc_pci_memt; 414 pba.pba_iot = &rcp->rc_pci_iot; 415 pba.pba_dmat = sc->sc_32bit_dmat; 416 pba.pba_dmat64 = sc->sc_64bit_dmat; 417 pba.pba_pc = &sc->sc_pci_chipset; 418 pba.pba_bus = 0; 419 pba.pba_bridgetag = NULL; 420 pba.pba_intrswiz = 0; 421 pba.pba_intrtag = 0; 422 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 423 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 424 425 (void) config_found_ia(self, "pcibus", &pba, pcibusprint); 426 } 427 428 /* 429 * rmixl_pcix_intcfg - init PCI-X interrupt control 430 */ 431 static void 432 rmixl_pcix_intcfg(rmixl_pcix_softc_t *sc) 433 { 434 DPRINTF(("%s\n", __func__)); 435 436 /* mask all interrupts until they are established */ 437 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, 438 PCIX_INTR_CONTROL_MASK_ALL); 439 440 /* 441 * read-to-clear any pre-existing interrupts 442 * XXX MSI bits in STATUS are also documented as write 1 to clear in PRM 443 */ 444 (void)RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 445 (void)RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 446 447 /* initialize the dispatch handles */ 448 for (int i=0; i < RMIXL_PCIX_NINTR; i++) { 449 rmixl_pcix_intr_t *ih = &sc->sc_intr[i]; 450 LIST_INIT(&ih->dispatch); 451 ih->ih = NULL; 452 ih->intrpin = i; 453 ih->enabled = false; 454 } 455 456 sc->sc_ih = rmixl_intr_establish(16, sc->sc_tmsk, 457 IPL_VM, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH, 458 rmixl_pcix_intr, sc); 459 if (sc->sc_ih == NULL) 460 panic("%s: cannot establish irq %d", __func__, 16); 461 462 sc->sc_fatal_ih = rmixl_intr_establish(24, sc->sc_tmsk, 463 IPL_VM, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH, 464 rmixl_pcix_error_intr, sc); 465 if (sc->sc_fatal_ih == NULL) 466 panic("%s: cannot establish irq %d", __func__, 24); 467 468 sc->sc_intr_init_done = true; 469 } 470 471 static void 472 rmixl_pcix_errata(rmixl_pcix_softc_t *sc) 473 { 474 /* nothing */ 475 } 476 477 static void 478 rmixl_pcix_init(rmixl_pcix_softc_t *sc) 479 { 480 pci_chipset_tag_t pc = &sc->sc_pci_chipset; 481 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 482 struct extent *ioext, *memext; 483 #endif 484 485 pc->pc_conf_v = (void *)sc; 486 pc->pc_attach_hook = rmixl_pcix_attach_hook; 487 pc->pc_bus_maxdevs = rmixl_pcix_bus_maxdevs; 488 pc->pc_make_tag = rmixl_pcix_make_tag; 489 pc->pc_decompose_tag = rmixl_pcix_decompose_tag; 490 pc->pc_conf_read = rmixl_pcix_conf_read; 491 pc->pc_conf_write = rmixl_pcix_conf_write; 492 493 pc->pc_intr_v = (void *)sc; 494 pc->pc_intr_map = rmixl_pcix_intr_map; 495 pc->pc_intr_string = rmixl_pcix_intr_string; 496 pc->pc_intr_evcnt = rmixl_pcix_intr_evcnt; 497 pc->pc_intr_establish = rmixl_pcix_intr_establish; 498 pc->pc_intr_disestablish = rmixl_pcix_intr_disestablish; 499 pc->pc_conf_interrupt = rmixl_conf_interrupt; 500 501 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 502 /* 503 * Configure the PCI bus. 504 */ 505 struct rmixl_config *rcp = &rmixl_configuration; 506 507 aprint_normal("%s: configuring PCI bus\n", 508 device_xname(sc->sc_dev)); 509 510 ioext = extent_create("pciio", 511 rcp->rc_pci_io_pbase, 512 rcp->rc_pci_io_pbase + rcp->rc_pci_io_size - 1, 513 M_DEVBUF, NULL, 0, EX_NOWAIT); 514 515 memext = extent_create("pcimem", 516 rcp->rc_pci_mem_pbase, 517 rcp->rc_pci_mem_pbase + rcp->rc_pci_mem_size - 1, 518 M_DEVBUF, NULL, 0, EX_NOWAIT); 519 520 pci_configure_bus(pc, ioext, memext, NULL, 0, 521 mips_cache_info.mci_dcache_align); 522 523 extent_destroy(ioext); 524 extent_destroy(memext); 525 #endif 526 } 527 528 static void 529 rmixl_pcix_init_errors(rmixl_pcix_softc_t *sc) 530 { 531 /* nothing */ 532 } 533 534 void 535 rmixl_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *iline) 536 { 537 DPRINTF(("%s: %p, %d, %d, %d, %d, %p\n", 538 __func__, v, bus, dev, ipin, swiz, iline)); 539 } 540 541 void 542 rmixl_pcix_attach_hook(struct device *parent, struct device *self, 543 struct pcibus_attach_args *pba) 544 { 545 DPRINTF(("%s: pba_bus %d, pba_bridgetag %p, pc_conf_v %p\n", 546 __func__, pba->pba_bus, pba->pba_bridgetag, 547 pba->pba_pc->pc_conf_v)); 548 } 549 550 int 551 rmixl_pcix_bus_maxdevs(void *v, int busno) 552 { 553 return (32); /* XXX depends on the family of XLS SoC */ 554 } 555 556 /* 557 * XLS pci tag is a 40 bit address composed thusly: 558 * 39:25 (reserved) 559 * 24 Swap (0=little, 1=big endian) 560 * 23:16 Bus number 561 * 15:11 Device number 562 * 10:8 Function number 563 * 7:0 Register number 564 * 565 * Note: this is the "native" composition for addressing CFG space, but not for ECFG space. 566 */ 567 pcitag_t 568 rmixl_pcix_make_tag(void *v, int bus, int dev, int fun) 569 { 570 return ((bus << 16) | (dev << 11) | (fun << 8)); 571 } 572 573 void 574 rmixl_pcix_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 575 { 576 if (bp != NULL) 577 *bp = (tag >> 16) & 0xff; 578 if (dp != NULL) 579 *dp = (tag >> 11) & 0x1f; 580 if (fp != NULL) 581 *fp = (tag >> 8) & 0x7; 582 } 583 584 void 585 rmixl_pcix_tag_print(const char *restrict s, void *v, pcitag_t tag, int offset, 586 vaddr_t va, u_long r) 587 { 588 int bus, dev, fun; 589 590 rmixl_pcix_decompose_tag(v, tag, &bus, &dev, &fun); 591 printf("%s: %d/%d/%d/%d - %#" PRIxVADDR ":%#lx\n", 592 s, bus, dev, fun, offset, va, r); 593 } 594 595 static int 596 rmixl_pcix_conf_setup(rmixl_pcix_softc_t *sc, 597 pcitag_t tag, int *offp, bus_space_tag_t *bstp, 598 bus_space_handle_t *bshp) 599 { 600 struct rmixl_config *rcp = &rmixl_configuration; 601 bus_space_tag_t bst; 602 bus_space_handle_t bsh; 603 bus_size_t size; 604 pcitag_t mask; 605 bus_addr_t ba; 606 int err; 607 static bus_space_handle_t cfg_bsh; 608 static bus_addr_t cfg_oba = -1; 609 610 /* 611 * bus space depends on offset 612 */ 613 if ((*offp >= 0) && (*offp < 0x100)) { 614 mask = __BITS(15,0); 615 bst = sc->sc_pci_cfg_memt; 616 ba = rcp->rc_pci_cfg_pbase; 617 ba += (tag & ~mask); 618 *offp += (tag & mask); 619 if (ba != cfg_oba) { 620 size = (bus_size_t)(mask + 1); 621 if (cfg_oba != -1) 622 bus_space_unmap(bst, cfg_bsh, size); 623 err = bus_space_map(bst, ba, size, 0, &cfg_bsh); 624 if (err != 0) { 625 #ifdef DEBUG 626 panic("%s: bus_space_map err %d, CFG space", 627 __func__, err); /* XXX */ 628 #endif 629 return -1; 630 } 631 cfg_oba = ba; 632 } 633 bsh = cfg_bsh; 634 } else { 635 #ifdef DEBUG 636 panic("%s: offset %#x: unknown", __func__, *offp); 637 #endif 638 return -1; 639 } 640 641 *bstp = bst; 642 *bshp = bsh; 643 644 return 0; 645 } 646 647 pcireg_t 648 rmixl_pcix_conf_read(void *v, pcitag_t tag, int offset) 649 { 650 rmixl_pcix_softc_t *sc = v; 651 static bus_space_handle_t bsh; 652 bus_space_tag_t bst; 653 pcireg_t rv; 654 uint64_t cfg0; 655 u_int s; 656 657 PCI_CONF_LOCK(s); 658 659 if (rmixl_pcix_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) { 660 cfg0 = rmixl_cache_err_dis(); 661 rv = bus_space_read_4(bst, bsh, (bus_size_t)offset); 662 if (rmixl_cache_err_check() != 0) { 663 #ifdef DIAGNOSTIC 664 int bus, dev, fun; 665 666 rmixl_pcix_decompose_tag(v, tag, &bus, &dev, &fun); 667 printf("%s: %d/%d/%d, offset %#x: bad address\n", 668 __func__, bus, dev, fun, offset); 669 #endif 670 rv = (pcireg_t) -1; 671 } 672 rmixl_cache_err_restore(cfg0); 673 } else { 674 rv = -1; 675 } 676 677 PCI_CONF_UNLOCK(s); 678 return rv; 679 } 680 681 void 682 rmixl_pcix_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 683 { 684 rmixl_pcix_softc_t *sc = v; 685 static bus_space_handle_t bsh; 686 bus_space_tag_t bst; 687 uint64_t cfg0; 688 u_int s; 689 690 PCI_CONF_LOCK(s); 691 692 if (rmixl_pcix_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) { 693 cfg0 = rmixl_cache_err_dis(); 694 bus_space_write_4(bst, bsh, (bus_size_t)offset, val); 695 if (rmixl_cache_err_check() != 0) { 696 #ifdef DIAGNOSTIC 697 int bus, dev, fun; 698 699 rmixl_pcix_decompose_tag(v, tag, &bus, &dev, &fun); 700 printf("%s: %d/%d/%d, offset %#x: bad address\n", 701 __func__, bus, dev, fun, offset); 702 #endif 703 } 704 rmixl_cache_err_restore(cfg0); 705 } 706 707 PCI_CONF_UNLOCK(s); 708 } 709 710 int 711 rmixl_pcix_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *pih) 712 { 713 const u_int irq = 16; /* PCIX index in IRT */ 714 715 #ifdef DEBUG 716 DPRINTF(("%s: ps_bus %d, pa_intrswiz %#x, pa_intrtag %#lx," 717 " pa_intrpin %d, pa_intrline %d, pa_rawintrpin %d\n", 718 __func__, pa->pa_bus, pa->pa_intrswiz, pa->pa_intrtag, 719 pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 720 #endif 721 722 if (pa->pa_intrpin != PCI_INTERRUPT_PIN_NONE) 723 *pih = rmixl_pcix_make_pih(pa->pa_intrpin - 1, irq); 724 else 725 *pih = ~0; 726 727 return 0; 728 } 729 730 const char * 731 rmixl_pcix_intr_string(void *v, pci_intr_handle_t pih) 732 { 733 u_int bitno, irq; 734 735 rmixl_pcix_decompose_pih(pih, &bitno, &irq); 736 737 if (! cpu_rmixlr(mips_options.mips_cpu)) 738 panic("%s: cpu %#x not supported\n", 739 __func__, mips_options.mips_cpu_id); 740 741 return rmixl_intr_string(irq); 742 } 743 744 const struct evcnt * 745 rmixl_pcix_intr_evcnt(void *v, pci_intr_handle_t pih) 746 { 747 return NULL; 748 } 749 750 static pci_intr_handle_t 751 rmixl_pcix_make_pih(u_int bitno, u_int irq) 752 { 753 pci_intr_handle_t pih; 754 755 KASSERT(bitno < 64); 756 KASSERT(irq < 32); 757 758 pih = (irq << 6); 759 pih |= bitno; 760 761 return pih; 762 } 763 764 static void 765 rmixl_pcix_decompose_pih(pci_intr_handle_t pih, u_int *bitno, u_int *irq) 766 { 767 *bitno = (u_int)(pih & 0x3f); 768 *irq = (u_int)(pih >> 6); 769 770 KASSERT(*bitno < 64); 771 KASSERT(*irq < 31); 772 } 773 774 static void 775 rmixl_pcix_intr_disestablish(void *v, void *ih) 776 { 777 rmixl_pcix_softc_t *sc = v; 778 rmixl_pcix_dispatch_t *dip = ih; 779 rmixl_pcix_intr_t *pip = &sc->sc_intr[dip->bitno];; 780 781 DPRINTF(("%s: pin=%d irq=%d\n", 782 __func__, dip->bitno + 1, dip->irq)); 783 KASSERT(dip->bitno < RMIXL_PCIX_NINTR); 784 785 LIST_REMOVE(dip, next); 786 evcnt_detach(&dip->count); 787 free(dip, M_DEVBUF); 788 789 if (LIST_EMPTY(&pip->dispatch)) { 790 uint32_t bit = 1 << (dip->bitno + 2); 791 uint32_t r; 792 793 r = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 794 r |= bit; /* set mask */ 795 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, r); 796 DPRINTF(("%s: disabled pin %d\n", __func__, dip->bitno + 1)); 797 798 pip->enabled = false; 799 } 800 } 801 802 static void * 803 rmixl_pcix_intr_establish(void *v, pci_intr_handle_t pih, int ipl, 804 int (*func)(void *), void *arg) 805 { 806 rmixl_pcix_softc_t *sc = v; 807 u_int bitno, irq; 808 rmixl_pcix_intr_t *pip; 809 rmixl_pcix_dispatch_t *dip; 810 int s; 811 812 if (pih == ~0) { 813 DPRINTF(("%s: bad pih=%#lx, implies PCI_INTERRUPT_PIN_NONE\n", 814 __func__, pih)); 815 return NULL; 816 } 817 818 rmixl_pcix_decompose_pih(pih, &bitno, &irq); 819 DPRINTF(("%s: pin=%d irq=%d\n", __func__, bitno + 1, irq)); 820 821 KASSERT(bitno < RMIXL_PCIX_NINTR); 822 pip = &sc->sc_intr[bitno]; 823 824 s = splhigh(); 825 826 /* 827 * all PCI-X device intrs get same ipl and sc 828 */ 829 KASSERT(sc == rmixl_pcix_sc); 830 KASSERT(ipl == IPL_VM); 831 832 /* 833 * allocate and initialize a dispatch handle 834 */ 835 dip = malloc(sizeof(*dip), M_DEVBUF, M_NOWAIT); 836 if (dip == NULL) { 837 printf("%s: cannot malloc dispatch handle\n", __func__); 838 goto out; 839 } 840 841 dip->bitno = bitno; 842 dip->irq = irq; 843 dip->func = func; 844 dip->arg = arg; 845 snprintf(dip->count_name, sizeof(dip->count_name), 846 "pin %d", bitno + 1); 847 evcnt_attach_dynamic(&dip->count, EVCNT_TYPE_INTR, NULL, 848 "rmixl_pcix", dip->count_name); 849 850 if (pip->enabled == false) { 851 uint32_t bit = 1 << (bitno + 2); 852 uint32_t r; 853 854 r = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 855 r &= ~bit; /* clear mask */ 856 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, r); 857 858 pip->sc = sc; 859 pip->ipl = ipl; 860 pip->enabled = true; 861 DPRINTF(("%s: enabled pin %d\n", __func__, bitno + 1)); 862 } 863 864 LIST_INSERT_HEAD(&pip->dispatch, dip, next); 865 866 out: 867 splx(s); 868 return dip; 869 } 870 871 static int 872 rmixl_pcix_intr(void *arg) 873 { 874 rmixl_pcix_softc_t *sc = arg; 875 int rv = 0; 876 877 uint32_t status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 878 DPRINTF(("%s: %#x\n", __func__, status)); 879 880 if (status != 0) { 881 for (int i=0; i < RMIXL_PCIX_NINTR; i++) { 882 uint32_t bit = 1 << i; 883 if ((status & bit) != 0) { 884 rmixl_pcix_intr_t *pip = &sc->sc_intr[i]; 885 rmixl_pcix_dispatch_t *dip; 886 LIST_FOREACH(dip, &pip->dispatch, next) { 887 (void)(*dip->func)(dip->arg); 888 dip->count.ev_count++; 889 rv = 1; 890 } 891 } 892 } 893 } 894 return rv; 895 } 896 897 static int 898 rmixl_pcix_error_intr(void *arg) 899 { 900 rmixl_pcix_softc_t *sc = arg; 901 uint32_t error_status; 902 903 error_status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 904 905 #ifdef DIAGNOSTIC 906 printf("%s: error status %#x\n", __func__, error_status); 907 #endif 908 909 #if DDB 910 Debugger(); 911 #endif 912 913 /* XXX reset and recover? */ 914 915 panic("%s: error %#x\n", device_xname(sc->sc_dev), error_status); 916 } 917 918 /* 919 * rmixl_physaddr_init_pcix: 920 * called from rmixl_physaddr_init to get region addrs & sizes 921 * from PCIX CFG, ECFG, IO, MEM BARs 922 */ 923 void 924 rmixl_physaddr_init_pcix(struct extent *ext) 925 { 926 u_long base; 927 u_long size; 928 uint32_t r; 929 930 r = RMIXL_PCIXREG_READ(RMIXLR_SBC_PCIX_CFG_BAR); 931 if ((r & RMIXL_PCIX_CFG_BAR_ENB) != 0) { 932 base = (u_long)(RMIXL_PCIX_CFG_BAR_TO_BA((uint64_t)r) 933 / (1024 * 1024)); 934 size = (u_long)RMIXL_PCIX_CFG_SIZE / (1024 * 1024); 935 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 936 __LINE__, "CFG", r, base * 1024 * 1024, size)); 937 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 938 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 939 "failed", __func__, ext, base, size, EX_NOWAIT); 940 } 941 942 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_MEM_BAR); 943 if ((r & RMIXL_PCIX_MEM_BAR_ENB) != 0) { 944 base = (u_long)(RMIXL_PCIX_MEM_BAR_TO_BA((uint64_t)r) 945 / (1024 * 1024)); 946 size = (u_long)(RMIXL_PCIX_MEM_BAR_TO_SIZE((uint64_t)r) 947 / (1024 * 1024)); 948 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 949 __LINE__, "MEM", r, base * 1024 * 1024, size)); 950 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 951 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 952 "failed", __func__, ext, base, size, EX_NOWAIT); 953 } 954 955 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_IO_BAR); 956 if ((r & RMIXL_PCIX_IO_BAR_ENB) != 0) { 957 base = (u_long)(RMIXL_PCIX_IO_BAR_TO_BA((uint64_t)r) 958 / (1024 * 1024)); 959 size = (u_long)(RMIXL_PCIX_IO_BAR_TO_SIZE((uint64_t)r) 960 / (1024 * 1024)); 961 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 962 __LINE__, "IO", r, base * 1024 * 1024, size)); 963 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 964 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 965 "failed", __func__, ext, base, size, EX_NOWAIT); 966 } 967 } 968 969 #ifdef DDB 970 int rmixl_pcix_intr_chk(void); 971 int 972 rmixl_pcix_intr_chk(void) 973 { 974 uint32_t control, status, error_status; 975 976 control = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 977 status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 978 error_status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 979 980 printf("%s: %#x, %#x, %#x\n", __func__, control, status, error_status); 981 982 control |= PCIX_INTR_CONTROL_DIA; 983 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, control); 984 985 control = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 986 status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 987 error_status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 988 989 printf("%s: %#x, %#x, %#x\n", __func__, control, status, error_status); 990 991 return 0; 992 } 993 #endif 994
Indexes created Sat Oct 18 23:09:54 GMT 2025