rmixl_pcix.c revision 1.1.2.13
1 /* rmixl_pcix.c,v 1.1.2.12 2012/01/04 16:17:54 matt Exp */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * PCI configuration support for RMI XLR SoC 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "rmixl_pcix.c,v 1.1.2.12 2012/01/04 16:17:54 matt Exp"); 44 45 #include "opt_pci.h" 46 #include "pci.h" 47 48 #include <sys/cdefs.h> 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/device.h> 53 #include <sys/extent.h> 54 #include <sys/malloc.h> 55 #include <sys/kernel.h> /* for 'hz' */ 56 #include <sys/cpu.h> 57 58 #include <uvm/uvm_extern.h> 59 60 #include <machine/bus.h> 61 #include <machine/intr.h> 62 63 #include <mips/rmi/rmixlreg.h> 64 #include <mips/rmi/rmixlvar.h> 65 #include <mips/rmi/rmixl_intr.h> 66 #include <mips/rmi/rmixl_pcixvar.h> 67 68 #include <mips/rmi/rmixl_obiovar.h> 69 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcidevs.h> 72 #include <dev/pci/pciconf.h> 73 74 #ifdef PCI_NETBSD_CONFIGURE 75 #include <mips/cache.h> 76 #endif 77 78 #include <machine/pci_machdep.h> 79 80 #ifdef PCI_DEBUG 81 int rmixl_pcix_debug = PCI_DEBUG; 82 # define DPRINTF(x) do { if (rmixl_pcix_debug) printf x ; } while (0) 83 #else 84 # define DPRINTF(x) 85 #endif 86 87 #ifndef DDB 88 # define STATIC static 89 #else 90 # define STATIC 91 #endif 92 93 94 /* 95 * XLR PCI-X Extended Configuration Registers 96 * Note: 97 * - MSI-related regs are omitted 98 * - Device mode regs are omitted 99 */ 100 #define RMIXL_PCIX_ECFG_HOST_BAR0_ADDR 0x100 /* Host BAR0 Address */ 101 #define RMIXL_PCIX_ECFG_HOST_BAR1_ADDR 0x104 /* Host BAR1 Address */ 102 #define RMIXL_PCIX_ECFG_HOST_BAR2_ADDR 0x108 /* Host BAR2 Address */ 103 #define RMIXL_PCIX_ECFG_HOST_BAR3_ADDR 0x10c /* Host BAR3 Address */ 104 #define RMIXL_PCIX_ECFG_HOST_BAR4_ADDR 0x110 /* Host BAR4 Address */ 105 #define RMIXL_PCIX_ECFG_HOST_BAR5_ADDR 0x114 /* Host BAR5 Address */ 106 #define RMIXL_PCIX_ECFG_HOST_BAR0_SIZE 0x118 /* Host BAR0 Size */ 107 #define RMIXL_PCIX_ECFG_HOST_BAR1_SIZE 0x11c /* Host BAR1 Size */ 108 #define RMIXL_PCIX_ECFG_HOST_BAR2_SIZE 0x120 /* Host BAR2 Size */ 109 #define RMIXL_PCIX_ECFG_HOST_BAR3_SIZE 0x124 /* Host BAR3 Size */ 110 #define RMIXL_PCIX_ECFG_HOST_BAR4_SIZE 0x128 /* Host BAR4 Size */ 111 #define RMIXL_PCIX_ECFG_HOST_BAR5_SIZE 0x12c /* Host BAR5 Size */ 112 #define RMIXL_PCIX_ECFG_MATCH_BIT_ADDR 0x130 /* Match Bit Address BAR */ 113 #define RMIXL_PCIX_ECFG_MATCH_BIT_SIZE 0x134 /* Match Bit Size BAR */ 114 #define RMIXL_PCIX_ECFG_XLR_CONTROL 0x138 /* XLR Control reg */ 115 #define RMIXL_PCIX_ECFG_INTR_CONTROL 0x13c /* Interrupt Control reg */ 116 #define RMIXL_PCIX_ECFG_INTR_STATUS 0x140 /* Interrupt Status reg */ 117 #define RMIXL_PCIX_ECFG_INTR_ERR_STATUS 0x144 /* Interrupt Error Status reg */ 118 #define RMIXL_PCIX_ECFG_HOST_MODE_STS 0x178 /* Host Mode Status */ 119 #define RMIXL_PCIX_ECFG_XLR_MBLE 0x17c /* XLR Match Byte Lane Enable */ 120 #define RMIXL_PCIX_ECFG_HOST_XROM_ADDR 0x180 /* Host Expansion ROM Address */ 121 #define RMIXL_PCIX_ECFG_HOST_XROM_SIZE 0x184 /* Host Expansion ROM Size */ 122 #define RMIXL_PCIX_ECFG_HOST_MODE_CTL 0x18c /* Host Mode Control */ 123 #define RMIXL_PCIX_ECFG_TXCAL_CTL 0x1a0 /* TX Calibration Preset Control */ 124 #define RMIXL_PCIX_ECFG_TXCAL_COUNT 0x1a4 /* TX Calibration Preset Count */ 125 126 /* 127 * RMIXL_PCIX_ECFG_INTR_CONTROL bit defines 128 */ 129 #define PCIX_INTR_CONTROL_RESV __BITS(31,8) 130 #define PCIX_INTR_CONTROL_MSI1_MASK __BIT(7) 131 #define PCIX_INTR_CONTROL_MSI0_MASK __BIT(6) 132 #define PCIX_INTR_CONTROL_INTD_MASK __BIT(5) 133 #define PCIX_INTR_CONTROL_INTC_MASK __BIT(4) 134 #define PCIX_INTR_CONTROL_INTB_MASK __BIT(3) 135 #define PCIX_INTR_CONTROL_INTA_MASK __BIT(2) 136 #define PCIX_INTR_CONTROL_TMSI __BIT(1) /* Trigger MSI Interrupt */ 137 #define PCIX_INTR_CONTROL_DIA __BIT(0) /* Device Interrupt through INTA Pin */ 138 #define PCIX_INTR_CONTROL_MASK_ALL \ 139 (PCIX_INTR_CONTROL_MSI1_MASK|PCIX_INTR_CONTROL_MSI0_MASK \ 140 |PCIX_INTR_CONTROL_INTD_MASK|PCIX_INTR_CONTROL_INTC_MASK \ 141 |PCIX_INTR_CONTROL_INTB_MASK|PCIX_INTR_CONTROL_INTA_MASK) 142 143 /* 144 * RMIXL_PCIX_ECFG_INTR_STATUS bit defines 145 */ 146 #define PCIX_INTR_STATUS_RESV __BITS(31,6) 147 #define PCIX_INTR_STATUS_MSI1 __BIT(5) 148 #define PCIX_INTR_STATUS_MSI0 __BIT(4) 149 #define PCIX_INTR_STATUS_INTD __BIT(3) 150 #define PCIX_INTR_STATUS_INTC __BIT(2) 151 #define PCIX_INTR_STATUS_INTB __BIT(1) 152 #define PCIX_INTR_STATUS_INTA __BIT(0) 153 154 /* 155 * RMIXL_PCIX_ECFG_INTR_ERR_STATUS bit defines 156 */ 157 #define PCIX_INTR_ERR_STATUS_RESa __BITS(31,5) 158 #define PCIX_INTR_ERR_STATUS_SERR __BIT(4) /* System Error */ 159 #define PCIX_INTR_ERR_STATUS_RESb __BIT(3) 160 #define PCIX_INTR_ERR_STATUS_TE __BIT(2) /* Target Error */ 161 #define PCIX_INTR_ERR_STATUS_IE __BIT(1) /* Initiator Error */ 162 #define PCIX_INTR_ERR_STATUS_RCE __BIT(0) /* Retry Count Expired */ 163 #define PCIX_INTR_ERR_STATUS_RESV \ 164 (PCIX_INTR_ERR_STATUS_RESa|PCIX_INTR_ERR_STATUS_RESb) 165 166 /* 167 * RMIXL_PCIX_ECFG_HOST_MODE_CTL bit defines 168 */ 169 #define PCIX_HOST_MODE_CTL_HDMSTAT __BIT(1) /* Host/Dev Mode status 170 * read-only 171 * 1 = host 172 * 0 = device 173 */ 174 #define PCIX_HOST_MODE_CTL_HOSTSWRST __BIT(0) /* Host soft reset 175 * set to 1 to reset 176 * set to 0 to un-reset 177 */ 178 179 180 #if BYTE_ORDER == BIG_ENDIAN 181 # define RMIXL_PCIXREG_BASE RMIXL_IO_DEV_PCIX_EB 182 #else 183 # define RMIXL_PCIXREG_BASE RMIXL_IO_DEV_PCIX_EL 184 #endif 185 186 #define RMIXL_PCIXREG_VADDR(o) \ 187 (volatile uint32_t *)MIPS_PHYS_TO_KSEG1( \ 188 rmixl_configuration.rc_io.r_pbase \ 189 + RMIXL_PCIXREG_BASE + (o)) 190 191 #define RMIXL_PCIXREG_READ(o) (*RMIXL_PCIXREG_VADDR(o)) 192 #define RMIXL_PCIXREG_WRITE(o,v) *RMIXL_PCIXREG_VADDR(o) = (v) 193 194 #define RMIXL_PCIX_BAR_INIT(rp, reg, bar, size, align) { \ 195 struct extent *ext = rmixl_configuration.rc_phys_ex; \ 196 u_long region_start; \ 197 int err; \ 198 \ 199 err = extent_alloc(ext, (size), (align), 0UL, EX_NOWAIT, \ 200 ®ion_start); \ 201 if (err != 0) \ 202 panic("%s: extent_alloc(%p, %#lx, %#lx, %#lx, %#x, %p)",\ 203 __func__, ext, size, align, 0UL, EX_NOWAIT, \ 204 ®ion_start); \ 205 const uint64_t ba = (uint64_t)region_start << 20; \ 206 bar = RMIXL_PCIX_##reg##_BAR(ba, 1); \ 207 DPRINTF(("PCIX %s BAR was not enabled by firmware\n" \ 208 "enabling %s at phys %#" PRIxBUSADDR ", size %lu MB\n", \ 209 __STRING(reg), __STRING(reg), ba, size)); \ 210 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_BRIDGE \ 211 + RMIXLR_SBC_PCIX_##reg##_BAR, bar); \ 212 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE \ 213 + RMIXLR_SBC_PCIX_##reg##_BAR); \ 214 DPRINTF(("%s: %s BAR %#x\n", __func__, __STRING(reg), bar)); \ 215 (rp)->r_pbase = ba; \ 216 (rp)->r_size = (size) << 20; \ 217 } 218 219 220 #define RMIXL_PCIX_EVCNT(sc, intrpin, cpu) \ 221 &(sc)->sc_evcnts[(intrpin) * (ncpu) + (cpu)] 222 223 224 static int rmixl_pcix_match(device_t, cfdata_t, void *); 225 static void rmixl_pcix_attach(device_t, device_t, void *); 226 static void rmixl_pcix_init(rmixl_pcix_softc_t *); 227 static void rmixl_pcix_init_errors(rmixl_pcix_softc_t *); 228 static void rmixl_pcix_attach_hook(struct device *, struct device *, 229 struct pcibus_attach_args *); 230 static void rmixl_pcix_intcfg(rmixl_pcix_softc_t *); 231 static void rmixl_pcix_errata(rmixl_pcix_softc_t *); 232 static void rmixl_conf_interrupt(void *, int, int, int, int, int *); 233 static int rmixl_pcix_bus_maxdevs(void *, int); 234 static pcitag_t rmixl_pcix_make_tag(void *, int, int, int); 235 static void rmixl_pcix_decompose_tag(void *, pcitag_t, int *, int *, int *); 236 void rmixl_pcix_tag_print(const char *restrict, void *, pcitag_t, int, vaddr_t, u_long); 237 static pcireg_t rmixl_pcix_conf_read(void *, pcitag_t, int); 238 static void rmixl_pcix_conf_write(void *, pcitag_t, int, pcireg_t); 239 #ifdef __PCI_DEV_FUNCORDER 240 static bool rmixl_pcix_dev_funcorder(void *, int, int, int, char *); 241 #endif 242 243 static int rmixl_pcix_intr_map(struct pci_attach_args *, 244 pci_intr_handle_t *); 245 static const char * 246 rmixl_pcix_intr_string(void *, pci_intr_handle_t); 247 static const struct evcnt * 248 rmixl_pcix_intr_evcnt(void *, pci_intr_handle_t); 249 static pci_intr_handle_t 250 rmixl_pcix_make_pih(u_int, u_int); 251 static void rmixl_pcix_decompose_pih(pci_intr_handle_t, u_int *, u_int *); 252 static void rmixl_pcix_intr_disestablish(void *, void *); 253 static void *rmixl_pcix_intr_establish(void *, pci_intr_handle_t, 254 int, int (*)(void *), void *); 255 static rmixl_pcix_intr_t * 256 rmixl_pcix_pip_add_1(rmixl_pcix_softc_t *, int, int); 257 static void rmixl_pcix_pip_free_callout(rmixl_pcix_intr_t *); 258 static void rmixl_pcix_pip_free(void *); 259 static int rmixl_pcix_intr(void *); 260 static int rmixl_pcix_error_intr(void *); 261 262 263 CFATTACH_DECL_NEW(rmixl_pcix, sizeof(rmixl_pcix_softc_t), 264 rmixl_pcix_match, rmixl_pcix_attach, NULL, NULL); 265 266 267 static int rmixl_pcix_found; 268 269 270 static int 271 rmixl_pcix_match(device_t parent, cfdata_t cf, void *aux) 272 { 273 uint32_t r; 274 275 /* 276 * PCI-X interface exists on XLR chips only 277 */ 278 if (! cpu_rmixlr(mips_options.mips_cpu)) 279 return 0; 280 281 /* XXX 282 * for now there is only one PCI-X Interface on chip 283 * and only one chip in the system 284 * this could change with furture RMI XL family designs 285 * or when we have multi-chip systems. 286 */ 287 if (rmixl_pcix_found) 288 return 0; 289 290 /* read Host Mode Control register */ 291 r = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_MODE_CTL); 292 r &= PCIX_HOST_MODE_CTL_HDMSTAT; 293 if (r == 0) 294 return 0; /* strapped for Device Mode */ 295 296 return 1; 297 } 298 299 static void 300 rmixl_pcix_attach(device_t parent, device_t self, void *aux) 301 { 302 rmixl_pcix_softc_t *sc = device_private(self); 303 struct obio_attach_args *obio = aux; 304 struct rmixl_config *rcp = &rmixl_configuration; 305 struct pcibus_attach_args pba; 306 uint32_t bar; 307 308 rmixl_pcix_found = 1; 309 sc->sc_dev = self; 310 sc->sc_dmat29 = obio->obio_dmat29; 311 sc->sc_dmat32 = obio->obio_dmat32; 312 sc->sc_dmat64 = obio->obio_dmat64; 313 sc->sc_pc = &rcp->rc_pci_chipset; 314 315 aprint_normal(": RMI XLR PCI-X Interface\n"); 316 317 mutex_init(&sc->sc_mutex, MUTEX_DEFAULT, IPL_HIGH); 318 319 rmixl_pcix_intcfg(sc); 320 321 rmixl_pcix_errata(sc); 322 323 /* 324 * check XLR Control Register 325 */ 326 DPRINTF(("%s: XLR_CONTROL=%#x\n", __func__, 327 RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_XLR_CONTROL))); 328 329 /* 330 * HBAR[0] if a 32 bit BAR, or 331 * HBAR[0,1] if a 64 bit BAR pair 332 * must cover all RAM 333 */ 334 extern u_quad_t avail_cluster_maxaddr; 335 uint64_t hbar_addr; 336 uint64_t hbar_size; 337 uint32_t hbar_size_lo, hbar_size_hi; 338 uint32_t hbar_addr_lo, hbar_addr_hi; 339 340 hbar_addr_lo = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR0_ADDR); 341 hbar_addr_hi = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR1_ADDR); 342 hbar_size_lo = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR0_SIZE); 343 hbar_size_hi = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR1_SIZE); 344 345 hbar_addr = (u_quad_t)(hbar_addr_lo & PCI_MAPREG_MEM_ADDR_MASK); 346 hbar_size = hbar_size_lo; 347 if ((hbar_size_lo & PCI_MAPREG_MEM_TYPE_64BIT) != 0) { 348 hbar_addr |= (uint64_t)hbar_addr_hi << 32; 349 hbar_size |= (uint64_t)hbar_size_hi << 32; 350 } 351 if ((hbar_addr != 0) || (hbar_size < avail_cluster_maxaddr)) { 352 int error; 353 354 aprint_error_dev(self, "HostBAR0 addr %#x, size %#x\n", 355 hbar_addr_lo, hbar_size_lo); 356 if ((hbar_size_lo & PCI_MAPREG_MEM_TYPE_64BIT) != 0) 357 aprint_error_dev(self, "HostBAR1 addr %#x, size %#x\n", 358 hbar_addr_hi, hbar_size_hi); 359 aprint_error_dev(self, "WARNING: firmware PCI-X setup error: " 360 "RAM %#"PRIx64"..%#"PRIx64" not accessible by Host BAR, " 361 "enabling DMA bounce buffers\n", 362 hbar_size, avail_cluster_maxaddr-1); 363 364 /* 365 * force use of bouce buffers for inaccessible RAM addrs 366 */ 367 if (hbar_size < ((uint64_t)1 << 32)) { 368 error = bus_dmatag_subregion(sc->sc_dmat32, 369 0, (bus_addr_t)hbar_size, &sc->sc_dmat32, 370 BUS_DMA_NOWAIT); 371 if (error) 372 panic("%s: failed to subregion 32-bit dma tag:" 373 " error %d", __func__, error); 374 sc->sc_dmat64 = NULL; 375 } else { 376 error = bus_dmatag_subregion(sc->sc_dmat64, 377 0, (bus_addr_t)hbar_size, &sc->sc_dmat64, 378 BUS_DMA_NOWAIT); 379 if (error) 380 panic("%s: failed to subregion 64-bit dma tag:" 381 " error %d", __func__, error); 382 } 383 } 384 385 /* 386 * check PCI-X interface byteswap setup 387 * ensure 'Match Byte Lane' is disabled 388 */ 389 uint32_t mble, mba, mbs; 390 mble = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_XLR_MBLE); 391 mba = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_MATCH_BIT_ADDR); 392 mbs = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_MATCH_BIT_SIZE); 393 DPRINTF(("%s: MBLE=%#x, MBA=%#x, MBS=%#x\n", __func__, mble, mba, mbs)); 394 if ((mble & __BIT(40)) != 0) 395 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_XLR_MBLE, 0); 396 397 /* 398 * get PCI config space base addr from SBC PCIe CFG BAR 399 * initialize it if necessary 400 */ 401 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_CFG_BAR); 402 DPRINTF(("%s: PCIX_CFG_BAR %#x\n", __func__, bar)); 403 if ((bar & RMIXL_PCIX_CFG_BAR_ENB) == 0) { 404 u_long n = RMIXL_PCIX_CFG_SIZE / (1024 * 1024); 405 RMIXL_PCIX_BAR_INIT(&rcp->rc_pci_cfg, CFG, bar, n, n); 406 } 407 408 /* 409 * get PCI MEM space base [addr, size] from SBC PCIe MEM BAR 410 * initialize it if necessary 411 */ 412 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_MEM_BAR); 413 DPRINTF(("%s: PCIX_MEM_BAR %#x\n", __func__, bar)); 414 if ((bar & RMIXL_PCIX_MEM_BAR_ENB) == 0) { 415 u_long n = 256; /* 256 MB */ 416 RMIXL_PCIX_BAR_INIT(&rcp->rc_pci_mem, MEM, bar, n, n); 417 } 418 419 /* 420 * get PCI IO space base [addr, size] from SBC PCIe IO BAR 421 * initialize it if necessary 422 */ 423 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_IO_BAR); 424 DPRINTF(("%s: PCIX_IO_BAR %#x\n", __func__, bar)); 425 if ((bar & RMIXL_PCIX_IO_BAR_ENB) == 0) { 426 u_long n = 32; /* 32 MB */ 427 RMIXL_PCIX_BAR_INIT(&rcp->rc_pci_io, IO, bar, n, n); 428 } 429 430 /* 431 * initialize the PCI CFG bus space tag 432 */ 433 sc->sc_pci_cfg_memt = &rcp->rc_pci_cfg_memt; 434 rmixl_pci_cfg_el_bus_mem_init(sc->sc_pci_cfg_memt, rcp); 435 if (bus_space_map(sc->sc_pci_cfg_memt, 0, rcp->rc_pci_cfg.r_size / 2, 436 0, &sc->sc_pci_cfg_memh)) 437 panic("%s: failed to map pci CFG space!\n", __func__); 438 439 /* 440 * initialize the PCI MEM and IO bus space tags 441 */ 442 rmixl_pci_el_bus_mem_init(&rcp->rc_pci_memt, rcp); 443 rmixl_pci_bus_io_init(&rcp->rc_pci_iot, rcp); 444 445 /* 446 * initialize the extended configuration regs 447 */ 448 rmixl_pcix_init_errors(sc); 449 450 /* 451 * initialize the PCI chipset tag 452 */ 453 rmixl_pcix_init(sc); 454 455 /* 456 * attach the PCI bus 457 */ 458 memset(&pba, 0, sizeof(pba)); 459 pba.pba_memt = &rcp->rc_pci_memt; 460 pba.pba_iot = &rcp->rc_pci_iot; 461 pba.pba_dmat = sc->sc_dmat32; 462 pba.pba_dmat64 = sc->sc_dmat64; 463 pba.pba_pc = sc->sc_pc; 464 pba.pba_bus = 0; 465 pba.pba_bridgetag = NULL; 466 pba.pba_intrswiz = 0; 467 pba.pba_intrtag = 0; 468 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 469 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 470 471 (void) config_found_ia(self, "pcibus", &pba, pcibusprint); 472 } 473 474 /* 475 * rmixl_pcix_intcfg - init PCI-X interrupt control 476 */ 477 static void 478 rmixl_pcix_intcfg(rmixl_pcix_softc_t *sc) 479 { 480 size_t size; 481 rmixl_pcix_evcnt_t *ev; 482 483 DPRINTF(("%s\n", __func__)); 484 485 /* mask all interrupts until they are established */ 486 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, 487 PCIX_INTR_CONTROL_MASK_ALL); 488 489 /* 490 * read-to-clear any pre-existing interrupts 491 * XXX MSI bits in STATUS are also documented as write 1 to clear in PRM 492 */ 493 (void)RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 494 (void)RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 495 496 /* initialize the (non-error interrupt) dispatch handles */ 497 sc->sc_intr = NULL; 498 499 /* 500 * allocate per-cpu, per-pin interrupt event counters 501 */ 502 size = ncpu * PCI_INTERRUPT_PIN_MAX * sizeof(rmixl_pcix_evcnt_t); 503 ev = malloc(size, M_DEVBUF, M_NOWAIT); 504 if (ev == NULL) 505 panic("%s: cannot malloc evcnts\n", __func__); 506 sc->sc_evcnts = ev; 507 for (int pin=PCI_INTERRUPT_PIN_A; pin <= PCI_INTERRUPT_PIN_MAX; pin++) { 508 for (int cpu=0; cpu < ncpu; cpu++) { 509 ev = RMIXL_PCIX_EVCNT(sc, pin - 1, cpu); 510 snprintf(ev->name, sizeof(ev->name), 511 "cpu%d, pin %d", cpu, pin); 512 evcnt_attach_dynamic(&ev->evcnt, EVCNT_TYPE_INTR, 513 NULL, "rmixl_pcix", ev->name); 514 } 515 } 516 517 /* 518 * establish PCIX error interrupt handler 519 */ 520 sc->sc_fatal_ih = rmixl_intr_establish(24, IPL_VM, IST_LEVEL_HIGH, 521 rmixl_pcix_error_intr, sc, false); 522 if (sc->sc_fatal_ih == NULL) 523 panic("%s: cannot establish irq %d", __func__, 24); 524 } 525 526 static void 527 rmixl_pcix_errata(rmixl_pcix_softc_t *sc) 528 { 529 /* nothing */ 530 } 531 532 static void 533 rmixl_pcix_init(rmixl_pcix_softc_t *sc) 534 { 535 pci_chipset_tag_t pc = sc->sc_pc; 536 537 pc->pc_conf_v = (void *)sc; 538 pc->pc_attach_hook = rmixl_pcix_attach_hook; 539 pc->pc_bus_maxdevs = rmixl_pcix_bus_maxdevs; 540 pc->pc_make_tag = rmixl_pcix_make_tag; 541 pc->pc_decompose_tag = rmixl_pcix_decompose_tag; 542 pc->pc_conf_read = rmixl_pcix_conf_read; 543 pc->pc_conf_write = rmixl_pcix_conf_write; 544 #ifdef __PCI_DEV_FUNCORDER 545 pc->pc_dev_funcorder = rmixl_pcix_dev_funcorder; 546 #endif 547 548 pc->pc_intr_v = (void *)sc; 549 pc->pc_intr_map = rmixl_pcix_intr_map; 550 pc->pc_intr_string = rmixl_pcix_intr_string; 551 pc->pc_intr_evcnt = rmixl_pcix_intr_evcnt; 552 pc->pc_intr_establish = rmixl_pcix_intr_establish; 553 pc->pc_intr_disestablish = rmixl_pcix_intr_disestablish; 554 pc->pc_conf_interrupt = rmixl_conf_interrupt; 555 556 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 557 /* 558 * Configure the PCI bus. 559 */ 560 struct rmixl_config *rcp = &rmixl_configuration; 561 struct extent *ioext, *memext; 562 563 aprint_normal_dev(sc->sc_dev, "configuring PCI bus\n"); 564 565 ioext = extent_create("pciio", 566 rcp->rc_pci_io.r_pbase, 567 rcp->rc_pci_io.r_pbase + rcp->rc_pci_io.r_size - 1, 568 M_DEVBUF, NULL, 0, EX_NOWAIT); 569 570 memext = extent_create("pcimem", 571 rcp->rc_pci_mem.r_pbase, 572 rcp->rc_pci_mem.r_pbase + rcp->rc_pci_mem.r_size - 1, 573 M_DEVBUF, NULL, 0, EX_NOWAIT); 574 575 pci_configure_bus(pc, ioext, memext, NULL, 0, 576 mips_cache_info.mci_dcache_align); 577 578 extent_destroy(ioext); 579 extent_destroy(memext); 580 #endif 581 } 582 583 static void 584 rmixl_pcix_init_errors(rmixl_pcix_softc_t *sc) 585 { 586 /* nothing */ 587 } 588 589 void 590 rmixl_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *iline) 591 { 592 DPRINTF(("%s: %p, %d, %d, %d, %d, %p\n", 593 __func__, v, bus, dev, ipin, swiz, iline)); 594 } 595 596 void 597 rmixl_pcix_attach_hook(struct device *parent, struct device *self, 598 struct pcibus_attach_args *pba) 599 { 600 DPRINTF(("%s: pba_bus %d, pba_bridgetag %p, pc_conf_v %p\n", 601 __func__, pba->pba_bus, pba->pba_bridgetag, 602 pba->pba_pc->pc_conf_v)); 603 } 604 605 int 606 rmixl_pcix_bus_maxdevs(void *v, int busno) 607 { 608 return (32); /* XXX depends on the family of XLS SoC */ 609 } 610 611 /* 612 * XLS pci tag is a 40 bit address composed thusly: 613 * 39:25 (reserved) 614 * 24 Swap (0=little, 1=big endian) 615 * 23:16 Bus number 616 * 15:11 Device number 617 * 10:8 Function number 618 * 7:0 Register number 619 * 620 * Note: this is the "native" composition for addressing CFG space, but not for ECFG space. 621 */ 622 pcitag_t 623 rmixl_pcix_make_tag(void *v, int bus, int dev, int fun) 624 { 625 return ((bus << 16) | (dev << 11) | (fun << 8)); 626 } 627 628 void 629 rmixl_pcix_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 630 { 631 if (bp != NULL) 632 *bp = (tag >> 16) & 0xff; 633 if (dp != NULL) 634 *dp = (tag >> 11) & 0x1f; 635 if (fp != NULL) 636 *fp = (tag >> 8) & 0x7; 637 } 638 639 void 640 rmixl_pcix_tag_print(const char *restrict s, void *v, pcitag_t tag, int offset, 641 vaddr_t va, u_long r) 642 { 643 int bus, dev, fun; 644 645 rmixl_pcix_decompose_tag(v, tag, &bus, &dev, &fun); 646 printf("%s: %d/%d/%d/%d - %#" PRIxVADDR ":%#lx\n", 647 s, bus, dev, fun, offset, va, r); 648 } 649 650 pcireg_t 651 rmixl_pcix_conf_read(void *v, pcitag_t tag, int offset) 652 { 653 rmixl_pcix_softc_t *sc = v; 654 bus_space_handle_t bsh = sc->sc_pci_cfg_memh; 655 bus_space_tag_t bst = sc->sc_pci_cfg_memt; 656 pcireg_t rv; 657 658 if (offset >= 0x100) 659 return -1; 660 661 if (__predict_true(!cold)) 662 mutex_enter(&sc->sc_mutex); 663 664 uint64_t cfg0 = rmixl_cache_err_dis(); 665 rv = bus_space_read_4(bst, bsh, (bus_size_t)tag + offset); 666 if (rmixl_cache_err_check() != 0) { 667 #ifdef DIAGNOSTIC 668 int bus, dev, fun; 669 670 rmixl_pcix_decompose_tag(v, tag, &bus, &dev, &fun); 671 printf("%s: %d/%d/%d, offset %#x: bad address\n", 672 __func__, bus, dev, fun, offset); 673 #endif 674 rv = (pcireg_t) -1; 675 } 676 rmixl_cache_err_restore(cfg0); 677 678 if (__predict_true(!cold)) 679 mutex_exit(&sc->sc_mutex); 680 681 return rv; 682 } 683 684 void 685 rmixl_pcix_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 686 { 687 rmixl_pcix_softc_t *sc = v; 688 bus_space_handle_t bsh = sc->sc_pci_cfg_memh; 689 bus_space_tag_t bst = sc->sc_pci_cfg_memt; 690 691 if (offset >= 0x100) 692 return; 693 694 if (__predict_true(!cold)) 695 mutex_enter(&sc->sc_mutex); 696 697 uint64_t cfg0 = rmixl_cache_err_dis(); 698 bus_space_write_4(bst, bsh, (bus_size_t)offset, val); 699 if (rmixl_cache_err_check() != 0) { 700 #ifdef DIAGNOSTIC 701 int bus, dev, fun; 702 703 rmixl_pcix_decompose_tag(v, tag, &bus, &dev, &fun); 704 printf("%s: %d/%d/%d, offset %#x: bad address\n", 705 __func__, bus, dev, fun, offset); 706 #endif 707 } 708 rmixl_cache_err_restore(cfg0); 709 710 if (__predict_true(!cold)) 711 mutex_exit(&sc->sc_mutex); 712 } 713 714 #ifdef __PCI_DEV_FUNCORDER 715 bool 716 rmixl_pcix_dev_funcorder(void *v, int bus, int device, int nfunctions, 717 char *funcs) 718 { 719 return false; 720 } 721 #endif 722 723 int 724 rmixl_pcix_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *pih) 725 { 726 const u_int irq = 16; /* PCIX index in IRT */ 727 728 #ifdef DEBUG 729 DPRINTF(("%s: ps_bus %d, pa_intrswiz %#x, pa_intrtag %#lx," 730 " pa_intrpin %d, pa_intrline %d, pa_rawintrpin %d\n", 731 __func__, pa->pa_bus, pa->pa_intrswiz, pa->pa_intrtag, 732 pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 733 #endif 734 735 if (pa->pa_intrpin != PCI_INTERRUPT_PIN_NONE) 736 *pih = rmixl_pcix_make_pih(pa->pa_intrpin - 1, irq); 737 else 738 *pih = ~0; 739 740 return 0; 741 } 742 743 const char * 744 rmixl_pcix_intr_string(void *v, pci_intr_handle_t pih) 745 { 746 u_int bitno, irq; 747 748 rmixl_pcix_decompose_pih(pih, &bitno, &irq); 749 750 if (! cpu_rmixlr(mips_options.mips_cpu)) 751 panic("%s: cpu %#x not supported\n", 752 __func__, mips_options.mips_cpu_id); 753 754 return rmixl_irt_string(irq); 755 } 756 757 const struct evcnt * 758 rmixl_pcix_intr_evcnt(void *v, pci_intr_handle_t pih) 759 { 760 return NULL; 761 } 762 763 static pci_intr_handle_t 764 rmixl_pcix_make_pih(u_int bitno, u_int irq) 765 { 766 pci_intr_handle_t pih; 767 768 KASSERT(bitno < 64); 769 KASSERT(irq < 32); 770 771 pih = (irq << 6); 772 pih |= bitno; 773 774 return pih; 775 } 776 777 static void 778 rmixl_pcix_decompose_pih(pci_intr_handle_t pih, u_int *bitno, u_int *irq) 779 { 780 *bitno = (u_int)(pih & 0x3f); 781 *irq = (u_int)(pih >> 6); 782 783 KASSERT(*bitno < 64); 784 KASSERT(*irq < 31); 785 } 786 787 static void 788 rmixl_pcix_intr_disestablish(void *v, void *ih) 789 { 790 rmixl_pcix_softc_t *sc = v; 791 rmixl_pcix_dispatch_t *dip = ih; 792 rmixl_pcix_intr_t *pip = sc->sc_intr; 793 bool busy; 794 795 DPRINTF(("%s: pin=%d irq=%d\n", 796 __func__, dip->bitno + 1, dip->irq)); 797 KASSERT(dip->bitno < RMIXL_PCIX_NINTR); 798 799 mutex_enter(&sc->sc_mutex); 800 801 dip->func = NULL; /* prevent further dispatch */ 802 803 /* 804 * if no other dispatch handle is using this interrupt, 805 * we can disable it 806 */ 807 busy = false; 808 for (int i=0; i < pip->dispatch_count; i++) { 809 rmixl_pcix_dispatch_t *d = &pip->dispatch_data[i]; 810 if (d == dip) 811 continue; 812 if (d->bitno == dip->bitno) { 813 busy = true; 814 break; 815 } 816 } 817 if (! busy) { 818 uint32_t bit = 1 << (dip->bitno + 2); 819 uint32_t r; 820 821 r = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 822 r |= bit; /* set mask */ 823 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, r); 824 DPRINTF(("%s: disabled pin %d\n", __func__, dip->bitno + 1)); 825 826 pip->intenb &= ~(1 << dip->bitno); 827 828 if ((r & PCIX_INTR_CONTROL_MASK_ALL) == 0) { 829 /* tear down interrupt for this pcix */ 830 rmixl_intr_disestablish(pip->ih); 831 832 /* commit NULL interrupt set */ 833 sc->sc_intr = NULL; 834 835 /* schedule delayed free of the old interrupt set */ 836 rmixl_pcix_pip_free_callout(pip); 837 } 838 } 839 840 mutex_exit(&sc->sc_mutex); 841 } 842 843 static void * 844 rmixl_pcix_intr_establish(void *v, pci_intr_handle_t pih, int ipl, 845 int (*func)(void *), void *arg) 846 { 847 rmixl_pcix_softc_t *sc = v; 848 u_int bitno, irq; 849 rmixl_pcix_intr_t *pip; 850 rmixl_pcix_dispatch_t *dip = NULL; 851 852 if (pih == ~0) { 853 DPRINTF(("%s: bad pih=%#lx, implies PCI_INTERRUPT_PIN_NONE\n", 854 __func__, pih)); 855 return NULL; 856 } 857 858 rmixl_pcix_decompose_pih(pih, &bitno, &irq); 859 DPRINTF(("%s: pin=%d irq=%d\n", __func__, bitno + 1, irq)); 860 861 KASSERT(bitno < RMIXL_PCIX_NINTR); 862 863 /* 864 * all PCI-X device intrs get same ipl 865 */ 866 KASSERT(ipl == IPL_VM); 867 868 mutex_enter(&sc->sc_mutex); 869 870 pip = rmixl_pcix_pip_add_1(sc, irq, ipl); 871 if (pip == NULL) 872 return NULL; 873 874 /* 875 * initializae our new interrupt, the last element in dispatch_data[] 876 */ 877 dip = &pip->dispatch_data[pip->dispatch_count - 1]; 878 dip->bitno = bitno; 879 dip->irq = irq; 880 dip->func = func; 881 dip->arg = arg; 882 dip->counts = RMIXL_PCIX_EVCNT(sc, bitno, 0); 883 #if NEVER 884 snprintf(dip->count_name, sizeof(dip->count_name), 885 "pin %d", bitno + 1); 886 evcnt_attach_dynamic(&dip->count, EVCNT_TYPE_INTR, NULL, 887 "rmixl_pcix", dip->count_name); 888 #endif 889 890 /* commit the new interrupt set */ 891 sc->sc_intr = pip; 892 893 /* enable this interrupt in the PCIX controller, if necessary */ 894 if ((pip->intenb & (1 << bitno)) == 0) { 895 uint32_t bit = 1 << (bitno + 2); 896 uint32_t r; 897 898 r = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 899 r &= ~bit; /* clear mask */ 900 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, r); 901 902 pip->sc = sc; 903 pip->ipl = ipl; 904 pip->intenb |= 1 << bitno; 905 DPRINTF(("%s: enabled pin %d\n", __func__, bitno + 1)); 906 } 907 908 mutex_exit(&sc->sc_mutex); 909 return dip; 910 } 911 912 rmixl_pcix_intr_t * 913 rmixl_pcix_pip_add_1(rmixl_pcix_softc_t *sc, int irq, int ipl) 914 { 915 rmixl_pcix_intr_t *pip_old = sc->sc_intr; 916 rmixl_pcix_intr_t *pip_new; 917 u_int dispatch_count; 918 size_t size; 919 920 dispatch_count = 1; 921 size = sizeof(rmixl_pcix_intr_t); 922 if (pip_old != NULL) { 923 /* 924 * count only those dispatch elements still in use 925 * unused ones will be pruned during copy 926 * i.e. we are "lazy" there is no rmixl_pcix_pip_sub_1 927 */ 928 for (int i=0; i < pip_old->dispatch_count; i++) { 929 if (pip_old->dispatch_data[i].func != NULL) { 930 dispatch_count++; 931 size += sizeof(rmixl_pcix_intr_t); 932 } 933 } 934 } 935 936 /* 937 * allocate and initialize softc intr struct 938 * with one or more dispatch handles 939 */ 940 pip_new = malloc(size, M_DEVBUF, M_NOWAIT|M_ZERO); 941 if (pip_new == NULL) { 942 #ifdef DIAGNOSTIC 943 printf("%s: cannot malloc\n", __func__); 944 #endif 945 return NULL; 946 } 947 948 if (pip_old == NULL) { 949 /* initialize the interrupt struct */ 950 pip_new->sc = sc; 951 pip_new->ipl = ipl; 952 pip_new->ih = rmixl_intr_establish(irq, ipl, IST_LEVEL_HIGH, 953 rmixl_pcix_intr, pip_new, false); 954 if (pip_new->ih == NULL) 955 panic("%s: cannot establish irq %d", __func__, irq); 956 } else { 957 /* 958 * all intrs on a softc get same ipl and sc 959 * first intr established sets the standard 960 */ 961 KASSERT(sc == pip_old->sc); 962 if (sc != pip_old->sc) { 963 printf("%s: sc %p mismatch\n", __func__, sc); 964 free(pip_new, M_DEVBUF); 965 return NULL; 966 } 967 KASSERT (ipl == pip_old->ipl); 968 if (ipl != pip_old->ipl) { 969 printf("%s: ipl %d mismatch\n", __func__, ipl); 970 free(pip_new, M_DEVBUF); 971 return NULL; 972 } 973 /* 974 * copy pip_old to pip_new, skipping unused dispatch elemets 975 */ 976 memcpy(pip_new, pip_old, sizeof(rmixl_pcix_intr_t)); 977 for (int j=0, i=0; i < pip_old->dispatch_count; i++) { 978 if (pip_old->dispatch_data[i].func != NULL) { 979 memcpy(&pip_new->dispatch_data[j], 980 &pip_old->dispatch_data[i], 981 sizeof(rmixl_pcix_dispatch_t)); 982 j++; 983 } 984 } 985 986 /* 987 * schedule delayed free of old interrupt set 988 */ 989 rmixl_pcix_pip_free_callout(pip_old); 990 } 991 pip_new->dispatch_count = dispatch_count; 992 993 return pip_new; 994 } 995 996 /* 997 * delay free of the old interrupt set 998 * to allow anyone still using it to do so safely 999 * XXX 2 seconds should be plenty? 1000 */ 1001 static void 1002 rmixl_pcix_pip_free_callout(rmixl_pcix_intr_t *pip) 1003 { 1004 callout_init(&pip->callout, 0); 1005 callout_reset(&pip->callout, 2 * hz, rmixl_pcix_pip_free, pip); 1006 } 1007 1008 static void 1009 rmixl_pcix_pip_free(void *arg) 1010 { 1011 rmixl_pcix_intr_t *pip = arg; 1012 1013 callout_destroy(&pip->callout); 1014 free(pip, M_DEVBUF); 1015 } 1016 1017 static int 1018 rmixl_pcix_intr(void *arg) 1019 { 1020 rmixl_pcix_intr_t *pip = arg; 1021 int rv = 0; 1022 1023 uint32_t status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 1024 DPRINTF(("%s: %#x\n", __func__, status)); 1025 1026 if (status != 0) { 1027 for (int i=0; i < pip->dispatch_count; i++) { 1028 rmixl_pcix_dispatch_t *dip = &pip->dispatch_data[i]; 1029 uint32_t bit = 1 << dip->bitno; 1030 int (*func)(void *) = dip->func; 1031 if ((func != NULL) && (status & bit) != 0) { 1032 (void)(*func)(dip->arg); 1033 dip->counts[cpu_index(curcpu())].evcnt.ev_count++; 1034 rv = 1; 1035 } 1036 } 1037 } 1038 return rv; 1039 } 1040 1041 static int 1042 rmixl_pcix_error_intr(void *arg) 1043 { 1044 rmixl_pcix_softc_t *sc = arg; 1045 uint32_t error_status; 1046 1047 error_status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 1048 1049 #ifdef DIAGNOSTIC 1050 printf("%s: error status %#x\n", __func__, error_status); 1051 #endif 1052 1053 #if DDB 1054 Debugger(); 1055 #endif 1056 1057 /* XXX reset and recover? */ 1058 1059 panic("%s: error %#x\n", device_xname(sc->sc_dev), error_status); 1060 } 1061 1062 /* 1063 * rmixl_physaddr_init_pcix: 1064 * called from rmixl_physaddr_init to get region addrs & sizes 1065 * from PCIX CFG, IO, MEM BARs 1066 */ 1067 void 1068 rmixl_physaddr_init_pcix(struct extent *ext) 1069 { 1070 struct rmixl_config * const rcp = &rmixl_configuration; 1071 uint32_t r; 1072 1073 r = RMIXL_PCIXREG_READ(RMIXLR_SBC_PCIX_CFG_BAR); 1074 if ((r & RMIXL_PCIX_CFG_BAR_ENB) != 0) { 1075 rmixl_physaddr_add(ext, "pcicfg", &rcp->rc_pci_cfg, 1076 (bus_addr_t)RMIXL_PCIX_CFG_BAR_TO_BA((uint64_t)r), 1077 (bus_size_t)RMIXL_PCIX_CFG_SIZE); 1078 } 1079 1080 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_MEM_BAR); 1081 if ((r & RMIXL_PCIE_MEM_BAR_ENB) != 0) { 1082 rmixl_physaddr_add(ext, "pcimem", &rcp->rc_pci_mem, 1083 (bus_addr_t)RMIXL_PCIX_MEM_BAR_TO_BA((uint64_t)r), 1084 (bus_size_t)RMIXL_PCIX_MEM_BAR_TO_SIZE((uint64_t)r)); 1085 } 1086 1087 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_IO_BAR); 1088 if ((r & RMIXL_PCIE_IO_BAR_ENB) != 0) { 1089 rmixl_physaddr_add(ext, "pciio", &rcp->rc_pci_io, 1090 (bus_addr_t)RMIXL_PCIX_IO_BAR_TO_BA((uint64_t)r), 1091 (bus_size_t)RMIXL_PCIX_IO_BAR_TO_SIZE((uint64_t)r)); 1092 } 1093 } 1094 1095 #ifdef DDB 1096 int rmixl_pcix_intr_chk(void); 1097 int 1098 rmixl_pcix_intr_chk(void) 1099 { 1100 uint32_t control, status, error_status; 1101 1102 control = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 1103 status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 1104 error_status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 1105 1106 printf("%s: %#x, %#x, %#x\n", __func__, control, status, error_status); 1107 1108 control |= PCIX_INTR_CONTROL_DIA; 1109 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, control); 1110 1111 control = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 1112 status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 1113 error_status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 1114 1115 printf("%s: %#x, %#x, %#x\n", __func__, control, status, error_status); 1116 1117 return 0; 1118 } 1119 #endif 1120
Indexes created Sat Oct 18 17:09:52 GMT 2025