rmixl_pcix.c revision 1.1.2.5
1 /* $NetBSD: rmixl_pcix.c,v 1.1.2.5 2010/04/17 07:34:08 cliff Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * PCI configuration support for RMI XLR SoC 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: rmixl_pcix.c,v 1.1.2.5 2010/04/17 07:34:08 cliff Exp $"); 44 45 #include "opt_pci.h" 46 #include "pci.h" 47 48 #include <sys/cdefs.h> 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/device.h> 53 #include <sys/extent.h> 54 #include <sys/malloc.h> 55 56 #include <uvm/uvm_extern.h> 57 58 #include <machine/bus.h> 59 #include <machine/intr.h> 60 61 #include <mips/rmi/rmixlreg.h> 62 #include <mips/rmi/rmixlvar.h> 63 #include <mips/rmi/rmixl_intr.h> 64 #include <mips/rmi/rmixl_pcixvar.h> 65 66 #include <mips/rmi/rmixl_obiovar.h> 67 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 #include <dev/pci/pciconf.h> 71 72 #ifdef PCI_NETBSD_CONFIGURE 73 #include <mips/cache.h> 74 #endif 75 76 #include <machine/pci_machdep.h> 77 78 #ifdef PCI_DEBUG 79 int rmixl_pcix_debug = PCI_DEBUG; 80 # define DPRINTF(x) do { if (rmixl_pcix_debug) printf x ; } while (0) 81 #else 82 # define DPRINTF(x) 83 #endif 84 85 #ifndef DDB 86 # define STATIC static 87 #else 88 # define STATIC 89 #endif 90 91 92 /* 93 * XLR PCI-X Extended Configuration Registers 94 * Note: 95 * - MSI-related regs are omitted 96 * - Device mode regs are omitted 97 */ 98 #define RMIXL_PCIX_ECFG_HOST_BAR0_ADDR 0x100 /* Host BAR0 Address */ 99 #define RMIXL_PCIX_ECFG_HOST_BAR1_ADDR 0x104 /* Host BAR1 Address */ 100 #define RMIXL_PCIX_ECFG_HOST_BAR2_ADDR 0x108 /* Host BAR2 Address */ 101 #define RMIXL_PCIX_ECFG_HOST_BAR3_ADDR 0x10c /* Host BAR3 Address */ 102 #define RMIXL_PCIX_ECFG_HOST_BAR4_ADDR 0x110 /* Host BAR4 Address */ 103 #define RMIXL_PCIX_ECFG_HOST_BAR5_ADDR 0x114 /* Host BAR5 Address */ 104 #define RMIXL_PCIX_ECFG_HOST_BAR0_SIZE 0x118 /* Host BAR0 Size */ 105 #define RMIXL_PCIX_ECFG_HOST_BAR1_SIZE 0x11c /* Host BAR1 Size */ 106 #define RMIXL_PCIX_ECFG_HOST_BAR2_SIZE 0x120 /* Host BAR2 Size */ 107 #define RMIXL_PCIX_ECFG_HOST_BAR3_SIZE 0x124 /* Host BAR3 Size */ 108 #define RMIXL_PCIX_ECFG_HOST_BAR4_SIZE 0x128 /* Host BAR4 Size */ 109 #define RMIXL_PCIX_ECFG_HOST_BAR5_SIZE 0x12c /* Host BAR5 Size */ 110 #define RMIXL_PCIX_ECFG_MATCH_BIT_ADDR 0x130 /* Match Bit Address BAR */ 111 #define RMIXL_PCIX_ECFG_MATCH_BIT_SIZE 0x134 /* Match Bit Size BAR */ 112 #define RMIXL_PCIX_ECFG_XLR_CONTROL 0x138 /* XLR Control reg */ 113 #define RMIXL_PCIX_ECFG_INTR_CONTROL 0x13c /* Interrupt Control reg */ 114 #define RMIXL_PCIX_ECFG_INTR_STATUS 0x140 /* Interrupt Status reg */ 115 #define RMIXL_PCIX_ECFG_INTR_ERR_STATUS 0x144 /* Interrupt Error Status reg */ 116 #define RMIXL_PCIX_ECFG_HOST_MODE_STS 0x178 /* Host Mode Status */ 117 #define RMIXL_PCIX_ECFG_XLR_MBLE 0x17c /* XLR Match Byte Lane Enable */ 118 #define RMIXL_PCIX_ECFG_HOST_XROM_ADDR 0x180 /* Host Expansion ROM Address */ 119 #define RMIXL_PCIX_ECFG_HOST_XROM_SIZE 0x184 /* Host Expansion ROM Size */ 120 #define RMIXL_PCIX_ECFG_HOST_MODE_CTL 0x18c /* Host Mode Control */ 121 #define RMIXL_PCIX_ECFG_TXCAL_CTL 0x1a0 /* TX Calibration Preset Control */ 122 #define RMIXL_PCIX_ECFG_TXCAL_COUNT 0x1a4 /* TX Calibration Preset Count */ 123 124 /* 125 * RMIXL_PCIX_ECFG_INTR_CONTROL bit defines 126 */ 127 #define PCIX_INTR_CONTROL_RESV __BITS(31,8) 128 #define PCIX_INTR_CONTROL_MSI1_MASK __BIT(7) 129 #define PCIX_INTR_CONTROL_MSI0_MASK __BIT(6) 130 #define PCIX_INTR_CONTROL_INTD_MASK __BIT(5) 131 #define PCIX_INTR_CONTROL_INTC_MASK __BIT(4) 132 #define PCIX_INTR_CONTROL_INTB_MASK __BIT(3) 133 #define PCIX_INTR_CONTROL_INTA_MASK __BIT(2) 134 #define PCIX_INTR_CONTROL_TMSI __BIT(1) /* Trigger MSI Interrupt */ 135 #define PCIX_INTR_CONTROL_DIA __BIT(0) /* Device Interrupt through INTA Pin */ 136 #define PCIX_INTR_CONTROL_MASK_ALL \ 137 (PCIX_INTR_CONTROL_MSI1_MASK|PCIX_INTR_CONTROL_MSI0_MASK \ 138 |PCIX_INTR_CONTROL_INTD_MASK|PCIX_INTR_CONTROL_INTC_MASK \ 139 |PCIX_INTR_CONTROL_INTB_MASK|PCIX_INTR_CONTROL_INTA_MASK) 140 141 /* 142 * RMIXL_PCIX_ECFG_INTR_STATUS bit defines 143 */ 144 #define PCIX_INTR_STATUS_RESV __BITS(31,6) 145 #define PCIX_INTR_STATUS_MSI1 __BIT(5) 146 #define PCIX_INTR_STATUS_MSI0 __BIT(4) 147 #define PCIX_INTR_STATUS_INTD __BIT(3) 148 #define PCIX_INTR_STATUS_INTC __BIT(2) 149 #define PCIX_INTR_STATUS_INTB __BIT(1) 150 #define PCIX_INTR_STATUS_INTA __BIT(0) 151 152 /* 153 * RMIXL_PCIX_ECFG_INTR_ERR_STATUS bit defines 154 */ 155 #define PCIX_INTR_ERR_STATUS_RESa __BITS(31,5) 156 #define PCIX_INTR_ERR_STATUS_SERR __BIT(4) /* System Error */ 157 #define PCIX_INTR_ERR_STATUS_RESb __BIT(3) 158 #define PCIX_INTR_ERR_STATUS_TE __BIT(2) /* Target Error */ 159 #define PCIX_INTR_ERR_STATUS_IE __BIT(1) /* Initiator Error */ 160 #define PCIX_INTR_ERR_STATUS_RCE __BIT(0) /* Retry Count Expired */ 161 #define PCIX_INTR_ERR_STATUS_RESV \ 162 (PCIX_INTR_ERR_STATUS_RESa|PCIX_INTR_ERR_STATUS_RESb) 163 164 /* 165 * RMIXL_PCIX_ECFG_HOST_MODE_CTL bit defines 166 */ 167 #define PCIX_HOST_MODE_CTL_HDMSTAT __BIT(1) /* Host/Dev Mode status 168 * read-only 169 * 1 = host 170 * 0 = device 171 */ 172 #define PCIX_HOST_MODE_CTL_HOSTSWRST __BIT(0) /* Host soft reset 173 * set to 1 to reset 174 * set to 0 to un-reset 175 */ 176 177 178 #if BYTE_ORDER == BIG_ENDIAN 179 # define RMIXL_PCIXREG_BASE RMIXL_IO_DEV_PCIX_EB 180 #else 181 # define RMIXL_PCIXREG_BASE RMIXL_IO_DEV_PCIX_EL 182 #endif 183 184 #define RMIXL_PCIXREG_VADDR(o) \ 185 (volatile uint32_t *)MIPS_PHYS_TO_KSEG1( \ 186 rmixl_configuration.rc_io_pbase \ 187 + RMIXL_PCIXREG_BASE + (o)) 188 189 #define RMIXL_PCIXREG_READ(o) (*RMIXL_PCIXREG_VADDR(o)) 190 #define RMIXL_PCIXREG_WRITE(o,v) *RMIXL_PCIXREG_VADDR(o) = (v) 191 192 /* 193 * XXX use locks 194 */ 195 #define PCI_CONF_LOCK(s) (s) = splhigh() 196 #define PCI_CONF_UNLOCK(s) splx((s)) 197 198 199 #define RMIXL_PCIX_CONCAT3(a,b,c) a ## b ## c 200 #define RMIXL_PCIX_BAR_INIT(reg, bar, size, align) { \ 201 struct extent *ext = rmixl_configuration.rc_phys_ex; \ 202 u_long region_start; \ 203 uint64_t ba; \ 204 int err; \ 205 \ 206 err = extent_alloc(ext, (size), (align), 0UL, EX_NOWAIT, \ 207 ®ion_start); \ 208 if (err != 0) \ 209 panic("%s: extent_alloc(%p, %#lx, %#lx, %#lx, %#x, %p)",\ 210 __func__, ext, size, align, 0UL, EX_NOWAIT, \ 211 ®ion_start); \ 212 ba = (uint64_t)region_start; \ 213 ba *= (1024 * 1024); \ 214 bar = RMIXL_PCIX_CONCAT3(RMIXL_PCIX_,reg,_BAR)(ba, 1); \ 215 DPRINTF(("PCIX %s BAR was not enabled by firmware\n" \ 216 "enabling %s at phys %#" PRIxBUSADDR ", size %lu MB\n", \ 217 __STRING(reg), __STRING(reg), ba, size)); \ 218 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_BRIDGE + \ 219 RMIXL_PCIX_CONCAT3(RMIXLR_SBC_PCIX_,reg,_BAR), bar); \ 220 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + \ 221 RMIXL_PCIX_CONCAT3(RMIXLR_SBC_PCIX_,reg,_BAR)); \ 222 DPRINTF(("%s: %s BAR %#x\n", __func__, __STRING(reg), bar)); \ 223 } 224 225 static int rmixl_pcix_match(device_t, cfdata_t, void *); 226 static void rmixl_pcix_attach(device_t, device_t, void *); 227 static void rmixl_pcix_init(rmixl_pcix_softc_t *); 228 static void rmixl_pcix_init_errors(rmixl_pcix_softc_t *); 229 static void rmixl_pcix_attach_hook(struct device *, struct device *, 230 struct pcibus_attach_args *); 231 static void rmixl_pcix_intcfg(rmixl_pcix_softc_t *); 232 static void rmixl_pcix_errata(rmixl_pcix_softc_t *); 233 static void rmixl_conf_interrupt(void *, int, int, int, int, int *); 234 static int rmixl_pcix_bus_maxdevs(void *, int); 235 static pcitag_t rmixl_pcix_make_tag(void *, int, int, int); 236 static void rmixl_pcix_decompose_tag(void *, pcitag_t, int *, int *, int *); 237 void rmixl_pcix_tag_print(const char *restrict, void *, pcitag_t, int, vaddr_t, u_long); 238 static int rmixl_pcix_conf_setup(rmixl_pcix_softc_t *, 239 pcitag_t, int *, bus_space_tag_t *, 240 bus_space_handle_t *); 241 static pcireg_t rmixl_pcix_conf_read(void *, pcitag_t, int); 242 static void rmixl_pcix_conf_write(void *, pcitag_t, int, pcireg_t); 243 244 static int rmixl_pcix_intr_map(struct pci_attach_args *, 245 pci_intr_handle_t *); 246 static const char * 247 rmixl_pcix_intr_string(void *, pci_intr_handle_t); 248 static const struct evcnt * 249 rmixl_pcix_intr_evcnt(void *, pci_intr_handle_t); 250 static pci_intr_handle_t 251 rmixl_pcix_make_pih(u_int, u_int); 252 static void rmixl_pcix_decompose_pih(pci_intr_handle_t, u_int *, u_int *); 253 static void rmixl_pcix_intr_disestablish(void *, void *); 254 static void *rmixl_pcix_intr_establish(void *, pci_intr_handle_t, 255 int, int (*)(void *), void *); 256 static int rmixl_pcix_intr(void *); 257 static int rmixl_pcix_error_intr(void *); 258 259 260 CFATTACH_DECL_NEW(rmixl_pcix, sizeof(rmixl_pcix_softc_t), 261 rmixl_pcix_match, rmixl_pcix_attach, NULL, NULL); 262 263 264 static int rmixl_pcix_found; 265 266 #if defined(DIAGNOSTIC) || defined(DEBUG) || defined(DDB) 267 static rmixl_pcix_softc_t *rmixl_pcix_sc; 268 #endif 269 270 271 static int 272 rmixl_pcix_match(device_t parent, cfdata_t cf, void *aux) 273 { 274 uint32_t r; 275 276 /* 277 * PCI-X interface exists on XLR chips only 278 */ 279 if (! cpu_rmixlr(mips_options.mips_cpu)) 280 return 0; 281 282 /* XXX 283 * for now there is only one PCI-X Interface on chip 284 * and only one chip in the system 285 * this could change with furture RMI XL family designs 286 * or when we have multi-chip systems. 287 */ 288 if (rmixl_pcix_found) 289 return 0; 290 291 /* read Host Mode Control register */ 292 r = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_MODE_CTL); 293 r &= PCIX_HOST_MODE_CTL_HDMSTAT; 294 if (r == 0) 295 return 0; /* strapped for Device Mode */ 296 297 return 1; 298 } 299 300 static void 301 rmixl_pcix_attach(device_t parent, device_t self, void *aux) 302 { 303 rmixl_pcix_softc_t *sc = device_private(self); 304 struct obio_attach_args *obio = aux; 305 struct rmixl_config *rcp = &rmixl_configuration; 306 struct pcibus_attach_args pba; 307 uint32_t bar; 308 309 rmixl_pcix_found = 1; 310 #ifdef DIAGNOSTIC 311 rmixl_pcix_sc = sc; 312 #endif 313 sc->sc_dev = self; 314 sc->sc_29bit_dmat = obio->obio_29bit_dmat; 315 sc->sc_32bit_dmat = obio->obio_32bit_dmat; 316 sc->sc_64bit_dmat = obio->obio_64bit_dmat; 317 sc->sc_tmsk = obio->obio_tmsk; 318 319 aprint_normal(": RMI XLR PCI-X Interface\n"); 320 321 rmixl_pcix_intcfg(sc); 322 323 rmixl_pcix_errata(sc); 324 325 /* 326 * check XLR Control Register 327 */ 328 DPRINTF(("%s: XLR_CONTROL=%#x\n", __func__, 329 RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_XLR_CONTROL))); 330 331 /* 332 * HBAR[0] if a 32 bit BAR, or 333 * HBAR[0,1] if a 64 bit BAR pair 334 * must cover all RAM 335 */ 336 extern u_quad_t mem_cluster_maxaddr; 337 uint64_t hbar_addr; 338 uint64_t hbar_size; 339 uint32_t hbar_size_lo, hbar_size_hi; 340 uint32_t hbar_addr_lo, hbar_addr_hi; 341 342 hbar_addr_lo = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR0_ADDR); 343 hbar_addr_hi = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR1_ADDR); 344 hbar_size_lo = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR0_SIZE); 345 hbar_size_hi = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR1_SIZE); 346 347 hbar_addr = (u_quad_t)(hbar_addr_lo & PCI_MAPREG_MEM_ADDR_MASK); 348 hbar_size = hbar_size_lo; 349 if ((hbar_size_lo & PCI_MAPREG_MEM_TYPE_64BIT) != 0) { 350 hbar_addr |= (uint64_t)hbar_addr_hi << 32; 351 hbar_size |= (uint64_t)hbar_size_hi << 32; 352 } 353 if ((hbar_addr != 0) || (hbar_size < mem_cluster_maxaddr)) { 354 int error; 355 356 aprint_error_dev(self, "HostBAR0 addr %#x, size %#x\n", 357 hbar_addr_lo, hbar_size_lo); 358 if ((hbar_size_lo & PCI_MAPREG_MEM_TYPE_64BIT) != 0) 359 aprint_error_dev(self, "HostBAR1 addr %#x, size %#x\n", 360 hbar_addr_hi, hbar_size_hi); 361 aprint_error_dev(self, "WARNING: firmware PCI-X setup error: " 362 "RAM %#"PRIx64"..%#"PRIx64" not accessible by Host BAR, " 363 "enabling DMA bounce buffers\n", 364 hbar_size, mem_cluster_maxaddr-1); 365 366 /* 367 * force use of bouce buffers for inaccessible RAM addrs 368 */ 369 if (hbar_size < ((uint64_t)1 << 32)) { 370 error = bus_dmatag_subregion(sc->sc_32bit_dmat, 371 0, (bus_addr_t)hbar_size, &sc->sc_32bit_dmat, 372 BUS_DMA_NOWAIT); 373 if (error) 374 panic("%s: failed to subregion 32-bit dma tag:" 375 " error %d", __func__, error); 376 sc->sc_64bit_dmat = NULL; 377 } else { 378 error = bus_dmatag_subregion(sc->sc_64bit_dmat, 379 0, (bus_addr_t)hbar_size, &sc->sc_64bit_dmat, 380 BUS_DMA_NOWAIT); 381 if (error) 382 panic("%s: failed to subregion 64-bit dma tag:" 383 " error %d", __func__, error); 384 } 385 } 386 387 /* 388 * check PCI-X interface byteswap setup 389 * ensure 'Match Byte Lane' is disabled 390 */ 391 uint32_t mble, mba, mbs; 392 mble = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_XLR_MBLE); 393 mba = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_MATCH_BIT_ADDR); 394 mbs = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_MATCH_BIT_SIZE); 395 DPRINTF(("%s: MBLE=%#x, MBA=%#x, MBS=%#x\n", __func__, mble, mba, mbs)); 396 if ((mble & __BIT(40)) != 0) 397 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_XLR_MBLE, 0); 398 399 /* 400 * get PCI config space base addr from SBC PCIe CFG BAR 401 * initialize it if necessary 402 */ 403 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_CFG_BAR); 404 DPRINTF(("%s: PCIX_CFG_BAR %#x\n", __func__, bar)); 405 if ((bar & RMIXL_PCIX_CFG_BAR_ENB) == 0) { 406 u_long n = RMIXL_PCIX_CFG_SIZE / (1024 * 1024); 407 RMIXL_PCIX_BAR_INIT(CFG, bar, n, n); 408 } 409 rcp->rc_pci_cfg_pbase = (bus_addr_t)RMIXL_PCIX_CFG_BAR_TO_BA(bar); 410 rcp->rc_pci_cfg_size = (bus_size_t)RMIXL_PCIX_CFG_SIZE; 411 412 /* 413 * get PCI MEM space base [addr, size] from SBC PCIe MEM BAR 414 * initialize it if necessary 415 */ 416 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_MEM_BAR); 417 DPRINTF(("%s: PCIX_MEM_BAR %#x\n", __func__, bar)); 418 if ((bar & RMIXL_PCIX_MEM_BAR_ENB) == 0) { 419 u_long n = 256; /* 256 MB */ 420 RMIXL_PCIX_BAR_INIT(MEM, bar, n, n); 421 } 422 rcp->rc_pci_mem_pbase = (bus_addr_t)RMIXL_PCIX_MEM_BAR_TO_BA(bar); 423 rcp->rc_pci_mem_size = (bus_size_t)RMIXL_PCIX_MEM_BAR_TO_SIZE(bar); 424 425 /* 426 * get PCI IO space base [addr, size] from SBC PCIe IO BAR 427 * initialize it if necessary 428 */ 429 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_IO_BAR); 430 DPRINTF(("%s: PCIX_IO_BAR %#x\n", __func__, bar)); 431 if ((bar & RMIXL_PCIX_IO_BAR_ENB) == 0) { 432 u_long n = 32; /* 32 MB */ 433 RMIXL_PCIX_BAR_INIT(IO, bar, n, n); 434 } 435 rcp->rc_pci_io_pbase = (bus_addr_t)RMIXL_PCIX_IO_BAR_TO_BA(bar); 436 rcp->rc_pci_io_size = (bus_size_t)RMIXL_PCIX_IO_BAR_TO_SIZE(bar); 437 438 /* 439 * initialize the PCI CFG bus space tag 440 */ 441 rmixl_pci_cfg_bus_mem_init(&rcp->rc_pci_cfg_memt, rcp); 442 sc->sc_pci_cfg_memt = &rcp->rc_pci_cfg_memt; 443 444 /* 445 * initialize the PCI MEM and IO bus space tags 446 */ 447 rmixl_pci_bus_mem_init(&rcp->rc_pci_memt, rcp); 448 rmixl_pci_bus_io_init(&rcp->rc_pci_iot, rcp); 449 450 /* 451 * initialize the extended configuration regs 452 */ 453 rmixl_pcix_init_errors(sc); 454 455 /* 456 * initialize the PCI chipset tag 457 */ 458 rmixl_pcix_init(sc); 459 460 /* 461 * attach the PCI bus 462 */ 463 memset(&pba, 0, sizeof(pba)); 464 pba.pba_memt = &rcp->rc_pci_memt; 465 pba.pba_iot = &rcp->rc_pci_iot; 466 pba.pba_dmat = sc->sc_32bit_dmat; 467 pba.pba_dmat64 = sc->sc_64bit_dmat; 468 pba.pba_pc = &sc->sc_pci_chipset; 469 pba.pba_bus = 0; 470 pba.pba_bridgetag = NULL; 471 pba.pba_intrswiz = 0; 472 pba.pba_intrtag = 0; 473 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 474 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 475 476 (void) config_found_ia(self, "pcibus", &pba, pcibusprint); 477 } 478 479 /* 480 * rmixl_pcix_intcfg - init PCI-X interrupt control 481 */ 482 static void 483 rmixl_pcix_intcfg(rmixl_pcix_softc_t *sc) 484 { 485 DPRINTF(("%s\n", __func__)); 486 487 /* mask all interrupts until they are established */ 488 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, 489 PCIX_INTR_CONTROL_MASK_ALL); 490 491 /* 492 * read-to-clear any pre-existing interrupts 493 * XXX MSI bits in STATUS are also documented as write 1 to clear in PRM 494 */ 495 (void)RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 496 (void)RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 497 498 /* initialize the dispatch handles */ 499 for (int i=0; i < RMIXL_PCIX_NINTR; i++) { 500 rmixl_pcix_intr_t *ih = &sc->sc_intr[i]; 501 LIST_INIT(&ih->dispatch); 502 ih->ih = NULL; 503 ih->intrpin = i; 504 ih->enabled = false; 505 } 506 507 sc->sc_ih = rmixl_intr_establish(16, sc->sc_tmsk, 508 IPL_VM, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH, 509 rmixl_pcix_intr, sc, false); 510 if (sc->sc_ih == NULL) 511 panic("%s: cannot establish irq %d", __func__, 16); 512 513 sc->sc_fatal_ih = rmixl_intr_establish(24, sc->sc_tmsk, 514 IPL_VM, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH, 515 rmixl_pcix_error_intr, sc, false); 516 if (sc->sc_fatal_ih == NULL) 517 panic("%s: cannot establish irq %d", __func__, 24); 518 519 sc->sc_intr_init_done = true; 520 } 521 522 static void 523 rmixl_pcix_errata(rmixl_pcix_softc_t *sc) 524 { 525 /* nothing */ 526 } 527 528 static void 529 rmixl_pcix_init(rmixl_pcix_softc_t *sc) 530 { 531 pci_chipset_tag_t pc = &sc->sc_pci_chipset; 532 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 533 struct extent *ioext, *memext; 534 #endif 535 536 pc->pc_conf_v = (void *)sc; 537 pc->pc_attach_hook = rmixl_pcix_attach_hook; 538 pc->pc_bus_maxdevs = rmixl_pcix_bus_maxdevs; 539 pc->pc_make_tag = rmixl_pcix_make_tag; 540 pc->pc_decompose_tag = rmixl_pcix_decompose_tag; 541 pc->pc_conf_read = rmixl_pcix_conf_read; 542 pc->pc_conf_write = rmixl_pcix_conf_write; 543 544 pc->pc_intr_v = (void *)sc; 545 pc->pc_intr_map = rmixl_pcix_intr_map; 546 pc->pc_intr_string = rmixl_pcix_intr_string; 547 pc->pc_intr_evcnt = rmixl_pcix_intr_evcnt; 548 pc->pc_intr_establish = rmixl_pcix_intr_establish; 549 pc->pc_intr_disestablish = rmixl_pcix_intr_disestablish; 550 pc->pc_conf_interrupt = rmixl_conf_interrupt; 551 552 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 553 /* 554 * Configure the PCI bus. 555 */ 556 struct rmixl_config *rcp = &rmixl_configuration; 557 558 aprint_normal_dev(sc->sc_dev, "%s: configuring PCI bus\n"); 559 560 ioext = extent_create("pciio", 561 rcp->rc_pci_io_pbase, 562 rcp->rc_pci_io_pbase + rcp->rc_pci_io_size - 1, 563 M_DEVBUF, NULL, 0, EX_NOWAIT); 564 565 memext = extent_create("pcimem", 566 rcp->rc_pci_mem_pbase, 567 rcp->rc_pci_mem_pbase + rcp->rc_pci_mem_size - 1, 568 M_DEVBUF, NULL, 0, EX_NOWAIT); 569 570 pci_configure_bus(pc, ioext, memext, NULL, 0, 571 mips_cache_info.mci_dcache_align); 572 573 extent_destroy(ioext); 574 extent_destroy(memext); 575 #endif 576 } 577 578 static void 579 rmixl_pcix_init_errors(rmixl_pcix_softc_t *sc) 580 { 581 /* nothing */ 582 } 583 584 void 585 rmixl_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *iline) 586 { 587 DPRINTF(("%s: %p, %d, %d, %d, %d, %p\n", 588 __func__, v, bus, dev, ipin, swiz, iline)); 589 } 590 591 void 592 rmixl_pcix_attach_hook(struct device *parent, struct device *self, 593 struct pcibus_attach_args *pba) 594 { 595 DPRINTF(("%s: pba_bus %d, pba_bridgetag %p, pc_conf_v %p\n", 596 __func__, pba->pba_bus, pba->pba_bridgetag, 597 pba->pba_pc->pc_conf_v)); 598 } 599 600 int 601 rmixl_pcix_bus_maxdevs(void *v, int busno) 602 { 603 return (32); /* XXX depends on the family of XLS SoC */ 604 } 605 606 /* 607 * XLS pci tag is a 40 bit address composed thusly: 608 * 39:25 (reserved) 609 * 24 Swap (0=little, 1=big endian) 610 * 23:16 Bus number 611 * 15:11 Device number 612 * 10:8 Function number 613 * 7:0 Register number 614 * 615 * Note: this is the "native" composition for addressing CFG space, but not for ECFG space. 616 */ 617 pcitag_t 618 rmixl_pcix_make_tag(void *v, int bus, int dev, int fun) 619 { 620 return ((bus << 16) | (dev << 11) | (fun << 8)); 621 } 622 623 void 624 rmixl_pcix_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 625 { 626 if (bp != NULL) 627 *bp = (tag >> 16) & 0xff; 628 if (dp != NULL) 629 *dp = (tag >> 11) & 0x1f; 630 if (fp != NULL) 631 *fp = (tag >> 8) & 0x7; 632 } 633 634 void 635 rmixl_pcix_tag_print(const char *restrict s, void *v, pcitag_t tag, int offset, 636 vaddr_t va, u_long r) 637 { 638 int bus, dev, fun; 639 640 rmixl_pcix_decompose_tag(v, tag, &bus, &dev, &fun); 641 printf("%s: %d/%d/%d/%d - %#" PRIxVADDR ":%#lx\n", 642 s, bus, dev, fun, offset, va, r); 643 } 644 645 static int 646 rmixl_pcix_conf_setup(rmixl_pcix_softc_t *sc, 647 pcitag_t tag, int *offp, bus_space_tag_t *bstp, 648 bus_space_handle_t *bshp) 649 { 650 struct rmixl_config *rcp = &rmixl_configuration; 651 bus_space_tag_t bst; 652 bus_space_handle_t bsh; 653 bus_size_t size; 654 pcitag_t mask; 655 bus_addr_t ba; 656 int err; 657 static bus_space_handle_t cfg_bsh; 658 static bus_addr_t cfg_oba = -1; 659 660 /* 661 * bus space depends on offset 662 */ 663 if ((*offp >= 0) && (*offp < 0x100)) { 664 mask = __BITS(15,0); 665 bst = sc->sc_pci_cfg_memt; 666 ba = rcp->rc_pci_cfg_pbase; 667 ba += (tag & ~mask); 668 *offp += (tag & mask); 669 if (ba != cfg_oba) { 670 size = (bus_size_t)(mask + 1); 671 if (cfg_oba != -1) 672 bus_space_unmap(bst, cfg_bsh, size); 673 err = bus_space_map(bst, ba, size, 0, &cfg_bsh); 674 if (err != 0) { 675 #ifdef DEBUG 676 panic("%s: bus_space_map err %d, CFG space", 677 __func__, err); /* XXX */ 678 #endif 679 return -1; 680 } 681 cfg_oba = ba; 682 } 683 bsh = cfg_bsh; 684 } else { 685 #ifdef DEBUG 686 panic("%s: offset %#x: unknown", __func__, *offp); 687 #endif 688 return -1; 689 } 690 691 *bstp = bst; 692 *bshp = bsh; 693 694 return 0; 695 } 696 697 pcireg_t 698 rmixl_pcix_conf_read(void *v, pcitag_t tag, int offset) 699 { 700 rmixl_pcix_softc_t *sc = v; 701 static bus_space_handle_t bsh; 702 bus_space_tag_t bst; 703 pcireg_t rv; 704 uint64_t cfg0; 705 u_int s; 706 707 PCI_CONF_LOCK(s); 708 709 if (rmixl_pcix_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) { 710 cfg0 = rmixl_cache_err_dis(); 711 rv = bus_space_read_4(bst, bsh, (bus_size_t)offset); 712 if (rmixl_cache_err_check() != 0) { 713 #ifdef DIAGNOSTIC 714 int bus, dev, fun; 715 716 rmixl_pcix_decompose_tag(v, tag, &bus, &dev, &fun); 717 printf("%s: %d/%d/%d, offset %#x: bad address\n", 718 __func__, bus, dev, fun, offset); 719 #endif 720 rv = (pcireg_t) -1; 721 } 722 rmixl_cache_err_restore(cfg0); 723 } else { 724 rv = -1; 725 } 726 727 PCI_CONF_UNLOCK(s); 728 return rv; 729 } 730 731 void 732 rmixl_pcix_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 733 { 734 rmixl_pcix_softc_t *sc = v; 735 static bus_space_handle_t bsh; 736 bus_space_tag_t bst; 737 uint64_t cfg0; 738 u_int s; 739 740 PCI_CONF_LOCK(s); 741 742 if (rmixl_pcix_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) { 743 cfg0 = rmixl_cache_err_dis(); 744 bus_space_write_4(bst, bsh, (bus_size_t)offset, val); 745 if (rmixl_cache_err_check() != 0) { 746 #ifdef DIAGNOSTIC 747 int bus, dev, fun; 748 749 rmixl_pcix_decompose_tag(v, tag, &bus, &dev, &fun); 750 printf("%s: %d/%d/%d, offset %#x: bad address\n", 751 __func__, bus, dev, fun, offset); 752 #endif 753 } 754 rmixl_cache_err_restore(cfg0); 755 } 756 757 PCI_CONF_UNLOCK(s); 758 } 759 760 int 761 rmixl_pcix_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *pih) 762 { 763 const u_int irq = 16; /* PCIX index in IRT */ 764 765 #ifdef DEBUG 766 DPRINTF(("%s: ps_bus %d, pa_intrswiz %#x, pa_intrtag %#lx," 767 " pa_intrpin %d, pa_intrline %d, pa_rawintrpin %d\n", 768 __func__, pa->pa_bus, pa->pa_intrswiz, pa->pa_intrtag, 769 pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 770 #endif 771 772 if (pa->pa_intrpin != PCI_INTERRUPT_PIN_NONE) 773 *pih = rmixl_pcix_make_pih(pa->pa_intrpin - 1, irq); 774 else 775 *pih = ~0; 776 777 return 0; 778 } 779 780 const char * 781 rmixl_pcix_intr_string(void *v, pci_intr_handle_t pih) 782 { 783 u_int bitno, irq; 784 785 rmixl_pcix_decompose_pih(pih, &bitno, &irq); 786 787 if (! cpu_rmixlr(mips_options.mips_cpu)) 788 panic("%s: cpu %#x not supported\n", 789 __func__, mips_options.mips_cpu_id); 790 791 return rmixl_intr_string(irq); 792 } 793 794 const struct evcnt * 795 rmixl_pcix_intr_evcnt(void *v, pci_intr_handle_t pih) 796 { 797 return NULL; 798 } 799 800 static pci_intr_handle_t 801 rmixl_pcix_make_pih(u_int bitno, u_int irq) 802 { 803 pci_intr_handle_t pih; 804 805 KASSERT(bitno < 64); 806 KASSERT(irq < 32); 807 808 pih = (irq << 6); 809 pih |= bitno; 810 811 return pih; 812 } 813 814 static void 815 rmixl_pcix_decompose_pih(pci_intr_handle_t pih, u_int *bitno, u_int *irq) 816 { 817 *bitno = (u_int)(pih & 0x3f); 818 *irq = (u_int)(pih >> 6); 819 820 KASSERT(*bitno < 64); 821 KASSERT(*irq < 31); 822 } 823 824 static void 825 rmixl_pcix_intr_disestablish(void *v, void *ih) 826 { 827 rmixl_pcix_softc_t *sc = v; 828 rmixl_pcix_dispatch_t *dip = ih; 829 rmixl_pcix_intr_t *pip = &sc->sc_intr[dip->bitno];; 830 831 DPRINTF(("%s: pin=%d irq=%d\n", 832 __func__, dip->bitno + 1, dip->irq)); 833 KASSERT(dip->bitno < RMIXL_PCIX_NINTR); 834 835 LIST_REMOVE(dip, next); 836 evcnt_detach(&dip->count); 837 free(dip, M_DEVBUF); 838 839 if (LIST_EMPTY(&pip->dispatch)) { 840 uint32_t bit = 1 << (dip->bitno + 2); 841 uint32_t r; 842 843 r = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 844 r |= bit; /* set mask */ 845 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, r); 846 DPRINTF(("%s: disabled pin %d\n", __func__, dip->bitno + 1)); 847 848 pip->enabled = false; 849 } 850 } 851 852 static void * 853 rmixl_pcix_intr_establish(void *v, pci_intr_handle_t pih, int ipl, 854 int (*func)(void *), void *arg) 855 { 856 rmixl_pcix_softc_t *sc = v; 857 u_int bitno, irq; 858 rmixl_pcix_intr_t *pip; 859 rmixl_pcix_dispatch_t *dip; 860 int s; 861 862 if (pih == ~0) { 863 DPRINTF(("%s: bad pih=%#lx, implies PCI_INTERRUPT_PIN_NONE\n", 864 __func__, pih)); 865 return NULL; 866 } 867 868 rmixl_pcix_decompose_pih(pih, &bitno, &irq); 869 DPRINTF(("%s: pin=%d irq=%d\n", __func__, bitno + 1, irq)); 870 871 KASSERT(bitno < RMIXL_PCIX_NINTR); 872 pip = &sc->sc_intr[bitno]; 873 874 s = splhigh(); 875 876 /* 877 * all PCI-X device intrs get same ipl and sc 878 */ 879 KASSERT(sc == rmixl_pcix_sc); 880 KASSERT(ipl == IPL_VM); 881 882 /* 883 * allocate and initialize a dispatch handle 884 */ 885 dip = malloc(sizeof(*dip), M_DEVBUF, M_NOWAIT); 886 if (dip == NULL) { 887 printf("%s: cannot malloc dispatch handle\n", __func__); 888 goto out; 889 } 890 891 dip->bitno = bitno; 892 dip->irq = irq; 893 dip->func = func; 894 dip->arg = arg; 895 snprintf(dip->count_name, sizeof(dip->count_name), 896 "pin %d", bitno + 1); 897 evcnt_attach_dynamic(&dip->count, EVCNT_TYPE_INTR, NULL, 898 "rmixl_pcix", dip->count_name); 899 900 if (pip->enabled == false) { 901 uint32_t bit = 1 << (bitno + 2); 902 uint32_t r; 903 904 r = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 905 r &= ~bit; /* clear mask */ 906 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, r); 907 908 pip->sc = sc; 909 pip->ipl = ipl; 910 pip->enabled = true; 911 DPRINTF(("%s: enabled pin %d\n", __func__, bitno + 1)); 912 } 913 914 LIST_INSERT_HEAD(&pip->dispatch, dip, next); 915 916 out: 917 splx(s); 918 return dip; 919 } 920 921 static int 922 rmixl_pcix_intr(void *arg) 923 { 924 rmixl_pcix_softc_t *sc = arg; 925 int rv = 0; 926 927 uint32_t status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 928 DPRINTF(("%s: %#x\n", __func__, status)); 929 930 if (status != 0) { 931 for (int i=0; i < RMIXL_PCIX_NINTR; i++) { 932 uint32_t bit = 1 << i; 933 if ((status & bit) != 0) { 934 rmixl_pcix_intr_t *pip = &sc->sc_intr[i]; 935 rmixl_pcix_dispatch_t *dip; 936 LIST_FOREACH(dip, &pip->dispatch, next) { 937 (void)(*dip->func)(dip->arg); 938 dip->count.ev_count++; 939 rv = 1; 940 } 941 } 942 } 943 } 944 return rv; 945 } 946 947 static int 948 rmixl_pcix_error_intr(void *arg) 949 { 950 rmixl_pcix_softc_t *sc = arg; 951 uint32_t error_status; 952 953 error_status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 954 955 #ifdef DIAGNOSTIC 956 printf("%s: error status %#x\n", __func__, error_status); 957 #endif 958 959 #if DDB 960 Debugger(); 961 #endif 962 963 /* XXX reset and recover? */ 964 965 panic("%s: error %#x\n", device_xname(sc->sc_dev), error_status); 966 } 967 968 /* 969 * rmixl_physaddr_init_pcix: 970 * called from rmixl_physaddr_init to get region addrs & sizes 971 * from PCIX CFG, ECFG, IO, MEM BARs 972 */ 973 void 974 rmixl_physaddr_init_pcix(struct extent *ext) 975 { 976 u_long base; 977 u_long size; 978 uint32_t r; 979 980 r = RMIXL_PCIXREG_READ(RMIXLR_SBC_PCIX_CFG_BAR); 981 if ((r & RMIXL_PCIX_CFG_BAR_ENB) != 0) { 982 base = (u_long)(RMIXL_PCIX_CFG_BAR_TO_BA((uint64_t)r) 983 / (1024 * 1024)); 984 size = (u_long)RMIXL_PCIX_CFG_SIZE / (1024 * 1024); 985 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 986 __LINE__, "CFG", r, base * 1024 * 1024, size)); 987 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 988 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 989 "failed", __func__, ext, base, size, EX_NOWAIT); 990 } 991 992 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_MEM_BAR); 993 if ((r & RMIXL_PCIX_MEM_BAR_ENB) != 0) { 994 base = (u_long)(RMIXL_PCIX_MEM_BAR_TO_BA((uint64_t)r) 995 / (1024 * 1024)); 996 size = (u_long)(RMIXL_PCIX_MEM_BAR_TO_SIZE((uint64_t)r) 997 / (1024 * 1024)); 998 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 999 __LINE__, "MEM", r, base * 1024 * 1024, size)); 1000 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1001 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1002 "failed", __func__, ext, base, size, EX_NOWAIT); 1003 } 1004 1005 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_IO_BAR); 1006 if ((r & RMIXL_PCIX_IO_BAR_ENB) != 0) { 1007 base = (u_long)(RMIXL_PCIX_IO_BAR_TO_BA((uint64_t)r) 1008 / (1024 * 1024)); 1009 size = (u_long)(RMIXL_PCIX_IO_BAR_TO_SIZE((uint64_t)r) 1010 / (1024 * 1024)); 1011 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1012 __LINE__, "IO", r, base * 1024 * 1024, size)); 1013 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1014 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1015 "failed", __func__, ext, base, size, EX_NOWAIT); 1016 } 1017 } 1018 1019 #ifdef DDB 1020 int rmixl_pcix_intr_chk(void); 1021 int 1022 rmixl_pcix_intr_chk(void) 1023 { 1024 uint32_t control, status, error_status; 1025 1026 control = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 1027 status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 1028 error_status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 1029 1030 printf("%s: %#x, %#x, %#x\n", __func__, control, status, error_status); 1031 1032 control |= PCIX_INTR_CONTROL_DIA; 1033 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, control); 1034 1035 control = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 1036 status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 1037 error_status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 1038 1039 printf("%s: %#x, %#x, %#x\n", __func__, control, status, error_status); 1040 1041 return 0; 1042 } 1043 #endif 1044
Indexes created Fri Oct 17 23:09:53 GMT 2025