rmixl_pcix.c revision 1.11
1 /* $NetBSD: rmixl_pcix.c,v 1.11 2014/03/11 08:19:45 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * PCI configuration support for RMI XLR SoC 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: rmixl_pcix.c,v 1.11 2014/03/11 08:19:45 mrg Exp $"); 44 45 #include "opt_pci.h" 46 #include "pci.h" 47 48 #include <sys/cdefs.h> 49 50 #include <sys/param.h> 51 #include <sys/bus.h> 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/extent.h> 55 #include <sys/intr.h> 56 #include <sys/malloc.h> 57 #include <sys/kernel.h> /* for 'hz' */ 58 #include <sys/systm.h> 59 60 #include <uvm/uvm_extern.h> 61 62 #include <mips/rmi/rmixlreg.h> 63 #include <mips/rmi/rmixlvar.h> 64 #include <mips/rmi/rmixl_intr.h> 65 #include <mips/rmi/rmixl_pcixvar.h> 66 67 #include <mips/rmi/rmixl_obiovar.h> 68 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pcidevs.h> 71 #include <dev/pci/pciconf.h> 72 73 #ifdef PCI_NETBSD_CONFIGURE 74 #include <mips/cache.h> 75 #endif 76 77 #ifdef PCI_DEBUG 78 int rmixl_pcix_debug = PCI_DEBUG; 79 # define DPRINTF(x) do { if (rmixl_pcix_debug) printf x ; } while (0) 80 #else 81 # define DPRINTF(x) 82 #endif 83 84 #ifndef DDB 85 # define STATIC static 86 #else 87 # define STATIC 88 #endif 89 90 91 /* 92 * XLR PCI-X Extended Configuration Registers 93 * Note: 94 * - MSI-related regs are omitted 95 * - Device mode regs are omitted 96 */ 97 #define RMIXL_PCIX_ECFG_HOST_BAR0_ADDR 0x100 /* Host BAR0 Address */ 98 #define RMIXL_PCIX_ECFG_HOST_BAR1_ADDR 0x104 /* Host BAR1 Address */ 99 #define RMIXL_PCIX_ECFG_HOST_BAR2_ADDR 0x108 /* Host BAR2 Address */ 100 #define RMIXL_PCIX_ECFG_HOST_BAR3_ADDR 0x10c /* Host BAR3 Address */ 101 #define RMIXL_PCIX_ECFG_HOST_BAR4_ADDR 0x110 /* Host BAR4 Address */ 102 #define RMIXL_PCIX_ECFG_HOST_BAR5_ADDR 0x114 /* Host BAR5 Address */ 103 #define RMIXL_PCIX_ECFG_HOST_BAR0_SIZE 0x118 /* Host BAR0 Size */ 104 #define RMIXL_PCIX_ECFG_HOST_BAR1_SIZE 0x11c /* Host BAR1 Size */ 105 #define RMIXL_PCIX_ECFG_HOST_BAR2_SIZE 0x120 /* Host BAR2 Size */ 106 #define RMIXL_PCIX_ECFG_HOST_BAR3_SIZE 0x124 /* Host BAR3 Size */ 107 #define RMIXL_PCIX_ECFG_HOST_BAR4_SIZE 0x128 /* Host BAR4 Size */ 108 #define RMIXL_PCIX_ECFG_HOST_BAR5_SIZE 0x12c /* Host BAR5 Size */ 109 #define RMIXL_PCIX_ECFG_MATCH_BIT_ADDR 0x130 /* Match Bit Address BAR */ 110 #define RMIXL_PCIX_ECFG_MATCH_BIT_SIZE 0x134 /* Match Bit Size BAR */ 111 #define RMIXL_PCIX_ECFG_XLR_CONTROL 0x138 /* XLR Control reg */ 112 #define RMIXL_PCIX_ECFG_INTR_CONTROL 0x13c /* Interrupt Control reg */ 113 #define RMIXL_PCIX_ECFG_INTR_STATUS 0x140 /* Interrupt Status reg */ 114 #define RMIXL_PCIX_ECFG_INTR_ERR_STATUS 0x144 /* Interrupt Error Status reg */ 115 #define RMIXL_PCIX_ECFG_HOST_MODE_STS 0x178 /* Host Mode Status */ 116 #define RMIXL_PCIX_ECFG_XLR_MBLE 0x17c /* XLR Match Byte Lane Enable */ 117 #define RMIXL_PCIX_ECFG_HOST_XROM_ADDR 0x180 /* Host Expansion ROM Address */ 118 #define RMIXL_PCIX_ECFG_HOST_XROM_SIZE 0x184 /* Host Expansion ROM Size */ 119 #define RMIXL_PCIX_ECFG_HOST_MODE_CTL 0x18c /* Host Mode Control */ 120 #define RMIXL_PCIX_ECFG_TXCAL_CTL 0x1a0 /* TX Calibration Preset Control */ 121 #define RMIXL_PCIX_ECFG_TXCAL_COUNT 0x1a4 /* TX Calibration Preset Count */ 122 123 /* 124 * RMIXL_PCIX_ECFG_INTR_CONTROL bit defines 125 */ 126 #define PCIX_INTR_CONTROL_RESV __BITS(31,8) 127 #define PCIX_INTR_CONTROL_MSI1_MASK __BIT(7) 128 #define PCIX_INTR_CONTROL_MSI0_MASK __BIT(6) 129 #define PCIX_INTR_CONTROL_INTD_MASK __BIT(5) 130 #define PCIX_INTR_CONTROL_INTC_MASK __BIT(4) 131 #define PCIX_INTR_CONTROL_INTB_MASK __BIT(3) 132 #define PCIX_INTR_CONTROL_INTA_MASK __BIT(2) 133 #define PCIX_INTR_CONTROL_TMSI __BIT(1) /* Trigger MSI Interrupt */ 134 #define PCIX_INTR_CONTROL_DIA __BIT(0) /* Device Interrupt through INTA Pin */ 135 #define PCIX_INTR_CONTROL_MASK_ALL \ 136 (PCIX_INTR_CONTROL_MSI1_MASK|PCIX_INTR_CONTROL_MSI0_MASK \ 137 |PCIX_INTR_CONTROL_INTD_MASK|PCIX_INTR_CONTROL_INTC_MASK \ 138 |PCIX_INTR_CONTROL_INTB_MASK|PCIX_INTR_CONTROL_INTA_MASK) 139 140 /* 141 * RMIXL_PCIX_ECFG_INTR_STATUS bit defines 142 */ 143 #define PCIX_INTR_STATUS_RESV __BITS(31,6) 144 #define PCIX_INTR_STATUS_MSI1 __BIT(5) 145 #define PCIX_INTR_STATUS_MSI0 __BIT(4) 146 #define PCIX_INTR_STATUS_INTD __BIT(3) 147 #define PCIX_INTR_STATUS_INTC __BIT(2) 148 #define PCIX_INTR_STATUS_INTB __BIT(1) 149 #define PCIX_INTR_STATUS_INTA __BIT(0) 150 151 /* 152 * RMIXL_PCIX_ECFG_INTR_ERR_STATUS bit defines 153 */ 154 #define PCIX_INTR_ERR_STATUS_RESa __BITS(31,5) 155 #define PCIX_INTR_ERR_STATUS_SERR __BIT(4) /* System Error */ 156 #define PCIX_INTR_ERR_STATUS_RESb __BIT(3) 157 #define PCIX_INTR_ERR_STATUS_TE __BIT(2) /* Target Error */ 158 #define PCIX_INTR_ERR_STATUS_IE __BIT(1) /* Initiator Error */ 159 #define PCIX_INTR_ERR_STATUS_RCE __BIT(0) /* Retry Count Expired */ 160 #define PCIX_INTR_ERR_STATUS_RESV \ 161 (PCIX_INTR_ERR_STATUS_RESa|PCIX_INTR_ERR_STATUS_RESb) 162 163 /* 164 * RMIXL_PCIX_ECFG_HOST_MODE_CTL bit defines 165 */ 166 #define PCIX_HOST_MODE_CTL_HDMSTAT __BIT(1) /* Host/Dev Mode status 167 * read-only 168 * 1 = host 169 * 0 = device 170 */ 171 #define PCIX_HOST_MODE_CTL_HOSTSWRST __BIT(0) /* Host soft reset 172 * set to 1 to reset 173 * set to 0 to un-reset 174 */ 175 176 177 #if BYTE_ORDER == BIG_ENDIAN 178 # define RMIXL_PCIXREG_BASE RMIXL_IO_DEV_PCIX_EB 179 #else 180 # define RMIXL_PCIXREG_BASE RMIXL_IO_DEV_PCIX_EL 181 #endif 182 183 #define RMIXL_PCIXREG_VADDR(o) \ 184 (volatile uint32_t *)MIPS_PHYS_TO_KSEG1( \ 185 rmixl_configuration.rc_io_pbase \ 186 + RMIXL_PCIXREG_BASE + (o)) 187 188 #define RMIXL_PCIXREG_READ(o) (*RMIXL_PCIXREG_VADDR(o)) 189 #define RMIXL_PCIXREG_WRITE(o,v) *RMIXL_PCIXREG_VADDR(o) = (v) 190 191 192 #define RMIXL_PCIX_CONCAT3(a,b,c) a ## b ## c 193 #define RMIXL_PCIX_BAR_INIT(reg, bar, size, align) { \ 194 struct extent *ext = rmixl_configuration.rc_phys_ex; \ 195 u_long region_start; \ 196 uint64_t ba; \ 197 int err; \ 198 \ 199 err = extent_alloc(ext, (size), (align), 0UL, EX_NOWAIT, \ 200 ®ion_start); \ 201 if (err != 0) \ 202 panic("%s: extent_alloc(%p, %#lx, %#lx, %#lx, %#x, %p)",\ 203 __func__, ext, size, align, 0UL, EX_NOWAIT, \ 204 ®ion_start); \ 205 ba = (uint64_t)region_start; \ 206 ba *= (1024 * 1024); \ 207 bar = RMIXL_PCIX_CONCAT3(RMIXL_PCIX_,reg,_BAR)(ba, 1); \ 208 DPRINTF(("PCIX %s BAR was not enabled by firmware\n" \ 209 "enabling %s at phys %#" PRIxBUSADDR ", size %lu MB\n", \ 210 __STRING(reg), __STRING(reg), ba, size)); \ 211 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_BRIDGE + \ 212 RMIXL_PCIX_CONCAT3(RMIXLR_SBC_PCIX_,reg,_BAR), bar); \ 213 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + \ 214 RMIXL_PCIX_CONCAT3(RMIXLR_SBC_PCIX_,reg,_BAR)); \ 215 DPRINTF(("%s: %s BAR %#x\n", __func__, __STRING(reg), bar)); \ 216 } 217 218 219 #define RMIXL_PCIX_EVCNT(sc, intrpin, cpu) \ 220 &(sc)->sc_evcnts[(intrpin) * (ncpu) + (cpu)] 221 222 223 static int rmixl_pcix_match(device_t, cfdata_t, void *); 224 static void rmixl_pcix_attach(device_t, device_t, void *); 225 static void rmixl_pcix_init(rmixl_pcix_softc_t *); 226 static void rmixl_pcix_init_errors(rmixl_pcix_softc_t *); 227 static void rmixl_pcix_attach_hook(device_t, device_t, 228 struct pcibus_attach_args *); 229 static void rmixl_pcix_intcfg(rmixl_pcix_softc_t *); 230 static void rmixl_pcix_errata(rmixl_pcix_softc_t *); 231 static void rmixl_conf_interrupt(void *, int, int, int, int, int *); 232 static int rmixl_pcix_bus_maxdevs(void *, int); 233 static pcitag_t rmixl_pcix_make_tag(void *, int, int, int); 234 static void rmixl_pcix_decompose_tag(void *, pcitag_t, int *, int *, int *); 235 void rmixl_pcix_tag_print(const char *restrict, void *, pcitag_t, int, vaddr_t, u_long); 236 static int rmixl_pcix_conf_setup(rmixl_pcix_softc_t *, 237 pcitag_t, int *, bus_space_tag_t *, 238 bus_space_handle_t *); 239 static pcireg_t rmixl_pcix_conf_read(void *, pcitag_t, int); 240 static void rmixl_pcix_conf_write(void *, pcitag_t, int, pcireg_t); 241 242 static int rmixl_pcix_intr_map(const struct pci_attach_args *, 243 pci_intr_handle_t *); 244 static const char * 245 rmixl_pcix_intr_string(void *, pci_intr_handle_t); 246 static const struct evcnt * 247 rmixl_pcix_intr_evcnt(void *, pci_intr_handle_t); 248 static pci_intr_handle_t 249 rmixl_pcix_make_pih(u_int, u_int); 250 static void rmixl_pcix_decompose_pih(pci_intr_handle_t, u_int *, u_int *); 251 static void rmixl_pcix_intr_disestablish(void *, void *); 252 static void *rmixl_pcix_intr_establish(void *, pci_intr_handle_t, 253 int, int (*)(void *), void *); 254 static rmixl_pcix_intr_t * 255 rmixl_pcix_pip_add_1(rmixl_pcix_softc_t *, int, int); 256 static void rmixl_pcix_pip_free_callout(rmixl_pcix_intr_t *); 257 static void rmixl_pcix_pip_free(void *); 258 static int rmixl_pcix_intr(void *); 259 static int rmixl_pcix_error_intr(void *); 260 261 262 CFATTACH_DECL_NEW(rmixl_pcix, sizeof(rmixl_pcix_softc_t), 263 rmixl_pcix_match, rmixl_pcix_attach, NULL, NULL); 264 265 266 static int rmixl_pcix_found; 267 268 269 static int 270 rmixl_pcix_match(device_t parent, cfdata_t cf, void *aux) 271 { 272 uint32_t r; 273 274 /* 275 * PCI-X interface exists on XLR chips only 276 */ 277 if (! cpu_rmixlr(mips_options.mips_cpu)) 278 return 0; 279 280 /* XXX 281 * for now there is only one PCI-X Interface on chip 282 * and only one chip in the system 283 * this could change with furture RMI XL family designs 284 * or when we have multi-chip systems. 285 */ 286 if (rmixl_pcix_found) 287 return 0; 288 289 /* read Host Mode Control register */ 290 r = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_MODE_CTL); 291 r &= PCIX_HOST_MODE_CTL_HDMSTAT; 292 if (r == 0) 293 return 0; /* strapped for Device Mode */ 294 295 return 1; 296 } 297 298 static void 299 rmixl_pcix_attach(device_t parent, device_t self, void *aux) 300 { 301 rmixl_pcix_softc_t *sc = device_private(self); 302 struct obio_attach_args *obio = aux; 303 struct rmixl_config *rcp = &rmixl_configuration; 304 struct pcibus_attach_args pba; 305 uint32_t bar; 306 307 rmixl_pcix_found = 1; 308 sc->sc_dev = self; 309 sc->sc_29bit_dmat = obio->obio_29bit_dmat; 310 sc->sc_32bit_dmat = obio->obio_32bit_dmat; 311 sc->sc_64bit_dmat = obio->obio_64bit_dmat; 312 sc->sc_tmsk = obio->obio_tmsk; 313 314 aprint_normal(": RMI XLR PCI-X Interface\n"); 315 316 mutex_init(&sc->sc_mutex, MUTEX_DEFAULT, IPL_HIGH); 317 318 rmixl_pcix_intcfg(sc); 319 320 rmixl_pcix_errata(sc); 321 322 /* 323 * check XLR Control Register 324 */ 325 DPRINTF(("%s: XLR_CONTROL=%#x\n", __func__, 326 RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_XLR_CONTROL))); 327 328 /* 329 * HBAR[0] if a 32 bit BAR, or 330 * HBAR[0,1] if a 64 bit BAR pair 331 * must cover all RAM 332 */ 333 extern u_quad_t mem_cluster_maxaddr; 334 uint64_t hbar_addr; 335 uint64_t hbar_size; 336 uint32_t hbar_size_lo, hbar_size_hi; 337 uint32_t hbar_addr_lo, hbar_addr_hi; 338 339 hbar_addr_lo = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR0_ADDR); 340 hbar_addr_hi = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR1_ADDR); 341 hbar_size_lo = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR0_SIZE); 342 hbar_size_hi = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR1_SIZE); 343 344 hbar_addr = (u_quad_t)(hbar_addr_lo & PCI_MAPREG_MEM_ADDR_MASK); 345 hbar_size = hbar_size_lo; 346 if ((hbar_size_lo & PCI_MAPREG_MEM_TYPE_64BIT) != 0) { 347 hbar_addr |= (uint64_t)hbar_addr_hi << 32; 348 hbar_size |= (uint64_t)hbar_size_hi << 32; 349 } 350 if ((hbar_addr != 0) || (hbar_size < mem_cluster_maxaddr)) { 351 int error; 352 353 aprint_error_dev(self, "HostBAR0 addr %#x, size %#x\n", 354 hbar_addr_lo, hbar_size_lo); 355 if ((hbar_size_lo & PCI_MAPREG_MEM_TYPE_64BIT) != 0) 356 aprint_error_dev(self, "HostBAR1 addr %#x, size %#x\n", 357 hbar_addr_hi, hbar_size_hi); 358 aprint_error_dev(self, "WARNING: firmware PCI-X setup error: " 359 "RAM %#"PRIx64"..%#"PRIx64" not accessible by Host BAR, " 360 "enabling DMA bounce buffers\n", 361 hbar_size, mem_cluster_maxaddr-1); 362 363 /* 364 * force use of bouce buffers for inaccessible RAM addrs 365 */ 366 if (hbar_size < ((uint64_t)1 << 32)) { 367 error = bus_dmatag_subregion(sc->sc_32bit_dmat, 368 0, (bus_addr_t)hbar_size, &sc->sc_32bit_dmat, 369 BUS_DMA_NOWAIT); 370 if (error) 371 panic("%s: failed to subregion 32-bit dma tag:" 372 " error %d", __func__, error); 373 sc->sc_64bit_dmat = NULL; 374 } else { 375 error = bus_dmatag_subregion(sc->sc_64bit_dmat, 376 0, (bus_addr_t)hbar_size, &sc->sc_64bit_dmat, 377 BUS_DMA_NOWAIT); 378 if (error) 379 panic("%s: failed to subregion 64-bit dma tag:" 380 " error %d", __func__, error); 381 } 382 } 383 384 /* 385 * check PCI-X interface byteswap setup 386 * ensure 'Match Byte Lane' is disabled 387 */ 388 uint32_t mble; 389 mble = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_XLR_MBLE); 390 #ifdef PCI_DEBUG 391 uint32_t mba, mbs; 392 mba = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_MATCH_BIT_ADDR); 393 mbs = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_MATCH_BIT_SIZE); 394 DPRINTF(("%s: MBLE=%#x, MBA=%#x, MBS=%#x\n", __func__, mble, mba, mbs)); 395 #endif 396 if ((mble & __BIT(40)) != 0) 397 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_XLR_MBLE, 0); 398 399 /* 400 * get PCI config space base addr from SBC PCIe CFG BAR 401 * initialize it if necessary 402 */ 403 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_CFG_BAR); 404 DPRINTF(("%s: PCIX_CFG_BAR %#x\n", __func__, bar)); 405 if ((bar & RMIXL_PCIX_CFG_BAR_ENB) == 0) { 406 u_long n = RMIXL_PCIX_CFG_SIZE / (1024 * 1024); 407 RMIXL_PCIX_BAR_INIT(CFG, bar, n, n); 408 } 409 rcp->rc_pci_cfg_pbase = (bus_addr_t)RMIXL_PCIX_CFG_BAR_TO_BA(bar); 410 rcp->rc_pci_cfg_size = (bus_size_t)RMIXL_PCIX_CFG_SIZE; 411 412 /* 413 * get PCI MEM space base [addr, size] from SBC PCIe MEM BAR 414 * initialize it if necessary 415 */ 416 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_MEM_BAR); 417 DPRINTF(("%s: PCIX_MEM_BAR %#x\n", __func__, bar)); 418 if ((bar & RMIXL_PCIX_MEM_BAR_ENB) == 0) { 419 u_long n = 256; /* 256 MB */ 420 RMIXL_PCIX_BAR_INIT(MEM, bar, n, n); 421 } 422 rcp->rc_pci_mem_pbase = (bus_addr_t)RMIXL_PCIX_MEM_BAR_TO_BA(bar); 423 rcp->rc_pci_mem_size = (bus_size_t)RMIXL_PCIX_MEM_BAR_TO_SIZE(bar); 424 425 /* 426 * get PCI IO space base [addr, size] from SBC PCIe IO BAR 427 * initialize it if necessary 428 */ 429 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_IO_BAR); 430 DPRINTF(("%s: PCIX_IO_BAR %#x\n", __func__, bar)); 431 if ((bar & RMIXL_PCIX_IO_BAR_ENB) == 0) { 432 u_long n = 32; /* 32 MB */ 433 RMIXL_PCIX_BAR_INIT(IO, bar, n, n); 434 } 435 rcp->rc_pci_io_pbase = (bus_addr_t)RMIXL_PCIX_IO_BAR_TO_BA(bar); 436 rcp->rc_pci_io_size = (bus_size_t)RMIXL_PCIX_IO_BAR_TO_SIZE(bar); 437 438 /* 439 * initialize the PCI CFG bus space tag 440 */ 441 rmixl_pci_cfg_bus_mem_init(&rcp->rc_pci_cfg_memt, rcp); 442 sc->sc_pci_cfg_memt = &rcp->rc_pci_cfg_memt; 443 444 /* 445 * initialize the PCI MEM and IO bus space tags 446 */ 447 rmixl_pci_bus_mem_init(&rcp->rc_pci_memt, rcp); 448 rmixl_pci_bus_io_init(&rcp->rc_pci_iot, rcp); 449 450 /* 451 * initialize the extended configuration regs 452 */ 453 rmixl_pcix_init_errors(sc); 454 455 /* 456 * initialize the PCI chipset tag 457 */ 458 rmixl_pcix_init(sc); 459 460 /* 461 * attach the PCI bus 462 */ 463 memset(&pba, 0, sizeof(pba)); 464 pba.pba_memt = &rcp->rc_pci_memt; 465 pba.pba_iot = &rcp->rc_pci_iot; 466 pba.pba_dmat = sc->sc_32bit_dmat; 467 pba.pba_dmat64 = sc->sc_64bit_dmat; 468 pba.pba_pc = &sc->sc_pci_chipset; 469 pba.pba_bus = 0; 470 pba.pba_bridgetag = NULL; 471 pba.pba_intrswiz = 0; 472 pba.pba_intrtag = 0; 473 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY | 474 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 475 476 (void) config_found_ia(self, "pcibus", &pba, pcibusprint); 477 } 478 479 /* 480 * rmixl_pcix_intcfg - init PCI-X interrupt control 481 */ 482 static void 483 rmixl_pcix_intcfg(rmixl_pcix_softc_t *sc) 484 { 485 size_t size; 486 rmixl_pcix_evcnt_t *ev; 487 488 DPRINTF(("%s\n", __func__)); 489 490 /* mask all interrupts until they are established */ 491 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, 492 PCIX_INTR_CONTROL_MASK_ALL); 493 494 /* 495 * read-to-clear any pre-existing interrupts 496 * XXX MSI bits in STATUS are also documented as write 1 to clear in PRM 497 */ 498 (void)RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 499 (void)RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 500 501 /* initialize the (non-error interrupt) dispatch handles */ 502 sc->sc_intr = NULL; 503 504 /* 505 * allocate per-cpu, per-pin interrupt event counters 506 */ 507 size = ncpu * PCI_INTERRUPT_PIN_MAX * sizeof(rmixl_pcix_evcnt_t); 508 ev = malloc(size, M_DEVBUF, M_NOWAIT); 509 if (ev == NULL) 510 panic("%s: cannot malloc evcnts\n", __func__); 511 sc->sc_evcnts = ev; 512 for (int pin=PCI_INTERRUPT_PIN_A; pin <= PCI_INTERRUPT_PIN_MAX; pin++) { 513 for (int cpu=0; cpu < ncpu; cpu++) { 514 ev = RMIXL_PCIX_EVCNT(sc, pin - 1, cpu); 515 snprintf(ev->name, sizeof(ev->name), 516 "cpu%d, pin %d", cpu, pin); 517 evcnt_attach_dynamic(&ev->evcnt, EVCNT_TYPE_INTR, 518 NULL, "rmixl_pcix", ev->name); 519 } 520 } 521 522 /* 523 * establish PCIX error interrupt handler 524 */ 525 sc->sc_fatal_ih = rmixl_intr_establish(24, sc->sc_tmsk, 526 IPL_VM, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH, 527 rmixl_pcix_error_intr, sc, false); 528 if (sc->sc_fatal_ih == NULL) 529 panic("%s: cannot establish irq %d", __func__, 24); 530 } 531 532 static void 533 rmixl_pcix_errata(rmixl_pcix_softc_t *sc) 534 { 535 /* nothing */ 536 } 537 538 static void 539 rmixl_pcix_init(rmixl_pcix_softc_t *sc) 540 { 541 pci_chipset_tag_t pc = &sc->sc_pci_chipset; 542 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 543 struct extent *ioext, *memext; 544 #endif 545 546 pc->pc_conf_v = (void *)sc; 547 pc->pc_attach_hook = rmixl_pcix_attach_hook; 548 pc->pc_bus_maxdevs = rmixl_pcix_bus_maxdevs; 549 pc->pc_make_tag = rmixl_pcix_make_tag; 550 pc->pc_decompose_tag = rmixl_pcix_decompose_tag; 551 pc->pc_conf_read = rmixl_pcix_conf_read; 552 pc->pc_conf_write = rmixl_pcix_conf_write; 553 554 pc->pc_intr_v = (void *)sc; 555 pc->pc_intr_map = rmixl_pcix_intr_map; 556 pc->pc_intr_string = rmixl_pcix_intr_string; 557 pc->pc_intr_evcnt = rmixl_pcix_intr_evcnt; 558 pc->pc_intr_establish = rmixl_pcix_intr_establish; 559 pc->pc_intr_disestablish = rmixl_pcix_intr_disestablish; 560 pc->pc_conf_interrupt = rmixl_conf_interrupt; 561 562 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 563 /* 564 * Configure the PCI bus. 565 */ 566 struct rmixl_config *rcp = &rmixl_configuration; 567 568 aprint_normal_dev(sc->sc_dev, "%s: configuring PCI bus\n"); 569 570 ioext = extent_create("pciio", 571 rcp->rc_pci_io_pbase, 572 rcp->rc_pci_io_pbase + rcp->rc_pci_io_size - 1, 573 M_DEVBUF, NULL, 0, EX_NOWAIT); 574 575 memext = extent_create("pcimem", 576 rcp->rc_pci_mem_pbase, 577 rcp->rc_pci_mem_pbase + rcp->rc_pci_mem_size - 1, 578 M_DEVBUF, NULL, 0, EX_NOWAIT); 579 580 pci_configure_bus(pc, ioext, memext, NULL, 0, 581 mips_cache_info.mci_dcache_align); 582 583 extent_destroy(ioext); 584 extent_destroy(memext); 585 #endif 586 } 587 588 static void 589 rmixl_pcix_init_errors(rmixl_pcix_softc_t *sc) 590 { 591 /* nothing */ 592 } 593 594 void 595 rmixl_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *iline) 596 { 597 DPRINTF(("%s: %p, %d, %d, %d, %d, %p\n", 598 __func__, v, bus, dev, ipin, swiz, iline)); 599 } 600 601 void 602 rmixl_pcix_attach_hook(device_t parent, device_t self, 603 struct pcibus_attach_args *pba) 604 { 605 DPRINTF(("%s: pba_bus %d, pba_bridgetag %p, pc_conf_v %p\n", 606 __func__, pba->pba_bus, pba->pba_bridgetag, 607 pba->pba_pc->pc_conf_v)); 608 } 609 610 int 611 rmixl_pcix_bus_maxdevs(void *v, int busno) 612 { 613 return (32); /* XXX depends on the family of XLS SoC */ 614 } 615 616 /* 617 * XLS pci tag is a 40 bit address composed thusly: 618 * 39:25 (reserved) 619 * 24 Swap (0=little, 1=big endian) 620 * 23:16 Bus number 621 * 15:11 Device number 622 * 10:8 Function number 623 * 7:0 Register number 624 * 625 * Note: this is the "native" composition for addressing CFG space, but not for ECFG space. 626 */ 627 pcitag_t 628 rmixl_pcix_make_tag(void *v, int bus, int dev, int fun) 629 { 630 return ((bus << 16) | (dev << 11) | (fun << 8)); 631 } 632 633 void 634 rmixl_pcix_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 635 { 636 if (bp != NULL) 637 *bp = (tag >> 16) & 0xff; 638 if (dp != NULL) 639 *dp = (tag >> 11) & 0x1f; 640 if (fp != NULL) 641 *fp = (tag >> 8) & 0x7; 642 } 643 644 void 645 rmixl_pcix_tag_print(const char *restrict s, void *v, pcitag_t tag, int offset, 646 vaddr_t va, u_long r) 647 { 648 int bus, dev, fun; 649 650 rmixl_pcix_decompose_tag(v, tag, &bus, &dev, &fun); 651 printf("%s: %d/%d/%d/%d - %#" PRIxVADDR ":%#lx\n", 652 s, bus, dev, fun, offset, va, r); 653 } 654 655 static int 656 rmixl_pcix_conf_setup(rmixl_pcix_softc_t *sc, 657 pcitag_t tag, int *offp, bus_space_tag_t *bstp, 658 bus_space_handle_t *bshp) 659 { 660 struct rmixl_config *rcp = &rmixl_configuration; 661 bus_space_tag_t bst; 662 bus_space_handle_t bsh; 663 bus_size_t size; 664 pcitag_t mask; 665 bus_addr_t ba; 666 int err; 667 static bus_space_handle_t cfg_bsh; 668 static bus_addr_t cfg_oba = -1; 669 670 /* 671 * bus space depends on offset 672 */ 673 if ((*offp >= 0) && (*offp < 0x100)) { 674 mask = __BITS(15,0); 675 bst = sc->sc_pci_cfg_memt; 676 ba = rcp->rc_pci_cfg_pbase; 677 ba += (tag & ~mask); 678 *offp += (tag & mask); 679 if (ba != cfg_oba) { 680 size = (bus_size_t)(mask + 1); 681 if (cfg_oba != -1) 682 bus_space_unmap(bst, cfg_bsh, size); 683 err = bus_space_map(bst, ba, size, 0, &cfg_bsh); 684 if (err != 0) { 685 #ifdef DEBUG 686 panic("%s: bus_space_map err %d, CFG space", 687 __func__, err); /* XXX */ 688 #endif 689 return -1; 690 } 691 cfg_oba = ba; 692 } 693 bsh = cfg_bsh; 694 } else { 695 #ifdef DEBUG 696 panic("%s: offset %#x: unknown", __func__, *offp); 697 #endif 698 return -1; 699 } 700 701 *bstp = bst; 702 *bshp = bsh; 703 704 return 0; 705 } 706 707 pcireg_t 708 rmixl_pcix_conf_read(void *v, pcitag_t tag, int offset) 709 { 710 rmixl_pcix_softc_t *sc = v; 711 static bus_space_handle_t bsh; 712 bus_space_tag_t bst; 713 pcireg_t rv; 714 uint64_t cfg0; 715 716 mutex_enter(&sc->sc_mutex); 717 718 if (rmixl_pcix_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) { 719 cfg0 = rmixl_cache_err_dis(); 720 rv = bus_space_read_4(bst, bsh, (bus_size_t)offset); 721 if (rmixl_cache_err_check() != 0) { 722 #ifdef DIAGNOSTIC 723 int bus, dev, fun; 724 725 rmixl_pcix_decompose_tag(v, tag, &bus, &dev, &fun); 726 printf("%s: %d/%d/%d, offset %#x: bad address\n", 727 __func__, bus, dev, fun, offset); 728 #endif 729 rv = (pcireg_t) -1; 730 } 731 rmixl_cache_err_restore(cfg0); 732 } else { 733 rv = -1; 734 } 735 736 mutex_exit(&sc->sc_mutex); 737 738 return rv; 739 } 740 741 void 742 rmixl_pcix_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 743 { 744 rmixl_pcix_softc_t *sc = v; 745 static bus_space_handle_t bsh; 746 bus_space_tag_t bst; 747 uint64_t cfg0; 748 749 mutex_enter(&sc->sc_mutex); 750 751 if (rmixl_pcix_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) { 752 cfg0 = rmixl_cache_err_dis(); 753 bus_space_write_4(bst, bsh, (bus_size_t)offset, val); 754 if (rmixl_cache_err_check() != 0) { 755 #ifdef DIAGNOSTIC 756 int bus, dev, fun; 757 758 rmixl_pcix_decompose_tag(v, tag, &bus, &dev, &fun); 759 printf("%s: %d/%d/%d, offset %#x: bad address\n", 760 __func__, bus, dev, fun, offset); 761 #endif 762 } 763 rmixl_cache_err_restore(cfg0); 764 } 765 766 mutex_exit(&sc->sc_mutex); 767 } 768 769 int 770 rmixl_pcix_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *pih) 771 { 772 const u_int irq = 16; /* PCIX index in IRT */ 773 774 #ifdef DEBUG 775 DPRINTF(("%s: ps_bus %d, pa_intrswiz %#x, pa_intrtag %#lx," 776 " pa_intrpin %d, pa_intrline %d, pa_rawintrpin %d\n", 777 __func__, pa->pa_bus, pa->pa_intrswiz, pa->pa_intrtag, 778 pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 779 #endif 780 781 if (pa->pa_intrpin != PCI_INTERRUPT_PIN_NONE) 782 *pih = rmixl_pcix_make_pih(pa->pa_intrpin - 1, irq); 783 else 784 *pih = ~0; 785 786 return 0; 787 } 788 789 const char * 790 rmixl_pcix_intr_string(void *v, pci_intr_handle_t pih) 791 { 792 u_int bitno, irq; 793 794 rmixl_pcix_decompose_pih(pih, &bitno, &irq); 795 796 if (! cpu_rmixlr(mips_options.mips_cpu)) 797 panic("%s: cpu %#x not supported\n", 798 __func__, mips_options.mips_cpu_id); 799 800 return rmixl_intr_string(RMIXL_IRT_VECTOR(irq)); 801 } 802 803 const struct evcnt * 804 rmixl_pcix_intr_evcnt(void *v, pci_intr_handle_t pih) 805 { 806 return NULL; 807 } 808 809 static pci_intr_handle_t 810 rmixl_pcix_make_pih(u_int bitno, u_int irq) 811 { 812 pci_intr_handle_t pih; 813 814 KASSERT(bitno < 64); 815 KASSERT(irq < 32); 816 817 pih = (irq << 6); 818 pih |= bitno; 819 820 return pih; 821 } 822 823 static void 824 rmixl_pcix_decompose_pih(pci_intr_handle_t pih, u_int *bitno, u_int *irq) 825 { 826 *bitno = (u_int)(pih & 0x3f); 827 *irq = (u_int)(pih >> 6); 828 829 KASSERT(*bitno < 64); 830 KASSERT(*irq < 31); 831 } 832 833 static void 834 rmixl_pcix_intr_disestablish(void *v, void *ih) 835 { 836 rmixl_pcix_softc_t *sc = v; 837 rmixl_pcix_dispatch_t *dip = ih; 838 rmixl_pcix_intr_t *pip = sc->sc_intr; 839 bool busy; 840 841 DPRINTF(("%s: pin=%d irq=%d\n", 842 __func__, dip->bitno + 1, dip->irq)); 843 KASSERT(dip->bitno < RMIXL_PCIX_NINTR); 844 845 mutex_enter(&sc->sc_mutex); 846 847 dip->func = NULL; /* prevent further dispatch */ 848 849 /* 850 * if no other dispatch handle is using this interrupt, 851 * we can disable it 852 */ 853 busy = false; 854 for (int i=0; i < pip->dispatch_count; i++) { 855 rmixl_pcix_dispatch_t *d = &pip->dispatch_data[i]; 856 if (d == dip) 857 continue; 858 if (d->bitno == dip->bitno) { 859 busy = true; 860 break; 861 } 862 } 863 if (! busy) { 864 uint32_t bit = 1 << (dip->bitno + 2); 865 uint32_t r; 866 867 r = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 868 r |= bit; /* set mask */ 869 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, r); 870 DPRINTF(("%s: disabled pin %d\n", __func__, dip->bitno + 1)); 871 872 pip->intenb &= ~(1 << dip->bitno); 873 874 if ((r & PCIX_INTR_CONTROL_MASK_ALL) == 0) { 875 /* tear down interrupt for this pcix */ 876 rmixl_intr_disestablish(pip->ih); 877 878 /* commit NULL interrupt set */ 879 sc->sc_intr = NULL; 880 881 /* schedule delayed free of the old interrupt set */ 882 rmixl_pcix_pip_free_callout(pip); 883 } 884 } 885 886 mutex_exit(&sc->sc_mutex); 887 } 888 889 static void * 890 rmixl_pcix_intr_establish(void *v, pci_intr_handle_t pih, int ipl, 891 int (*func)(void *), void *arg) 892 { 893 rmixl_pcix_softc_t *sc = v; 894 u_int bitno, irq; 895 rmixl_pcix_intr_t *pip; 896 rmixl_pcix_dispatch_t *dip = NULL; 897 898 if (pih == ~0) { 899 DPRINTF(("%s: bad pih=%#lx, implies PCI_INTERRUPT_PIN_NONE\n", 900 __func__, pih)); 901 return NULL; 902 } 903 904 rmixl_pcix_decompose_pih(pih, &bitno, &irq); 905 DPRINTF(("%s: pin=%d irq=%d\n", __func__, bitno + 1, irq)); 906 907 KASSERT(bitno < RMIXL_PCIX_NINTR); 908 909 /* 910 * all PCI-X device intrs get same ipl 911 */ 912 KASSERT(ipl == IPL_VM); 913 914 mutex_enter(&sc->sc_mutex); 915 916 pip = rmixl_pcix_pip_add_1(sc, irq, ipl); 917 if (pip == NULL) 918 return NULL; 919 920 /* 921 * initializae our new interrupt, the last element in dispatch_data[] 922 */ 923 dip = &pip->dispatch_data[pip->dispatch_count - 1]; 924 dip->bitno = bitno; 925 dip->irq = irq; 926 dip->func = func; 927 dip->arg = arg; 928 dip->counts = RMIXL_PCIX_EVCNT(sc, bitno, 0); 929 #if NEVER 930 snprintf(dip->count_name, sizeof(dip->count_name), 931 "pin %d", bitno + 1); 932 evcnt_attach_dynamic(&dip->count, EVCNT_TYPE_INTR, NULL, 933 "rmixl_pcix", dip->count_name); 934 #endif 935 936 /* commit the new interrupt set */ 937 sc->sc_intr = pip; 938 939 /* enable this interrupt in the PCIX controller, if necessary */ 940 if ((pip->intenb & (1 << bitno)) == 0) { 941 uint32_t bit = 1 << (bitno + 2); 942 uint32_t r; 943 944 r = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 945 r &= ~bit; /* clear mask */ 946 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, r); 947 948 pip->sc = sc; 949 pip->ipl = ipl; 950 pip->intenb |= 1 << bitno; 951 DPRINTF(("%s: enabled pin %d\n", __func__, bitno + 1)); 952 } 953 954 mutex_exit(&sc->sc_mutex); 955 return dip; 956 } 957 958 rmixl_pcix_intr_t * 959 rmixl_pcix_pip_add_1(rmixl_pcix_softc_t *sc, int irq, int ipl) 960 { 961 rmixl_pcix_intr_t *pip_old = sc->sc_intr; 962 rmixl_pcix_intr_t *pip_new; 963 u_int dispatch_count; 964 size_t size; 965 966 dispatch_count = 1; 967 size = sizeof(rmixl_pcix_intr_t); 968 if (pip_old != NULL) { 969 /* 970 * count only those dispatch elements still in use 971 * unused ones will be pruned during copy 972 * i.e. we are "lazy" there is no rmixl_pcix_pip_sub_1 973 */ 974 for (int i=0; i < pip_old->dispatch_count; i++) { 975 if (pip_old->dispatch_data[i].func != NULL) { 976 dispatch_count++; 977 size += sizeof(rmixl_pcix_intr_t); 978 } 979 } 980 } 981 982 /* 983 * allocate and initialize softc intr struct 984 * with one or more dispatch handles 985 */ 986 pip_new = malloc(size, M_DEVBUF, M_NOWAIT|M_ZERO); 987 if (pip_new == NULL) { 988 #ifdef DIAGNOSTIC 989 printf("%s: cannot malloc\n", __func__); 990 #endif 991 return NULL; 992 } 993 994 if (pip_old == NULL) { 995 /* initialize the interrupt struct */ 996 pip_new->sc = sc; 997 pip_new->ipl = ipl; 998 pip_new->ih = rmixl_intr_establish(irq, sc->sc_tmsk, 999 ipl, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH, 1000 rmixl_pcix_intr, pip_new, false); 1001 if (pip_new->ih == NULL) 1002 panic("%s: cannot establish irq %d", __func__, irq); 1003 } else { 1004 /* 1005 * all intrs on a softc get same ipl and sc 1006 * first intr established sets the standard 1007 */ 1008 KASSERT(sc == pip_old->sc); 1009 if (sc != pip_old->sc) { 1010 printf("%s: sc %p mismatch\n", __func__, sc); 1011 free(pip_new, M_DEVBUF); 1012 return NULL; 1013 } 1014 KASSERT (ipl == pip_old->ipl); 1015 if (ipl != pip_old->ipl) { 1016 printf("%s: ipl %d mismatch\n", __func__, ipl); 1017 free(pip_new, M_DEVBUF); 1018 return NULL; 1019 } 1020 /* 1021 * copy pip_old to pip_new, skipping unused dispatch elemets 1022 */ 1023 memcpy(pip_new, pip_old, sizeof(rmixl_pcix_intr_t)); 1024 for (int j=0, i=0; i < pip_old->dispatch_count; i++) { 1025 if (pip_old->dispatch_data[i].func != NULL) { 1026 memcpy(&pip_new->dispatch_data[j], 1027 &pip_old->dispatch_data[i], 1028 sizeof(rmixl_pcix_dispatch_t)); 1029 j++; 1030 } 1031 } 1032 1033 /* 1034 * schedule delayed free of old interrupt set 1035 */ 1036 rmixl_pcix_pip_free_callout(pip_old); 1037 } 1038 pip_new->dispatch_count = dispatch_count; 1039 1040 return pip_new; 1041 } 1042 1043 /* 1044 * delay free of the old interrupt set 1045 * to allow anyone still using it to do so safely 1046 * XXX 2 seconds should be plenty? 1047 */ 1048 static void 1049 rmixl_pcix_pip_free_callout(rmixl_pcix_intr_t *pip) 1050 { 1051 callout_init(&pip->callout, 0); 1052 callout_reset(&pip->callout, 2 * hz, rmixl_pcix_pip_free, pip); 1053 } 1054 1055 static void 1056 rmixl_pcix_pip_free(void *arg) 1057 { 1058 rmixl_pcix_intr_t *pip = arg; 1059 1060 callout_destroy(&pip->callout); 1061 free(pip, M_DEVBUF); 1062 } 1063 1064 static int 1065 rmixl_pcix_intr(void *arg) 1066 { 1067 rmixl_pcix_intr_t *pip = arg; 1068 int rv = 0; 1069 1070 uint32_t status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 1071 DPRINTF(("%s: %#x\n", __func__, status)); 1072 1073 if (status != 0) { 1074 for (int i=0; i < pip->dispatch_count; i++) { 1075 rmixl_pcix_dispatch_t *dip = &pip->dispatch_data[i]; 1076 uint32_t bit = 1 << dip->bitno; 1077 int (*func)(void *) = dip->func; 1078 if ((func != NULL) && (status & bit) != 0) { 1079 (void)(*func)(dip->arg); 1080 dip->counts[cpu_index(curcpu())].evcnt.ev_count++; 1081 rv = 1; 1082 } 1083 } 1084 } 1085 return rv; 1086 } 1087 1088 static int 1089 rmixl_pcix_error_intr(void *arg) 1090 { 1091 rmixl_pcix_softc_t *sc = arg; 1092 uint32_t error_status; 1093 1094 error_status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 1095 1096 #ifdef DIAGNOSTIC 1097 printf("%s: error status %#x\n", __func__, error_status); 1098 #endif 1099 1100 #if DDB 1101 Debugger(); 1102 #endif 1103 1104 /* XXX reset and recover? */ 1105 1106 panic("%s: error %#x\n", device_xname(sc->sc_dev), error_status); 1107 } 1108 1109 /* 1110 * rmixl_physaddr_init_pcix: 1111 * called from rmixl_physaddr_init to get region addrs & sizes 1112 * from PCIX CFG, ECFG, IO, MEM BARs 1113 */ 1114 void 1115 rmixl_physaddr_init_pcix(struct extent *ext) 1116 { 1117 u_long base; 1118 u_long size; 1119 uint32_t r; 1120 1121 r = RMIXL_PCIXREG_READ(RMIXLR_SBC_PCIX_CFG_BAR); 1122 if ((r & RMIXL_PCIX_CFG_BAR_ENB) != 0) { 1123 base = (u_long)(RMIXL_PCIX_CFG_BAR_TO_BA((uint64_t)r) 1124 / (1024 * 1024)); 1125 size = (u_long)RMIXL_PCIX_CFG_SIZE / (1024 * 1024); 1126 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1127 __LINE__, "CFG", r, base * 1024 * 1024, size)); 1128 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1129 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1130 "failed", __func__, ext, base, size, EX_NOWAIT); 1131 } 1132 1133 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_MEM_BAR); 1134 if ((r & RMIXL_PCIX_MEM_BAR_ENB) != 0) { 1135 base = (u_long)(RMIXL_PCIX_MEM_BAR_TO_BA((uint64_t)r) 1136 / (1024 * 1024)); 1137 size = (u_long)(RMIXL_PCIX_MEM_BAR_TO_SIZE((uint64_t)r) 1138 / (1024 * 1024)); 1139 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1140 __LINE__, "MEM", r, base * 1024 * 1024, size)); 1141 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1142 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1143 "failed", __func__, ext, base, size, EX_NOWAIT); 1144 } 1145 1146 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_IO_BAR); 1147 if ((r & RMIXL_PCIX_IO_BAR_ENB) != 0) { 1148 base = (u_long)(RMIXL_PCIX_IO_BAR_TO_BA((uint64_t)r) 1149 / (1024 * 1024)); 1150 size = (u_long)(RMIXL_PCIX_IO_BAR_TO_SIZE((uint64_t)r) 1151 / (1024 * 1024)); 1152 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1153 __LINE__, "IO", r, base * 1024 * 1024, size)); 1154 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1155 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1156 "failed", __func__, ext, base, size, EX_NOWAIT); 1157 } 1158 } 1159 1160 #ifdef DDB 1161 int rmixl_pcix_intr_chk(void); 1162 int 1163 rmixl_pcix_intr_chk(void) 1164 { 1165 uint32_t control, status, error_status; 1166 1167 control = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 1168 status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 1169 error_status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 1170 1171 printf("%s: %#x, %#x, %#x\n", __func__, control, status, error_status); 1172 1173 control |= PCIX_INTR_CONTROL_DIA; 1174 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, control); 1175 1176 control = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 1177 status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 1178 error_status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 1179 1180 printf("%s: %#x, %#x, %#x\n", __func__, control, status, error_status); 1181 1182 return 0; 1183 } 1184 #endif 1185
Indexes created Fri Sep 26 08:10:20 GMT 2025