rmixl_pcix.c revision 1.13.18.1
1 /* $NetBSD: rmixl_pcix.c,v 1.13.18.1 2020/04/13 08:04:00 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * PCI configuration support for RMI XLR SoC 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: rmixl_pcix.c,v 1.13.18.1 2020/04/13 08:04:00 martin Exp $"); 44 45 #include "opt_pci.h" 46 #include "pci.h" 47 48 #include <sys/cdefs.h> 49 50 #include <sys/param.h> 51 #include <sys/bus.h> 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/extent.h> 55 #include <sys/intr.h> 56 #include <sys/malloc.h> 57 #include <sys/kernel.h> /* for 'hz' */ 58 #include <sys/systm.h> 59 60 #include <uvm/uvm_extern.h> 61 62 #include <mips/rmi/rmixlreg.h> 63 #include <mips/rmi/rmixlvar.h> 64 #include <mips/rmi/rmixl_intr.h> 65 #include <mips/rmi/rmixl_pcixvar.h> 66 67 #include <mips/rmi/rmixl_obiovar.h> 68 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pcidevs.h> 71 #include <dev/pci/pciconf.h> 72 73 #ifdef PCI_NETBSD_CONFIGURE 74 #include <mips/cache.h> 75 #endif 76 77 #ifdef PCI_DEBUG 78 int rmixl_pcix_debug = PCI_DEBUG; 79 # define DPRINTF(x) do { if (rmixl_pcix_debug) printf x ; } while (0) 80 #else 81 # define DPRINTF(x) 82 #endif 83 84 #ifndef DDB 85 # define STATIC static 86 #else 87 # define STATIC 88 #endif 89 90 91 /* 92 * XLR PCI-X Extended Configuration Registers 93 * Note: 94 * - MSI-related regs are omitted 95 * - Device mode regs are omitted 96 */ 97 #define RMIXL_PCIX_ECFG_HOST_BAR0_ADDR 0x100 /* Host BAR0 Address */ 98 #define RMIXL_PCIX_ECFG_HOST_BAR1_ADDR 0x104 /* Host BAR1 Address */ 99 #define RMIXL_PCIX_ECFG_HOST_BAR2_ADDR 0x108 /* Host BAR2 Address */ 100 #define RMIXL_PCIX_ECFG_HOST_BAR3_ADDR 0x10c /* Host BAR3 Address */ 101 #define RMIXL_PCIX_ECFG_HOST_BAR4_ADDR 0x110 /* Host BAR4 Address */ 102 #define RMIXL_PCIX_ECFG_HOST_BAR5_ADDR 0x114 /* Host BAR5 Address */ 103 #define RMIXL_PCIX_ECFG_HOST_BAR0_SIZE 0x118 /* Host BAR0 Size */ 104 #define RMIXL_PCIX_ECFG_HOST_BAR1_SIZE 0x11c /* Host BAR1 Size */ 105 #define RMIXL_PCIX_ECFG_HOST_BAR2_SIZE 0x120 /* Host BAR2 Size */ 106 #define RMIXL_PCIX_ECFG_HOST_BAR3_SIZE 0x124 /* Host BAR3 Size */ 107 #define RMIXL_PCIX_ECFG_HOST_BAR4_SIZE 0x128 /* Host BAR4 Size */ 108 #define RMIXL_PCIX_ECFG_HOST_BAR5_SIZE 0x12c /* Host BAR5 Size */ 109 #define RMIXL_PCIX_ECFG_MATCH_BIT_ADDR 0x130 /* Match Bit Address BAR */ 110 #define RMIXL_PCIX_ECFG_MATCH_BIT_SIZE 0x134 /* Match Bit Size BAR */ 111 #define RMIXL_PCIX_ECFG_XLR_CONTROL 0x138 /* XLR Control reg */ 112 #define RMIXL_PCIX_ECFG_INTR_CONTROL 0x13c /* Interrupt Control reg */ 113 #define RMIXL_PCIX_ECFG_INTR_STATUS 0x140 /* Interrupt Status reg */ 114 #define RMIXL_PCIX_ECFG_INTR_ERR_STATUS 0x144 /* Interrupt Error Status reg */ 115 #define RMIXL_PCIX_ECFG_HOST_MODE_STS 0x178 /* Host Mode Status */ 116 #define RMIXL_PCIX_ECFG_XLR_MBLE 0x17c /* XLR Match Byte Lane Enable */ 117 #define RMIXL_PCIX_ECFG_HOST_XROM_ADDR 0x180 /* Host Expansion ROM Address */ 118 #define RMIXL_PCIX_ECFG_HOST_XROM_SIZE 0x184 /* Host Expansion ROM Size */ 119 #define RMIXL_PCIX_ECFG_HOST_MODE_CTL 0x18c /* Host Mode Control */ 120 #define RMIXL_PCIX_ECFG_TXCAL_CTL 0x1a0 /* TX Calibration Preset Control */ 121 #define RMIXL_PCIX_ECFG_TXCAL_COUNT 0x1a4 /* TX Calibration Preset Count */ 122 123 /* 124 * RMIXL_PCIX_ECFG_INTR_CONTROL bit defines 125 */ 126 #define PCIX_INTR_CONTROL_RESV __BITS(31,8) 127 #define PCIX_INTR_CONTROL_MSI1_MASK __BIT(7) 128 #define PCIX_INTR_CONTROL_MSI0_MASK __BIT(6) 129 #define PCIX_INTR_CONTROL_INTD_MASK __BIT(5) 130 #define PCIX_INTR_CONTROL_INTC_MASK __BIT(4) 131 #define PCIX_INTR_CONTROL_INTB_MASK __BIT(3) 132 #define PCIX_INTR_CONTROL_INTA_MASK __BIT(2) 133 #define PCIX_INTR_CONTROL_TMSI __BIT(1) /* Trigger MSI Interrupt */ 134 #define PCIX_INTR_CONTROL_DIA __BIT(0) /* Device Interrupt through INTA Pin */ 135 #define PCIX_INTR_CONTROL_MASK_ALL \ 136 (PCIX_INTR_CONTROL_MSI1_MASK|PCIX_INTR_CONTROL_MSI0_MASK \ 137 |PCIX_INTR_CONTROL_INTD_MASK|PCIX_INTR_CONTROL_INTC_MASK \ 138 |PCIX_INTR_CONTROL_INTB_MASK|PCIX_INTR_CONTROL_INTA_MASK) 139 140 /* 141 * RMIXL_PCIX_ECFG_INTR_STATUS bit defines 142 */ 143 #define PCIX_INTR_STATUS_RESV __BITS(31,6) 144 #define PCIX_INTR_STATUS_MSI1 __BIT(5) 145 #define PCIX_INTR_STATUS_MSI0 __BIT(4) 146 #define PCIX_INTR_STATUS_INTD __BIT(3) 147 #define PCIX_INTR_STATUS_INTC __BIT(2) 148 #define PCIX_INTR_STATUS_INTB __BIT(1) 149 #define PCIX_INTR_STATUS_INTA __BIT(0) 150 151 /* 152 * RMIXL_PCIX_ECFG_INTR_ERR_STATUS bit defines 153 */ 154 #define PCIX_INTR_ERR_STATUS_RESa __BITS(31,5) 155 #define PCIX_INTR_ERR_STATUS_SERR __BIT(4) /* System Error */ 156 #define PCIX_INTR_ERR_STATUS_RESb __BIT(3) 157 #define PCIX_INTR_ERR_STATUS_TE __BIT(2) /* Target Error */ 158 #define PCIX_INTR_ERR_STATUS_IE __BIT(1) /* Initiator Error */ 159 #define PCIX_INTR_ERR_STATUS_RCE __BIT(0) /* Retry Count Expired */ 160 #define PCIX_INTR_ERR_STATUS_RESV \ 161 (PCIX_INTR_ERR_STATUS_RESa|PCIX_INTR_ERR_STATUS_RESb) 162 163 /* 164 * RMIXL_PCIX_ECFG_HOST_MODE_CTL bit defines 165 */ 166 #define PCIX_HOST_MODE_CTL_HDMSTAT __BIT(1) /* Host/Dev Mode status 167 * read-only 168 * 1 = host 169 * 0 = device 170 */ 171 #define PCIX_HOST_MODE_CTL_HOSTSWRST __BIT(0) /* Host soft reset 172 * set to 1 to reset 173 * set to 0 to un-reset 174 */ 175 176 177 #if BYTE_ORDER == BIG_ENDIAN 178 # define RMIXL_PCIXREG_BASE RMIXL_IO_DEV_PCIX_EB 179 #else 180 # define RMIXL_PCIXREG_BASE RMIXL_IO_DEV_PCIX_EL 181 #endif 182 183 #define RMIXL_PCIXREG_VADDR(o) \ 184 (volatile uint32_t *)MIPS_PHYS_TO_KSEG1( \ 185 rmixl_configuration.rc_io_pbase \ 186 + RMIXL_PCIXREG_BASE + (o)) 187 188 #define RMIXL_PCIXREG_READ(o) (*RMIXL_PCIXREG_VADDR(o)) 189 #define RMIXL_PCIXREG_WRITE(o,v) *RMIXL_PCIXREG_VADDR(o) = (v) 190 191 192 #define RMIXL_PCIX_CONCAT3(a,b,c) a ## b ## c 193 #define RMIXL_PCIX_BAR_INIT(reg, bar, size, align) { \ 194 struct extent *ext = rmixl_configuration.rc_phys_ex; \ 195 u_long region_start; \ 196 uint64_t ba; \ 197 int err; \ 198 \ 199 err = extent_alloc(ext, (size), (align), 0UL, EX_NOWAIT, \ 200 ®ion_start); \ 201 if (err != 0) \ 202 panic("%s: extent_alloc(%p, %#lx, %#lx, %#lx, %#x, %p)",\ 203 __func__, ext, size, align, 0UL, EX_NOWAIT, \ 204 ®ion_start); \ 205 ba = (uint64_t)region_start; \ 206 ba *= (1024 * 1024); \ 207 bar = RMIXL_PCIX_CONCAT3(RMIXL_PCIX_,reg,_BAR)(ba, 1); \ 208 DPRINTF(("PCIX %s BAR was not enabled by firmware\n" \ 209 "enabling %s at phys %#" PRIxBUSADDR ", size %lu MB\n", \ 210 __STRING(reg), __STRING(reg), ba, size)); \ 211 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_BRIDGE + \ 212 RMIXL_PCIX_CONCAT3(RMIXLR_SBC_PCIX_,reg,_BAR), bar); \ 213 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + \ 214 RMIXL_PCIX_CONCAT3(RMIXLR_SBC_PCIX_,reg,_BAR)); \ 215 DPRINTF(("%s: %s BAR %#x\n", __func__, __STRING(reg), bar)); \ 216 } 217 218 219 #define RMIXL_PCIX_EVCNT(sc, intrpin, cpu) \ 220 &(sc)->sc_evcnts[(intrpin) * (ncpu) + (cpu)] 221 222 223 static int rmixl_pcix_match(device_t, cfdata_t, void *); 224 static void rmixl_pcix_attach(device_t, device_t, void *); 225 static void rmixl_pcix_init(rmixl_pcix_softc_t *); 226 static void rmixl_pcix_init_errors(rmixl_pcix_softc_t *); 227 static void rmixl_pcix_attach_hook(device_t, device_t, 228 struct pcibus_attach_args *); 229 static void rmixl_pcix_intcfg(rmixl_pcix_softc_t *); 230 static void rmixl_pcix_errata(rmixl_pcix_softc_t *); 231 static void rmixl_conf_interrupt(void *, int, int, int, int, int *); 232 static int rmixl_pcix_bus_maxdevs(void *, int); 233 static pcitag_t rmixl_pcix_make_tag(void *, int, int, int); 234 static void rmixl_pcix_decompose_tag(void *, pcitag_t, int *, int *, int *); 235 void rmixl_pcix_tag_print(const char *restrict, void *, pcitag_t, int, vaddr_t, u_long); 236 static int rmixl_pcix_conf_setup(rmixl_pcix_softc_t *, 237 pcitag_t, int *, bus_space_tag_t *, 238 bus_space_handle_t *); 239 static pcireg_t rmixl_pcix_conf_read(void *, pcitag_t, int); 240 static void rmixl_pcix_conf_write(void *, pcitag_t, int, pcireg_t); 241 242 static int rmixl_pcix_intr_map(const struct pci_attach_args *, 243 pci_intr_handle_t *); 244 static const char * 245 rmixl_pcix_intr_string(void *, pci_intr_handle_t, 246 char *, size_t); 247 static const struct evcnt * 248 rmixl_pcix_intr_evcnt(void *, pci_intr_handle_t); 249 static pci_intr_handle_t 250 rmixl_pcix_make_pih(u_int, u_int); 251 static void rmixl_pcix_decompose_pih(pci_intr_handle_t, u_int *, u_int *); 252 static void rmixl_pcix_intr_disestablish(void *, void *); 253 static void *rmixl_pcix_intr_establish(void *, pci_intr_handle_t, 254 int, int (*)(void *), void *); 255 static rmixl_pcix_intr_t * 256 rmixl_pcix_pip_add_1(rmixl_pcix_softc_t *, int, int); 257 static void rmixl_pcix_pip_free_callout(rmixl_pcix_intr_t *); 258 static void rmixl_pcix_pip_free(void *); 259 static int rmixl_pcix_intr(void *); 260 static int rmixl_pcix_error_intr(void *); 261 262 263 CFATTACH_DECL_NEW(rmixl_pcix, sizeof(rmixl_pcix_softc_t), 264 rmixl_pcix_match, rmixl_pcix_attach, NULL, NULL); 265 266 267 static int rmixl_pcix_found; 268 269 270 static int 271 rmixl_pcix_match(device_t parent, cfdata_t cf, void *aux) 272 { 273 uint32_t r; 274 275 /* 276 * PCI-X interface exists on XLR chips only 277 */ 278 if (! cpu_rmixlr(mips_options.mips_cpu)) 279 return 0; 280 281 /* XXX 282 * for now there is only one PCI-X Interface on chip 283 * and only one chip in the system 284 * this could change with furture RMI XL family designs 285 * or when we have multi-chip systems. 286 */ 287 if (rmixl_pcix_found) 288 return 0; 289 290 /* read Host Mode Control register */ 291 r = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_MODE_CTL); 292 r &= PCIX_HOST_MODE_CTL_HDMSTAT; 293 if (r == 0) 294 return 0; /* strapped for Device Mode */ 295 296 return 1; 297 } 298 299 static void 300 rmixl_pcix_attach(device_t parent, device_t self, void *aux) 301 { 302 rmixl_pcix_softc_t *sc = device_private(self); 303 struct obio_attach_args *obio = aux; 304 struct rmixl_config *rcp = &rmixl_configuration; 305 struct pcibus_attach_args pba; 306 uint32_t bar; 307 308 rmixl_pcix_found = 1; 309 sc->sc_dev = self; 310 sc->sc_29bit_dmat = obio->obio_29bit_dmat; 311 sc->sc_32bit_dmat = obio->obio_32bit_dmat; 312 sc->sc_64bit_dmat = obio->obio_64bit_dmat; 313 sc->sc_tmsk = obio->obio_tmsk; 314 315 aprint_normal(": RMI XLR PCI-X Interface\n"); 316 317 mutex_init(&sc->sc_mutex, MUTEX_DEFAULT, IPL_HIGH); 318 319 rmixl_pcix_intcfg(sc); 320 321 rmixl_pcix_errata(sc); 322 323 /* 324 * check XLR Control Register 325 */ 326 DPRINTF(("%s: XLR_CONTROL=%#x\n", __func__, 327 RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_XLR_CONTROL))); 328 329 /* 330 * HBAR[0] if a 32 bit BAR, or 331 * HBAR[0,1] if a 64 bit BAR pair 332 * must cover all RAM 333 */ 334 extern u_quad_t mem_cluster_maxaddr; 335 uint64_t hbar_addr; 336 uint64_t hbar_size; 337 uint32_t hbar_size_lo, hbar_size_hi; 338 uint32_t hbar_addr_lo, hbar_addr_hi; 339 340 hbar_addr_lo = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR0_ADDR); 341 hbar_addr_hi = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR1_ADDR); 342 hbar_size_lo = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR0_SIZE); 343 hbar_size_hi = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR1_SIZE); 344 345 hbar_addr = (u_quad_t)(hbar_addr_lo & PCI_MAPREG_MEM_ADDR_MASK); 346 hbar_size = hbar_size_lo; 347 if ((hbar_size_lo & PCI_MAPREG_MEM_TYPE_64BIT) != 0) { 348 hbar_addr |= (uint64_t)hbar_addr_hi << 32; 349 hbar_size |= (uint64_t)hbar_size_hi << 32; 350 } 351 if ((hbar_addr != 0) || (hbar_size < mem_cluster_maxaddr)) { 352 int error; 353 354 aprint_error_dev(self, "HostBAR0 addr %#x, size %#x\n", 355 hbar_addr_lo, hbar_size_lo); 356 if ((hbar_size_lo & PCI_MAPREG_MEM_TYPE_64BIT) != 0) 357 aprint_error_dev(self, "HostBAR1 addr %#x, size %#x\n", 358 hbar_addr_hi, hbar_size_hi); 359 aprint_error_dev(self, "WARNING: firmware PCI-X setup error: " 360 "RAM %#"PRIx64"..%#"PRIx64" not accessible by Host BAR, " 361 "enabling DMA bounce buffers\n", 362 hbar_size, mem_cluster_maxaddr-1); 363 364 /* 365 * force use of bouce buffers for inaccessible RAM addrs 366 */ 367 if (hbar_size < ((uint64_t)1 << 32)) { 368 error = bus_dmatag_subregion(sc->sc_32bit_dmat, 369 0, (bus_addr_t)hbar_size, &sc->sc_32bit_dmat, 370 BUS_DMA_NOWAIT); 371 if (error) 372 panic("%s: failed to subregion 32-bit dma tag:" 373 " error %d", __func__, error); 374 sc->sc_64bit_dmat = NULL; 375 } else { 376 error = bus_dmatag_subregion(sc->sc_64bit_dmat, 377 0, (bus_addr_t)hbar_size, &sc->sc_64bit_dmat, 378 BUS_DMA_NOWAIT); 379 if (error) 380 panic("%s: failed to subregion 64-bit dma tag:" 381 " error %d", __func__, error); 382 } 383 } 384 385 /* 386 * check PCI-X interface byteswap setup 387 * ensure 'Match Byte Lane' is disabled 388 */ 389 uint32_t mble; 390 mble = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_XLR_MBLE); 391 #ifdef PCI_DEBUG 392 uint32_t mba, mbs; 393 mba = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_MATCH_BIT_ADDR); 394 mbs = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_MATCH_BIT_SIZE); 395 DPRINTF(("%s: MBLE=%#x, MBA=%#x, MBS=%#x\n", __func__, mble, mba, mbs)); 396 #endif 397 if ((mble & __BIT(40)) != 0) 398 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_XLR_MBLE, 0); 399 400 /* 401 * get PCI config space base addr from SBC PCIe CFG BAR 402 * initialize it if necessary 403 */ 404 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_CFG_BAR); 405 DPRINTF(("%s: PCIX_CFG_BAR %#x\n", __func__, bar)); 406 if ((bar & RMIXL_PCIX_CFG_BAR_ENB) == 0) { 407 u_long n = RMIXL_PCIX_CFG_SIZE / (1024 * 1024); 408 RMIXL_PCIX_BAR_INIT(CFG, bar, n, n); 409 } 410 rcp->rc_pci_cfg_pbase = (bus_addr_t)RMIXL_PCIX_CFG_BAR_TO_BA(bar); 411 rcp->rc_pci_cfg_size = (bus_size_t)RMIXL_PCIX_CFG_SIZE; 412 413 /* 414 * get PCI MEM space base [addr, size] from SBC PCIe MEM BAR 415 * initialize it if necessary 416 */ 417 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_MEM_BAR); 418 DPRINTF(("%s: PCIX_MEM_BAR %#x\n", __func__, bar)); 419 if ((bar & RMIXL_PCIX_MEM_BAR_ENB) == 0) { 420 u_long n = 256; /* 256 MB */ 421 RMIXL_PCIX_BAR_INIT(MEM, bar, n, n); 422 } 423 rcp->rc_pci_mem_pbase = (bus_addr_t)RMIXL_PCIX_MEM_BAR_TO_BA(bar); 424 rcp->rc_pci_mem_size = (bus_size_t)RMIXL_PCIX_MEM_BAR_TO_SIZE(bar); 425 426 /* 427 * get PCI IO space base [addr, size] from SBC PCIe IO BAR 428 * initialize it if necessary 429 */ 430 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_IO_BAR); 431 DPRINTF(("%s: PCIX_IO_BAR %#x\n", __func__, bar)); 432 if ((bar & RMIXL_PCIX_IO_BAR_ENB) == 0) { 433 u_long n = 32; /* 32 MB */ 434 RMIXL_PCIX_BAR_INIT(IO, bar, n, n); 435 } 436 rcp->rc_pci_io_pbase = (bus_addr_t)RMIXL_PCIX_IO_BAR_TO_BA(bar); 437 rcp->rc_pci_io_size = (bus_size_t)RMIXL_PCIX_IO_BAR_TO_SIZE(bar); 438 439 /* 440 * initialize the PCI CFG bus space tag 441 */ 442 rmixl_pci_cfg_bus_mem_init(&rcp->rc_pci_cfg_memt, rcp); 443 sc->sc_pci_cfg_memt = &rcp->rc_pci_cfg_memt; 444 445 /* 446 * initialize the PCI MEM and IO bus space tags 447 */ 448 rmixl_pci_bus_mem_init(&rcp->rc_pci_memt, rcp); 449 rmixl_pci_bus_io_init(&rcp->rc_pci_iot, rcp); 450 451 /* 452 * initialize the extended configuration regs 453 */ 454 rmixl_pcix_init_errors(sc); 455 456 /* 457 * initialize the PCI chipset tag 458 */ 459 rmixl_pcix_init(sc); 460 461 /* 462 * attach the PCI bus 463 */ 464 memset(&pba, 0, sizeof(pba)); 465 pba.pba_memt = &rcp->rc_pci_memt; 466 pba.pba_iot = &rcp->rc_pci_iot; 467 pba.pba_dmat = sc->sc_32bit_dmat; 468 pba.pba_dmat64 = sc->sc_64bit_dmat; 469 pba.pba_pc = &sc->sc_pci_chipset; 470 pba.pba_bus = 0; 471 pba.pba_bridgetag = NULL; 472 pba.pba_intrswiz = 0; 473 pba.pba_intrtag = 0; 474 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY | 475 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 476 477 (void) config_found_ia(self, "pcibus", &pba, pcibusprint); 478 } 479 480 /* 481 * rmixl_pcix_intcfg - init PCI-X interrupt control 482 */ 483 static void 484 rmixl_pcix_intcfg(rmixl_pcix_softc_t *sc) 485 { 486 size_t size; 487 rmixl_pcix_evcnt_t *ev; 488 489 DPRINTF(("%s\n", __func__)); 490 491 /* mask all interrupts until they are established */ 492 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, 493 PCIX_INTR_CONTROL_MASK_ALL); 494 495 /* 496 * read-to-clear any pre-existing interrupts 497 * XXX MSI bits in STATUS are also documented as write 1 to clear in PRM 498 */ 499 (void)RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 500 (void)RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 501 502 /* initialize the (non-error interrupt) dispatch handles */ 503 sc->sc_intr = NULL; 504 505 /* 506 * allocate per-cpu, per-pin interrupt event counters 507 */ 508 size = ncpu * PCI_INTERRUPT_PIN_MAX * sizeof(rmixl_pcix_evcnt_t); 509 ev = malloc(size, M_DEVBUF, M_WAITOK); 510 sc->sc_evcnts = ev; 511 for (int pin=PCI_INTERRUPT_PIN_A; pin <= PCI_INTERRUPT_PIN_MAX; pin++) { 512 for (int cpu=0; cpu < ncpu; cpu++) { 513 ev = RMIXL_PCIX_EVCNT(sc, pin - 1, cpu); 514 snprintf(ev->name, sizeof(ev->name), 515 "cpu%d, pin %d", cpu, pin); 516 evcnt_attach_dynamic(&ev->evcnt, EVCNT_TYPE_INTR, 517 NULL, "rmixl_pcix", ev->name); 518 } 519 } 520 521 /* 522 * establish PCIX error interrupt handler 523 */ 524 sc->sc_fatal_ih = rmixl_intr_establish(24, sc->sc_tmsk, 525 IPL_VM, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH, 526 rmixl_pcix_error_intr, sc, false); 527 if (sc->sc_fatal_ih == NULL) 528 panic("%s: cannot establish irq %d", __func__, 24); 529 } 530 531 static void 532 rmixl_pcix_errata(rmixl_pcix_softc_t *sc) 533 { 534 /* nothing */ 535 } 536 537 static void 538 rmixl_pcix_init(rmixl_pcix_softc_t *sc) 539 { 540 pci_chipset_tag_t pc = &sc->sc_pci_chipset; 541 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 542 struct extent *ioext, *memext; 543 #endif 544 545 pc->pc_conf_v = (void *)sc; 546 pc->pc_attach_hook = rmixl_pcix_attach_hook; 547 pc->pc_bus_maxdevs = rmixl_pcix_bus_maxdevs; 548 pc->pc_make_tag = rmixl_pcix_make_tag; 549 pc->pc_decompose_tag = rmixl_pcix_decompose_tag; 550 pc->pc_conf_read = rmixl_pcix_conf_read; 551 pc->pc_conf_write = rmixl_pcix_conf_write; 552 553 pc->pc_intr_v = (void *)sc; 554 pc->pc_intr_map = rmixl_pcix_intr_map; 555 pc->pc_intr_string = rmixl_pcix_intr_string; 556 pc->pc_intr_evcnt = rmixl_pcix_intr_evcnt; 557 pc->pc_intr_establish = rmixl_pcix_intr_establish; 558 pc->pc_intr_disestablish = rmixl_pcix_intr_disestablish; 559 pc->pc_conf_interrupt = rmixl_conf_interrupt; 560 561 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 562 /* 563 * Configure the PCI bus. 564 */ 565 struct rmixl_config *rcp = &rmixl_configuration; 566 567 aprint_normal_dev(sc->sc_dev, "%s: configuring PCI bus\n"); 568 569 ioext = extent_create("pciio", 570 rcp->rc_pci_io_pbase, 571 rcp->rc_pci_io_pbase + rcp->rc_pci_io_size - 1, 572 M_DEVBUF, NULL, 0, EX_NOWAIT); 573 574 memext = extent_create("pcimem", 575 rcp->rc_pci_mem_pbase, 576 rcp->rc_pci_mem_pbase + rcp->rc_pci_mem_size - 1, 577 M_DEVBUF, NULL, 0, EX_NOWAIT); 578 579 pci_configure_bus(pc, ioext, memext, NULL, 0, 580 mips_cache_info.mci_dcache_align); 581 582 extent_destroy(ioext); 583 extent_destroy(memext); 584 #endif 585 } 586 587 static void 588 rmixl_pcix_init_errors(rmixl_pcix_softc_t *sc) 589 { 590 /* nothing */ 591 } 592 593 void 594 rmixl_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *iline) 595 { 596 DPRINTF(("%s: %p, %d, %d, %d, %d, %p\n", 597 __func__, v, bus, dev, ipin, swiz, iline)); 598 } 599 600 void 601 rmixl_pcix_attach_hook(device_t parent, device_t self, 602 struct pcibus_attach_args *pba) 603 { 604 DPRINTF(("%s: pba_bus %d, pba_bridgetag %p, pc_conf_v %p\n", 605 __func__, pba->pba_bus, pba->pba_bridgetag, 606 pba->pba_pc->pc_conf_v)); 607 } 608 609 int 610 rmixl_pcix_bus_maxdevs(void *v, int busno) 611 { 612 return (32); /* XXX depends on the family of XLS SoC */ 613 } 614 615 /* 616 * XLS pci tag is a 40 bit address composed thusly: 617 * 39:25 (reserved) 618 * 24 Swap (0=little, 1=big endian) 619 * 23:16 Bus number 620 * 15:11 Device number 621 * 10:8 Function number 622 * 7:0 Register number 623 * 624 * Note: this is the "native" composition for addressing CFG space, but not for ECFG space. 625 */ 626 pcitag_t 627 rmixl_pcix_make_tag(void *v, int bus, int dev, int fun) 628 { 629 return ((bus << 16) | (dev << 11) | (fun << 8)); 630 } 631 632 void 633 rmixl_pcix_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 634 { 635 if (bp != NULL) 636 *bp = (tag >> 16) & 0xff; 637 if (dp != NULL) 638 *dp = (tag >> 11) & 0x1f; 639 if (fp != NULL) 640 *fp = (tag >> 8) & 0x7; 641 } 642 643 void 644 rmixl_pcix_tag_print(const char *restrict s, void *v, pcitag_t tag, int offset, 645 vaddr_t va, u_long r) 646 { 647 int bus, dev, fun; 648 649 rmixl_pcix_decompose_tag(v, tag, &bus, &dev, &fun); 650 printf("%s: %d/%d/%d/%d - %#" PRIxVADDR ":%#lx\n", 651 s, bus, dev, fun, offset, va, r); 652 } 653 654 static int 655 rmixl_pcix_conf_setup(rmixl_pcix_softc_t *sc, 656 pcitag_t tag, int *offp, bus_space_tag_t *bstp, 657 bus_space_handle_t *bshp) 658 { 659 struct rmixl_config *rcp = &rmixl_configuration; 660 bus_space_tag_t bst; 661 bus_space_handle_t bsh; 662 bus_size_t size; 663 pcitag_t mask; 664 bus_addr_t ba; 665 int err; 666 static bus_space_handle_t cfg_bsh; 667 static bus_addr_t cfg_oba = -1; 668 669 /* 670 * bus space depends on offset 671 */ 672 if ((*offp >= 0) && (*offp < 0x100)) { 673 mask = __BITS(15,0); 674 bst = sc->sc_pci_cfg_memt; 675 ba = rcp->rc_pci_cfg_pbase; 676 ba += (tag & ~mask); 677 *offp += (tag & mask); 678 if (ba != cfg_oba) { 679 size = (bus_size_t)(mask + 1); 680 if (cfg_oba != -1) 681 bus_space_unmap(bst, cfg_bsh, size); 682 err = bus_space_map(bst, ba, size, 0, &cfg_bsh); 683 if (err != 0) { 684 #ifdef DEBUG 685 panic("%s: bus_space_map err %d, CFG space", 686 __func__, err); /* XXX */ 687 #endif 688 return -1; 689 } 690 cfg_oba = ba; 691 } 692 bsh = cfg_bsh; 693 } else { 694 return -1; 695 } 696 697 *bstp = bst; 698 *bshp = bsh; 699 700 return 0; 701 } 702 703 pcireg_t 704 rmixl_pcix_conf_read(void *v, pcitag_t tag, int offset) 705 { 706 rmixl_pcix_softc_t *sc = v; 707 static bus_space_handle_t bsh; 708 bus_space_tag_t bst; 709 pcireg_t rv; 710 uint64_t cfg0; 711 712 mutex_enter(&sc->sc_mutex); 713 714 if (rmixl_pcix_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) { 715 cfg0 = rmixl_cache_err_dis(); 716 rv = bus_space_read_4(bst, bsh, (bus_size_t)offset); 717 if (rmixl_cache_err_check() != 0) { 718 #ifdef DIAGNOSTIC 719 int bus, dev, fun; 720 721 rmixl_pcix_decompose_tag(v, tag, &bus, &dev, &fun); 722 printf("%s: %d/%d/%d, offset %#x: bad address\n", 723 __func__, bus, dev, fun, offset); 724 #endif 725 rv = (pcireg_t) -1; 726 } 727 rmixl_cache_err_restore(cfg0); 728 } else { 729 rv = -1; 730 } 731 732 mutex_exit(&sc->sc_mutex); 733 734 return rv; 735 } 736 737 void 738 rmixl_pcix_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 739 { 740 rmixl_pcix_softc_t *sc = v; 741 static bus_space_handle_t bsh; 742 bus_space_tag_t bst; 743 uint64_t cfg0; 744 745 mutex_enter(&sc->sc_mutex); 746 747 if (rmixl_pcix_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) { 748 cfg0 = rmixl_cache_err_dis(); 749 bus_space_write_4(bst, bsh, (bus_size_t)offset, val); 750 if (rmixl_cache_err_check() != 0) { 751 #ifdef DIAGNOSTIC 752 int bus, dev, fun; 753 754 rmixl_pcix_decompose_tag(v, tag, &bus, &dev, &fun); 755 printf("%s: %d/%d/%d, offset %#x: bad address\n", 756 __func__, bus, dev, fun, offset); 757 #endif 758 } 759 rmixl_cache_err_restore(cfg0); 760 } 761 762 mutex_exit(&sc->sc_mutex); 763 } 764 765 int 766 rmixl_pcix_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *pih) 767 { 768 const u_int irq = 16; /* PCIX index in IRT */ 769 770 #ifdef DEBUG 771 DPRINTF(("%s: ps_bus %d, pa_intrswiz %#x, pa_intrtag %#lx," 772 " pa_intrpin %d, pa_intrline %d, pa_rawintrpin %d\n", 773 __func__, pa->pa_bus, pa->pa_intrswiz, pa->pa_intrtag, 774 pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 775 #endif 776 777 if (pa->pa_intrpin != PCI_INTERRUPT_PIN_NONE) 778 *pih = rmixl_pcix_make_pih(pa->pa_intrpin - 1, irq); 779 else 780 *pih = ~0; 781 782 return 0; 783 } 784 785 const char * 786 rmixl_pcix_intr_string(void *v, pci_intr_handle_t pih, char *buf, size_t len) 787 { 788 u_int bitno, irq; 789 790 rmixl_pcix_decompose_pih(pih, &bitno, &irq); 791 792 if (! cpu_rmixlr(mips_options.mips_cpu)) 793 panic("%s: cpu %#x not supported\n", 794 __func__, mips_options.mips_cpu_id); 795 796 strlcpy(buf, rmixl_intr_string(RMIXL_IRT_VECTOR(irq)), len); 797 return buf; 798 } 799 800 const struct evcnt * 801 rmixl_pcix_intr_evcnt(void *v, pci_intr_handle_t pih) 802 { 803 return NULL; 804 } 805 806 static pci_intr_handle_t 807 rmixl_pcix_make_pih(u_int bitno, u_int irq) 808 { 809 pci_intr_handle_t pih; 810 811 KASSERT(bitno < 64); 812 KASSERT(irq < 32); 813 814 pih = (irq << 6); 815 pih |= bitno; 816 817 return pih; 818 } 819 820 static void 821 rmixl_pcix_decompose_pih(pci_intr_handle_t pih, u_int *bitno, u_int *irq) 822 { 823 *bitno = (u_int)(pih & 0x3f); 824 *irq = (u_int)(pih >> 6); 825 826 KASSERT(*bitno < 64); 827 KASSERT(*irq < 31); 828 } 829 830 static void 831 rmixl_pcix_intr_disestablish(void *v, void *ih) 832 { 833 rmixl_pcix_softc_t *sc = v; 834 rmixl_pcix_dispatch_t *dip = ih; 835 rmixl_pcix_intr_t *pip = sc->sc_intr; 836 bool busy; 837 838 DPRINTF(("%s: pin=%d irq=%d\n", 839 __func__, dip->bitno + 1, dip->irq)); 840 KASSERT(dip->bitno < RMIXL_PCIX_NINTR); 841 842 mutex_enter(&sc->sc_mutex); 843 844 dip->func = NULL; /* prevent further dispatch */ 845 846 /* 847 * if no other dispatch handle is using this interrupt, 848 * we can disable it 849 */ 850 busy = false; 851 for (int i=0; i < pip->dispatch_count; i++) { 852 rmixl_pcix_dispatch_t *d = &pip->dispatch_data[i]; 853 if (d == dip) 854 continue; 855 if (d->bitno == dip->bitno) { 856 busy = true; 857 break; 858 } 859 } 860 if (! busy) { 861 uint32_t bit = 1 << (dip->bitno + 2); 862 uint32_t r; 863 864 r = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 865 r |= bit; /* set mask */ 866 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, r); 867 DPRINTF(("%s: disabled pin %d\n", __func__, dip->bitno + 1)); 868 869 pip->intenb &= ~(1 << dip->bitno); 870 871 if ((r & PCIX_INTR_CONTROL_MASK_ALL) == 0) { 872 /* tear down interrupt for this pcix */ 873 rmixl_intr_disestablish(pip->ih); 874 875 /* commit NULL interrupt set */ 876 sc->sc_intr = NULL; 877 878 /* schedule delayed free of the old interrupt set */ 879 rmixl_pcix_pip_free_callout(pip); 880 } 881 } 882 883 mutex_exit(&sc->sc_mutex); 884 } 885 886 static void * 887 rmixl_pcix_intr_establish(void *v, pci_intr_handle_t pih, int ipl, 888 int (*func)(void *), void *arg) 889 { 890 rmixl_pcix_softc_t *sc = v; 891 u_int bitno, irq; 892 rmixl_pcix_intr_t *pip; 893 rmixl_pcix_dispatch_t *dip = NULL; 894 895 if (pih == ~0) { 896 DPRINTF(("%s: bad pih=%#lx, implies PCI_INTERRUPT_PIN_NONE\n", 897 __func__, pih)); 898 return NULL; 899 } 900 901 rmixl_pcix_decompose_pih(pih, &bitno, &irq); 902 DPRINTF(("%s: pin=%d irq=%d\n", __func__, bitno + 1, irq)); 903 904 KASSERT(bitno < RMIXL_PCIX_NINTR); 905 906 /* 907 * all PCI-X device intrs get same ipl 908 */ 909 KASSERT(ipl == IPL_VM); 910 911 mutex_enter(&sc->sc_mutex); 912 913 pip = rmixl_pcix_pip_add_1(sc, irq, ipl); 914 if (pip == NULL) 915 return NULL; 916 917 /* 918 * initializae our new interrupt, the last element in dispatch_data[] 919 */ 920 dip = &pip->dispatch_data[pip->dispatch_count - 1]; 921 dip->bitno = bitno; 922 dip->irq = irq; 923 dip->func = func; 924 dip->arg = arg; 925 dip->counts = RMIXL_PCIX_EVCNT(sc, bitno, 0); 926 #if NEVER 927 snprintf(dip->count_name, sizeof(dip->count_name), 928 "pin %d", bitno + 1); 929 evcnt_attach_dynamic(&dip->count, EVCNT_TYPE_INTR, NULL, 930 "rmixl_pcix", dip->count_name); 931 #endif 932 933 /* commit the new interrupt set */ 934 sc->sc_intr = pip; 935 936 /* enable this interrupt in the PCIX controller, if necessary */ 937 if ((pip->intenb & (1 << bitno)) == 0) { 938 uint32_t bit = 1 << (bitno + 2); 939 uint32_t r; 940 941 r = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 942 r &= ~bit; /* clear mask */ 943 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, r); 944 945 pip->sc = sc; 946 pip->ipl = ipl; 947 pip->intenb |= 1 << bitno; 948 DPRINTF(("%s: enabled pin %d\n", __func__, bitno + 1)); 949 } 950 951 mutex_exit(&sc->sc_mutex); 952 return dip; 953 } 954 955 rmixl_pcix_intr_t * 956 rmixl_pcix_pip_add_1(rmixl_pcix_softc_t *sc, int irq, int ipl) 957 { 958 rmixl_pcix_intr_t *pip_old = sc->sc_intr; 959 rmixl_pcix_intr_t *pip_new; 960 u_int dispatch_count; 961 size_t size; 962 963 dispatch_count = 1; 964 size = sizeof(rmixl_pcix_intr_t); 965 if (pip_old != NULL) { 966 /* 967 * count only those dispatch elements still in use 968 * unused ones will be pruned during copy 969 * i.e. we are "lazy" there is no rmixl_pcix_pip_sub_1 970 */ 971 for (int i=0; i < pip_old->dispatch_count; i++) { 972 if (pip_old->dispatch_data[i].func != NULL) { 973 dispatch_count++; 974 size += sizeof(rmixl_pcix_intr_t); 975 } 976 } 977 } 978 979 /* 980 * allocate and initialize softc intr struct 981 * with one or more dispatch handles 982 */ 983 pip_new = malloc(size, M_DEVBUF, M_WAITOK|M_ZERO); 984 if (pip_old == NULL) { 985 /* initialize the interrupt struct */ 986 pip_new->sc = sc; 987 pip_new->ipl = ipl; 988 pip_new->ih = rmixl_intr_establish(irq, sc->sc_tmsk, 989 ipl, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH, 990 rmixl_pcix_intr, pip_new, false); 991 if (pip_new->ih == NULL) 992 panic("%s: cannot establish irq %d", __func__, irq); 993 } else { 994 /* 995 * all intrs on a softc get same ipl and sc 996 * first intr established sets the standard 997 */ 998 KASSERT(sc == pip_old->sc); 999 if (sc != pip_old->sc) { 1000 printf("%s: sc %p mismatch\n", __func__, sc); 1001 free(pip_new, M_DEVBUF); 1002 return NULL; 1003 } 1004 KASSERT (ipl == pip_old->ipl); 1005 if (ipl != pip_old->ipl) { 1006 printf("%s: ipl %d mismatch\n", __func__, ipl); 1007 free(pip_new, M_DEVBUF); 1008 return NULL; 1009 } 1010 /* 1011 * copy pip_old to pip_new, skipping unused dispatch elemets 1012 */ 1013 memcpy(pip_new, pip_old, sizeof(rmixl_pcix_intr_t)); 1014 for (int j=0, i=0; i < pip_old->dispatch_count; i++) { 1015 if (pip_old->dispatch_data[i].func != NULL) { 1016 memcpy(&pip_new->dispatch_data[j], 1017 &pip_old->dispatch_data[i], 1018 sizeof(rmixl_pcix_dispatch_t)); 1019 j++; 1020 } 1021 } 1022 1023 /* 1024 * schedule delayed free of old interrupt set 1025 */ 1026 rmixl_pcix_pip_free_callout(pip_old); 1027 } 1028 pip_new->dispatch_count = dispatch_count; 1029 1030 return pip_new; 1031 } 1032 1033 /* 1034 * delay free of the old interrupt set 1035 * to allow anyone still using it to do so safely 1036 * XXX 2 seconds should be plenty? 1037 */ 1038 static void 1039 rmixl_pcix_pip_free_callout(rmixl_pcix_intr_t *pip) 1040 { 1041 callout_init(&pip->callout, 0); 1042 callout_reset(&pip->callout, 2 * hz, rmixl_pcix_pip_free, pip); 1043 } 1044 1045 static void 1046 rmixl_pcix_pip_free(void *arg) 1047 { 1048 rmixl_pcix_intr_t *pip = arg; 1049 1050 callout_destroy(&pip->callout); 1051 free(pip, M_DEVBUF); 1052 } 1053 1054 static int 1055 rmixl_pcix_intr(void *arg) 1056 { 1057 rmixl_pcix_intr_t *pip = arg; 1058 int rv = 0; 1059 1060 uint32_t status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 1061 DPRINTF(("%s: %#x\n", __func__, status)); 1062 1063 if (status != 0) { 1064 for (int i=0; i < pip->dispatch_count; i++) { 1065 rmixl_pcix_dispatch_t *dip = &pip->dispatch_data[i]; 1066 uint32_t bit = 1 << dip->bitno; 1067 int (*func)(void *) = dip->func; 1068 if ((func != NULL) && (status & bit) != 0) { 1069 (void)(*func)(dip->arg); 1070 dip->counts[cpu_index(curcpu())].evcnt.ev_count++; 1071 rv = 1; 1072 } 1073 } 1074 } 1075 return rv; 1076 } 1077 1078 static int 1079 rmixl_pcix_error_intr(void *arg) 1080 { 1081 rmixl_pcix_softc_t *sc = arg; 1082 uint32_t error_status; 1083 1084 error_status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 1085 1086 #ifdef DIAGNOSTIC 1087 printf("%s: error status %#x\n", __func__, error_status); 1088 #endif 1089 1090 #if DDB 1091 Debugger(); 1092 #endif 1093 1094 /* XXX reset and recover? */ 1095 1096 panic("%s: error %#x\n", device_xname(sc->sc_dev), error_status); 1097 } 1098 1099 /* 1100 * rmixl_physaddr_init_pcix: 1101 * called from rmixl_physaddr_init to get region addrs & sizes 1102 * from PCIX CFG, ECFG, IO, MEM BARs 1103 */ 1104 void 1105 rmixl_physaddr_init_pcix(struct extent *ext) 1106 { 1107 u_long base; 1108 u_long size; 1109 uint32_t r; 1110 1111 r = RMIXL_PCIXREG_READ(RMIXLR_SBC_PCIX_CFG_BAR); 1112 if ((r & RMIXL_PCIX_CFG_BAR_ENB) != 0) { 1113 base = (u_long)(RMIXL_PCIX_CFG_BAR_TO_BA((uint64_t)r) 1114 / (1024 * 1024)); 1115 size = (u_long)RMIXL_PCIX_CFG_SIZE / (1024 * 1024); 1116 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1117 __LINE__, "CFG", r, base * 1024 * 1024, size)); 1118 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1119 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1120 "failed", __func__, ext, base, size, EX_NOWAIT); 1121 } 1122 1123 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_MEM_BAR); 1124 if ((r & RMIXL_PCIX_MEM_BAR_ENB) != 0) { 1125 base = (u_long)(RMIXL_PCIX_MEM_BAR_TO_BA((uint64_t)r) 1126 / (1024 * 1024)); 1127 size = (u_long)(RMIXL_PCIX_MEM_BAR_TO_SIZE((uint64_t)r) 1128 / (1024 * 1024)); 1129 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1130 __LINE__, "MEM", r, base * 1024 * 1024, size)); 1131 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1132 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1133 "failed", __func__, ext, base, size, EX_NOWAIT); 1134 } 1135 1136 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_IO_BAR); 1137 if ((r & RMIXL_PCIX_IO_BAR_ENB) != 0) { 1138 base = (u_long)(RMIXL_PCIX_IO_BAR_TO_BA((uint64_t)r) 1139 / (1024 * 1024)); 1140 size = (u_long)(RMIXL_PCIX_IO_BAR_TO_SIZE((uint64_t)r) 1141 / (1024 * 1024)); 1142 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1143 __LINE__, "IO", r, base * 1024 * 1024, size)); 1144 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1145 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1146 "failed", __func__, ext, base, size, EX_NOWAIT); 1147 } 1148 } 1149 1150 #ifdef DDB 1151 int rmixl_pcix_intr_chk(void); 1152 int 1153 rmixl_pcix_intr_chk(void) 1154 { 1155 uint32_t control, status, error_status; 1156 1157 control = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 1158 status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 1159 error_status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 1160 1161 printf("%s: %#x, %#x, %#x\n", __func__, control, status, error_status); 1162 1163 control |= PCIX_INTR_CONTROL_DIA; 1164 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, control); 1165 1166 control = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 1167 status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 1168 error_status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 1169 1170 printf("%s: %#x, %#x, %#x\n", __func__, control, status, error_status); 1171 1172 return 0; 1173 } 1174 #endif 1175
Indexes created Tue Oct 21 16:10:11 GMT 2025