rmixl_pcix.c revision 1.2.2.2
1 /* $NetBSD: rmixl_pcix.c,v 1.2.2.2 2011/03/05 20:51:11 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * PCI configuration support for RMI XLR SoC 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: rmixl_pcix.c,v 1.2.2.2 2011/03/05 20:51:11 rmind Exp $"); 44 45 #include "opt_pci.h" 46 #include "pci.h" 47 48 #include <sys/cdefs.h> 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/device.h> 53 #include <sys/extent.h> 54 #include <sys/malloc.h> 55 #include <sys/kernel.h> /* for 'hz' */ 56 #include <sys/cpu.h> 57 58 #include <uvm/uvm_extern.h> 59 60 #include <machine/bus.h> 61 #include <machine/intr.h> 62 63 #include <mips/rmi/rmixlreg.h> 64 #include <mips/rmi/rmixlvar.h> 65 #include <mips/rmi/rmixl_intr.h> 66 #include <mips/rmi/rmixl_pcixvar.h> 67 68 #include <mips/rmi/rmixl_obiovar.h> 69 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcidevs.h> 72 #include <dev/pci/pciconf.h> 73 74 #ifdef PCI_NETBSD_CONFIGURE 75 #include <mips/cache.h> 76 #endif 77 78 #include <machine/pci_machdep.h> 79 80 #ifdef PCI_DEBUG 81 int rmixl_pcix_debug = PCI_DEBUG; 82 # define DPRINTF(x) do { if (rmixl_pcix_debug) printf x ; } while (0) 83 #else 84 # define DPRINTF(x) 85 #endif 86 87 #ifndef DDB 88 # define STATIC static 89 #else 90 # define STATIC 91 #endif 92 93 94 /* 95 * XLR PCI-X Extended Configuration Registers 96 * Note: 97 * - MSI-related regs are omitted 98 * - Device mode regs are omitted 99 */ 100 #define RMIXL_PCIX_ECFG_HOST_BAR0_ADDR 0x100 /* Host BAR0 Address */ 101 #define RMIXL_PCIX_ECFG_HOST_BAR1_ADDR 0x104 /* Host BAR1 Address */ 102 #define RMIXL_PCIX_ECFG_HOST_BAR2_ADDR 0x108 /* Host BAR2 Address */ 103 #define RMIXL_PCIX_ECFG_HOST_BAR3_ADDR 0x10c /* Host BAR3 Address */ 104 #define RMIXL_PCIX_ECFG_HOST_BAR4_ADDR 0x110 /* Host BAR4 Address */ 105 #define RMIXL_PCIX_ECFG_HOST_BAR5_ADDR 0x114 /* Host BAR5 Address */ 106 #define RMIXL_PCIX_ECFG_HOST_BAR0_SIZE 0x118 /* Host BAR0 Size */ 107 #define RMIXL_PCIX_ECFG_HOST_BAR1_SIZE 0x11c /* Host BAR1 Size */ 108 #define RMIXL_PCIX_ECFG_HOST_BAR2_SIZE 0x120 /* Host BAR2 Size */ 109 #define RMIXL_PCIX_ECFG_HOST_BAR3_SIZE 0x124 /* Host BAR3 Size */ 110 #define RMIXL_PCIX_ECFG_HOST_BAR4_SIZE 0x128 /* Host BAR4 Size */ 111 #define RMIXL_PCIX_ECFG_HOST_BAR5_SIZE 0x12c /* Host BAR5 Size */ 112 #define RMIXL_PCIX_ECFG_MATCH_BIT_ADDR 0x130 /* Match Bit Address BAR */ 113 #define RMIXL_PCIX_ECFG_MATCH_BIT_SIZE 0x134 /* Match Bit Size BAR */ 114 #define RMIXL_PCIX_ECFG_XLR_CONTROL 0x138 /* XLR Control reg */ 115 #define RMIXL_PCIX_ECFG_INTR_CONTROL 0x13c /* Interrupt Control reg */ 116 #define RMIXL_PCIX_ECFG_INTR_STATUS 0x140 /* Interrupt Status reg */ 117 #define RMIXL_PCIX_ECFG_INTR_ERR_STATUS 0x144 /* Interrupt Error Status reg */ 118 #define RMIXL_PCIX_ECFG_HOST_MODE_STS 0x178 /* Host Mode Status */ 119 #define RMIXL_PCIX_ECFG_XLR_MBLE 0x17c /* XLR Match Byte Lane Enable */ 120 #define RMIXL_PCIX_ECFG_HOST_XROM_ADDR 0x180 /* Host Expansion ROM Address */ 121 #define RMIXL_PCIX_ECFG_HOST_XROM_SIZE 0x184 /* Host Expansion ROM Size */ 122 #define RMIXL_PCIX_ECFG_HOST_MODE_CTL 0x18c /* Host Mode Control */ 123 #define RMIXL_PCIX_ECFG_TXCAL_CTL 0x1a0 /* TX Calibration Preset Control */ 124 #define RMIXL_PCIX_ECFG_TXCAL_COUNT 0x1a4 /* TX Calibration Preset Count */ 125 126 /* 127 * RMIXL_PCIX_ECFG_INTR_CONTROL bit defines 128 */ 129 #define PCIX_INTR_CONTROL_RESV __BITS(31,8) 130 #define PCIX_INTR_CONTROL_MSI1_MASK __BIT(7) 131 #define PCIX_INTR_CONTROL_MSI0_MASK __BIT(6) 132 #define PCIX_INTR_CONTROL_INTD_MASK __BIT(5) 133 #define PCIX_INTR_CONTROL_INTC_MASK __BIT(4) 134 #define PCIX_INTR_CONTROL_INTB_MASK __BIT(3) 135 #define PCIX_INTR_CONTROL_INTA_MASK __BIT(2) 136 #define PCIX_INTR_CONTROL_TMSI __BIT(1) /* Trigger MSI Interrupt */ 137 #define PCIX_INTR_CONTROL_DIA __BIT(0) /* Device Interrupt through INTA Pin */ 138 #define PCIX_INTR_CONTROL_MASK_ALL \ 139 (PCIX_INTR_CONTROL_MSI1_MASK|PCIX_INTR_CONTROL_MSI0_MASK \ 140 |PCIX_INTR_CONTROL_INTD_MASK|PCIX_INTR_CONTROL_INTC_MASK \ 141 |PCIX_INTR_CONTROL_INTB_MASK|PCIX_INTR_CONTROL_INTA_MASK) 142 143 /* 144 * RMIXL_PCIX_ECFG_INTR_STATUS bit defines 145 */ 146 #define PCIX_INTR_STATUS_RESV __BITS(31,6) 147 #define PCIX_INTR_STATUS_MSI1 __BIT(5) 148 #define PCIX_INTR_STATUS_MSI0 __BIT(4) 149 #define PCIX_INTR_STATUS_INTD __BIT(3) 150 #define PCIX_INTR_STATUS_INTC __BIT(2) 151 #define PCIX_INTR_STATUS_INTB __BIT(1) 152 #define PCIX_INTR_STATUS_INTA __BIT(0) 153 154 /* 155 * RMIXL_PCIX_ECFG_INTR_ERR_STATUS bit defines 156 */ 157 #define PCIX_INTR_ERR_STATUS_RESa __BITS(31,5) 158 #define PCIX_INTR_ERR_STATUS_SERR __BIT(4) /* System Error */ 159 #define PCIX_INTR_ERR_STATUS_RESb __BIT(3) 160 #define PCIX_INTR_ERR_STATUS_TE __BIT(2) /* Target Error */ 161 #define PCIX_INTR_ERR_STATUS_IE __BIT(1) /* Initiator Error */ 162 #define PCIX_INTR_ERR_STATUS_RCE __BIT(0) /* Retry Count Expired */ 163 #define PCIX_INTR_ERR_STATUS_RESV \ 164 (PCIX_INTR_ERR_STATUS_RESa|PCIX_INTR_ERR_STATUS_RESb) 165 166 /* 167 * RMIXL_PCIX_ECFG_HOST_MODE_CTL bit defines 168 */ 169 #define PCIX_HOST_MODE_CTL_HDMSTAT __BIT(1) /* Host/Dev Mode status 170 * read-only 171 * 1 = host 172 * 0 = device 173 */ 174 #define PCIX_HOST_MODE_CTL_HOSTSWRST __BIT(0) /* Host soft reset 175 * set to 1 to reset 176 * set to 0 to un-reset 177 */ 178 179 180 #if BYTE_ORDER == BIG_ENDIAN 181 # define RMIXL_PCIXREG_BASE RMIXL_IO_DEV_PCIX_EB 182 #else 183 # define RMIXL_PCIXREG_BASE RMIXL_IO_DEV_PCIX_EL 184 #endif 185 186 #define RMIXL_PCIXREG_VADDR(o) \ 187 (volatile uint32_t *)MIPS_PHYS_TO_KSEG1( \ 188 rmixl_configuration.rc_io_pbase \ 189 + RMIXL_PCIXREG_BASE + (o)) 190 191 #define RMIXL_PCIXREG_READ(o) (*RMIXL_PCIXREG_VADDR(o)) 192 #define RMIXL_PCIXREG_WRITE(o,v) *RMIXL_PCIXREG_VADDR(o) = (v) 193 194 195 #define RMIXL_PCIX_CONCAT3(a,b,c) a ## b ## c 196 #define RMIXL_PCIX_BAR_INIT(reg, bar, size, align) { \ 197 struct extent *ext = rmixl_configuration.rc_phys_ex; \ 198 u_long region_start; \ 199 uint64_t ba; \ 200 int err; \ 201 \ 202 err = extent_alloc(ext, (size), (align), 0UL, EX_NOWAIT, \ 203 ®ion_start); \ 204 if (err != 0) \ 205 panic("%s: extent_alloc(%p, %#lx, %#lx, %#lx, %#x, %p)",\ 206 __func__, ext, size, align, 0UL, EX_NOWAIT, \ 207 ®ion_start); \ 208 ba = (uint64_t)region_start; \ 209 ba *= (1024 * 1024); \ 210 bar = RMIXL_PCIX_CONCAT3(RMIXL_PCIX_,reg,_BAR)(ba, 1); \ 211 DPRINTF(("PCIX %s BAR was not enabled by firmware\n" \ 212 "enabling %s at phys %#" PRIxBUSADDR ", size %lu MB\n", \ 213 __STRING(reg), __STRING(reg), ba, size)); \ 214 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_BRIDGE + \ 215 RMIXL_PCIX_CONCAT3(RMIXLR_SBC_PCIX_,reg,_BAR), bar); \ 216 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + \ 217 RMIXL_PCIX_CONCAT3(RMIXLR_SBC_PCIX_,reg,_BAR)); \ 218 DPRINTF(("%s: %s BAR %#x\n", __func__, __STRING(reg), bar)); \ 219 } 220 221 222 #define RMIXL_PCIX_EVCNT(sc, intrpin, cpu) \ 223 &(sc)->sc_evcnts[(intrpin) * (ncpu) + (cpu)] 224 225 226 static int rmixl_pcix_match(device_t, cfdata_t, void *); 227 static void rmixl_pcix_attach(device_t, device_t, void *); 228 static void rmixl_pcix_init(rmixl_pcix_softc_t *); 229 static void rmixl_pcix_init_errors(rmixl_pcix_softc_t *); 230 static void rmixl_pcix_attach_hook(struct device *, struct device *, 231 struct pcibus_attach_args *); 232 static void rmixl_pcix_intcfg(rmixl_pcix_softc_t *); 233 static void rmixl_pcix_errata(rmixl_pcix_softc_t *); 234 static void rmixl_conf_interrupt(void *, int, int, int, int, int *); 235 static int rmixl_pcix_bus_maxdevs(void *, int); 236 static pcitag_t rmixl_pcix_make_tag(void *, int, int, int); 237 static void rmixl_pcix_decompose_tag(void *, pcitag_t, int *, int *, int *); 238 void rmixl_pcix_tag_print(const char *restrict, void *, pcitag_t, int, vaddr_t, u_long); 239 static int rmixl_pcix_conf_setup(rmixl_pcix_softc_t *, 240 pcitag_t, int *, bus_space_tag_t *, 241 bus_space_handle_t *); 242 static pcireg_t rmixl_pcix_conf_read(void *, pcitag_t, int); 243 static void rmixl_pcix_conf_write(void *, pcitag_t, int, pcireg_t); 244 245 static int rmixl_pcix_intr_map(struct pci_attach_args *, 246 pci_intr_handle_t *); 247 static const char * 248 rmixl_pcix_intr_string(void *, pci_intr_handle_t); 249 static const struct evcnt * 250 rmixl_pcix_intr_evcnt(void *, pci_intr_handle_t); 251 static pci_intr_handle_t 252 rmixl_pcix_make_pih(u_int, u_int); 253 static void rmixl_pcix_decompose_pih(pci_intr_handle_t, u_int *, u_int *); 254 static void rmixl_pcix_intr_disestablish(void *, void *); 255 static void *rmixl_pcix_intr_establish(void *, pci_intr_handle_t, 256 int, int (*)(void *), void *); 257 static rmixl_pcix_intr_t * 258 rmixl_pcix_pip_add_1(rmixl_pcix_softc_t *, int, int); 259 static void rmixl_pcix_pip_free_callout(rmixl_pcix_intr_t *); 260 static void rmixl_pcix_pip_free(void *); 261 static int rmixl_pcix_intr(void *); 262 static int rmixl_pcix_error_intr(void *); 263 264 265 CFATTACH_DECL_NEW(rmixl_pcix, sizeof(rmixl_pcix_softc_t), 266 rmixl_pcix_match, rmixl_pcix_attach, NULL, NULL); 267 268 269 static int rmixl_pcix_found; 270 271 272 static int 273 rmixl_pcix_match(device_t parent, cfdata_t cf, void *aux) 274 { 275 uint32_t r; 276 277 /* 278 * PCI-X interface exists on XLR chips only 279 */ 280 if (! cpu_rmixlr(mips_options.mips_cpu)) 281 return 0; 282 283 /* XXX 284 * for now there is only one PCI-X Interface on chip 285 * and only one chip in the system 286 * this could change with furture RMI XL family designs 287 * or when we have multi-chip systems. 288 */ 289 if (rmixl_pcix_found) 290 return 0; 291 292 /* read Host Mode Control register */ 293 r = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_MODE_CTL); 294 r &= PCIX_HOST_MODE_CTL_HDMSTAT; 295 if (r == 0) 296 return 0; /* strapped for Device Mode */ 297 298 return 1; 299 } 300 301 static void 302 rmixl_pcix_attach(device_t parent, device_t self, void *aux) 303 { 304 rmixl_pcix_softc_t *sc = device_private(self); 305 struct obio_attach_args *obio = aux; 306 struct rmixl_config *rcp = &rmixl_configuration; 307 struct pcibus_attach_args pba; 308 uint32_t bar; 309 310 rmixl_pcix_found = 1; 311 sc->sc_dev = self; 312 sc->sc_29bit_dmat = obio->obio_29bit_dmat; 313 sc->sc_32bit_dmat = obio->obio_32bit_dmat; 314 sc->sc_64bit_dmat = obio->obio_64bit_dmat; 315 sc->sc_tmsk = obio->obio_tmsk; 316 317 aprint_normal(": RMI XLR PCI-X Interface\n"); 318 319 rmixl_pcix_intcfg(sc); 320 321 rmixl_pcix_errata(sc); 322 323 /* 324 * check XLR Control Register 325 */ 326 DPRINTF(("%s: XLR_CONTROL=%#x\n", __func__, 327 RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_XLR_CONTROL))); 328 329 /* 330 * HBAR[0] if a 32 bit BAR, or 331 * HBAR[0,1] if a 64 bit BAR pair 332 * must cover all RAM 333 */ 334 extern u_quad_t mem_cluster_maxaddr; 335 uint64_t hbar_addr; 336 uint64_t hbar_size; 337 uint32_t hbar_size_lo, hbar_size_hi; 338 uint32_t hbar_addr_lo, hbar_addr_hi; 339 340 hbar_addr_lo = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR0_ADDR); 341 hbar_addr_hi = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR1_ADDR); 342 hbar_size_lo = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR0_SIZE); 343 hbar_size_hi = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR1_SIZE); 344 345 hbar_addr = (u_quad_t)(hbar_addr_lo & PCI_MAPREG_MEM_ADDR_MASK); 346 hbar_size = hbar_size_lo; 347 if ((hbar_size_lo & PCI_MAPREG_MEM_TYPE_64BIT) != 0) { 348 hbar_addr |= (uint64_t)hbar_addr_hi << 32; 349 hbar_size |= (uint64_t)hbar_size_hi << 32; 350 } 351 if ((hbar_addr != 0) || (hbar_size < mem_cluster_maxaddr)) { 352 int error; 353 354 aprint_error_dev(self, "HostBAR0 addr %#x, size %#x\n", 355 hbar_addr_lo, hbar_size_lo); 356 if ((hbar_size_lo & PCI_MAPREG_MEM_TYPE_64BIT) != 0) 357 aprint_error_dev(self, "HostBAR1 addr %#x, size %#x\n", 358 hbar_addr_hi, hbar_size_hi); 359 aprint_error_dev(self, "WARNING: firmware PCI-X setup error: " 360 "RAM %#"PRIx64"..%#"PRIx64" not accessible by Host BAR, " 361 "enabling DMA bounce buffers\n", 362 hbar_size, mem_cluster_maxaddr-1); 363 364 /* 365 * force use of bouce buffers for inaccessible RAM addrs 366 */ 367 if (hbar_size < ((uint64_t)1 << 32)) { 368 error = bus_dmatag_subregion(sc->sc_32bit_dmat, 369 0, (bus_addr_t)hbar_size, &sc->sc_32bit_dmat, 370 BUS_DMA_NOWAIT); 371 if (error) 372 panic("%s: failed to subregion 32-bit dma tag:" 373 " error %d", __func__, error); 374 sc->sc_64bit_dmat = NULL; 375 } else { 376 error = bus_dmatag_subregion(sc->sc_64bit_dmat, 377 0, (bus_addr_t)hbar_size, &sc->sc_64bit_dmat, 378 BUS_DMA_NOWAIT); 379 if (error) 380 panic("%s: failed to subregion 64-bit dma tag:" 381 " error %d", __func__, error); 382 } 383 } 384 385 /* 386 * check PCI-X interface byteswap setup 387 * ensure 'Match Byte Lane' is disabled 388 */ 389 uint32_t mble, mba, mbs; 390 mble = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_XLR_MBLE); 391 mba = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_MATCH_BIT_ADDR); 392 mbs = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_MATCH_BIT_SIZE); 393 DPRINTF(("%s: MBLE=%#x, MBA=%#x, MBS=%#x\n", __func__, mble, mba, mbs)); 394 if ((mble & __BIT(40)) != 0) 395 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_XLR_MBLE, 0); 396 397 /* 398 * get PCI config space base addr from SBC PCIe CFG BAR 399 * initialize it if necessary 400 */ 401 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_CFG_BAR); 402 DPRINTF(("%s: PCIX_CFG_BAR %#x\n", __func__, bar)); 403 if ((bar & RMIXL_PCIX_CFG_BAR_ENB) == 0) { 404 u_long n = RMIXL_PCIX_CFG_SIZE / (1024 * 1024); 405 RMIXL_PCIX_BAR_INIT(CFG, bar, n, n); 406 } 407 rcp->rc_pci_cfg_pbase = (bus_addr_t)RMIXL_PCIX_CFG_BAR_TO_BA(bar); 408 rcp->rc_pci_cfg_size = (bus_size_t)RMIXL_PCIX_CFG_SIZE; 409 410 /* 411 * get PCI MEM space base [addr, size] from SBC PCIe MEM BAR 412 * initialize it if necessary 413 */ 414 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_MEM_BAR); 415 DPRINTF(("%s: PCIX_MEM_BAR %#x\n", __func__, bar)); 416 if ((bar & RMIXL_PCIX_MEM_BAR_ENB) == 0) { 417 u_long n = 256; /* 256 MB */ 418 RMIXL_PCIX_BAR_INIT(MEM, bar, n, n); 419 } 420 rcp->rc_pci_mem_pbase = (bus_addr_t)RMIXL_PCIX_MEM_BAR_TO_BA(bar); 421 rcp->rc_pci_mem_size = (bus_size_t)RMIXL_PCIX_MEM_BAR_TO_SIZE(bar); 422 423 /* 424 * get PCI IO space base [addr, size] from SBC PCIe IO BAR 425 * initialize it if necessary 426 */ 427 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_IO_BAR); 428 DPRINTF(("%s: PCIX_IO_BAR %#x\n", __func__, bar)); 429 if ((bar & RMIXL_PCIX_IO_BAR_ENB) == 0) { 430 u_long n = 32; /* 32 MB */ 431 RMIXL_PCIX_BAR_INIT(IO, bar, n, n); 432 } 433 rcp->rc_pci_io_pbase = (bus_addr_t)RMIXL_PCIX_IO_BAR_TO_BA(bar); 434 rcp->rc_pci_io_size = (bus_size_t)RMIXL_PCIX_IO_BAR_TO_SIZE(bar); 435 436 /* 437 * initialize the PCI CFG bus space tag 438 */ 439 rmixl_pci_cfg_bus_mem_init(&rcp->rc_pci_cfg_memt, rcp); 440 sc->sc_pci_cfg_memt = &rcp->rc_pci_cfg_memt; 441 442 /* 443 * initialize the PCI MEM and IO bus space tags 444 */ 445 rmixl_pci_bus_mem_init(&rcp->rc_pci_memt, rcp); 446 rmixl_pci_bus_io_init(&rcp->rc_pci_iot, rcp); 447 448 /* 449 * initialize the extended configuration regs 450 */ 451 rmixl_pcix_init_errors(sc); 452 453 /* 454 * initialize the PCI chipset tag 455 */ 456 rmixl_pcix_init(sc); 457 458 /* 459 * attach the PCI bus 460 */ 461 memset(&pba, 0, sizeof(pba)); 462 pba.pba_memt = &rcp->rc_pci_memt; 463 pba.pba_iot = &rcp->rc_pci_iot; 464 pba.pba_dmat = sc->sc_32bit_dmat; 465 pba.pba_dmat64 = sc->sc_64bit_dmat; 466 pba.pba_pc = &sc->sc_pci_chipset; 467 pba.pba_bus = 0; 468 pba.pba_bridgetag = NULL; 469 pba.pba_intrswiz = 0; 470 pba.pba_intrtag = 0; 471 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 472 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 473 474 (void) config_found_ia(self, "pcibus", &pba, pcibusprint); 475 } 476 477 /* 478 * rmixl_pcix_intcfg - init PCI-X interrupt control 479 */ 480 static void 481 rmixl_pcix_intcfg(rmixl_pcix_softc_t *sc) 482 { 483 size_t size; 484 rmixl_pcix_evcnt_t *ev; 485 486 DPRINTF(("%s\n", __func__)); 487 488 /* mask all interrupts until they are established */ 489 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, 490 PCIX_INTR_CONTROL_MASK_ALL); 491 492 /* 493 * read-to-clear any pre-existing interrupts 494 * XXX MSI bits in STATUS are also documented as write 1 to clear in PRM 495 */ 496 (void)RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 497 (void)RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 498 499 /* initialize the (non-error interrupt) dispatch handles */ 500 sc->sc_intr = NULL; 501 502 /* 503 * allocate per-cpu, per-pin interrupt event counters 504 */ 505 size = ncpu * PCI_INTERRUPT_PIN_MAX * sizeof(rmixl_pcix_evcnt_t); 506 ev = malloc(size, M_DEVBUF, M_NOWAIT); 507 if (ev == NULL) 508 panic("%s: cannot malloc evcnts\n", __func__); 509 sc->sc_evcnts = ev; 510 for (int pin=PCI_INTERRUPT_PIN_A; pin <= PCI_INTERRUPT_PIN_MAX; pin++) { 511 for (int cpu=0; cpu < ncpu; cpu++) { 512 ev = RMIXL_PCIX_EVCNT(sc, pin - 1, cpu); 513 snprintf(ev->name, sizeof(ev->name), 514 "cpu%d, pin %d", cpu, pin); 515 evcnt_attach_dynamic(&ev->evcnt, EVCNT_TYPE_INTR, 516 NULL, "rmixl_pcix", ev->name); 517 } 518 } 519 520 /* 521 * establish PCIX error interrupt handler 522 */ 523 sc->sc_fatal_ih = rmixl_intr_establish(24, sc->sc_tmsk, 524 IPL_VM, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH, 525 rmixl_pcix_error_intr, sc, false); 526 if (sc->sc_fatal_ih == NULL) 527 panic("%s: cannot establish irq %d", __func__, 24); 528 } 529 530 static void 531 rmixl_pcix_errata(rmixl_pcix_softc_t *sc) 532 { 533 /* nothing */ 534 } 535 536 static void 537 rmixl_pcix_init(rmixl_pcix_softc_t *sc) 538 { 539 pci_chipset_tag_t pc = &sc->sc_pci_chipset; 540 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 541 struct extent *ioext, *memext; 542 #endif 543 544 pc->pc_conf_v = (void *)sc; 545 pc->pc_attach_hook = rmixl_pcix_attach_hook; 546 pc->pc_bus_maxdevs = rmixl_pcix_bus_maxdevs; 547 pc->pc_make_tag = rmixl_pcix_make_tag; 548 pc->pc_decompose_tag = rmixl_pcix_decompose_tag; 549 pc->pc_conf_read = rmixl_pcix_conf_read; 550 pc->pc_conf_write = rmixl_pcix_conf_write; 551 552 pc->pc_intr_v = (void *)sc; 553 pc->pc_intr_map = rmixl_pcix_intr_map; 554 pc->pc_intr_string = rmixl_pcix_intr_string; 555 pc->pc_intr_evcnt = rmixl_pcix_intr_evcnt; 556 pc->pc_intr_establish = rmixl_pcix_intr_establish; 557 pc->pc_intr_disestablish = rmixl_pcix_intr_disestablish; 558 pc->pc_conf_interrupt = rmixl_conf_interrupt; 559 560 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 561 /* 562 * Configure the PCI bus. 563 */ 564 struct rmixl_config *rcp = &rmixl_configuration; 565 566 aprint_normal_dev(sc->sc_dev, "%s: configuring PCI bus\n"); 567 568 ioext = extent_create("pciio", 569 rcp->rc_pci_io_pbase, 570 rcp->rc_pci_io_pbase + rcp->rc_pci_io_size - 1, 571 M_DEVBUF, NULL, 0, EX_NOWAIT); 572 573 memext = extent_create("pcimem", 574 rcp->rc_pci_mem_pbase, 575 rcp->rc_pci_mem_pbase + rcp->rc_pci_mem_size - 1, 576 M_DEVBUF, NULL, 0, EX_NOWAIT); 577 578 pci_configure_bus(pc, ioext, memext, NULL, 0, 579 mips_cache_info.mci_dcache_align); 580 581 extent_destroy(ioext); 582 extent_destroy(memext); 583 #endif 584 } 585 586 static void 587 rmixl_pcix_init_errors(rmixl_pcix_softc_t *sc) 588 { 589 /* nothing */ 590 } 591 592 void 593 rmixl_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *iline) 594 { 595 DPRINTF(("%s: %p, %d, %d, %d, %d, %p\n", 596 __func__, v, bus, dev, ipin, swiz, iline)); 597 } 598 599 void 600 rmixl_pcix_attach_hook(struct device *parent, struct device *self, 601 struct pcibus_attach_args *pba) 602 { 603 DPRINTF(("%s: pba_bus %d, pba_bridgetag %p, pc_conf_v %p\n", 604 __func__, pba->pba_bus, pba->pba_bridgetag, 605 pba->pba_pc->pc_conf_v)); 606 } 607 608 int 609 rmixl_pcix_bus_maxdevs(void *v, int busno) 610 { 611 return (32); /* XXX depends on the family of XLS SoC */ 612 } 613 614 /* 615 * XLS pci tag is a 40 bit address composed thusly: 616 * 39:25 (reserved) 617 * 24 Swap (0=little, 1=big endian) 618 * 23:16 Bus number 619 * 15:11 Device number 620 * 10:8 Function number 621 * 7:0 Register number 622 * 623 * Note: this is the "native" composition for addressing CFG space, but not for ECFG space. 624 */ 625 pcitag_t 626 rmixl_pcix_make_tag(void *v, int bus, int dev, int fun) 627 { 628 return ((bus << 16) | (dev << 11) | (fun << 8)); 629 } 630 631 void 632 rmixl_pcix_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 633 { 634 if (bp != NULL) 635 *bp = (tag >> 16) & 0xff; 636 if (dp != NULL) 637 *dp = (tag >> 11) & 0x1f; 638 if (fp != NULL) 639 *fp = (tag >> 8) & 0x7; 640 } 641 642 void 643 rmixl_pcix_tag_print(const char *restrict s, void *v, pcitag_t tag, int offset, 644 vaddr_t va, u_long r) 645 { 646 int bus, dev, fun; 647 648 rmixl_pcix_decompose_tag(v, tag, &bus, &dev, &fun); 649 printf("%s: %d/%d/%d/%d - %#" PRIxVADDR ":%#lx\n", 650 s, bus, dev, fun, offset, va, r); 651 } 652 653 static int 654 rmixl_pcix_conf_setup(rmixl_pcix_softc_t *sc, 655 pcitag_t tag, int *offp, bus_space_tag_t *bstp, 656 bus_space_handle_t *bshp) 657 { 658 struct rmixl_config *rcp = &rmixl_configuration; 659 bus_space_tag_t bst; 660 bus_space_handle_t bsh; 661 bus_size_t size; 662 pcitag_t mask; 663 bus_addr_t ba; 664 int err; 665 static bus_space_handle_t cfg_bsh; 666 static bus_addr_t cfg_oba = -1; 667 668 /* 669 * bus space depends on offset 670 */ 671 if ((*offp >= 0) && (*offp < 0x100)) { 672 mask = __BITS(15,0); 673 bst = sc->sc_pci_cfg_memt; 674 ba = rcp->rc_pci_cfg_pbase; 675 ba += (tag & ~mask); 676 *offp += (tag & mask); 677 if (ba != cfg_oba) { 678 size = (bus_size_t)(mask + 1); 679 if (cfg_oba != -1) 680 bus_space_unmap(bst, cfg_bsh, size); 681 err = bus_space_map(bst, ba, size, 0, &cfg_bsh); 682 if (err != 0) { 683 #ifdef DEBUG 684 panic("%s: bus_space_map err %d, CFG space", 685 __func__, err); /* XXX */ 686 #endif 687 return -1; 688 } 689 cfg_oba = ba; 690 } 691 bsh = cfg_bsh; 692 } else { 693 #ifdef DEBUG 694 panic("%s: offset %#x: unknown", __func__, *offp); 695 #endif 696 return -1; 697 } 698 699 *bstp = bst; 700 *bshp = bsh; 701 702 return 0; 703 } 704 705 pcireg_t 706 rmixl_pcix_conf_read(void *v, pcitag_t tag, int offset) 707 { 708 rmixl_pcix_softc_t *sc = v; 709 static bus_space_handle_t bsh; 710 bus_space_tag_t bst; 711 pcireg_t rv; 712 uint64_t cfg0; 713 714 mutex_enter(&sc->sc_mutex); 715 716 if (rmixl_pcix_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) { 717 cfg0 = rmixl_cache_err_dis(); 718 rv = bus_space_read_4(bst, bsh, (bus_size_t)offset); 719 if (rmixl_cache_err_check() != 0) { 720 #ifdef DIAGNOSTIC 721 int bus, dev, fun; 722 723 rmixl_pcix_decompose_tag(v, tag, &bus, &dev, &fun); 724 printf("%s: %d/%d/%d, offset %#x: bad address\n", 725 __func__, bus, dev, fun, offset); 726 #endif 727 rv = (pcireg_t) -1; 728 } 729 rmixl_cache_err_restore(cfg0); 730 } else { 731 rv = -1; 732 } 733 734 mutex_exit(&sc->sc_mutex); 735 736 return rv; 737 } 738 739 void 740 rmixl_pcix_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 741 { 742 rmixl_pcix_softc_t *sc = v; 743 static bus_space_handle_t bsh; 744 bus_space_tag_t bst; 745 uint64_t cfg0; 746 747 mutex_enter(&sc->sc_mutex); 748 749 if (rmixl_pcix_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) { 750 cfg0 = rmixl_cache_err_dis(); 751 bus_space_write_4(bst, bsh, (bus_size_t)offset, val); 752 if (rmixl_cache_err_check() != 0) { 753 #ifdef DIAGNOSTIC 754 int bus, dev, fun; 755 756 rmixl_pcix_decompose_tag(v, tag, &bus, &dev, &fun); 757 printf("%s: %d/%d/%d, offset %#x: bad address\n", 758 __func__, bus, dev, fun, offset); 759 #endif 760 } 761 rmixl_cache_err_restore(cfg0); 762 } 763 764 mutex_exit(&sc->sc_mutex); 765 } 766 767 int 768 rmixl_pcix_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *pih) 769 { 770 const u_int irq = 16; /* PCIX index in IRT */ 771 772 #ifdef DEBUG 773 DPRINTF(("%s: ps_bus %d, pa_intrswiz %#x, pa_intrtag %#lx," 774 " pa_intrpin %d, pa_intrline %d, pa_rawintrpin %d\n", 775 __func__, pa->pa_bus, pa->pa_intrswiz, pa->pa_intrtag, 776 pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 777 #endif 778 779 if (pa->pa_intrpin != PCI_INTERRUPT_PIN_NONE) 780 *pih = rmixl_pcix_make_pih(pa->pa_intrpin - 1, irq); 781 else 782 *pih = ~0; 783 784 return 0; 785 } 786 787 const char * 788 rmixl_pcix_intr_string(void *v, pci_intr_handle_t pih) 789 { 790 u_int bitno, irq; 791 792 rmixl_pcix_decompose_pih(pih, &bitno, &irq); 793 794 if (! cpu_rmixlr(mips_options.mips_cpu)) 795 panic("%s: cpu %#x not supported\n", 796 __func__, mips_options.mips_cpu_id); 797 798 return rmixl_intr_string(irq); 799 } 800 801 const struct evcnt * 802 rmixl_pcix_intr_evcnt(void *v, pci_intr_handle_t pih) 803 { 804 return NULL; 805 } 806 807 static pci_intr_handle_t 808 rmixl_pcix_make_pih(u_int bitno, u_int irq) 809 { 810 pci_intr_handle_t pih; 811 812 KASSERT(bitno < 64); 813 KASSERT(irq < 32); 814 815 pih = (irq << 6); 816 pih |= bitno; 817 818 return pih; 819 } 820 821 static void 822 rmixl_pcix_decompose_pih(pci_intr_handle_t pih, u_int *bitno, u_int *irq) 823 { 824 *bitno = (u_int)(pih & 0x3f); 825 *irq = (u_int)(pih >> 6); 826 827 KASSERT(*bitno < 64); 828 KASSERT(*irq < 31); 829 } 830 831 static void 832 rmixl_pcix_intr_disestablish(void *v, void *ih) 833 { 834 rmixl_pcix_softc_t *sc = v; 835 rmixl_pcix_dispatch_t *dip = ih; 836 rmixl_pcix_intr_t *pip = sc->sc_intr; 837 bool busy; 838 839 DPRINTF(("%s: pin=%d irq=%d\n", 840 __func__, dip->bitno + 1, dip->irq)); 841 KASSERT(dip->bitno < RMIXL_PCIX_NINTR); 842 843 mutex_enter(&sc->sc_mutex); 844 845 dip->func = NULL; /* prevent further dispatch */ 846 847 /* 848 * if no other dispatch handle is using this interrupt, 849 * we can disable it 850 */ 851 busy = false; 852 for (int i=0; i < pip->dispatch_count; i++) { 853 rmixl_pcix_dispatch_t *d = &pip->dispatch_data[i]; 854 if (d == dip) 855 continue; 856 if (d->bitno == dip->bitno) { 857 busy = true; 858 break; 859 } 860 } 861 if (! busy) { 862 uint32_t bit = 1 << (dip->bitno + 2); 863 uint32_t r; 864 865 r = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 866 r |= bit; /* set mask */ 867 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, r); 868 DPRINTF(("%s: disabled pin %d\n", __func__, dip->bitno + 1)); 869 870 pip->intenb &= ~(1 << dip->bitno); 871 872 if ((r & PCIX_INTR_CONTROL_MASK_ALL) == 0) { 873 /* tear down interrupt for this pcix */ 874 rmixl_intr_disestablish(pip->ih); 875 876 /* commit NULL interrupt set */ 877 sc->sc_intr = NULL; 878 879 /* schedule delayed free of the old interrupt set */ 880 rmixl_pcix_pip_free_callout(pip); 881 } 882 } 883 884 mutex_exit(&sc->sc_mutex); 885 } 886 887 static void * 888 rmixl_pcix_intr_establish(void *v, pci_intr_handle_t pih, int ipl, 889 int (*func)(void *), void *arg) 890 { 891 rmixl_pcix_softc_t *sc = v; 892 u_int bitno, irq; 893 rmixl_pcix_intr_t *pip; 894 rmixl_pcix_dispatch_t *dip = NULL; 895 896 if (pih == ~0) { 897 DPRINTF(("%s: bad pih=%#lx, implies PCI_INTERRUPT_PIN_NONE\n", 898 __func__, pih)); 899 return NULL; 900 } 901 902 rmixl_pcix_decompose_pih(pih, &bitno, &irq); 903 DPRINTF(("%s: pin=%d irq=%d\n", __func__, bitno + 1, irq)); 904 905 KASSERT(bitno < RMIXL_PCIX_NINTR); 906 907 /* 908 * all PCI-X device intrs get same ipl 909 */ 910 KASSERT(ipl == IPL_VM); 911 912 mutex_enter(&sc->sc_mutex); 913 914 pip = rmixl_pcix_pip_add_1(sc, irq, ipl); 915 if (pip == NULL) 916 return NULL; 917 918 /* 919 * initializae our new interrupt, the last element in dispatch_data[] 920 */ 921 dip = &pip->dispatch_data[pip->dispatch_count - 1]; 922 dip->bitno = bitno; 923 dip->irq = irq; 924 dip->func = func; 925 dip->arg = arg; 926 #if NEVER 927 snprintf(dip->count_name, sizeof(dip->count_name), 928 "pin %d", bitno + 1); 929 evcnt_attach_dynamic(&dip->count, EVCNT_TYPE_INTR, NULL, 930 "rmixl_pcix", dip->count_name); 931 #endif 932 933 /* commit the new interrupt set */ 934 sc->sc_intr = pip; 935 936 /* enable this interrupt in the PCIX controller, if necessary */ 937 if ((pip->intenb & (1 << bitno)) == 0) { 938 uint32_t bit = 1 << (bitno + 2); 939 uint32_t r; 940 941 r = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 942 r &= ~bit; /* clear mask */ 943 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, r); 944 945 pip->sc = sc; 946 pip->ipl = ipl; 947 pip->intenb |= 1 << bitno; 948 DPRINTF(("%s: enabled pin %d\n", __func__, bitno + 1)); 949 } 950 951 mutex_exit(&sc->sc_mutex); 952 return dip; 953 } 954 955 rmixl_pcix_intr_t * 956 rmixl_pcix_pip_add_1(rmixl_pcix_softc_t *sc, int irq, int ipl) 957 { 958 rmixl_pcix_intr_t *pip_old = sc->sc_intr; 959 rmixl_pcix_intr_t *pip_new; 960 u_int dispatch_count; 961 size_t size; 962 963 dispatch_count = 1; 964 size = sizeof(rmixl_pcix_intr_t); 965 if (pip_old != NULL) { 966 /* 967 * count only those dispatch elements still in use 968 * unused ones will be pruned during copy 969 * i.e. we are "lazy" there is no rmixl_pcix_pip_sub_1 970 */ 971 for (int i=0; i < pip_old->dispatch_count; i++) { 972 if (pip_old->dispatch_data[i].func != NULL) { 973 dispatch_count++; 974 size += sizeof(rmixl_pcix_intr_t); 975 } 976 } 977 } 978 979 /* 980 * allocate and initialize softc intr struct 981 * with one or more dispatch handles 982 */ 983 pip_new = malloc(size, M_DEVBUF, M_NOWAIT); 984 if (pip_new == NULL) { 985 #ifdef DIAGNOSTIC 986 printf("%s: cannot malloc\n", __func__); 987 #endif 988 return NULL; 989 } 990 991 if (pip_old == NULL) { 992 /* initialize the interrupt struct */ 993 pip_new->sc = sc; 994 pip_new->ipl = ipl; 995 pip_new->ih = rmixl_intr_establish(irq, sc->sc_tmsk, 996 ipl, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH, 997 rmixl_pcix_intr, pip_new, false); 998 if (pip_new->ih == NULL) 999 panic("%s: cannot establish irq %d", __func__, irq); 1000 } else { 1001 /* 1002 * all intrs on a softc get same ipl and sc 1003 * first intr established sets the standard 1004 */ 1005 KASSERT(sc == pip_old->sc); 1006 if (sc != pip_old->sc) { 1007 printf("%s: sc %p mismatch\n", __func__, sc); 1008 free(pip_new, M_DEVBUF); 1009 return NULL; 1010 } 1011 KASSERT (ipl == pip_old->ipl); 1012 if (ipl != pip_old->ipl) { 1013 printf("%s: ipl %d mismatch\n", __func__, ipl); 1014 free(pip_new, M_DEVBUF); 1015 return NULL; 1016 } 1017 /* 1018 * copy pip_old to pip_new, skipping unused dispatch elemets 1019 */ 1020 memcpy(pip_new, pip_old, sizeof(rmixl_pcix_intr_t)); 1021 for (int j=0, i=0; i < pip_old->dispatch_count; i++) { 1022 if (pip_old->dispatch_data[i].func != NULL) { 1023 memcpy(&pip_new->dispatch_data[j], 1024 &pip_old->dispatch_data[i], 1025 sizeof(rmixl_pcix_dispatch_t)); 1026 j++; 1027 } 1028 } 1029 1030 /* 1031 * schedule delayed free of old interrupt set 1032 */ 1033 rmixl_pcix_pip_free_callout(pip_old); 1034 } 1035 pip_new->dispatch_count = dispatch_count; 1036 1037 return pip_new; 1038 } 1039 1040 /* 1041 * delay free of the old interrupt set 1042 * to allow anyone still using it to do so safely 1043 * XXX 2 seconds should be plenty? 1044 */ 1045 static void 1046 rmixl_pcix_pip_free_callout(rmixl_pcix_intr_t *pip) 1047 { 1048 callout_init(&pip->callout, 0); 1049 callout_reset(&pip->callout, 2 * hz, rmixl_pcix_pip_free, pip); 1050 } 1051 1052 static void 1053 rmixl_pcix_pip_free(void *arg) 1054 { 1055 rmixl_pcix_intr_t *pip = arg; 1056 1057 callout_destroy(&pip->callout); 1058 free(pip, M_DEVBUF); 1059 } 1060 1061 static int 1062 rmixl_pcix_intr(void *arg) 1063 { 1064 rmixl_pcix_intr_t *pip = arg; 1065 int rv = 0; 1066 1067 uint32_t status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 1068 DPRINTF(("%s: %#x\n", __func__, status)); 1069 1070 if (status != 0) { 1071 for (int i=0; i < pip->dispatch_count; i++) { 1072 rmixl_pcix_dispatch_t *dip = &pip->dispatch_data[i]; 1073 uint32_t bit = 1 << dip->bitno; 1074 int (*func)(void *) = dip->func; 1075 if ((func != NULL) && (status & bit) != 0) { 1076 (void)(*func)(dip->arg); 1077 dip->counts[cpu_index(curcpu())].evcnt.ev_count++; 1078 rv = 1; 1079 } 1080 } 1081 } 1082 return rv; 1083 } 1084 1085 static int 1086 rmixl_pcix_error_intr(void *arg) 1087 { 1088 rmixl_pcix_softc_t *sc = arg; 1089 uint32_t error_status; 1090 1091 error_status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 1092 1093 #ifdef DIAGNOSTIC 1094 printf("%s: error status %#x\n", __func__, error_status); 1095 #endif 1096 1097 #if DDB 1098 Debugger(); 1099 #endif 1100 1101 /* XXX reset and recover? */ 1102 1103 panic("%s: error %#x\n", device_xname(sc->sc_dev), error_status); 1104 } 1105 1106 /* 1107 * rmixl_physaddr_init_pcix: 1108 * called from rmixl_physaddr_init to get region addrs & sizes 1109 * from PCIX CFG, ECFG, IO, MEM BARs 1110 */ 1111 void 1112 rmixl_physaddr_init_pcix(struct extent *ext) 1113 { 1114 u_long base; 1115 u_long size; 1116 uint32_t r; 1117 1118 r = RMIXL_PCIXREG_READ(RMIXLR_SBC_PCIX_CFG_BAR); 1119 if ((r & RMIXL_PCIX_CFG_BAR_ENB) != 0) { 1120 base = (u_long)(RMIXL_PCIX_CFG_BAR_TO_BA((uint64_t)r) 1121 / (1024 * 1024)); 1122 size = (u_long)RMIXL_PCIX_CFG_SIZE / (1024 * 1024); 1123 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1124 __LINE__, "CFG", r, base * 1024 * 1024, size)); 1125 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1126 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1127 "failed", __func__, ext, base, size, EX_NOWAIT); 1128 } 1129 1130 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_MEM_BAR); 1131 if ((r & RMIXL_PCIX_MEM_BAR_ENB) != 0) { 1132 base = (u_long)(RMIXL_PCIX_MEM_BAR_TO_BA((uint64_t)r) 1133 / (1024 * 1024)); 1134 size = (u_long)(RMIXL_PCIX_MEM_BAR_TO_SIZE((uint64_t)r) 1135 / (1024 * 1024)); 1136 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1137 __LINE__, "MEM", r, base * 1024 * 1024, size)); 1138 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1139 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1140 "failed", __func__, ext, base, size, EX_NOWAIT); 1141 } 1142 1143 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_IO_BAR); 1144 if ((r & RMIXL_PCIX_IO_BAR_ENB) != 0) { 1145 base = (u_long)(RMIXL_PCIX_IO_BAR_TO_BA((uint64_t)r) 1146 / (1024 * 1024)); 1147 size = (u_long)(RMIXL_PCIX_IO_BAR_TO_SIZE((uint64_t)r) 1148 / (1024 * 1024)); 1149 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1150 __LINE__, "IO", r, base * 1024 * 1024, size)); 1151 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1152 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1153 "failed", __func__, ext, base, size, EX_NOWAIT); 1154 } 1155 } 1156 1157 #ifdef DDB 1158 int rmixl_pcix_intr_chk(void); 1159 int 1160 rmixl_pcix_intr_chk(void) 1161 { 1162 uint32_t control, status, error_status; 1163 1164 control = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 1165 status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 1166 error_status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 1167 1168 printf("%s: %#x, %#x, %#x\n", __func__, control, status, error_status); 1169 1170 control |= PCIX_INTR_CONTROL_DIA; 1171 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, control); 1172 1173 control = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 1174 status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 1175 error_status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 1176 1177 printf("%s: %#x, %#x, %#x\n", __func__, control, status, error_status); 1178 1179 return 0; 1180 } 1181 #endif 1182
Indexes created Sun Oct 19 16:10:00 GMT 2025