rmixl_pcix.c revision 1.9
1 /* $NetBSD: rmixl_pcix.c,v 1.9 2011/07/10 23:13:22 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * PCI configuration support for RMI XLR SoC 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: rmixl_pcix.c,v 1.9 2011/07/10 23:13:22 matt Exp $"); 44 45 #include "opt_pci.h" 46 #include "pci.h" 47 48 #include <sys/cdefs.h> 49 50 #include <sys/param.h> 51 #include <sys/bus.h> 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/extent.h> 55 #include <sys/intr.h> 56 #include <sys/malloc.h> 57 #include <sys/kernel.h> /* for 'hz' */ 58 #include <sys/systm.h> 59 60 #include <uvm/uvm_extern.h> 61 62 #include <mips/rmi/rmixlreg.h> 63 #include <mips/rmi/rmixlvar.h> 64 #include <mips/rmi/rmixl_intr.h> 65 #include <mips/rmi/rmixl_pcixvar.h> 66 67 #include <mips/rmi/rmixl_obiovar.h> 68 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pcidevs.h> 71 #include <dev/pci/pciconf.h> 72 73 #ifdef PCI_NETBSD_CONFIGURE 74 #include <mips/cache.h> 75 #endif 76 77 #ifdef PCI_DEBUG 78 int rmixl_pcix_debug = PCI_DEBUG; 79 # define DPRINTF(x) do { if (rmixl_pcix_debug) printf x ; } while (0) 80 #else 81 # define DPRINTF(x) 82 #endif 83 84 #ifndef DDB 85 # define STATIC static 86 #else 87 # define STATIC 88 #endif 89 90 91 /* 92 * XLR PCI-X Extended Configuration Registers 93 * Note: 94 * - MSI-related regs are omitted 95 * - Device mode regs are omitted 96 */ 97 #define RMIXL_PCIX_ECFG_HOST_BAR0_ADDR 0x100 /* Host BAR0 Address */ 98 #define RMIXL_PCIX_ECFG_HOST_BAR1_ADDR 0x104 /* Host BAR1 Address */ 99 #define RMIXL_PCIX_ECFG_HOST_BAR2_ADDR 0x108 /* Host BAR2 Address */ 100 #define RMIXL_PCIX_ECFG_HOST_BAR3_ADDR 0x10c /* Host BAR3 Address */ 101 #define RMIXL_PCIX_ECFG_HOST_BAR4_ADDR 0x110 /* Host BAR4 Address */ 102 #define RMIXL_PCIX_ECFG_HOST_BAR5_ADDR 0x114 /* Host BAR5 Address */ 103 #define RMIXL_PCIX_ECFG_HOST_BAR0_SIZE 0x118 /* Host BAR0 Size */ 104 #define RMIXL_PCIX_ECFG_HOST_BAR1_SIZE 0x11c /* Host BAR1 Size */ 105 #define RMIXL_PCIX_ECFG_HOST_BAR2_SIZE 0x120 /* Host BAR2 Size */ 106 #define RMIXL_PCIX_ECFG_HOST_BAR3_SIZE 0x124 /* Host BAR3 Size */ 107 #define RMIXL_PCIX_ECFG_HOST_BAR4_SIZE 0x128 /* Host BAR4 Size */ 108 #define RMIXL_PCIX_ECFG_HOST_BAR5_SIZE 0x12c /* Host BAR5 Size */ 109 #define RMIXL_PCIX_ECFG_MATCH_BIT_ADDR 0x130 /* Match Bit Address BAR */ 110 #define RMIXL_PCIX_ECFG_MATCH_BIT_SIZE 0x134 /* Match Bit Size BAR */ 111 #define RMIXL_PCIX_ECFG_XLR_CONTROL 0x138 /* XLR Control reg */ 112 #define RMIXL_PCIX_ECFG_INTR_CONTROL 0x13c /* Interrupt Control reg */ 113 #define RMIXL_PCIX_ECFG_INTR_STATUS 0x140 /* Interrupt Status reg */ 114 #define RMIXL_PCIX_ECFG_INTR_ERR_STATUS 0x144 /* Interrupt Error Status reg */ 115 #define RMIXL_PCIX_ECFG_HOST_MODE_STS 0x178 /* Host Mode Status */ 116 #define RMIXL_PCIX_ECFG_XLR_MBLE 0x17c /* XLR Match Byte Lane Enable */ 117 #define RMIXL_PCIX_ECFG_HOST_XROM_ADDR 0x180 /* Host Expansion ROM Address */ 118 #define RMIXL_PCIX_ECFG_HOST_XROM_SIZE 0x184 /* Host Expansion ROM Size */ 119 #define RMIXL_PCIX_ECFG_HOST_MODE_CTL 0x18c /* Host Mode Control */ 120 #define RMIXL_PCIX_ECFG_TXCAL_CTL 0x1a0 /* TX Calibration Preset Control */ 121 #define RMIXL_PCIX_ECFG_TXCAL_COUNT 0x1a4 /* TX Calibration Preset Count */ 122 123 /* 124 * RMIXL_PCIX_ECFG_INTR_CONTROL bit defines 125 */ 126 #define PCIX_INTR_CONTROL_RESV __BITS(31,8) 127 #define PCIX_INTR_CONTROL_MSI1_MASK __BIT(7) 128 #define PCIX_INTR_CONTROL_MSI0_MASK __BIT(6) 129 #define PCIX_INTR_CONTROL_INTD_MASK __BIT(5) 130 #define PCIX_INTR_CONTROL_INTC_MASK __BIT(4) 131 #define PCIX_INTR_CONTROL_INTB_MASK __BIT(3) 132 #define PCIX_INTR_CONTROL_INTA_MASK __BIT(2) 133 #define PCIX_INTR_CONTROL_TMSI __BIT(1) /* Trigger MSI Interrupt */ 134 #define PCIX_INTR_CONTROL_DIA __BIT(0) /* Device Interrupt through INTA Pin */ 135 #define PCIX_INTR_CONTROL_MASK_ALL \ 136 (PCIX_INTR_CONTROL_MSI1_MASK|PCIX_INTR_CONTROL_MSI0_MASK \ 137 |PCIX_INTR_CONTROL_INTD_MASK|PCIX_INTR_CONTROL_INTC_MASK \ 138 |PCIX_INTR_CONTROL_INTB_MASK|PCIX_INTR_CONTROL_INTA_MASK) 139 140 /* 141 * RMIXL_PCIX_ECFG_INTR_STATUS bit defines 142 */ 143 #define PCIX_INTR_STATUS_RESV __BITS(31,6) 144 #define PCIX_INTR_STATUS_MSI1 __BIT(5) 145 #define PCIX_INTR_STATUS_MSI0 __BIT(4) 146 #define PCIX_INTR_STATUS_INTD __BIT(3) 147 #define PCIX_INTR_STATUS_INTC __BIT(2) 148 #define PCIX_INTR_STATUS_INTB __BIT(1) 149 #define PCIX_INTR_STATUS_INTA __BIT(0) 150 151 /* 152 * RMIXL_PCIX_ECFG_INTR_ERR_STATUS bit defines 153 */ 154 #define PCIX_INTR_ERR_STATUS_RESa __BITS(31,5) 155 #define PCIX_INTR_ERR_STATUS_SERR __BIT(4) /* System Error */ 156 #define PCIX_INTR_ERR_STATUS_RESb __BIT(3) 157 #define PCIX_INTR_ERR_STATUS_TE __BIT(2) /* Target Error */ 158 #define PCIX_INTR_ERR_STATUS_IE __BIT(1) /* Initiator Error */ 159 #define PCIX_INTR_ERR_STATUS_RCE __BIT(0) /* Retry Count Expired */ 160 #define PCIX_INTR_ERR_STATUS_RESV \ 161 (PCIX_INTR_ERR_STATUS_RESa|PCIX_INTR_ERR_STATUS_RESb) 162 163 /* 164 * RMIXL_PCIX_ECFG_HOST_MODE_CTL bit defines 165 */ 166 #define PCIX_HOST_MODE_CTL_HDMSTAT __BIT(1) /* Host/Dev Mode status 167 * read-only 168 * 1 = host 169 * 0 = device 170 */ 171 #define PCIX_HOST_MODE_CTL_HOSTSWRST __BIT(0) /* Host soft reset 172 * set to 1 to reset 173 * set to 0 to un-reset 174 */ 175 176 177 #if BYTE_ORDER == BIG_ENDIAN 178 # define RMIXL_PCIXREG_BASE RMIXL_IO_DEV_PCIX_EB 179 #else 180 # define RMIXL_PCIXREG_BASE RMIXL_IO_DEV_PCIX_EL 181 #endif 182 183 #define RMIXL_PCIXREG_VADDR(o) \ 184 (volatile uint32_t *)MIPS_PHYS_TO_KSEG1( \ 185 rmixl_configuration.rc_io_pbase \ 186 + RMIXL_PCIXREG_BASE + (o)) 187 188 #define RMIXL_PCIXREG_READ(o) (*RMIXL_PCIXREG_VADDR(o)) 189 #define RMIXL_PCIXREG_WRITE(o,v) *RMIXL_PCIXREG_VADDR(o) = (v) 190 191 192 #define RMIXL_PCIX_CONCAT3(a,b,c) a ## b ## c 193 #define RMIXL_PCIX_BAR_INIT(reg, bar, size, align) { \ 194 struct extent *ext = rmixl_configuration.rc_phys_ex; \ 195 u_long region_start; \ 196 uint64_t ba; \ 197 int err; \ 198 \ 199 err = extent_alloc(ext, (size), (align), 0UL, EX_NOWAIT, \ 200 ®ion_start); \ 201 if (err != 0) \ 202 panic("%s: extent_alloc(%p, %#lx, %#lx, %#lx, %#x, %p)",\ 203 __func__, ext, size, align, 0UL, EX_NOWAIT, \ 204 ®ion_start); \ 205 ba = (uint64_t)region_start; \ 206 ba *= (1024 * 1024); \ 207 bar = RMIXL_PCIX_CONCAT3(RMIXL_PCIX_,reg,_BAR)(ba, 1); \ 208 DPRINTF(("PCIX %s BAR was not enabled by firmware\n" \ 209 "enabling %s at phys %#" PRIxBUSADDR ", size %lu MB\n", \ 210 __STRING(reg), __STRING(reg), ba, size)); \ 211 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_BRIDGE + \ 212 RMIXL_PCIX_CONCAT3(RMIXLR_SBC_PCIX_,reg,_BAR), bar); \ 213 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + \ 214 RMIXL_PCIX_CONCAT3(RMIXLR_SBC_PCIX_,reg,_BAR)); \ 215 DPRINTF(("%s: %s BAR %#x\n", __func__, __STRING(reg), bar)); \ 216 } 217 218 219 #define RMIXL_PCIX_EVCNT(sc, intrpin, cpu) \ 220 &(sc)->sc_evcnts[(intrpin) * (ncpu) + (cpu)] 221 222 223 static int rmixl_pcix_match(device_t, cfdata_t, void *); 224 static void rmixl_pcix_attach(device_t, device_t, void *); 225 static void rmixl_pcix_init(rmixl_pcix_softc_t *); 226 static void rmixl_pcix_init_errors(rmixl_pcix_softc_t *); 227 static void rmixl_pcix_attach_hook(struct device *, struct device *, 228 struct pcibus_attach_args *); 229 static void rmixl_pcix_intcfg(rmixl_pcix_softc_t *); 230 static void rmixl_pcix_errata(rmixl_pcix_softc_t *); 231 static void rmixl_conf_interrupt(void *, int, int, int, int, int *); 232 static int rmixl_pcix_bus_maxdevs(void *, int); 233 static pcitag_t rmixl_pcix_make_tag(void *, int, int, int); 234 static void rmixl_pcix_decompose_tag(void *, pcitag_t, int *, int *, int *); 235 void rmixl_pcix_tag_print(const char *restrict, void *, pcitag_t, int, vaddr_t, u_long); 236 static int rmixl_pcix_conf_setup(rmixl_pcix_softc_t *, 237 pcitag_t, int *, bus_space_tag_t *, 238 bus_space_handle_t *); 239 static pcireg_t rmixl_pcix_conf_read(void *, pcitag_t, int); 240 static void rmixl_pcix_conf_write(void *, pcitag_t, int, pcireg_t); 241 242 static int rmixl_pcix_intr_map(const struct pci_attach_args *, 243 pci_intr_handle_t *); 244 static const char * 245 rmixl_pcix_intr_string(void *, pci_intr_handle_t); 246 static const struct evcnt * 247 rmixl_pcix_intr_evcnt(void *, pci_intr_handle_t); 248 static pci_intr_handle_t 249 rmixl_pcix_make_pih(u_int, u_int); 250 static void rmixl_pcix_decompose_pih(pci_intr_handle_t, u_int *, u_int *); 251 static void rmixl_pcix_intr_disestablish(void *, void *); 252 static void *rmixl_pcix_intr_establish(void *, pci_intr_handle_t, 253 int, int (*)(void *), void *); 254 static rmixl_pcix_intr_t * 255 rmixl_pcix_pip_add_1(rmixl_pcix_softc_t *, int, int); 256 static void rmixl_pcix_pip_free_callout(rmixl_pcix_intr_t *); 257 static void rmixl_pcix_pip_free(void *); 258 static int rmixl_pcix_intr(void *); 259 static int rmixl_pcix_error_intr(void *); 260 261 262 CFATTACH_DECL_NEW(rmixl_pcix, sizeof(rmixl_pcix_softc_t), 263 rmixl_pcix_match, rmixl_pcix_attach, NULL, NULL); 264 265 266 static int rmixl_pcix_found; 267 268 269 static int 270 rmixl_pcix_match(device_t parent, cfdata_t cf, void *aux) 271 { 272 uint32_t r; 273 274 /* 275 * PCI-X interface exists on XLR chips only 276 */ 277 if (! cpu_rmixlr(mips_options.mips_cpu)) 278 return 0; 279 280 /* XXX 281 * for now there is only one PCI-X Interface on chip 282 * and only one chip in the system 283 * this could change with furture RMI XL family designs 284 * or when we have multi-chip systems. 285 */ 286 if (rmixl_pcix_found) 287 return 0; 288 289 /* read Host Mode Control register */ 290 r = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_MODE_CTL); 291 r &= PCIX_HOST_MODE_CTL_HDMSTAT; 292 if (r == 0) 293 return 0; /* strapped for Device Mode */ 294 295 return 1; 296 } 297 298 static void 299 rmixl_pcix_attach(device_t parent, device_t self, void *aux) 300 { 301 rmixl_pcix_softc_t *sc = device_private(self); 302 struct obio_attach_args *obio = aux; 303 struct rmixl_config *rcp = &rmixl_configuration; 304 struct pcibus_attach_args pba; 305 uint32_t bar; 306 307 rmixl_pcix_found = 1; 308 sc->sc_dev = self; 309 sc->sc_29bit_dmat = obio->obio_29bit_dmat; 310 sc->sc_32bit_dmat = obio->obio_32bit_dmat; 311 sc->sc_64bit_dmat = obio->obio_64bit_dmat; 312 sc->sc_tmsk = obio->obio_tmsk; 313 314 aprint_normal(": RMI XLR PCI-X Interface\n"); 315 316 mutex_init(&sc->sc_mutex, MUTEX_DEFAULT, IPL_HIGH); 317 318 rmixl_pcix_intcfg(sc); 319 320 rmixl_pcix_errata(sc); 321 322 /* 323 * check XLR Control Register 324 */ 325 DPRINTF(("%s: XLR_CONTROL=%#x\n", __func__, 326 RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_XLR_CONTROL))); 327 328 /* 329 * HBAR[0] if a 32 bit BAR, or 330 * HBAR[0,1] if a 64 bit BAR pair 331 * must cover all RAM 332 */ 333 extern u_quad_t mem_cluster_maxaddr; 334 uint64_t hbar_addr; 335 uint64_t hbar_size; 336 uint32_t hbar_size_lo, hbar_size_hi; 337 uint32_t hbar_addr_lo, hbar_addr_hi; 338 339 hbar_addr_lo = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR0_ADDR); 340 hbar_addr_hi = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR1_ADDR); 341 hbar_size_lo = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR0_SIZE); 342 hbar_size_hi = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_HOST_BAR1_SIZE); 343 344 hbar_addr = (u_quad_t)(hbar_addr_lo & PCI_MAPREG_MEM_ADDR_MASK); 345 hbar_size = hbar_size_lo; 346 if ((hbar_size_lo & PCI_MAPREG_MEM_TYPE_64BIT) != 0) { 347 hbar_addr |= (uint64_t)hbar_addr_hi << 32; 348 hbar_size |= (uint64_t)hbar_size_hi << 32; 349 } 350 if ((hbar_addr != 0) || (hbar_size < mem_cluster_maxaddr)) { 351 int error; 352 353 aprint_error_dev(self, "HostBAR0 addr %#x, size %#x\n", 354 hbar_addr_lo, hbar_size_lo); 355 if ((hbar_size_lo & PCI_MAPREG_MEM_TYPE_64BIT) != 0) 356 aprint_error_dev(self, "HostBAR1 addr %#x, size %#x\n", 357 hbar_addr_hi, hbar_size_hi); 358 aprint_error_dev(self, "WARNING: firmware PCI-X setup error: " 359 "RAM %#"PRIx64"..%#"PRIx64" not accessible by Host BAR, " 360 "enabling DMA bounce buffers\n", 361 hbar_size, mem_cluster_maxaddr-1); 362 363 /* 364 * force use of bouce buffers for inaccessible RAM addrs 365 */ 366 if (hbar_size < ((uint64_t)1 << 32)) { 367 error = bus_dmatag_subregion(sc->sc_32bit_dmat, 368 0, (bus_addr_t)hbar_size, &sc->sc_32bit_dmat, 369 BUS_DMA_NOWAIT); 370 if (error) 371 panic("%s: failed to subregion 32-bit dma tag:" 372 " error %d", __func__, error); 373 sc->sc_64bit_dmat = NULL; 374 } else { 375 error = bus_dmatag_subregion(sc->sc_64bit_dmat, 376 0, (bus_addr_t)hbar_size, &sc->sc_64bit_dmat, 377 BUS_DMA_NOWAIT); 378 if (error) 379 panic("%s: failed to subregion 64-bit dma tag:" 380 " error %d", __func__, error); 381 } 382 } 383 384 /* 385 * check PCI-X interface byteswap setup 386 * ensure 'Match Byte Lane' is disabled 387 */ 388 uint32_t mble, mba, mbs; 389 mble = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_XLR_MBLE); 390 mba = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_MATCH_BIT_ADDR); 391 mbs = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_MATCH_BIT_SIZE); 392 DPRINTF(("%s: MBLE=%#x, MBA=%#x, MBS=%#x\n", __func__, mble, mba, mbs)); 393 if ((mble & __BIT(40)) != 0) 394 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_XLR_MBLE, 0); 395 396 /* 397 * get PCI config space base addr from SBC PCIe CFG BAR 398 * initialize it if necessary 399 */ 400 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_CFG_BAR); 401 DPRINTF(("%s: PCIX_CFG_BAR %#x\n", __func__, bar)); 402 if ((bar & RMIXL_PCIX_CFG_BAR_ENB) == 0) { 403 u_long n = RMIXL_PCIX_CFG_SIZE / (1024 * 1024); 404 RMIXL_PCIX_BAR_INIT(CFG, bar, n, n); 405 } 406 rcp->rc_pci_cfg_pbase = (bus_addr_t)RMIXL_PCIX_CFG_BAR_TO_BA(bar); 407 rcp->rc_pci_cfg_size = (bus_size_t)RMIXL_PCIX_CFG_SIZE; 408 409 /* 410 * get PCI MEM space base [addr, size] from SBC PCIe MEM BAR 411 * initialize it if necessary 412 */ 413 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_MEM_BAR); 414 DPRINTF(("%s: PCIX_MEM_BAR %#x\n", __func__, bar)); 415 if ((bar & RMIXL_PCIX_MEM_BAR_ENB) == 0) { 416 u_long n = 256; /* 256 MB */ 417 RMIXL_PCIX_BAR_INIT(MEM, bar, n, n); 418 } 419 rcp->rc_pci_mem_pbase = (bus_addr_t)RMIXL_PCIX_MEM_BAR_TO_BA(bar); 420 rcp->rc_pci_mem_size = (bus_size_t)RMIXL_PCIX_MEM_BAR_TO_SIZE(bar); 421 422 /* 423 * get PCI IO space base [addr, size] from SBC PCIe IO BAR 424 * initialize it if necessary 425 */ 426 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_IO_BAR); 427 DPRINTF(("%s: PCIX_IO_BAR %#x\n", __func__, bar)); 428 if ((bar & RMIXL_PCIX_IO_BAR_ENB) == 0) { 429 u_long n = 32; /* 32 MB */ 430 RMIXL_PCIX_BAR_INIT(IO, bar, n, n); 431 } 432 rcp->rc_pci_io_pbase = (bus_addr_t)RMIXL_PCIX_IO_BAR_TO_BA(bar); 433 rcp->rc_pci_io_size = (bus_size_t)RMIXL_PCIX_IO_BAR_TO_SIZE(bar); 434 435 /* 436 * initialize the PCI CFG bus space tag 437 */ 438 rmixl_pci_cfg_bus_mem_init(&rcp->rc_pci_cfg_memt, rcp); 439 sc->sc_pci_cfg_memt = &rcp->rc_pci_cfg_memt; 440 441 /* 442 * initialize the PCI MEM and IO bus space tags 443 */ 444 rmixl_pci_bus_mem_init(&rcp->rc_pci_memt, rcp); 445 rmixl_pci_bus_io_init(&rcp->rc_pci_iot, rcp); 446 447 /* 448 * initialize the extended configuration regs 449 */ 450 rmixl_pcix_init_errors(sc); 451 452 /* 453 * initialize the PCI chipset tag 454 */ 455 rmixl_pcix_init(sc); 456 457 /* 458 * attach the PCI bus 459 */ 460 memset(&pba, 0, sizeof(pba)); 461 pba.pba_memt = &rcp->rc_pci_memt; 462 pba.pba_iot = &rcp->rc_pci_iot; 463 pba.pba_dmat = sc->sc_32bit_dmat; 464 pba.pba_dmat64 = sc->sc_64bit_dmat; 465 pba.pba_pc = &sc->sc_pci_chipset; 466 pba.pba_bus = 0; 467 pba.pba_bridgetag = NULL; 468 pba.pba_intrswiz = 0; 469 pba.pba_intrtag = 0; 470 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY | 471 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 472 473 (void) config_found_ia(self, "pcibus", &pba, pcibusprint); 474 } 475 476 /* 477 * rmixl_pcix_intcfg - init PCI-X interrupt control 478 */ 479 static void 480 rmixl_pcix_intcfg(rmixl_pcix_softc_t *sc) 481 { 482 size_t size; 483 rmixl_pcix_evcnt_t *ev; 484 485 DPRINTF(("%s\n", __func__)); 486 487 /* mask all interrupts until they are established */ 488 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, 489 PCIX_INTR_CONTROL_MASK_ALL); 490 491 /* 492 * read-to-clear any pre-existing interrupts 493 * XXX MSI bits in STATUS are also documented as write 1 to clear in PRM 494 */ 495 (void)RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 496 (void)RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 497 498 /* initialize the (non-error interrupt) dispatch handles */ 499 sc->sc_intr = NULL; 500 501 /* 502 * allocate per-cpu, per-pin interrupt event counters 503 */ 504 size = ncpu * PCI_INTERRUPT_PIN_MAX * sizeof(rmixl_pcix_evcnt_t); 505 ev = malloc(size, M_DEVBUF, M_NOWAIT); 506 if (ev == NULL) 507 panic("%s: cannot malloc evcnts\n", __func__); 508 sc->sc_evcnts = ev; 509 for (int pin=PCI_INTERRUPT_PIN_A; pin <= PCI_INTERRUPT_PIN_MAX; pin++) { 510 for (int cpu=0; cpu < ncpu; cpu++) { 511 ev = RMIXL_PCIX_EVCNT(sc, pin - 1, cpu); 512 snprintf(ev->name, sizeof(ev->name), 513 "cpu%d, pin %d", cpu, pin); 514 evcnt_attach_dynamic(&ev->evcnt, EVCNT_TYPE_INTR, 515 NULL, "rmixl_pcix", ev->name); 516 } 517 } 518 519 /* 520 * establish PCIX error interrupt handler 521 */ 522 sc->sc_fatal_ih = rmixl_intr_establish(24, sc->sc_tmsk, 523 IPL_VM, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH, 524 rmixl_pcix_error_intr, sc, false); 525 if (sc->sc_fatal_ih == NULL) 526 panic("%s: cannot establish irq %d", __func__, 24); 527 } 528 529 static void 530 rmixl_pcix_errata(rmixl_pcix_softc_t *sc) 531 { 532 /* nothing */ 533 } 534 535 static void 536 rmixl_pcix_init(rmixl_pcix_softc_t *sc) 537 { 538 pci_chipset_tag_t pc = &sc->sc_pci_chipset; 539 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 540 struct extent *ioext, *memext; 541 #endif 542 543 pc->pc_conf_v = (void *)sc; 544 pc->pc_attach_hook = rmixl_pcix_attach_hook; 545 pc->pc_bus_maxdevs = rmixl_pcix_bus_maxdevs; 546 pc->pc_make_tag = rmixl_pcix_make_tag; 547 pc->pc_decompose_tag = rmixl_pcix_decompose_tag; 548 pc->pc_conf_read = rmixl_pcix_conf_read; 549 pc->pc_conf_write = rmixl_pcix_conf_write; 550 551 pc->pc_intr_v = (void *)sc; 552 pc->pc_intr_map = rmixl_pcix_intr_map; 553 pc->pc_intr_string = rmixl_pcix_intr_string; 554 pc->pc_intr_evcnt = rmixl_pcix_intr_evcnt; 555 pc->pc_intr_establish = rmixl_pcix_intr_establish; 556 pc->pc_intr_disestablish = rmixl_pcix_intr_disestablish; 557 pc->pc_conf_interrupt = rmixl_conf_interrupt; 558 559 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 560 /* 561 * Configure the PCI bus. 562 */ 563 struct rmixl_config *rcp = &rmixl_configuration; 564 565 aprint_normal_dev(sc->sc_dev, "%s: configuring PCI bus\n"); 566 567 ioext = extent_create("pciio", 568 rcp->rc_pci_io_pbase, 569 rcp->rc_pci_io_pbase + rcp->rc_pci_io_size - 1, 570 M_DEVBUF, NULL, 0, EX_NOWAIT); 571 572 memext = extent_create("pcimem", 573 rcp->rc_pci_mem_pbase, 574 rcp->rc_pci_mem_pbase + rcp->rc_pci_mem_size - 1, 575 M_DEVBUF, NULL, 0, EX_NOWAIT); 576 577 pci_configure_bus(pc, ioext, memext, NULL, 0, 578 mips_cache_info.mci_dcache_align); 579 580 extent_destroy(ioext); 581 extent_destroy(memext); 582 #endif 583 } 584 585 static void 586 rmixl_pcix_init_errors(rmixl_pcix_softc_t *sc) 587 { 588 /* nothing */ 589 } 590 591 void 592 rmixl_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *iline) 593 { 594 DPRINTF(("%s: %p, %d, %d, %d, %d, %p\n", 595 __func__, v, bus, dev, ipin, swiz, iline)); 596 } 597 598 void 599 rmixl_pcix_attach_hook(struct device *parent, struct device *self, 600 struct pcibus_attach_args *pba) 601 { 602 DPRINTF(("%s: pba_bus %d, pba_bridgetag %p, pc_conf_v %p\n", 603 __func__, pba->pba_bus, pba->pba_bridgetag, 604 pba->pba_pc->pc_conf_v)); 605 } 606 607 int 608 rmixl_pcix_bus_maxdevs(void *v, int busno) 609 { 610 return (32); /* XXX depends on the family of XLS SoC */ 611 } 612 613 /* 614 * XLS pci tag is a 40 bit address composed thusly: 615 * 39:25 (reserved) 616 * 24 Swap (0=little, 1=big endian) 617 * 23:16 Bus number 618 * 15:11 Device number 619 * 10:8 Function number 620 * 7:0 Register number 621 * 622 * Note: this is the "native" composition for addressing CFG space, but not for ECFG space. 623 */ 624 pcitag_t 625 rmixl_pcix_make_tag(void *v, int bus, int dev, int fun) 626 { 627 return ((bus << 16) | (dev << 11) | (fun << 8)); 628 } 629 630 void 631 rmixl_pcix_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 632 { 633 if (bp != NULL) 634 *bp = (tag >> 16) & 0xff; 635 if (dp != NULL) 636 *dp = (tag >> 11) & 0x1f; 637 if (fp != NULL) 638 *fp = (tag >> 8) & 0x7; 639 } 640 641 void 642 rmixl_pcix_tag_print(const char *restrict s, void *v, pcitag_t tag, int offset, 643 vaddr_t va, u_long r) 644 { 645 int bus, dev, fun; 646 647 rmixl_pcix_decompose_tag(v, tag, &bus, &dev, &fun); 648 printf("%s: %d/%d/%d/%d - %#" PRIxVADDR ":%#lx\n", 649 s, bus, dev, fun, offset, va, r); 650 } 651 652 static int 653 rmixl_pcix_conf_setup(rmixl_pcix_softc_t *sc, 654 pcitag_t tag, int *offp, bus_space_tag_t *bstp, 655 bus_space_handle_t *bshp) 656 { 657 struct rmixl_config *rcp = &rmixl_configuration; 658 bus_space_tag_t bst; 659 bus_space_handle_t bsh; 660 bus_size_t size; 661 pcitag_t mask; 662 bus_addr_t ba; 663 int err; 664 static bus_space_handle_t cfg_bsh; 665 static bus_addr_t cfg_oba = -1; 666 667 /* 668 * bus space depends on offset 669 */ 670 if ((*offp >= 0) && (*offp < 0x100)) { 671 mask = __BITS(15,0); 672 bst = sc->sc_pci_cfg_memt; 673 ba = rcp->rc_pci_cfg_pbase; 674 ba += (tag & ~mask); 675 *offp += (tag & mask); 676 if (ba != cfg_oba) { 677 size = (bus_size_t)(mask + 1); 678 if (cfg_oba != -1) 679 bus_space_unmap(bst, cfg_bsh, size); 680 err = bus_space_map(bst, ba, size, 0, &cfg_bsh); 681 if (err != 0) { 682 #ifdef DEBUG 683 panic("%s: bus_space_map err %d, CFG space", 684 __func__, err); /* XXX */ 685 #endif 686 return -1; 687 } 688 cfg_oba = ba; 689 } 690 bsh = cfg_bsh; 691 } else { 692 #ifdef DEBUG 693 panic("%s: offset %#x: unknown", __func__, *offp); 694 #endif 695 return -1; 696 } 697 698 *bstp = bst; 699 *bshp = bsh; 700 701 return 0; 702 } 703 704 pcireg_t 705 rmixl_pcix_conf_read(void *v, pcitag_t tag, int offset) 706 { 707 rmixl_pcix_softc_t *sc = v; 708 static bus_space_handle_t bsh; 709 bus_space_tag_t bst; 710 pcireg_t rv; 711 uint64_t cfg0; 712 713 mutex_enter(&sc->sc_mutex); 714 715 if (rmixl_pcix_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) { 716 cfg0 = rmixl_cache_err_dis(); 717 rv = bus_space_read_4(bst, bsh, (bus_size_t)offset); 718 if (rmixl_cache_err_check() != 0) { 719 #ifdef DIAGNOSTIC 720 int bus, dev, fun; 721 722 rmixl_pcix_decompose_tag(v, tag, &bus, &dev, &fun); 723 printf("%s: %d/%d/%d, offset %#x: bad address\n", 724 __func__, bus, dev, fun, offset); 725 #endif 726 rv = (pcireg_t) -1; 727 } 728 rmixl_cache_err_restore(cfg0); 729 } else { 730 rv = -1; 731 } 732 733 mutex_exit(&sc->sc_mutex); 734 735 return rv; 736 } 737 738 void 739 rmixl_pcix_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 740 { 741 rmixl_pcix_softc_t *sc = v; 742 static bus_space_handle_t bsh; 743 bus_space_tag_t bst; 744 uint64_t cfg0; 745 746 mutex_enter(&sc->sc_mutex); 747 748 if (rmixl_pcix_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) { 749 cfg0 = rmixl_cache_err_dis(); 750 bus_space_write_4(bst, bsh, (bus_size_t)offset, val); 751 if (rmixl_cache_err_check() != 0) { 752 #ifdef DIAGNOSTIC 753 int bus, dev, fun; 754 755 rmixl_pcix_decompose_tag(v, tag, &bus, &dev, &fun); 756 printf("%s: %d/%d/%d, offset %#x: bad address\n", 757 __func__, bus, dev, fun, offset); 758 #endif 759 } 760 rmixl_cache_err_restore(cfg0); 761 } 762 763 mutex_exit(&sc->sc_mutex); 764 } 765 766 int 767 rmixl_pcix_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *pih) 768 { 769 const u_int irq = 16; /* PCIX index in IRT */ 770 771 #ifdef DEBUG 772 DPRINTF(("%s: ps_bus %d, pa_intrswiz %#x, pa_intrtag %#lx," 773 " pa_intrpin %d, pa_intrline %d, pa_rawintrpin %d\n", 774 __func__, pa->pa_bus, pa->pa_intrswiz, pa->pa_intrtag, 775 pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 776 #endif 777 778 if (pa->pa_intrpin != PCI_INTERRUPT_PIN_NONE) 779 *pih = rmixl_pcix_make_pih(pa->pa_intrpin - 1, irq); 780 else 781 *pih = ~0; 782 783 return 0; 784 } 785 786 const char * 787 rmixl_pcix_intr_string(void *v, pci_intr_handle_t pih) 788 { 789 u_int bitno, irq; 790 791 rmixl_pcix_decompose_pih(pih, &bitno, &irq); 792 793 if (! cpu_rmixlr(mips_options.mips_cpu)) 794 panic("%s: cpu %#x not supported\n", 795 __func__, mips_options.mips_cpu_id); 796 797 return rmixl_intr_string(RMIXL_IRT_VECTOR(irq)); 798 } 799 800 const struct evcnt * 801 rmixl_pcix_intr_evcnt(void *v, pci_intr_handle_t pih) 802 { 803 return NULL; 804 } 805 806 static pci_intr_handle_t 807 rmixl_pcix_make_pih(u_int bitno, u_int irq) 808 { 809 pci_intr_handle_t pih; 810 811 KASSERT(bitno < 64); 812 KASSERT(irq < 32); 813 814 pih = (irq << 6); 815 pih |= bitno; 816 817 return pih; 818 } 819 820 static void 821 rmixl_pcix_decompose_pih(pci_intr_handle_t pih, u_int *bitno, u_int *irq) 822 { 823 *bitno = (u_int)(pih & 0x3f); 824 *irq = (u_int)(pih >> 6); 825 826 KASSERT(*bitno < 64); 827 KASSERT(*irq < 31); 828 } 829 830 static void 831 rmixl_pcix_intr_disestablish(void *v, void *ih) 832 { 833 rmixl_pcix_softc_t *sc = v; 834 rmixl_pcix_dispatch_t *dip = ih; 835 rmixl_pcix_intr_t *pip = sc->sc_intr; 836 bool busy; 837 838 DPRINTF(("%s: pin=%d irq=%d\n", 839 __func__, dip->bitno + 1, dip->irq)); 840 KASSERT(dip->bitno < RMIXL_PCIX_NINTR); 841 842 mutex_enter(&sc->sc_mutex); 843 844 dip->func = NULL; /* prevent further dispatch */ 845 846 /* 847 * if no other dispatch handle is using this interrupt, 848 * we can disable it 849 */ 850 busy = false; 851 for (int i=0; i < pip->dispatch_count; i++) { 852 rmixl_pcix_dispatch_t *d = &pip->dispatch_data[i]; 853 if (d == dip) 854 continue; 855 if (d->bitno == dip->bitno) { 856 busy = true; 857 break; 858 } 859 } 860 if (! busy) { 861 uint32_t bit = 1 << (dip->bitno + 2); 862 uint32_t r; 863 864 r = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 865 r |= bit; /* set mask */ 866 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, r); 867 DPRINTF(("%s: disabled pin %d\n", __func__, dip->bitno + 1)); 868 869 pip->intenb &= ~(1 << dip->bitno); 870 871 if ((r & PCIX_INTR_CONTROL_MASK_ALL) == 0) { 872 /* tear down interrupt for this pcix */ 873 rmixl_intr_disestablish(pip->ih); 874 875 /* commit NULL interrupt set */ 876 sc->sc_intr = NULL; 877 878 /* schedule delayed free of the old interrupt set */ 879 rmixl_pcix_pip_free_callout(pip); 880 } 881 } 882 883 mutex_exit(&sc->sc_mutex); 884 } 885 886 static void * 887 rmixl_pcix_intr_establish(void *v, pci_intr_handle_t pih, int ipl, 888 int (*func)(void *), void *arg) 889 { 890 rmixl_pcix_softc_t *sc = v; 891 u_int bitno, irq; 892 rmixl_pcix_intr_t *pip; 893 rmixl_pcix_dispatch_t *dip = NULL; 894 895 if (pih == ~0) { 896 DPRINTF(("%s: bad pih=%#lx, implies PCI_INTERRUPT_PIN_NONE\n", 897 __func__, pih)); 898 return NULL; 899 } 900 901 rmixl_pcix_decompose_pih(pih, &bitno, &irq); 902 DPRINTF(("%s: pin=%d irq=%d\n", __func__, bitno + 1, irq)); 903 904 KASSERT(bitno < RMIXL_PCIX_NINTR); 905 906 /* 907 * all PCI-X device intrs get same ipl 908 */ 909 KASSERT(ipl == IPL_VM); 910 911 mutex_enter(&sc->sc_mutex); 912 913 pip = rmixl_pcix_pip_add_1(sc, irq, ipl); 914 if (pip == NULL) 915 return NULL; 916 917 /* 918 * initializae our new interrupt, the last element in dispatch_data[] 919 */ 920 dip = &pip->dispatch_data[pip->dispatch_count - 1]; 921 dip->bitno = bitno; 922 dip->irq = irq; 923 dip->func = func; 924 dip->arg = arg; 925 dip->counts = RMIXL_PCIX_EVCNT(sc, bitno, 0); 926 #if NEVER 927 snprintf(dip->count_name, sizeof(dip->count_name), 928 "pin %d", bitno + 1); 929 evcnt_attach_dynamic(&dip->count, EVCNT_TYPE_INTR, NULL, 930 "rmixl_pcix", dip->count_name); 931 #endif 932 933 /* commit the new interrupt set */ 934 sc->sc_intr = pip; 935 936 /* enable this interrupt in the PCIX controller, if necessary */ 937 if ((pip->intenb & (1 << bitno)) == 0) { 938 uint32_t bit = 1 << (bitno + 2); 939 uint32_t r; 940 941 r = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 942 r &= ~bit; /* clear mask */ 943 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, r); 944 945 pip->sc = sc; 946 pip->ipl = ipl; 947 pip->intenb |= 1 << bitno; 948 DPRINTF(("%s: enabled pin %d\n", __func__, bitno + 1)); 949 } 950 951 mutex_exit(&sc->sc_mutex); 952 return dip; 953 } 954 955 rmixl_pcix_intr_t * 956 rmixl_pcix_pip_add_1(rmixl_pcix_softc_t *sc, int irq, int ipl) 957 { 958 rmixl_pcix_intr_t *pip_old = sc->sc_intr; 959 rmixl_pcix_intr_t *pip_new; 960 u_int dispatch_count; 961 size_t size; 962 963 dispatch_count = 1; 964 size = sizeof(rmixl_pcix_intr_t); 965 if (pip_old != NULL) { 966 /* 967 * count only those dispatch elements still in use 968 * unused ones will be pruned during copy 969 * i.e. we are "lazy" there is no rmixl_pcix_pip_sub_1 970 */ 971 for (int i=0; i < pip_old->dispatch_count; i++) { 972 if (pip_old->dispatch_data[i].func != NULL) { 973 dispatch_count++; 974 size += sizeof(rmixl_pcix_intr_t); 975 } 976 } 977 } 978 979 /* 980 * allocate and initialize softc intr struct 981 * with one or more dispatch handles 982 */ 983 pip_new = malloc(size, M_DEVBUF, M_NOWAIT|M_ZERO); 984 if (pip_new == NULL) { 985 #ifdef DIAGNOSTIC 986 printf("%s: cannot malloc\n", __func__); 987 #endif 988 return NULL; 989 } 990 991 if (pip_old == NULL) { 992 /* initialize the interrupt struct */ 993 pip_new->sc = sc; 994 pip_new->ipl = ipl; 995 pip_new->ih = rmixl_intr_establish(irq, sc->sc_tmsk, 996 ipl, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH, 997 rmixl_pcix_intr, pip_new, false); 998 if (pip_new->ih == NULL) 999 panic("%s: cannot establish irq %d", __func__, irq); 1000 } else { 1001 /* 1002 * all intrs on a softc get same ipl and sc 1003 * first intr established sets the standard 1004 */ 1005 KASSERT(sc == pip_old->sc); 1006 if (sc != pip_old->sc) { 1007 printf("%s: sc %p mismatch\n", __func__, sc); 1008 free(pip_new, M_DEVBUF); 1009 return NULL; 1010 } 1011 KASSERT (ipl == pip_old->ipl); 1012 if (ipl != pip_old->ipl) { 1013 printf("%s: ipl %d mismatch\n", __func__, ipl); 1014 free(pip_new, M_DEVBUF); 1015 return NULL; 1016 } 1017 /* 1018 * copy pip_old to pip_new, skipping unused dispatch elemets 1019 */ 1020 memcpy(pip_new, pip_old, sizeof(rmixl_pcix_intr_t)); 1021 for (int j=0, i=0; i < pip_old->dispatch_count; i++) { 1022 if (pip_old->dispatch_data[i].func != NULL) { 1023 memcpy(&pip_new->dispatch_data[j], 1024 &pip_old->dispatch_data[i], 1025 sizeof(rmixl_pcix_dispatch_t)); 1026 j++; 1027 } 1028 } 1029 1030 /* 1031 * schedule delayed free of old interrupt set 1032 */ 1033 rmixl_pcix_pip_free_callout(pip_old); 1034 } 1035 pip_new->dispatch_count = dispatch_count; 1036 1037 return pip_new; 1038 } 1039 1040 /* 1041 * delay free of the old interrupt set 1042 * to allow anyone still using it to do so safely 1043 * XXX 2 seconds should be plenty? 1044 */ 1045 static void 1046 rmixl_pcix_pip_free_callout(rmixl_pcix_intr_t *pip) 1047 { 1048 callout_init(&pip->callout, 0); 1049 callout_reset(&pip->callout, 2 * hz, rmixl_pcix_pip_free, pip); 1050 } 1051 1052 static void 1053 rmixl_pcix_pip_free(void *arg) 1054 { 1055 rmixl_pcix_intr_t *pip = arg; 1056 1057 callout_destroy(&pip->callout); 1058 free(pip, M_DEVBUF); 1059 } 1060 1061 static int 1062 rmixl_pcix_intr(void *arg) 1063 { 1064 rmixl_pcix_intr_t *pip = arg; 1065 int rv = 0; 1066 1067 uint32_t status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 1068 DPRINTF(("%s: %#x\n", __func__, status)); 1069 1070 if (status != 0) { 1071 for (int i=0; i < pip->dispatch_count; i++) { 1072 rmixl_pcix_dispatch_t *dip = &pip->dispatch_data[i]; 1073 uint32_t bit = 1 << dip->bitno; 1074 int (*func)(void *) = dip->func; 1075 if ((func != NULL) && (status & bit) != 0) { 1076 (void)(*func)(dip->arg); 1077 dip->counts[cpu_index(curcpu())].evcnt.ev_count++; 1078 rv = 1; 1079 } 1080 } 1081 } 1082 return rv; 1083 } 1084 1085 static int 1086 rmixl_pcix_error_intr(void *arg) 1087 { 1088 rmixl_pcix_softc_t *sc = arg; 1089 uint32_t error_status; 1090 1091 error_status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 1092 1093 #ifdef DIAGNOSTIC 1094 printf("%s: error status %#x\n", __func__, error_status); 1095 #endif 1096 1097 #if DDB 1098 Debugger(); 1099 #endif 1100 1101 /* XXX reset and recover? */ 1102 1103 panic("%s: error %#x\n", device_xname(sc->sc_dev), error_status); 1104 } 1105 1106 /* 1107 * rmixl_physaddr_init_pcix: 1108 * called from rmixl_physaddr_init to get region addrs & sizes 1109 * from PCIX CFG, ECFG, IO, MEM BARs 1110 */ 1111 void 1112 rmixl_physaddr_init_pcix(struct extent *ext) 1113 { 1114 u_long base; 1115 u_long size; 1116 uint32_t r; 1117 1118 r = RMIXL_PCIXREG_READ(RMIXLR_SBC_PCIX_CFG_BAR); 1119 if ((r & RMIXL_PCIX_CFG_BAR_ENB) != 0) { 1120 base = (u_long)(RMIXL_PCIX_CFG_BAR_TO_BA((uint64_t)r) 1121 / (1024 * 1024)); 1122 size = (u_long)RMIXL_PCIX_CFG_SIZE / (1024 * 1024); 1123 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1124 __LINE__, "CFG", r, base * 1024 * 1024, size)); 1125 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1126 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1127 "failed", __func__, ext, base, size, EX_NOWAIT); 1128 } 1129 1130 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_MEM_BAR); 1131 if ((r & RMIXL_PCIX_MEM_BAR_ENB) != 0) { 1132 base = (u_long)(RMIXL_PCIX_MEM_BAR_TO_BA((uint64_t)r) 1133 / (1024 * 1024)); 1134 size = (u_long)(RMIXL_PCIX_MEM_BAR_TO_SIZE((uint64_t)r) 1135 / (1024 * 1024)); 1136 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1137 __LINE__, "MEM", r, base * 1024 * 1024, size)); 1138 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1139 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1140 "failed", __func__, ext, base, size, EX_NOWAIT); 1141 } 1142 1143 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLR_SBC_PCIX_IO_BAR); 1144 if ((r & RMIXL_PCIX_IO_BAR_ENB) != 0) { 1145 base = (u_long)(RMIXL_PCIX_IO_BAR_TO_BA((uint64_t)r) 1146 / (1024 * 1024)); 1147 size = (u_long)(RMIXL_PCIX_IO_BAR_TO_SIZE((uint64_t)r) 1148 / (1024 * 1024)); 1149 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 1150 __LINE__, "IO", r, base * 1024 * 1024, size)); 1151 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1152 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1153 "failed", __func__, ext, base, size, EX_NOWAIT); 1154 } 1155 } 1156 1157 #ifdef DDB 1158 int rmixl_pcix_intr_chk(void); 1159 int 1160 rmixl_pcix_intr_chk(void) 1161 { 1162 uint32_t control, status, error_status; 1163 1164 control = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 1165 status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 1166 error_status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 1167 1168 printf("%s: %#x, %#x, %#x\n", __func__, control, status, error_status); 1169 1170 control |= PCIX_INTR_CONTROL_DIA; 1171 RMIXL_PCIXREG_WRITE(RMIXL_PCIX_ECFG_INTR_CONTROL, control); 1172 1173 control = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_CONTROL); 1174 status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_STATUS); 1175 error_status = RMIXL_PCIXREG_READ(RMIXL_PCIX_ECFG_INTR_ERR_STATUS); 1176 1177 printf("%s: %#x, %#x, %#x\n", __func__, control, status, error_status); 1178 1179 return 0; 1180 } 1181 #endif 1182
Indexes created Fri Sep 26 20:09:58 GMT 2025