rmixlreg.h revision 1.1.2.10
1 /* $NetBSD: rmixlreg.h,v 1.1.2.10 2010/03/24 19:14:09 cliff Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Cliff Neighbors 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 33 #ifndef _MIPS_RMI_RMIXLREGS_H_ 34 #define _MIPS_RMI_RMIXLREGS_H_ 35 36 #include <sys/endian.h> 37 38 /* 39 * on chip I/O register byte order is 40 * BIG ENDIAN regardless of code model 41 */ 42 #define RMIXL_IOREG_VADDR(o) \ 43 (volatile uint32_t *)MIPS_PHYS_TO_KSEG1( \ 44 rmixl_configuration.rc_io_pbase + (o)) 45 #define RMIXL_IOREG_READ(o) be32toh(*RMIXL_IOREG_VADDR(o)) 46 #define RMIXL_IOREG_WRITE(o,v) *RMIXL_IOREG_VADDR(o) = htobe32(v) 47 48 49 /* 50 * RMIXL Coprocessor 2 registers: 51 */ 52 #ifdef _LOCORE 53 #define _(n) __CONCAT($,n) 54 #else 55 #define _(n) n 56 #endif 57 /* 58 * Note CP2 FMN register scope or "context" 59 * L : Local : per thread register 60 * G : Global : per FMN Station (per core) register 61 * L/G : "partly global" : ??? 62 * Global regs should be managed by a single thread 63 * (see XLS PRM "Coprocessor 2 Register Summary") 64 */ 65 /* context ---------------+ */ 66 /* #sels --------------+ | */ 67 /* #regs -----------+ | | */ 68 /* What: #bits --+ | | | */ 69 /* v v v v */ 70 #define RMIXL_COP_2_TXBUF _(0) /* Transmit Buffers 64 [1][4] L */ 71 #define RMIXL_COP_2_RXBUF _(1) /* Receive Buffers 64 [1][4] L */ 72 #define RMIXL_COP_2_MSG_STS _(2) /* Mesage Status 32 [1][2] L/G */ 73 #define RMIXL_COP_2_MSG_CFG _(3) /* MEssage Config 32 [1][2] G */ 74 #define RMIXL_COP_2_MSG_BSZ _(4) /* Message Bucket Size 32 [1][8] G */ 75 #define RMIXL_COP_2_CREDITS _(16) /* Credit Counters 8 [16][8] G */ 76 77 /* 78 * MsgStatus: RMIXL_COP_2_MSG_STS (CP2 Reg 2, Select 0) bits 79 */ 80 #define RMIXL_MSG_STS0_RFBE __BITS(31,24) /* RX FIFO Buckets bit mask 81 * 0=not empty 82 * 1=empty 83 */ 84 #define RMIXL_MSG_STS0_RFBE_SHIFT 24 85 #define RMIXL_MSG_STS0_RESV __BIT(23) 86 #define RMIXL_MSG_STS0_RMSID __BITS(22,16) /* Source ID */ 87 #define RMIXL_MSG_STS0_RMSID_SHIFT 16 88 #define RMIXL_MSG_STS0_RMSC __BITS(15,8) /* RX Message Software Code */ 89 #define RMIXL_MSG_STS0_RMSC_SHIFT 8 90 #define RMIXL_MSG_STS0_RMS __BITS(7,6) /* RX Message Size (minus 1) */ 91 #define RMIXL_MSG_STS0_RMS_SHIFT 6 92 #define RMIXL_MSG_STS0_LEF __BIT(5) /* Load Empty Fail */ 93 #define RMIXL_MSG_STS0_LPF __BIT(4) /* Load Pending Fail */ 94 #define RMIXL_MSG_STS0_LMP __BIT(3) /* Load Message Pending */ 95 #define RMIXL_MSG_STS0_SCF __BIT(2) /* Send Credit Fail */ 96 #define RMIXL_MSG_STS0_SPF __BIT(1) /* Send Pending Fail */ 97 #define RMIXL_MSG_STS0_SMP __BIT(0) /* Send Message Pending */ 98 #define RMIXL_MSG_STS0_ERRS \ 99 (RMIXL_MSG_STS0_LEF|RMIXL_MSG_STS0_LPF|RMIXL_MSG_STS0_LMP \ 100 |RMIXL_MSG_STS0_SCF|RMIXL_MSG_STS0_SPF|RMIXL_MSG_STS0_SMP) 101 102 /* 103 * MsgStatus1: RMIXL_COP_2_MSG_STS (CP2 Reg 2, Select 1) bits 104 */ 105 #define RMIXL_MSG_STS1_RESV __BIT(31) 106 #define RMIXL_MSG_STS1_C __BIT(30) /* Credit Overrun Error */ 107 #define RMIXL_MSG_STS1_CCFCME __BITS(29,23) /* Credit Counter of Free Credit Message with Error */ 108 #define RMIXL_MSG_STS1_CCFCME_SHIFT 23 109 #define RMIXL_MSG_STS1_SIDFCME __BITS(22,16) /* Source ID of Free Credit Message with Error */ 110 #define RMIXL_MSG_STS1_SIDFCME_SHIFT 16 111 #define RMIXL_MSG_STS1_T __BIT(15) /* Invalid Target Error */ 112 #define RMIXL_MSG_STS1_F __BIT(14) /* Receive Queue "Write When Full" Error */ 113 #define RMIXL_MSG_STS1_SIDE __BITS(13,7) /* Source ID of incoming msg with Error */ 114 #define RMIXL_MSG_STS1_SIDE_SHIFT 7 115 #define RMIXL_MSG_STS1_DIDE __BITS(6,0) /* Destination ID of the incoming message Message with Error */ 116 #define RMIXL_MSG_STS1_DIDE_SHIFT 0 117 #define RMIXL_MSG_STS1_ERRS \ 118 (RMIXL_MSG_STS1_C|RMIXL_MSG_STS1_T|RMIXL_MSG_STS1_F) 119 120 /* 121 * MsgConfig: RMIXL_COP_2_MSG_CFG (CP2 Reg 3, Select 0) bits 122 */ 123 #define RMIXL_MSG_CFG0_WM __BITS(31,24) /* Watermark level */ 124 #define RMIXL_MSG_CFG0_WMSHIFT 24 125 #define RMIXL_MSG_CFG0_RESa __BITS(23,22) 126 #define RMIXL_MSG_CFG0_IV __BITS(21,16) /* Interrupt Vector */ 127 #define RMIXL_MSG_CFG0_IV_SHIFT 16 128 #define RMIXL_MSG_CFG0_RESb __BITS(15,12) 129 #define RMIXL_MSG_CFG0_ITM __BITS(11,8) /* Interrupt Thread Mask */ 130 #define RMIXL_MSG_CFG0_ITM_SHIFT 8 131 #define RMIXL_MSG_CFG0_RESc __BITS(7,2) 132 #define RMIXL_MSG_CFG0_WIE __BIT(1) /* Watermark Interrupt Enable */ 133 #define RMIXL_MSG_CFG0_EIE __BIT(0) /* Receive Queue Not Empty Enable */ 134 #define RMIXL_MSG_CFG0_RESV \ 135 (RMIXL_MSG_CFG0_RESa|RMIXL_MSG_CFG0_RESb|RMIXL_MSG_CFG0_RESc) 136 137 /* 138 * MsgConfig1: RMIXL_COP_2_MSG_CFG (CP2 Reg 3, Select 1) bits 139 * Note: reg width is 64 bits in PRM reg description, but 32 bits in reg summary 140 */ 141 #define RMIXL_MSG_CFG1_RESV __BITS(63,3) 142 #define RMIXL_MSG_CFG1_T __BIT(2) /* Trace Mode Enable */ 143 #define RMIXL_MSG_CFG1_C __BIT(1) /* Credit Over-run Interrupt Enable */ 144 #define RMIXL_MSG_CFG1_M __BIT(0) /* Messaging Errors Interrupt Enable */ 145 146 147 /* 148 * MsgBucketSize: RMIXL_COP_2_MSG_BSZ (CP2 Reg 4, Select [0..7]) bits 149 * Note: reg width is 64 bits in PRM reg description, but 32 bits in reg summary 150 * Size: 151 * - 0 means bucket disabled, else 152 * - must be power of 2 153 * - must be >=4 154 */ 155 #define RMIXL_MSG_BSZ_RESV __BITS(63,8) 156 #define RMIXL_MSG_BSZ_SIZE __BITS(7,0) 157 158 159 160 161 /* 162 * RMIXL Processor Control Register addresses 163 * - Offset in bits 7..0 164 * - BlockID in bits 15..8 165 */ 166 #define RMIXL_PCR_THREADEN 0x0000 167 #define RMIXL_PCR_SOFTWARE_SLEEP 0x0001 168 #define RMIXL_PCR_SCHEDULING 0x0002 169 #define RMIXL_PCR_SCHEDULING_COUNTERS 0x0003 170 #define RMIXL_PCR_BHRPM 0x0004 171 #define RMIXL_PCR_IFU_DEFEATURE 0x0006 172 #define RMIXL_PCR_ICU_DEFEATURE 0x0100 173 #define RMIXL_PCR_ICU_ERROR_LOGGING 0x0101 174 #define RMIXL_PCR_ICU_DEBUG_ACCESS_ADDR 0x0102 175 #define RMIXL_PCR_ICU_DEBUG_ACCESS_DATALO 0x0103 176 #define RMIXL_PCR_ICU_DEBUG_ACCESS_DATAHI 0x0104 177 #define RMIXL_PCR_ICU_SAMPLING_LFSR 0x0105 178 #define RMIXL_PCR_ICU_SAMPLING_PC 0x0106 179 #define RMIXL_PCR_ICU_SAMPLING_SETUP 0x0107 180 #define RMIXL_PCR_ICU_SAMPLING_TIMER 0x0108 181 #define RMIXL_PCR_ICU_SAMPLING_PC_UPPER 0x0109 182 #define RMIXL_PCR_IEU_DEFEATURE 0x0200 183 #define RMIXL_PCR_TARGET_PC_REGISTER 0x0207 184 #define RMIXL_PCR_L1D_CONFIG0 0x0300 185 #define RMIXL_PCR_L1D_CONFIG1 0x0301 186 #define RMIXL_PCR_L1D_CONFIG2 0x0302 187 #define RMIXL_PCR_L1D_CONFIG3 0x0303 188 #define RMIXL_PCR_L1D_CONFIG4 0x0304 189 #define RMIXL_PCR_L1D_STATUS 0x0305 190 #define RMIXL_PCR_L1D_DEFEATURE 0x0306 191 #define RMIXL_PCR_L1D_DEBUG0 0x0307 192 #define RMIXL_PCR_L1D_DEBUG1 0x0308 193 #define RMIXL_PCR_L1D_CACHE_ERROR_LOG 0x0309 194 #define RMIXL_PCR_L1D_CACHE_ERROR_OVF_LO 0x030A 195 #define RMIXL_PCR_L1D_CACHE_INTERRUPT 0x030B 196 #define RMIXL_PCR_MMU_SETUP 0x0400 197 #define RMIXL_PCR_PRF_SMP_EVENT 0x0500 198 #define RMIXL_PCR_RF_SMP_RPLY_BUF 0x0501 199 200 /* PCR bit defines TBD */ 201 202 203 /* 204 * Memory Distributed Interconnect (MDI) System Memory Map 205 */ 206 #define RMIXL_PHYSADDR_MAX 0xffffffffffLL /* 1TB Physical Address space */ 207 #define RMIXL_IO_DEV_PBASE 0x1ef00000 /* default phys. from XL[RS]_IO_BAR */ 208 #define RMIXL_IO_DEV_VBASE MIPS_PHYS_TO_KSEG1(RMIXL_IO_DEV_PBASE) 209 /* default virtual base address */ 210 #define RMIXL_IO_DEV_SIZE 0x100000 /* I/O Conf. space is 1MB region */ 211 212 213 214 /* 215 * Peripheral and I/O Configuration Region of Memory 216 * 217 * These are relocatable; we run using the reset value defaults, 218 * and we expect to inherit those intact from the boot firmware. 219 * 220 * Many of these overlap between XLR and XLS, exceptions are ifdef'ed. 221 * 222 * Device region offsets are relative to RMIXL_IO_DEV_PBASE. 223 */ 224 #define RMIXL_IO_DEV_BRIDGE 0x00000 /* System Bridge Controller (SBC) */ 225 #define RMIXL_IO_DEV_DDR_CHNA 0x01000 /* DDR1/DDR2 DRAM_A Channel, Port MA */ 226 #define RMIXL_IO_DEV_DDR_CHNB 0x02000 /* DDR1/DDR2 DRAM_B Channel, Port MB */ 227 #define RMIXL_IO_DEV_DDR_CHNC 0x03000 /* DDR1/DDR2 DRAM_C Channel, Port MC */ 228 #define RMIXL_IO_DEV_DDR_CHND 0x04000 /* DDR1/DDR2 DRAM_D Channel, Port MD */ 229 #if defined(MIPS64_XLR) 230 #define RMIXL_IO_DEV_SRAM 0x07000 /* SRAM Controller, Port SA */ 231 #endif /* MIPS64_XLR */ 232 #define RMIXL_IO_DEV_PIC 0x08000 /* Programmable Interrupt Controller */ 233 #if defined(MIPS64_XLR) 234 #define RMIXL_IO_DEV_PCIX 0x09000 /* PCI-X */ 235 #define RMIXL_IO_DEV_HT 0x0a000 /* HyperTransport */ 236 #endif /* MIPS64_XLR */ 237 #define RMIXL_IO_DEV_SAE 0x0b000 /* Security Acceleration Engine */ 238 #if defined(MIPS64_XLS) 239 #define XAUI_INTERFACE_0 0x0c000 /* XAUI Interface_0 */ 240 /* when SGMII Interface_[0-3] are not used */ 241 #define RMIXL_IO_DEV_GMAC_0 0x0c000 /* SGMII-Interface_0, Port SGMII0 */ 242 #define RMIXL_IO_DEV_GMAC_1 0x0d000 /* SGMII-Interface_1, Port SGMII1 */ 243 #define RMIXL_IO_DEV_GMAC_2 0x0e000 /* SGMII-Interface_2, Port SGMII2 */ 244 #define RMIXL_IO_DEV_GMAC_3 0x0f000 /* SGMII-Interface_3, Port SGMII3 */ 245 #endif /* MIPS64_XLS */ 246 #if defined(MIPS64_XLR) 247 #define RMIXL_IO_DEV_GMAC_A 0x0c000 /* RGMII-Interface_0, Port RA */ 248 #define RMIXL_IO_DEV_GMAC_B 0x0d000 /* RGMII-Interface_1, Port RB */ 249 #define RMIXL_IO_DEV_GMAC_C 0x0e000 /* RGMII-Interface_2, Port RC */ 250 #define RMIXL_IO_DEV_GMAC_D 0x0f000 /* RGMII-Interface_3, Port RD */ 251 #define RMIXL_IO_DEV_SPI4_A 0x10000 /* SPI-4.2-Interface_A, Port XA */ 252 #define RMIXL_IO_DEV_XGMAC_A 0x11000 /* XGMII-Interface_A, Port XA */ 253 #define RMIXL_IO_DEV_SPI4_B 0x12000 /* SPI-4.2-Interface_B, Port XB */ 254 #define RMIXL_IO_DEV_XGMAC_B 0x13000 /* XGMII-Interface_B, Port XB */ 255 #endif /* MIPS64_XLR */ 256 #define RMIXL_IO_DEV_UART_1 0x14000 /* UART_1 (16550 w/ ax4 addrs) */ 257 #define RMIXL_IO_DEV_UART_2 0x15000 /* UART_2 (16550 w/ ax4 addrs) */ 258 #define RMIXL_IO_DEV_I2C_1 0x16000 /* I2C_1 */ 259 #define RMIXL_IO_DEV_I2C_2 0x17000 /* I2C_2 */ 260 #define RMIXL_IO_DEV_GPIO 0x18000 /* GPIO */ 261 #define RMIXL_IO_DEV_FLASH 0x19000 /* Flash ROM */ 262 #define RMIXL_IO_DEV_DMA 0x1a000 /* DMA */ 263 #define RMIXL_IO_DEV_L2 0x1b000 /* L2 Cache */ 264 #define RMIXL_IO_DEV_TB 0x1c000 /* Trace Buffer */ 265 #if defined(MIPS64_XLS) 266 #define RMIXL_IO_DEV_CDE 0x1d000 /* Compression/Decompression Engine */ 267 #define RMIXL_IO_DEV_PCIE_BE 0x1e000 /* PCI-Express_BE */ 268 #define RMIXL_IO_DEV_PCIE_LE 0x1f000 /* PCI-Express_LE */ 269 #define RMIXL_IO_DEV_SRIO_BE 0x1e000 /* SRIO_BE */ 270 #define RMIXL_IO_DEV_SRIO_LE 0x1f000 /* SRIO_LE */ 271 #define RMIXL_IO_DEV_XAUI_1 0x20000 /* XAUI Interface_1 */ 272 /* when SGMII Interface_[4-7] are not used */ 273 #define RMIXL_IO_DEV_GMAC_4 0x20000 /* SGMII-Interface_4, Port SGMII4 */ 274 #define RMIXL_IO_DEV_GMAC_5 0x21000 /* SGMII-Interface_5, Port SGMII5 */ 275 #define RMIXL_IO_DEV_GMAC_6 0x22000 /* SGMII-Interface_6, Port SGMII6 */ 276 #define RMIXL_IO_DEV_GMAC_7 0x23000 /* SGMII-Interface_7, Port SGMII7 */ 277 #define RMIXL_IO_DEV_USB_A 0x24000 /* USB Interface Low Address Space */ 278 #define RMIXL_IO_DEV_USB_B 0x25000 /* USB Interface High Address Space */ 279 #endif /* MIPS64_XLS */ 280 281 282 /* 283 * the Programming Reference Manual 284 * lists "Reg ID" values not offsets; 285 * offset = id * 4 286 */ 287 #define _RMIXL_OFFSET(id) ((id) * 4) 288 289 290 /* 291 * System Bridge Controller registers 292 * offsets are relative to RMIXL_IO_DEV_BRIDGE 293 */ 294 #define RMIXL_SBC_DRAM_NBARS 8 295 #define RMIXL_SBC_DRAM_BAR(n) _RMIXL_OFFSET(0x000 + (n)) 296 /* DRAM Region Base Address Regs[0-7] */ 297 #define RMIXL_SBC_DRAM_CHNAC_DTR(n) _RMIXL_OFFSET(0x008 + (n)) 298 /* DRAM Region Channels A,C Address Translation Regs[0-7] */ 299 #define RMIXL_SBC_DRAM_CHNBD_DTR(n) _RMIXL_OFFSET(0x010 + (n)) 300 /* DRAM Region Channels B,D Address Translation Regs[0-7] */ 301 #define RMIXL_SBC_DRAM_BRIDGE_CFG _RMIXL_OFFSET(0x18) /* SBC DRAM config reg */ 302 #define RMIXL_SBC_XLS_IO_BAR _RMIXL_OFFSET(0x19) /* I/O Config Base Addr reg */ 303 #define RMIXL_SBC_XLS_FLASH_BAR _RMIXL_OFFSET(0x20) /* Flash Memory Base Addr reg */ 304 #define RMIXL_SBC_PCIE_CFG_BAR _RMIXL_OFFSET(0x40) /* PCI Configuration BAR */ 305 #define RMIXL_SBC_PCIE_ECFG_BAR _RMIXL_OFFSET(0x41) /* PCI Extended Configuration BAR */ 306 #define RMIXL_SBC_PCIE_MEM_BAR _RMIXL_OFFSET(0x42) /* PCI Memory region BAR */ 307 #define RMIXL_SBC_PCIE_IO_BAR _RMIXL_OFFSET(0x43) /* PCI IO region BAR */ 308 309 /* 310 * Address Error registers 311 * offsets are relative to RMIXL_IO_DEV_BRIDGE 312 */ 313 #define RMIXL_ADDR_ERR_DEVICE_MASK _RMIXL_OFFSET(0x25) /* Address Error Device Mask */ 314 #define RMIXL_ADDR_ERR_DEVICE_MASK_2 _RMIXL_OFFSET(0x44) /* extension of Device Mask */ 315 #define RMIXL_ADDR_ERR_AERR0_LOG1 _RMIXL_OFFSET(0x26) /* Address Error Set 0 Log 1 */ 316 #define RMIXL_ADDR_ERR_AERR0_LOG2 _RMIXL_OFFSET(0x27) /* Address Error Set 0 Log 2 */ 317 #define RMIXL_ADDR_ERR_AERR0_LOG3 _RMIXL_OFFSET(0x28) /* Address Error Set 0 Log 3 */ 318 #define RMIXL_ADDR_ERR_AERR0_DEVSTAT _RMIXL_OFFSET(0x29) /* Address Error Set 0 irpt status */ 319 #define RMIXL_ADDR_ERR_AERR1_LOG1 _RMIXL_OFFSET(0x2a) /* Address Error Set 1 Log 1 */ 320 #define RMIXL_ADDR_ERR_AERR1_LOG2 _RMIXL_OFFSET(0x2b) /* Address Error Set 1 Log 2 */ 321 #define RMIXL_ADDR_ERR_AERR1_LOG3 _RMIXL_OFFSET(0x2c) /* Address Error Set 1 Log 3 */ 322 #define RMIXL_ADDR_ERR_AERR1_DEVSTAT _RMIXL_OFFSET(0x2d) /* Address Error Set 1 irpt status */ 323 #define RMIXL_ADDR_ERR_AERR0_EN _RMIXL_OFFSET(0x2e) /* Address Error Set 0 irpt enable */ 324 #define RMIXL_ADDR_ERR_AERR0_UPG _RMIXL_OFFSET(0x2f) /* Address Error Set 0 Upgrade */ 325 #define RMIXL_ADDR_ERR_AERR0_CLEAR _RMIXL_OFFSET(0x30) /* Address Error Set 0 irpt clear */ 326 #define RMIXL_ADDR_ERR_AERR1_CLEAR _RMIXL_OFFSET(0x31) /* Address Error Set 1 irpt clear */ 327 #define RMIXL_ADDR_ERR_SBE_COUNTS _RMIXL_OFFSET(0x32) /* Single Bit Error Counts */ 328 #define RMIXL_ADDR_ERR_DBE_COUNTS _RMIXL_OFFSET(0x33) /* Double Bit Error Counts */ 329 #define RMIXL_ADDR_ERR_BITERR_INT_EN _RMIXL_OFFSET(0x33) /* Bit Error intr enable */ 330 331 /* 332 * RMIXL_SBC_DRAM_BAR bit defines 333 */ 334 #define RMIXL_DRAM_BAR_BASE_ADDR __BITS(31,16) /* bits 39:24 of Base Address */ 335 #define DRAM_BAR_TO_BASE(r) \ 336 (((r) & RMIXL_DRAM_BAR_BASE_ADDR) << (24 - 16)) 337 #define RMIXL_DRAM_BAR_ADDR_MASK __BITS(15,4) /* bits 35:24 of Address Mask */ 338 #define DRAM_BAR_TO_SIZE(r) \ 339 ((((r) & RMIXL_DRAM_BAR_ADDR_MASK) + __BIT(4)) << (24 - 4)) 340 #define RMIXL_DRAM_BAR_INTERLEAVE __BITS(3,1) /* Interleave Mode */ 341 #define RMIXL_DRAM_BAR_STATUS __BIT(0) /* 1='region enabled' */ 342 343 /* 344 * RMIXL_SBC_DRAM_CHNAC_DTR and 345 * RMIXL_SBC_DRAM_CHNBD_DTR bit defines 346 * insert 'divisions' (0, 1 or 2) bits 347 * of value 'partition' 348 * at 'position' bit location. 349 */ 350 #define RMIXL_DRAM_DTR_RESa __BITS(31,14) 351 #define RMIXL_DRAM_DTR_PARTITION __BITS(13,12) 352 #define RMIXL_DRAM_DTR_RESb __BITS(11,10) 353 #define RMIXL_DRAM_DTR_DIVISIONS __BITS(9,8) 354 #define RMIXL_DRAM_DTR_RESc __BITS(7,6) 355 #define RMIXL_DRAM_DTR_POSITION __BITS(5,0) 356 #define RMIXL_DRAM_DTR_RESV \ 357 (RMIXL_DRAM_DTR_RESa|RMIXL_DRAM_DTR_RESb|RMIXL_DRAM_DTR_RESc) 358 359 /* 360 * RMIXL_SBC_DRAM_BRIDGE_CFG bit defines 361 */ 362 #define RMIXL_DRAM_CFG_RESa __BITS(31,13) 363 #define RMIXL_DRAM_CFG_CHANNEL_MODE __BIT(12) 364 #define RMIXL_DRAM_CFG_RESb __BIT(11) 365 #define RMIXL_DRAM_CFG_INTERLEAVE_MODE __BITS(10,8) 366 #define RMIXL_DRAM_CFG_RESc __BITS(7,5) 367 #define RMIXL_DRAM_CFG_BUS_MODE __BIT(4) 368 #define RMIXL_DRAM_CFG_RESd __BITS(3,2) 369 #define RMIXL_DRAM_CFG_DRAM_MODE __BITS(1,0) /* 1=DDR2 */ 370 371 /* 372 * RMIXL_SBC_PCIE_CFG_BAR bit defines 373 */ 374 #define RMIXL_PCIE_CFG_BAR_BASE __BITS(31,17) /* phys address bits 39:25 */ 375 #define RMIXL_PCIE_CFG_BAR_BA_SHIFT (25 - 17) 376 #define RMIXL_PCIE_CFG_BAR_TO_BA(r) \ 377 (((r) & RMIXL_PCIE_CFG_BAR_BASE) << RMIXL_PCIE_CFG_BAR_BA_SHIFT) 378 #define RMIXL_PCIE_CFG_BAR_RESV __BITS(16,1) /* (reserved) */ 379 #define RMIXL_PCIE_CFG_BAR_ENB __BIT(0) /* 1=Enable */ 380 #define RMIXL_PCIE_CFG_SIZE __BIT(25) 381 #define RMIXL_PCIE_CFG_BAR(ba, en) \ 382 ((uint32_t)(((ba) >> (25 - 17)) | ((en) ? RMIXL_PCIE_CFG_BAR_ENB : 0))) 383 384 /* 385 * RMIXL_SBC_PCIE_ECFG_BAR bit defines 386 * (PCIe extended config space) 387 */ 388 #define RMIXL_PCIE_ECFG_BAR_BASE __BITS(31,21) /* phys address bits 39:29 */ 389 #define RMIXL_PCIE_ECFG_BAR_BA_SHIFT (29 - 21) 390 #define RMIXL_PCIE_ECFG_BAR_TO_BA(r) \ 391 (((r) & RMIXL_PCIE_ECFG_BAR_BASE) << RMIXL_PCIE_ECFG_BAR_BA_SHIFT) 392 #define RMIXL_PCIE_ECFG_BAR_RESV __BITS(20,1) /* (reserved) */ 393 #define RMIXL_PCIE_ECFG_BAR_ENB __BIT(0) /* 1=Enable */ 394 #define RMIXL_PCIE_ECFG_SIZE __BIT(29) 395 #define RMIXL_PCIE_ECFG_BAR(ba, en) \ 396 ((uint32_t)(((ba) >> (29 - 21)) | ((en) ? RMIXL_PCIE_ECFG_BAR_ENB : 0))) 397 398 /* 399 * RMIXL_SBC_PCIE_MEM_BAR bit defines 400 */ 401 #define RMIXL_PCIE_MEM_BAR_BASE __BITS(31,16) /* phys address bits 39:24 */ 402 #define RMIXL_PCIE_MEM_BAR_TO_BA(r) \ 403 (((r) & RMIXL_PCIE_MEM_BAR_BASE) << (24 - 16)) 404 #define RMIXL_PCIE_MEM_BAR_MASK __BITS(15,1) /* phys address mask bits 38:24 */ 405 #define RMIXL_PCIE_MEM_BAR_TO_SIZE(r) \ 406 ((((r) & RMIXL_PCIE_MEM_BAR_MASK) + 2) << (24 - 1)) 407 #define RMIXL_PCIE_MEM_BAR_ENB __BIT(0) /* 1=Enable */ 408 #define RMIXL_PCIE_MEM_BAR(ba, en) \ 409 ((uint32_t)(((ba) >> (24 - 16)) | ((en) ? RMIXL_PCIE_MEM_BAR_ENB : 0))) 410 411 /* 412 * RMIXL_SBC_PCIE_IO_BAR bit defines 413 */ 414 #define RMIXL_PCIE_IO_BAR_BASE __BITS(31,18) /* phys address bits 39:26 */ 415 #define RMIXL_PCIE_IO_BAR_TO_BA(r) \ 416 (((r) & RMIXL_PCIE_IO_BAR_BASE) << (26 - 18)) 417 #define RMIXL_PCIE_IO_BAR_RESV __BITS(17,7) /* (reserve) */ 418 #define RMIXL_PCIE_IO_BAR_MASK __BITS(6,1) /* phys address mask bits 31:26 */ 419 #define RMIXL_PCIE_IO_BAR_TO_SIZE(r) \ 420 ((((r) & RMIXL_PCIE_IO_BAR_MASK) + 2) << (26 - 1)) 421 #define RMIXL_PCIE_IO_BAR_ENB __BIT(0) /* 1=Enable */ 422 #define RMIXL_PCIE_IO_BAR(ba, en) \ 423 ((uint32_t)(((ba) >> (26 - 18)) | ((en) ? RMIXL_PCIE_IO_BAR_ENB : 0))) 424 425 426 /* 427 * Programmable Interrupt Controller registers 428 * the Programming Reference Manual table 10.4 429 * lists "Reg ID" values not offsets 430 * Offsets are relative to RMIXL_IO_DEV_BRIDGE 431 */ 432 #define RMIXL_PIC_CONTROL _RMIXL_OFFSET(0x0) 433 #define RMIXL_PIC_IPIBASE _RMIXL_OFFSET(0x4) 434 #define RMIXL_PIC_INTRACK _RMIXL_OFFSET(0x6) 435 #define RMIXL_PIC_WATCHdOGMAXVALUE0 _RMIXL_OFFSET(0x8) 436 #define RMIXL_PIC_WATCHDOGMAXVALUE1 _RMIXL_OFFSET(0x9) 437 #define RMIXL_PIC_WATCHDOGMASK0 _RMIXL_OFFSET(0xa) 438 #define RMIXL_PIC_WATCHDOGMASK1 _RMIXL_OFFSET(0xb) 439 #define RMIXL_PIC_WATCHDOGHEARTBEAT0 _RMIXL_OFFSET(0xc) 440 #define RMIXL_PIC_WATCHDOGHEARTBEAT1 _RMIXL_OFFSET(0xd) 441 #define RMIXL_PIC_IRTENTRYC0(n) _RMIXL_OFFSET(0x40 + (n)) /* 0<=n<=31 */ 442 #define RMIXL_PIC_IRTENTRYC1(n) _RMIXL_OFFSET(0x80 + (n)) /* 0<=n<=31 */ 443 #define RMIXL_PIC_SYSTMRMAXVALC0(n) _RMIXL_OFFSET(0x100 + (n)) /* 0<=n<=7 */ 444 #define RMIXL_PIC_SYSTMRMAXVALC1(n) _RMIXL_OFFSET(0x110 + (n)) /* 0<=n<=7 */ 445 #define RMIXL_PIC_SYSTMRC0(n) _RMIXL_OFFSET(0x120 + (n)) /* 0<=n<=7 */ 446 #define RMIXL_PIC_SYSTMRC1(n) _RMIXL_OFFSET(0x130 + (n)) /* 0<=n<=7 */ 447 448 /* 449 * RMIXL_PIC_CONTROL bits 450 */ 451 #define RMIXL_PIC_CONTROL_WATCHDOG_ENB __BIT(0) 452 #define RMIXL_PIC_CONTROL_GEN_NMI __BITS(2,1) /* do NMI after n WDog irpts */ 453 #define RMIXL_PIC_CONTROL_GEN_NMIn(n) (((n) << 1) & RMIXL_PIC_CONTROL_GEN_NMI) 454 #define RMIXL_PIC_CONTROL_RESa __BITS(7,3) 455 #define RMIXL_PIC_CONTROL_TIMER_ENB __BITS(15,8) /* per-Timer enable bits */ 456 #define RMIXL_PIC_CONTROL_TIMER_ENBn(n) ((1 << (8 + (n))) & RMIXL_PIC_CONTROL_TIMER_ENB) 457 #define RMIXL_PIC_CONTROL_RESb __BITS(31,16) 458 #define RMIXL_PIC_CONTROL_RESV \ 459 (RMIXL_PIC_CONTROL_RESa|RMIXL_PIC_CONTROL_RESb) 460 461 /* 462 * RMIXL_PIC_IPIBASE bits 463 */ 464 #define RMIXL_PIC_IPIBASE_VECTORNUM __BITS(5,0) 465 #define RMIXL_PIC_IPIBASE_RESa __BIT(6) /* undocumented bit */ 466 #define RMIXL_PIC_IPIBASE_BCAST __BIT(7) 467 #define RMIXL_PIC_IPIBASE_NMI __BIT(8) 468 #define RMIXL_PIC_IPIBASE_ID __BITS(31,16) 469 #define RMIXL_PIC_IPIBASE_ID_RESb __BITS(31,23) 470 #define RMIXL_PIC_IPIBASE_ID_CORE __BITS(22,20) /* Physical CPU ID */ 471 #define RMIXL_PIC_IPIBASE_ID_CORE_SHIFT 20 472 #define RMIXL_PIC_IPIBASE_ID_RESc __BITS(19,18) 473 #define RMIXL_PIC_IPIBASE_ID_THREAD __BITS(17,16) /* Thread ID */ 474 #define RMIXL_PIC_IPIBASE_ID_THREAD_SHIFT 16 475 #define RMIXL_PIC_IPIBASE_ID_RESV \ 476 (RMIXL_PIC_IPIBASE_ID_RESa|RMIXL_PIC_IPIBASE_ID_RESb \ 477 |RMIXL_PIC_IPIBASE_ID_RESc) 478 479 /* 480 * RMIXL_PIC_IRTENTRYC0 bits 481 * IRT Entry low word 482 */ 483 #define RMIXL_PIC_IRTENTRYC0_TMASK __BITS(7,0) /* Thread Mask */ 484 #define RMIXL_PIC_IRTENTRYC0_RESa __BITS(3,2) /* write as 0 */ 485 #define RMIXL_PIC_IRTENTRYC0_RESb __BITS(31,8) /* write as 0 */ 486 #define RMIXL_PIC_IRTENTRYC0_RESV \ 487 (RMIXL_PIC_IRTENTRYC0_RESa | RMIXL_PIC_IRTENTRYC0_RESb) 488 489 /* 490 * RMIXL_PIC_IRTENTRYC1 bits 491 * IRT Entry high word 492 */ 493 #define RMIXL_PIC_IRTENTRYC1_INTVEC __BITS(5,0) /* maps to bit# in CPU's EIRR */ 494 #define RMIXL_PIC_IRTENTRYC1_GL __BIT(6) /* 0=Global; 1=Local */ 495 #define RMIXL_PIC_IRTENTRYC1_NMI __BIT(7) /* 0=Maskable; 1=NMI */ 496 #define RMIXL_PIC_IRTENTRYC1_RESV __BITS(28,8) 497 #define RMIXL_PIC_IRTENTRYC1_P __BIT(29) /* 0=Rising/High; 1=Falling/Low */ 498 #define RMIXL_PIC_IRTENTRYC1_TRG __BIT(30) /* 0=Edge; 1=Level */ 499 #define RMIXL_PIC_IRTENTRYC1_VALID __BIT(31) /* 0=Invalid; 1=Valid IRT Entry */ 500 501 502 /* 503 * GPIO Controller registers 504 */ 505 506 /* GPIO Signal Registers */ 507 #define RMIXL_GPIO_INT_ENB _RMIXL_OFFSET(0x0) /* Interrupt Enable register */ 508 #define RMIXL_GPIO_INT_INV _RMIXL_OFFSET(0x1) /* Interrupt Inversion register */ 509 #define RMIXL_GPIO_IO_DIR _RMIXL_OFFSET(0x2) /* I/O Direction register */ 510 #define RMIXL_GPIO_OUTPUT _RMIXL_OFFSET(0x3) /* Output Write register */ 511 #define RMIXL_GPIO_INPUT _RMIXL_OFFSET(0x4) /* Intput Read register */ 512 #define RMIXL_GPIO_INT_CLR _RMIXL_OFFSET(0x5) /* Interrupt Inversion register */ 513 #define RMIXL_GPIO_INT_STS _RMIXL_OFFSET(0x6) /* Interrupt Status register */ 514 #define RMIXL_GPIO_INT_TYP _RMIXL_OFFSET(0x7) /* Interrupt Type register */ 515 #define RMIXL_GPIO_RESET _RMIXL_OFFSET(0x8) /* XLS Soft Reset register */ 516 517 /* 518 * RMIXL_GPIO_RESET bits 519 */ 520 #define RMIXL_GPIO_RESET_RESV __BITS(31,1) 521 #define RMIXL_GPIO_RESET_RESET __BIT(0) 522 523 524 /* GPIO System Control Registers */ 525 #define RMIXL_GPIO_RESET_CFG _RMIXL_OFFSET(0x15) /* Reset Configuration register */ 526 #define RMIXL_GPIO_THERMAL_CSR _RMIXL_OFFSET(0x16) /* Thermal Control/Status register */ 527 #define RMIXL_GPIO_THERMAL_SHFT _RMIXL_OFFSET(0x17) /* Thermal Shift register */ 528 #define RMIXL_GPIO_BIST_ALL_STS _RMIXL_OFFSET(0x18) /* BIST All Status register */ 529 #define RMIXL_GPIO_BIST_EACH_STS _RMIXL_OFFSET(0x19) /* BIST Each Status register */ 530 #define RMIXL_GPIO_SGMII_0_3_PHY_CTL _RMIXL_OFFSET(0x20) /* SGMII #0..3 PHY Control register */ 531 #define RMIXL_GPIO_AUI_0_PHY_CTL _RMIXL_OFFSET(0x20) /* AUI port#0 PHY Control register */ 532 #define RMIXL_GPIO_SGMII_4_7_PLL_CTL _RMIXL_OFFSET(0x21) /* SGMII #4..7 PLL Control register */ 533 #define RMIXL_GPIO_AUI_1_PLL_CTL _RMIXL_OFFSET(0x21) /* AUI port#1 PLL Control register */ 534 #define RMIXL_GPIO_SGMII_4_7_PHY_CTL _RMIXL_OFFSET(0x22) /* SGMII #4..7 PHY Control register */ 535 #define RMIXL_GPIO_AUI_1_PHY_CTL _RMIXL_OFFSET(0x22) /* AUI port#1 PHY Control register */ 536 #define RMIXL_GPIO_INT_MAP _RMIXL_OFFSET(0x25) /* Interrupt Map to PIC, 0=int14, 1=int30 */ 537 #define RMIXL_GPIO_EXT_INT _RMIXL_OFFSET(0x26) /* External Interrupt control register */ 538 #define RMIXL_GPIO_CPU_RST _RMIXL_OFFSET(0x28) /* CPU Reset control register */ 539 #define RMIXL_GPIO_LOW_PWR_DIS _RMIXL_OFFSET(0x29) /* Low Power Dissipation register */ 540 #define RMIXL_GPIO_RANDOM _RMIXL_OFFSET(0x2b) /* Low Power Dissipation register */ 541 #define RMIXL_GPIO_CPU_CLK_DIS _RMIXL_OFFSET(0x2d) /* CPU Clock Disable register */ 542 543 /* 544 * RMIXL_GPIO_RESET_CFG bits 545 */ 546 #define RMIXL_GPIO_RESET_CFG_RESa __BITS(31,28) 547 #define RMIXL_GPIO_RESET_CFG_PCIE_SRIO_SEL __BITS(27,26) /* PCIe or SRIO Select: 548 * 00 = PCIe selected, SRIO not available 549 * 01 = SRIO selected, 1.25 Gbaud (1.0 Gbps) 550 * 10 = SRIO selected, 2.25 Gbaud (2.0 Gbps) 551 * 11 = SRIO selected, 3.125 Gbaud (2.5 Gbps) 552 */ 553 #define RMIXL_GPIO_RESET_CFG_XAUI_PORT1_SEL __BIT(25) /* XAUI Port 1 Select: 554 * 0 = Disabled - Port is SGMII ports 4-7 555 * 1 = Enabled - Port is 4-lane XAUI Port 1 556 */ 557 #define RMIXL_GPIO_RESET_CFG_XAUI_PORT0_SEL __BIT(24) /* XAUI Port 0 Select: 558 * 0 = Disabled - Port is SGMII ports 0-3 559 * 1 = Enabled - Port is 4-lane XAUI Port 0 560 */ 561 #define RMIXL_GPIO_RESET_CFG_RESb __BIT(23) 562 #define RMIXL_GPIO_RESET_CFG_USB_DEV __BIT(22) /* USB Device: 563 * 0 = Device Mode 564 * 1 = Host Mode 565 */ 566 #define RMIXL_GPIO_RESET_CFG_PCIE_CFG __BITS(21,20) /* PCIe or SRIO configuration */ 567 #define RMIXL_GPIO_RESET_CFG_FLASH33_EN __BIT(19) /* Flash 33 MHZ Enable: 568 * 0 = 66.67 MHz 569 * 1 = 33.33 MHz 570 */ 571 #define RMIXL_GPIO_RESET_CFG_BIST_DIAG_EN __BIT(18) /* BIST Diagnostics enable */ 572 #define RMIXL_GPIO_RESET_CFG_BIST_RUN_EN __BIT(18) /* BIST Run enable */ 573 #define RMIXL_GPIO_RESET_CFG_NOOT_NAND __BIT(16) /* Enable boot from NAND Flash */ 574 #define RMIXL_GPIO_RESET_CFG_BOOT_PCMCIA __BIT(15) /* Enable boot from PCMCIA */ 575 #define RMIXL_GPIO_RESET_CFG_FLASH_CFG __BIT(14) /* Flash 32-bit Data Configuration: 576 * 0 = 32-bit address / 16-bit data 577 * 1 = 32-bit address / 32-bit data 578 */ 579 #define RMIXL_GPIO_RESET_CFG_PCMCIA_EN __BIT(13) /* PCMCIA Enable Status */ 580 #define RMIXL_GPIO_RESET_CFG_PARITY_EN __BIT(12) /* Parity Enable Status */ 581 #define RMIXL_GPIO_RESET_CFG_BIGEND __BIT(11) /* Big Endian Mode Enable Status */ 582 #define RMIXL_GPIO_RESET_CFG_PLL1_OUT_DIV __BITS(10,8) /* PLL1 (Core PLL) Output Divider */ 583 #define RMIXL_GPIO_RESET_CFG_PLL1_FB_DIV __BITS(7,0) /* PLL1 Feedback Divider */ 584 585 /* 586 * RMIXL_GPIO_LOW_PWR_DIS bits 587 * except as noted, all bits are: 588 * 0 = feature enable (default) 589 * 1 = feature disable 590 */ 591 /* XXX defines are for XLS6xx, XLS4xx-Lite and XLS4xx Devices */ 592 #define RMIXL_GPIO_LOW_PWR_DIS_LP __BIT(0) /* Low Power disable */ 593 #define RMIXL_GPIO_LOW_PWR_DIS_GMAC_QD_0 __BIT(1) /* GMAC Quad 0 (GMAC 0..3) disable */ 594 #define RMIXL_GPIO_LOW_PWR_DIS_GMAC_QD_1 __BIT(2) /* GMAC Quad 1 (GMAC 4..7) disable */ 595 #define RMIXL_GPIO_LOW_PWR_DIS_USB __BIT(3) /* USB disable */ 596 #define RMIXL_GPIO_LOW_PWR_DIS_PCIE __BIT(4) /* PCIE disable */ 597 #define RMIXL_GPIO_LOW_PWR_DIS_CDE __BIT(5) /* Compression/Decompression Engine disable */ 598 #define RMIXL_GPIO_LOW_PWR_DIS_DMA __BIT(6) /* DMA Engine disable */ 599 #define RMIXL_GPIO_LOW_PWR_DIS_SAE __BITS(8,7) /* Security Acceleration Engine disable: 600 * 00 = enable (default) 601 * 01 = reserved 602 * 10 = reserved 603 * 11 = disable 604 */ 605 #define RMIXL_GPIO_LOW_PWR_DIS_RESV __BITS(31,9) 606 607 608 /* 609 * PCIE Interface Controller registers 610 */ 611 #define RMIXL_PCIE_CTRL1 _RMIXL_OFFSET(0x0) 612 #define RMIXL_PCIE_CTRL2 _RMIXL_OFFSET(0x1) 613 #define RMIXL_PCIE_CTRL3 _RMIXL_OFFSET(0x2) 614 #define RMIXL_PCIE_CTRL4 _RMIXL_OFFSET(0x3) 615 #define RMIXL_PCIE_CTRL _RMIXL_OFFSET(0x4) 616 #define RMIXL_PCIE_IOBM_TIMER _RMIXL_OFFSET(0x5) 617 #define RMIXL_PCIE_MSI_CMD _RMIXL_OFFSET(0x6) 618 #define RMIXL_PCIE_MSI_RESP _RMIXL_OFFSET(0x7) 619 #define RMIXL_PCIE_DWC_CRTL5 _RMIXL_OFFSET(0x8) /* not on XLS408Lite, XLS404Lite */ 620 #define RMIXL_PCIE_DWC_CRTL6 _RMIXL_OFFSET(0x9) /* not on XLS408Lite, XLS404Lite */ 621 #define RMIXL_PCIE_IOBM_SWAP_MEM_BASE _RMIXL_OFFSET(0x10) 622 #define RMIXL_PCIE_IOBM_SWAP_MEM_LIMIT _RMIXL_OFFSET(0x11) 623 #define RMIXL_PCIE_IOBM_SWAP_IO_BASE _RMIXL_OFFSET(0x12) 624 #define RMIXL_PCIE_IOBM_SWAP_IO_LIMIT _RMIXL_OFFSET(0x13) 625 #define RMIXL_PCIE_TRGT_CHRNT_MEM_BASE _RMIXL_OFFSET(0x14) 626 #define RMIXL_PCIE_TRGT_CHRNT_MEM_LIMIT _RMIXL_OFFSET(0x15) 627 #define RMIXL_PCIE_TRGT_L2ALC_MEM_BASE _RMIXL_OFFSET(0x16) 628 #define RMIXL_PCIE_TRGT_L2ALC_MEM_LIMIT _RMIXL_OFFSET(0x17) 629 #define RMIXL_PCIE_TRGT_REX_MEM_BASE _RMIXL_OFFSET(0x18) 630 #define RMIXL_PCIE_TRGT_REX_MEM_LIMIT _RMIXL_OFFSET(0x19) 631 #define RMIXL_PCIE_EP_MEM_BASE _RMIXL_OFFSET(0x1a) 632 #define RMIXL_PCIE_EP_MEM_LIMIT _RMIXL_OFFSET(0x1b) 633 #define RMIXL_PCIE_EP_ADDR_MAP_ENTRY0 _RMIXL_OFFSET(0x1c) 634 #define RMIXL_PCIE_EP_ADDR_MAP_ENTRY1 _RMIXL_OFFSET(0x1d) 635 #define RMIXL_PCIE_EP_ADDR_MAP_ENTRY2 _RMIXL_OFFSET(0x1e) 636 #define RMIXL_PCIE_EP_ADDR_MAP_ENTRY3 _RMIXL_OFFSET(0x1f) 637 #define RMIXL_PCIE_LINK0_STATE _RMIXL_OFFSET(0x20) 638 #define RMIXL_PCIE_LINK1_STATE _RMIXL_OFFSET(0x21) 639 #define RMIXL_PCIE_IOBM_INT_STATUS _RMIXL_OFFSET(0x22) 640 #define RMIXL_PCIE_IOBM_INT_ENABLE _RMIXL_OFFSET(0x23) 641 #define RMIXL_PCIE_LINK0_MSI_STATUS _RMIXL_OFFSET(0x24) 642 #define RMIXL_PCIE_LINK1_MSI_STATUS _RMIXL_OFFSET(0x25) 643 #define RMIXL_PCIE_LINK0_MSI_ENABLE _RMIXL_OFFSET(0x26) 644 #define RMIXL_PCIE_LINK1_MSI_ENABLE _RMIXL_OFFSET(0x27) 645 #define RMIXL_PCIE_LINK0_INT_STATUS0 _RMIXL_OFFSET(0x28) 646 #define RMIXL_PCIE_LINK1_INT_STATUS0 _RMIXL_OFFSET(0x29) 647 #define RMIXL_PCIE_LINK0_INT_STATUS1 _RMIXL_OFFSET(0x2a) 648 #define RMIXL_PCIE_LINK1_INT_STATUS1 _RMIXL_OFFSET(0x2b) 649 #define RMIXL_PCIE_LINK0_INT_ENABLE0 _RMIXL_OFFSET(0x2c) 650 #define RMIXL_PCIE_LINK1_INT_ENABLE0 _RMIXL_OFFSET(0x2d) 651 #define RMIXL_PCIE_LINK0_INT_ENABLE1 _RMIXL_OFFSET(0x2e) 652 #define RMIXL_PCIE_LINK1_INT_ENABLE1 _RMIXL_OFFSET(0x2f) 653 #define RMIXL_PCIE_PHY_CR_CMD _RMIXL_OFFSET(0x30) 654 #define RMIXL_PCIE_PHY_CR_WR_DATA _RMIXL_OFFSET(0x31) 655 #define RMIXL_PCIE_PHY_CR_RESP _RMIXL_OFFSET(0x32) 656 #define RMIXL_PCIE_PHY_CR_RD_DATA _RMIXL_OFFSET(0x33) 657 #define RMIXL_PCIE_IOBM_ERR_CMD _RMIXL_OFFSET(0x34) 658 #define RMIXL_PCIE_IOBM_ERR_LOWER_ADDR _RMIXL_OFFSET(0x35) 659 #define RMIXL_PCIE_IOBM_ERR_UPPER_ADDR _RMIXL_OFFSET(0x36) 660 #define RMIXL_PCIE_IOBM_ERR_BE _RMIXL_OFFSET(0x37) 661 #define RMIXL_PCIE_LINK2_STATE _RMIXL_OFFSET(0x60) /* not on XLS408Lite, XLS404Lite */ 662 #define RMIXL_PCIE_LINK3_STATE _RMIXL_OFFSET(0x61) /* not on XLS408Lite, XLS404Lite */ 663 #define RMIXL_PCIE_LINK2_MSI_STATUS _RMIXL_OFFSET(0x64) /* not on XLS408Lite, XLS404Lite */ 664 #define RMIXL_PCIE_LINK3_MSI_STATUS _RMIXL_OFFSET(0x65) /* not on XLS408Lite, XLS404Lite */ 665 #define RMIXL_PCIE_LINK2_MSI_ENABLE _RMIXL_OFFSET(0x66) /* not on XLS408Lite, XLS404Lite */ 666 #define RMIXL_PCIE_LINK3_MSI_ENABLE _RMIXL_OFFSET(0x67) /* not on XLS408Lite, XLS404Lite */ 667 #define RMIXL_PCIE_LINK2_INT_STATUS0 _RMIXL_OFFSET(0x68) /* not on XLS408Lite, XLS404Lite */ 668 #define RMIXL_PCIE_LINK3_INT_STATUS0 _RMIXL_OFFSET(0x69) /* not on XLS408Lite, XLS404Lite */ 669 #define RMIXL_PCIE_LINK2_INT_STATUS1 _RMIXL_OFFSET(0x6a) /* not on XLS408Lite, XLS404Lite */ 670 #define RMIXL_PCIE_LINK3_INT_STATUS1 _RMIXL_OFFSET(0x6b) /* not on XLS408Lite, XLS404Lite */ 671 #define RMIXL_PCIE_LINK2_INT_ENABLE0 _RMIXL_OFFSET(0x6c) /* not on XLS408Lite, XLS404Lite */ 672 #define RMIXL_PCIE_LINK3_INT_ENABLE0 _RMIXL_OFFSET(0x6d) /* not on XLS408Lite, XLS404Lite */ 673 #define RMIXL_PCIE_LINK2_INT_ENABLE1 _RMIXL_OFFSET(0x6e) /* not on XLS408Lite, XLS404Lite */ 674 #define RMIXL_PCIE_LINK3_INT_ENABLE1 _RMIXL_OFFSET(0x6f) /* not on XLS408Lite, XLS404Lite */ 675 #define RMIXL_VC0_POSTED_RX_QUEUE_CTRL _RMIXL_OFFSET(0x1d2) 676 #define RMIXL_VC0_POSTED_BUFFER_DEPTH _RMIXL_OFFSET(0x1ea) 677 #define RMIXL_PCIE_MSG_TX_THRESHOLD _RMIXL_OFFSET(0x308) 678 #define RMIXL_PCIE_MSG_BUCKET_SIZE_0 _RMIXL_OFFSET(0x320) 679 #define RMIXL_PCIE_MSG_BUCKET_SIZE_1 _RMIXL_OFFSET(0x321) 680 #define RMIXL_PCIE_MSG_BUCKET_SIZE_2 _RMIXL_OFFSET(0x322) 681 #define RMIXL_PCIE_MSG_BUCKET_SIZE_3 _RMIXL_OFFSET(0x323) 682 #define RMIXL_PCIE_MSG_BUCKET_SIZE_4 _RMIXL_OFFSET(0x324) /* not on XLS408Lite, XLS404Lite */ 683 #define RMIXL_PCIE_MSG_BUCKET_SIZE_5 _RMIXL_OFFSET(0x325) /* not on XLS408Lite, XLS404Lite */ 684 #define RMIXL_PCIE_MSG_BUCKET_SIZE_6 _RMIXL_OFFSET(0x326) /* not on XLS408Lite, XLS404Lite */ 685 #define RMIXL_PCIE_MSG_BUCKET_SIZE_7 _RMIXL_OFFSET(0x327) /* not on XLS408Lite, XLS404Lite */ 686 #define RMIXL_PCIE_MSG_CREDIT_FIRST _RMIXL_OFFSET(0x380) 687 #define RMIXL_PCIE_MSG_CREDIT_LAST _RMIXL_OFFSET(0x3ff) 688 689 /* 690 * USB General Interface registers 691 * these are opffset from REGSPACE selected by __BIT(12) == 1 692 * RMIXL_IOREG_VADDR(RMIXL_IO_DEV_USB_B + reg) 693 * see Tables 18-7 and 18-14 in the XLS PRM 694 */ 695 #define RMIXL_USB_GEN_CTRL1 0x00 696 #define RMIXL_USB_GEN_CTRL2 0x04 697 #define RMIXL_USB_GEN_CTRL3 0x08 698 #define RMIXL_USB_IOBM_TIMER 0x0C 699 #define RMIXL_USB_VBUS_TIMER 0x10 700 #define RMIXL_USB_BYTESWAP_EN 0x14 701 #define RMIXL_USB_COHERENT_MEM_BASE 0x40 702 #define RMIXL_USB_COHERENT_MEM_LIMIT 0x44 703 #define RMIXL_USB_L2ALLOC_MEM_BASE 0x48 704 #define RMIXL_USB_L2ALLOC_MEM_LIMIT 0x4C 705 #define RMIXL_USB_READEX_MEM_BASE 0x50 706 #define RMIXL_USB_READEX_MEM_LIMIT 0x54 707 #define RMIXL_USB_PHY_STATUS 0xC0 708 #define RMIXL_USB_INTERRUPT_STATUS 0xC4 709 #define RMIXL_USB_INTERRUPT_ENABLE 0xC8 710 711 /* 712 * RMIXL_USB_GEN_CTRL1 bits 713 */ 714 #define RMIXL_UG_CTRL1_RESV __BITS(31,2) 715 #define RMIXL_UG_CTRL1_HOST_RST __BIT(1) /* Resets the Host Controller 716 * 0: reset 717 * 1: normal operation 718 */ 719 #define RMIXL_UG_CTRL1_DEV_RST __BIT(0) /* Resets the Device Controller 720 * 0: reset 721 * 1: normal operation 722 */ 723 724 /* 725 * RMIXL_USB_GEN_CTRL2 bits 726 */ 727 #define RMIXL_UG_CTRL2_RESa __BITS(31,20) 728 #define RMIXL_UG_CTRL2_TX_TUNE_1 __BITS(19,18) /* Port_1 Transmitter Tuning for High-Speed Operation. 729 * 00: ~-4.5% 730 * 01: Design default 731 * 10: ~+4.5% 732 * 11: ~+9% = Recommended Operating setting 733 */ 734 #define RMIXL_UG_CTRL2_TX_TUNE_0 __BITS(17,16) /* Port_0 Transmitter Tuning for High-Speed Operation 735 * 11: Recommended Operating condition 736 */ 737 #define RMIXL_UG_CTRL2_RESb __BIT(15) 738 #define RMIXL_UG_CTRL2_WEAK_PDEN __BIT(14) /* 500kOhm Pull-Down Resistor on D+ and D- Enable */ 739 #define RMIXL_UG_CTRL2_DP_PULLUP_ESD __BIT(13) /* D+ Pull-Up Resistor Enable */ 740 #define RMIXL_UG_CTRL2_ESD_TEST_MODE __BIT(12) /* D+ Pull-Up Resistor Control Select */ 741 #define RMIXL_UG_CTRL2_TX_BIT_STUFF_EN_H_1 \ 742 __BIT(11) /* Port_1 High-Byte Transmit Bit-Stuffing Enable */ 743 #define RMIXL_UG_CTRL2_TX_BIT_STUFF_EN_H_0 \ 744 __BIT(10) /* Port_0 High-Byte Transmit Bit-Stuffing Enable */ 745 #define RMIXL_UG_CTRL2_TX_BIT_STUFF_EN_L_1 \ 746 __BIT(9) /* Port_1 Low-Byte Transmit Bit-Stuffing Enable */ 747 #define RMIXL_UG_CTRL2_TX_BIT_STUFF_EN_L_0 \ 748 __BIT(8) /* Port_0 Low-Byte Transmit Bit-Stuffing Enable */ 749 #define RMIXL_UG_CTRL2_RESc __BITS(7,6) 750 #define RMIXL_UG_CTRL2_LOOPBACK_ENB_1 __BIT(5) /* Port_1 Loopback Test Enable */ 751 #define RMIXL_UG_CTRL2_LOOPBACK_ENB_0 __BIT(4) /* Port_0 Loopback Test Enable */ 752 #define RMIXL_UG_CTRL2_DEVICE_VBUS __BIT(3) /* VBUS detected (Device mode only) */ 753 #define RMIXL_UG_CTRL2_PHY_PORT_RST_1 __BIT(2) /* Resets Port_1 of the PHY 754 * 1: normal operation 755 * 0: reset 756 */ 757 #define RMIXL_UG_CTRL2_PHY_PORT_RST_0 __BIT(1) /* Resets Port_0 of the PHY 758 * 1: normal operation 759 * 0: reset 760 */ 761 #define RMIXL_UG_CTRL2_PHY_RST __BIT(0) /* Resets the PHY 762 * 1: normal operation 763 * 0: reset 764 */ 765 #define RMIXL_UG_CTRL2_RESV \ 766 (RMIXL_UG_CTRL2_RESa | RMIXL_UG_CTRL2_RESb | RMIXL_UG_CTRL2_RESc) 767 768 769 /* 770 * RMIXL_USB_GEN_CTRL3 bits 771 */ 772 #define RMIXL_UG_CTRL3_RESa __BITS(31,11) 773 #define RMIXL_UG_CTRL3_PREFETCH_SIZE __BITS(10,8) /* The pre-fetch size for a memory read transfer 774 * between USB Interface and DI station. 775 * Valid value ranges is from 1 to 4. 776 */ 777 #define RMIXL_UG_CTRL3_RESb __BIT(7) 778 #define RMIXL_UG_CTRL3_DEV_UPPERADDR __BITS(6,1) /* Device controller address space selector */ 779 #define RMIXL_UG_CTRL3_USB_FLUSH __BIT(0) /* Flush the USB interface */ 780 781 /* 782 * RMIXL_USB_PHY_STATUS bits 783 */ 784 #define RMIXL_UB_PHY_STATUS_RESV __BITS(31,1) 785 #define RMIXL_UB_PHY_STATUS_VBUS __BIT(0) /* USB VBUS status */ 786 787 /* 788 * RMIXL_USB_INTERRUPT_STATUS and RMIXL_USB_INTERRUPT_ENABLE bits 789 */ 790 #define RMIXL_UB_INTERRUPT_RESV __BITS(31,6) 791 #define RMIXL_UB_INTERRUPT_FORCE __BIT(5) /* USB force interrupt */ 792 #define RMIXL_UB_INTERRUPT_PHY __BIT(4) /* USB PHY interrupt */ 793 #define RMIXL_UB_INTERRUPT_DEV __BIT(3) /* USB Device Controller interrupt */ 794 #define RMIXL_UB_INTERRUPT_EHCI __BIT(2) /* USB EHCI interrupt */ 795 #define RMIXL_UB_INTERRUPT_OHCI_1 __BIT(1) /* USB OHCI #1 interrupt */ 796 #define RMIXL_UB_INTERRUPT_OHCI_0 __BIT(0) /* USB OHCI #0 interrupt */ 797 #define RMIXL_UB_INTERRUPT_MAX 5 798 799 800 /* 801 * USB Device Controller registers 802 * these are opffset from REGSPACE selected by __BIT(12) == 0 803 * RMIXL_IOREG_VADDR(RMIXL_IO_DEV_USB_A + reg) 804 * see Table 18-7 in the XLS PRM 805 */ 806 #define RMIXL_USB_UDC_GAHBCFG 0x008 /* UDC Configuration A (UDC_GAHBCFG) */ 807 #define RMIXL_USB_UDC_GUSBCFG 0x00C /* UDC Configuration B (UDC_GUSBCFG) */ 808 #define RMIXL_USB_UDC_GRSTCTL 0x010 /* UDC Reset */ 809 #define RMIXL_USB_UDC_GINTSTS 0x014 /* UDC Interrupt Register */ 810 #define RMIXL_USB_UDC_GINTMSK 0x018 /* UDC Interrupt Mask Register */ 811 #define RMIXL_USB_UDC_GRXSTSP 0x020 /* UDC Receive Status Read /Pop Register (Read Only) */ 812 #define RMIXL_USB_UDC_GRXFSIZ 0x024 /* UDC Receive FIFO Size Register */ 813 #define RMIXL_USB_UDC_GNPTXFSIZ 0x028 /* UDC Non-periodic Transmit FIFO Size Register */ 814 #define RMIXL_USB_UDC_GUID 0x03C /* UDC User ID Register (UDC_GUID) */ 815 #define RMIXL_USB_UDC_GSNPSID 0x040 /* UDC ID Register (Read Only) */ 816 #define RMIXL_USB_UDC_GHWCFG1 0x044 /* UDC User HW Config1 Register (Read Only) */ 817 #define RMIXL_USB_UDC_GHWCFG2 0x048 /* UDC User HW Config2 Register (Read Only) */ 818 #define RMIXL_USB_UDC_GHWCFG3 0x04C /* UDC User HW Config3 Register (Read Only) */ 819 #define RMIXL_USB_UDC_GHWCFG4 0x050 /* UDC User HW Config4 Register (Read Only) */ 820 #define RMIXL_USB_UDC_DPTXFSIZ0 0x104 821 #define RMIXL_USB_UDC_DPTXFSIZ1 0x108 822 #define RMIXL_USB_UDC_DPTXFSIZ2 0x10c 823 #define RMIXL_USB_UDC_DPTXFSIZn(n) (0x104 + (4 * (n))) 824 /* UDC Device IN Endpoint Transmit FIFO-n 825 Size Registers (UDC_DPTXFSIZn) */ 826 #define RMIXL_USB_UDC_DCFG 0x800 /* UDC Configuration C */ 827 #define RMIXL_USB_UDC_DCTL 0x804 /* UDC Control Register */ 828 #define RMIXL_USB_UDC_DSTS 0x808 /* UDC Status Register (Read Only) */ 829 #define RMIXL_USB_UDC_DIEPMSK 0x810 /* UDC Device IN Endpoint Common 830 Interrupt Mask Register (UDC_DIEPMSK) */ 831 #define RMIXL_USB_UDC_DOEPMSK 0x814 /* UDC Device OUT Endpoint Common Interrupt Mask register */ 832 #define RMIXL_USB_UDC_DAINT 0x818 /* UDC Device All Endpoints Interrupt Register */ 833 #define RMIXL_USB_UDC_DAINTMSK 0x81C /* UDC Device All Endpoints Interrupt Mask Register */ 834 #define RMIXL_USB_UDC_DTKNQR3 0x830 /* Device Threshold Control Register */ 835 #define RMIXL_USB_UDC_DTKNQR4 0x834 /* Device IN Endpoint FIFO Empty Interrupt Mask Register */ 836 #define RMIXL_USB_UDC_DIEPCTL 0x900 /* Device Control IN Endpoint 0 Control Register */ 837 #define RMIXL_USB_UDC_DIEPINT 0x908 /* Device IN Endpoint 0 Interrupt Register */ 838 #define RMIXL_USB_UDC_DIEPTSIZ 0x910 /* Device IN Endpoint 0 Transfer Size Register */ 839 #define RMIXL_USB_UDC_DIEPDMA 0x914 /* Device IN Endpoint 0 DMA Address Register */ 840 #define RMIXL_USB_UDC_DTXFSTS 0x918 /* Device IN Endpoint Transmit FIFO Status Register */ 841 #define RMIXL_USB_DEV_IN_ENDPT(d,n) (0x920 + ((d) * 0x20) + ((n) * 4)) 842 /* Device IN Endpoint #d Register #n */ 843 844 /* 845 * USB Host Controller register base addrs 846 * these are offset from REGSPACE selected by __BIT(12) == 0 847 * RMIXL_IOREG_VADDR(RMIXL_IO_DEV_USB_A + reg) 848 * see Table 18-14 in the XLS PRM 849 * specific Host Controller is selected by __BITS(11,10) 850 */ 851 #define RMIXL_USB_HOST_EHCI_BASE 0x000 852 #define RMIXL_USB_HOST_0HCI0_BASE 0x400 853 #define RMIXL_USB_HOST_0HCI1_BASE 0x800 854 #define RMIXL_USB_HOST_RESV 0xc00 855 #define RMIXL_USB_HOST_MASK 0xc00 856 857 858 /* 859 * FMN non-core station configuration registers 860 */ 861 #define RMIXL_FMN_BS_FIRST _RMIXL_OFFSET(0x320) 862 863 /* 864 * SGMII bucket size regs 865 */ 866 #define RMIXL_FMN_BS_SGMII_UNUSED0 _RMIXL_OFFSET(0x320) /* initialize as 0 */ 867 #define RMIXL_FMN_BS_SGMII_FCB _RMIXL_OFFSET(0x321) /* Free Credit Bucket size */ 868 #define RMIXL_FMN_BS_SGMII_TX0 _RMIXL_OFFSET(0x322) 869 #define RMIXL_FMN_BS_SGMII_TX1 _RMIXL_OFFSET(0x323) 870 #define RMIXL_FMN_BS_SGMII_TX2 _RMIXL_OFFSET(0x324) 871 #define RMIXL_FMN_BS_SGMII_TX3 _RMIXL_OFFSET(0x325) 872 #define RMIXL_FMN_BS_SGMII_UNUSED1 _RMIXL_OFFSET(0x326) /* initialize as 0 */ 873 #define RMIXL_FMN_BS_SGMII_FCB1 _RMIXL_OFFSET(0x321) /* Free Credit Bucket1 size */ 874 875 /* 876 * SAE bucket size regs 877 */ 878 #define RMIXL_FMN_BS_SAE_PIPE0 _RMIXL_OFFSET(0x320) 879 #define RMIXL_FMN_BS_SAE_RSA_PIPE _RMIXL_OFFSET(0x321) 880 881 /* 882 * DMA bucket size regs 883 */ 884 #define RMIXL_FMN_BS_DMA_CHAN0 _RMIXL_OFFSET(0x320) 885 #define RMIXL_FMN_BS_DMA_CHAN1 _RMIXL_OFFSET(0x321) 886 #define RMIXL_FMN_BS_DMA_CHAN2 _RMIXL_OFFSET(0x322) 887 #define RMIXL_FMN_BS_DMA_CHAN3 _RMIXL_OFFSET(0x323) 888 889 /* 890 * CDE bucket size regs 891 */ 892 #define RMIXL_FMN_BS_CDE_FREE_DESC _RMIXL_OFFSET(0x320) 893 #define RMIXL_FMN_BS_CDE_COMPDECOMP _RMIXL_OFFSET(0x321) 894 895 /* 896 * PCIe bucket size regs 897 */ 898 #define RMIXL_FMN_BS_PCIE_TX0 _RMIXL_OFFSET(0x320) 899 #define RMIXL_FMN_BS_PCIE_RX0 _RMIXL_OFFSET(0x321) 900 #define RMIXL_FMN_BS_PCIE_TX1 _RMIXL_OFFSET(0x322) 901 #define RMIXL_FMN_BS_PCIE_RX1 _RMIXL_OFFSET(0x323) 902 #define RMIXL_FMN_BS_PCIE_TX2 _RMIXL_OFFSET(0x324) 903 #define RMIXL_FMN_BS_PCIE_RX2 _RMIXL_OFFSET(0x325) 904 #define RMIXL_FMN_BS_PCIE_TX3 _RMIXL_OFFSET(0x326) 905 #define RMIXL_FMN_BS_PCIE_RX3 _RMIXL_OFFSET(0x327) 906 907 /* 908 * non-core Credit Counter offsets 909 */ 910 #define RMIXL_FMN_CC_FIRST _RMIXL_OFFSET(0x380) 911 #define RMIXL_FMN_CC_LAST _RMIXL_OFFSET(0x3ff) 912 913 /* 914 * non-core Credit Counter bit defines 915 */ 916 #define RMIXL_FMN_CC_RESV __BITS(31,8) 917 #define RMIXL_FMN_CC_COUNT __BITS(7,0) 918 919 #endif /* _MIPS_RMI_RMIRMIXLEGS_H_ */ 920 921
Indexes created Mon Oct 27 08:10:08 GMT 2025