rmixlreg.h revision 1.1.2.18
1 /* $NetBSD: rmixlreg.h,v 1.1.2.18 2011/12/31 04:54:28 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Cliff Neighbors 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 33 #ifndef _MIPS_RMI_RMIXLREG_H_ 34 #define _MIPS_RMI_RMIXLREG_H_ 35 36 #include <sys/endian.h> 37 38 /* 39 * on chip I/O register byte order is 40 * BIG ENDIAN regardless of code model 41 */ 42 #define RMIXL_IOREG_VADDR(o) \ 43 (volatile uint32_t *)MIPS_PHYS_TO_KSEG1( \ 44 rmixl_configuration.rc_io.r_pbase + (o)) 45 #define RMIXL_IOREG_READ(o) be32toh(*RMIXL_IOREG_VADDR(o)) 46 #define RMIXL_IOREG_WRITE(o,v) *RMIXL_IOREG_VADDR(o) = htobe32(v) 47 48 49 /* 50 * RMIXL Coprocessor 2 registers: 51 */ 52 #ifdef _LOCORE 53 #define _(n) __CONCAT($,n) 54 #else 55 #define _(n) n 56 #endif 57 /* 58 * Note CP2 FMN register scope or "context" 59 * L : Local : per thread register 60 * G : Global : per FMN Station (per core) register 61 * L/G : "partly global" : ??? 62 * Global regs should be managed by a single thread 63 * (see XLS PRM "Coprocessor 2 Register Summary") 64 */ 65 /* context ---------------+ */ 66 /* #sels --------------+ | */ 67 /* #regs -----------+ | | */ 68 /* What: #bits --+ | | | */ 69 /* v v v v */ 70 #define RMIXL_COP_2_TXBUF _(0) /* Transmit Buffers 64 [1][4] L */ 71 #define RMIXL_COP_2_RXBUF _(1) /* Receive Buffers 64 [1][4] L */ 72 #define RMIXL_COP_2_MSG_STS _(2) /* Mesage Status 32 [1][2] L/G */ 73 #define RMIXL_COP_2_MSG_CFG _(3) /* MEssage Config 32 [1][2] G */ 74 #define RMIXL_COP_2_MSG_BSZ _(4) /* Message Bucket Size 32 [1][8] G */ 75 #define RMIXL_COP_2_CREDITS _(16) /* Credit Counters 8 [16][8] G */ 76 77 /* 78 * MsgStatus: RMIXL_COP_2_MSG_STS (CP2 Reg 2, Select 0) bits 79 */ 80 #define RMIXL_MSG_STS0_RFBE __BITS(31,24) /* RX FIFO Buckets bit mask 81 * 0=not empty 82 * 1=empty 83 */ 84 #define RMIXL_MSG_STS0_RFBE_SHIFT 24 85 #define RMIXL_MSG_STS0_RESV __BIT(23) 86 #define RMIXL_MSG_STS0_RMSID __BITS(22,16) /* Source ID */ 87 #define RMIXL_MSG_STS0_RMSID_SHIFT 16 88 #define RMIXL_MSG_STS0_RMSC __BITS(15,8) /* RX Message Software Code */ 89 #define RMIXL_MSG_STS0_RMSC_SHIFT 8 90 #define RMIXL_MSG_STS0_RMS __BITS(7,6) /* RX Message Size (minus 1) */ 91 #define RMIXL_MSG_STS0_RMS_SHIFT 6 92 #define RMIXL_MSG_STS0_LEF __BIT(5) /* Load Empty Fail */ 93 #define RMIXL_MSG_STS0_LPF __BIT(4) /* Load Pending Fail */ 94 #define RMIXL_MSG_STS0_LMP __BIT(3) /* Load Message Pending */ 95 #define RMIXL_MSG_STS0_SCF __BIT(2) /* Send Credit Fail */ 96 #define RMIXL_MSG_STS0_SPF __BIT(1) /* Send Pending Fail */ 97 #define RMIXL_MSG_STS0_SMP __BIT(0) /* Send Message Pending */ 98 #define RMIXL_MSG_STS0_ERRS \ 99 (RMIXL_MSG_STS0_LEF|RMIXL_MSG_STS0_LPF|RMIXL_MSG_STS0_LMP \ 100 |RMIXL_MSG_STS0_SCF|RMIXL_MSG_STS0_SPF|RMIXL_MSG_STS0_SMP) 101 102 /* 103 * MsgStatus1: RMIXL_COP_2_MSG_STS (CP2 Reg 2, Select 1) bits 104 */ 105 #define RMIXL_MSG_STS1_RESV __BIT(31) 106 #define RMIXL_MSG_STS1_C __BIT(30) /* Credit Overrun Error */ 107 #define RMIXL_MSG_STS1_CCFCME __BITS(29,23) /* Credit Counter of Free Credit Message with Error */ 108 #define RMIXL_MSG_STS1_CCFCME_SHIFT 23 109 #define RMIXL_MSG_STS1_SIDFCME __BITS(22,16) /* Source ID of Free Credit Message with Error */ 110 #define RMIXL_MSG_STS1_SIDFCME_SHIFT 16 111 #define RMIXL_MSG_STS1_T __BIT(15) /* Invalid Target Error */ 112 #define RMIXL_MSG_STS1_F __BIT(14) /* Receive Queue "Write When Full" Error */ 113 #define RMIXL_MSG_STS1_SIDE __BITS(13,7) /* Source ID of incoming msg with Error */ 114 #define RMIXL_MSG_STS1_SIDE_SHIFT 7 115 #define RMIXL_MSG_STS1_DIDE __BITS(6,0) /* Destination ID of the incoming message Message with Error */ 116 #define RMIXL_MSG_STS1_DIDE_SHIFT 0 117 #define RMIXL_MSG_STS1_ERRS \ 118 (RMIXL_MSG_STS1_C|RMIXL_MSG_STS1_T|RMIXL_MSG_STS1_F) 119 120 /* 121 * MsgConfig: RMIXL_COP_2_MSG_CFG (CP2 Reg 3, Select 0) bits 122 */ 123 #define RMIXL_MSG_CFG0_WM __BITS(31,24) /* Watermark level */ 124 #define RMIXL_MSG_CFG0_WMSHIFT 24 125 #define RMIXL_MSG_CFG0_RESa __BITS(23,22) 126 #define RMIXL_MSG_CFG0_IV __BITS(21,16) /* Interrupt Vector */ 127 #define RMIXL_MSG_CFG0_IV_SHIFT 16 128 #define RMIXL_MSG_CFG0_RESb __BITS(15,12) 129 #define RMIXL_MSG_CFG0_ITM __BITS(11,8) /* Interrupt Thread Mask */ 130 #define RMIXL_MSG_CFG0_ITM_SHIFT 8 131 #define RMIXL_MSG_CFG0_RESc __BITS(7,2) 132 #define RMIXL_MSG_CFG0_WIE __BIT(1) /* Watermark Interrupt Enable */ 133 #define RMIXL_MSG_CFG0_EIE __BIT(0) /* Receive Queue Not Empty Enable */ 134 #define RMIXL_MSG_CFG0_RESV \ 135 (RMIXL_MSG_CFG0_RESa|RMIXL_MSG_CFG0_RESb|RMIXL_MSG_CFG0_RESc) 136 137 /* 138 * MsgConfig1: RMIXL_COP_2_MSG_CFG (CP2 Reg 3, Select 1) bits 139 * Note: reg width is 64 bits in PRM reg description, but 32 bits in reg summary 140 */ 141 #define RMIXL_MSG_CFG1_RESV __BITS(63,3) 142 #define RMIXL_MSG_CFG1_T __BIT(2) /* Trace Mode Enable */ 143 #define RMIXL_MSG_CFG1_C __BIT(1) /* Credit Over-run Interrupt Enable */ 144 #define RMIXL_MSG_CFG1_M __BIT(0) /* Messaging Errors Interrupt Enable */ 145 146 147 /* 148 * MsgBucketSize: RMIXL_COP_2_MSG_BSZ (CP2 Reg 4, Select [0..7]) bits 149 * Note: reg width is 64 bits in PRM reg description, but 32 bits in reg summary 150 * Size: 151 * - 0 means bucket disabled, else 152 * - must be power of 2 153 * - must be >=4 154 */ 155 #define RMIXL_MSG_BSZ_RESV __BITS(63,8) 156 #define RMIXL_MSG_BSZ_SIZE __BITS(7,0) 157 158 159 160 161 /* 162 * RMIXL Processor Control Register addresses 163 * - Offset in bits 7..0 164 * - BlockID in bits 15..8 165 */ 166 #define RMIXL_PCR_THREADEN 0x0000 167 #define RMIXL_PCR_SOFTWARE_SLEEP 0x0001 168 #define RMIXL_PCR_SCHEDULING 0x0002 169 #define RMIXL_PCR_SCHEDULING_COUNTERS 0x0003 170 #define RMIXL_PCR_BHRPM 0x0004 171 #define RMIXL_PCR_IFU_DEFEATURE 0x0006 172 #define RMIXL_PCR_ICU_DEFEATURE 0x0100 173 #define RMIXL_PCR_ICU_ERROR_LOGGING 0x0101 174 #define RMIXL_PCR_ICU_DEBUG_ACCESS_ADDR 0x0102 175 #define RMIXL_PCR_ICU_DEBUG_ACCESS_DATALO 0x0103 176 #define RMIXL_PCR_ICU_DEBUG_ACCESS_DATAHI 0x0104 177 #define RMIXL_PCR_ICU_SAMPLING_LFSR 0x0105 178 #define RMIXL_PCR_ICU_SAMPLING_PC 0x0106 179 #define RMIXL_PCR_ICU_SAMPLING_SETUP 0x0107 180 #define RMIXL_PCR_ICU_SAMPLING_TIMER 0x0108 181 #define RMIXL_PCR_ICU_SAMPLING_PC_UPPER 0x0109 182 #define RMIXL_PCR_IEU_DEFEATURE 0x0200 183 #define RMIXL_PCR_TARGET_PC_REGISTER 0x0207 184 #define RMIXL_PCR_L1D_CONFIG0 0x0300 185 #define RMIXL_PCR_L1D_CONFIG1 0x0301 186 #define RMIXL_PCR_L1D_CONFIG2 0x0302 187 #define RMIXL_PCR_L1D_CONFIG3 0x0303 188 #define RMIXL_PCR_L1D_CONFIG4 0x0304 189 #define RMIXL_PCR_L1D_STATUS 0x0305 190 #define RMIXL_PCR_L1D_DEFEATURE 0x0306 191 #define RMIXL_PCR_L1D_DEBUG0 0x0307 192 #define RMIXL_PCR_L1D_DEBUG1 0x0308 193 #define RMIXL_PCR_L1D_CACHE_ERROR_LOG 0x0309 194 #define RMIXL_PCR_L1D_CACHE_ERROR_OVF_LO 0x030A 195 #define RMIXL_PCR_L1D_CACHE_INTERRUPT 0x030B 196 #define RMIXL_PCR_MMU_SETUP 0x0400 197 #define RMIXL_PCR_PRF_SMP_EVENT 0x0500 198 #define RMIXL_PCR_RF_SMP_RPLY_BUF 0x0501 199 200 /* PCR bit defines TBD */ 201 202 /* XLP Instruction Fetch Unit Registers */ 203 #define RMIXLP_PCR_IFU_THREAD_EN 0x0000 204 #define RMIXLP_PCR_IFU_SW_SLEEP 0x0001 205 #define RMIXLP_PCR_IFU_THREAD_SCHED_MODE 0x0002 206 #define RMIXLP_PCR_IFU_THREAD_SCHED_COUNTER 0x0003 207 #define RMIXLP_PCR_IFU_BHR_PROG_MASK 0x0004 208 #define RMIXLP_PCR_IFU_SLEEP_STATE 0x0006 209 #define RMIXLP_PCR_IFU_BRUB_RESERVE 0x0007 210 211 /* XLP Instruction Cache Unit Registers */ 212 #define RMIXLP_PCR_ICU_DEFEATURE 0x0100 213 #define RMIXLP_PCR_ICU_CACHE_ERR_INT 0x0101 /* RW1C */ 214 #define RMIXLP_PCR_ICU_ERR_LOG0 0x0110 215 #define RMIXLP_PCR_ICU_ERR_LOG1 0x0111 216 #define RMIXLP_PCR_ICU_ERR_LOG2 0x0112 217 #define RMIXLP_PCR_ICU_ERR_INJECT0 0x0113 218 #define RMIXLP_PCR_ICU_ERR_INJECT1 0x0114 219 220 /* XLP Load Store Unit Registers */ 221 #define RMIXLP_PCR_LSU_CONFIG0 0x0300 222 #define RMIXLP_PCR_LSU_CONFIG1 0x0301 223 #define RMIXLP_PCR_LSU_DEFEATURE 0x0304 224 #define RMIXLP_PCR_LSU_DEBUG_ADDR 0x0305 225 #define RMIXLP_PCR_LSU_DEBUG_DATA 0x0306 226 #define RMIXLP_PCR_LSU_CERR_LOG0 0x0308 227 #define RMIXLP_PCR_LSU_CERR_LOG1 0x0309 228 #define RMIXLP_PCR_LSU_CERR_INJ0 0x030a 229 #define RMIXLP_PCR_LSU_CERR_INJ1 0x030b 230 #define RMIXLP_PCR_LSU_CERR_INT 0x030c 231 232 #define RMIXLP_PCR_LSE_DEFEATURE_EUL __BIT(30) 233 234 /* XLP MMU Registers */ 235 #define RMIXLP_PCR_MMU_SETUP 0x0400 236 #define RMIXLP_PCR_LFSRSEED 0x0401 237 #define RMIXLP_PCR_HPW_NUM_PAGE_LVL 0x0410 238 #define RMIXLP_PCR_PGWKR_PGDBASE 0x0411 239 #define RMIXLP_PCR_PGWKR_PGDSHIFT 0x0412 240 #define RMIXLP_PCR_PGWKR_PGDMASK 0x0413 241 #define RMIXLP_PCR_PGWKR_PUDSHIFT 0x0414 242 #define RMIXLP_PCR_PGWKR_PUDMASK 0x0415 243 #define RMIXLP_PCR_PGWKR_PMDSHIFT 0x0416 244 #define RMIXLP_PCR_PGWKR_PMDMASK 0x0417 245 #define RMIXLP_PCR_PGWKR_PTESHIFT 0x0418 246 #define RMIXLP_PCR_PGWKR_PTEMASK 0x0419 247 248 #define RMIXLP_PCR_MMU_SETUP_HASHFUNCTIONEN __BIT(13) 249 #define RMIXLP_PCR_MMU_SETUP_LOCCLKGATE __BIT(3) 250 #define RMIXLP_PCR_MMU_SETUP_TLB_GLOBAL __BIT(0) 251 #define RMIXLP_PCR_PGWKR_PxxSHIFT_MASK __BITS(5,0) 252 #define RMIXLP_PCR_PGWKR_PxxMASK_MASK __BITS(31,0) 253 254 /* XLP L2 Cache Registers */ 255 #define RMIXLP_PCR_L2_FTR_CTL0 0x800 256 #define RMIXLP_PCR_L2_FTR_CTL1 0x801 257 #define RMIXLP_PCR_L2_CRERR_INT_VID 0x802 258 #define RMIXLP_PCR_L2_DIS_WAY 0x803 259 #define RMIXLP_PCR_L2_ERR_LOG0 0x810 260 #define RMIXLP_PCR_L2_ERR_LOG1 0x811 261 #define RMIXLP_PCR_L2_ERR_LOG2 0x812 262 #define RMIXLP_PCR_L2_ERR_INJ0 0x813 263 #define RMIXLP_PCR_L2_ERR_INJ1 0x814 264 265 /* XLP Mapping Unit Registers */ 266 #define RMIXLP_PCR_MAP_T0_LRQ_MASK 0x0602 267 #define RMIXLP_PCR_MAP_T1_LRQ_MASK 0x0603 268 #define RMIXLP_PCR_MAP_T2_LRQ_MASK 0x0604 269 #define RMIXLP_PCR_MAP_T3_LRQ_MASK 0x0605 270 #define RMIXLP_PCR_MAP_T0_SRQ_MASK 0x0606 271 #define RMIXLP_PCR_MAP_T1_SRQ_MASK 0x0607 272 #define RMIXLP_PCR_MAP_T2_SRQ_MASK 0x0608 273 #define RMIXLP_PCR_MAP_T3_SRQ_MASK 0x0609 274 #define RMIXLP_PCR_MAP_THREAD_MODE 0x0a00 275 #define RMIXLP_PCR_MAP_EXT_EBASE_ENABLE 0x0a02 276 #define RMIXLP_PCR_MAP_CCD_CONFIG 0x0a02 277 #define RMIXLP_PCR_MAP_T0_DEBUG_MODE 0x0a03 278 #define RMIXLP_PCR_MAP_T1_DEBUG_MODE 0x0a04 279 #define RMIXLP_PCR_MAP_T2_DEBUG_MODE 0x0a05 280 #define RMIXLP_PCR_MAP_T3_DEBUG_MODE 0x0a06 281 #define RMIXLP_PCR_MAP_THREAD_STATE 0x0a10 282 #define RMIXLP_PCR_MAP_T0_CCD_STATUS 0x0a11 283 #define RMIXLP_PCR_MAP_T1_CCD_STATUS 0x0a12 284 #define RMIXLP_PCR_MAP_T2_CCD_STATUS 0x0a13 285 #define RMIXLP_PCR_MAP_T3_CCD_STATUS 0x0a14 286 287 /* 288 * Memory Distributed Interconnect (MDI) System Memory Map 289 */ 290 #define RMIXL_PHYSADDR_MAX 0xffffffffffLL /* 1TB Physical Address space */ 291 #define RMIXL_IO_DEV_PBASE 0x1ef00000 /* default phys. from XL[RS]_IO_BAR */ 292 #define RMIXL_IO_DEV_VBASE MIPS_PHYS_TO_KSEG1(RMIXL_IO_DEV_PBASE) 293 /* default virtual base address */ 294 #define RMIXL_IO_DEV_SIZE 0x100000 /* I/O Conf. space is 1MB region */ 295 296 297 298 /* 299 * Peripheral and I/O Configuration Region of Memory 300 * 301 * These are relocatable; we run using the reset value defaults, 302 * and we expect to inherit those intact from the boot firmware. 303 * 304 * Many of these overlap between XLR and XLS, exceptions are ifdef'ed. 305 * 306 * Device region offsets are relative to RMIXL_IO_DEV_PBASE. 307 */ 308 #define RMIXL_IO_DEV_BRIDGE 0x00000 /* System Bridge Controller (SBC) */ 309 #define RMIXL_IO_DEV_DDR_CHNA 0x01000 /* DDR1/DDR2 DRAM_A Channel, Port MA */ 310 #define RMIXL_IO_DEV_DDR_CHNB 0x02000 /* DDR1/DDR2 DRAM_B Channel, Port MB */ 311 #define RMIXL_IO_DEV_DDR_CHNC 0x03000 /* DDR1/DDR2 DRAM_C Channel, Port MC */ 312 #define RMIXL_IO_DEV_DDR_CHND 0x04000 /* DDR1/DDR2 DRAM_D Channel, Port MD */ 313 #if defined(MIPS64_XLR) 314 #define RMIXL_IO_DEV_SRAM 0x07000 /* SRAM Controller, Port SA */ 315 #endif /* MIPS64_XLR */ 316 #define RMIXL_IO_DEV_PIC 0x08000 /* Programmable Interrupt Controller */ 317 #if defined(MIPS64_XLR) 318 #define RMIXL_IO_DEV_PCIX 0x09000 /* PCI-X */ 319 #define RMIXL_IO_DEV_PCIX_EL \ 320 RMIXL_IO_DEV_PCIX /* PXI-X little endian */ 321 #define RMIXL_IO_DEV_PCIX_EB \ 322 (RMIXL_IO_DEV_PCIX | __BIT(11)) /* PXI-X big endian */ 323 #define RMIXL_IO_DEV_HT 0x0a000 /* HyperTransport */ 324 #endif /* MIPS64_XLR */ 325 #define RMIXL_IO_DEV_SAE 0x0b000 /* Security Acceleration Engine */ 326 #if defined(MIPS64_XLS) 327 #define XAUI_INTERFACE_0 0x0c000 /* XAUI Interface_0 */ 328 /* when SGMII Interface_[0-3] are not used */ 329 #define RMIXL_IO_DEV_GMAC_0 0x0c000 /* SGMII-Interface_0, Port SGMII0 */ 330 #define RMIXL_IO_DEV_GMAC_1 0x0d000 /* SGMII-Interface_1, Port SGMII1 */ 331 #define RMIXL_IO_DEV_GMAC_2 0x0e000 /* SGMII-Interface_2, Port SGMII2 */ 332 #define RMIXL_IO_DEV_GMAC_3 0x0f000 /* SGMII-Interface_3, Port SGMII3 */ 333 #endif /* MIPS64_XLS */ 334 #if defined(MIPS64_XLR) 335 #define RMIXL_IO_DEV_GMAC_A 0x0c000 /* RGMII-Interface_0, Port RA */ 336 #define RMIXL_IO_DEV_GMAC_B 0x0d000 /* RGMII-Interface_1, Port RB */ 337 #define RMIXL_IO_DEV_GMAC_C 0x0e000 /* RGMII-Interface_2, Port RC */ 338 #define RMIXL_IO_DEV_GMAC_D 0x0f000 /* RGMII-Interface_3, Port RD */ 339 #define RMIXL_IO_DEV_SPI4_A 0x10000 /* SPI-4.2-Interface_A, Port XA */ 340 #define RMIXL_IO_DEV_XGMAC_A 0x11000 /* XGMII-Interface_A, Port XA */ 341 #define RMIXL_IO_DEV_SPI4_B 0x12000 /* SPI-4.2-Interface_B, Port XB */ 342 #define RMIXL_IO_DEV_XGMAC_B 0x13000 /* XGMII-Interface_B, Port XB */ 343 #endif /* MIPS64_XLR */ 344 #define RMIXL_IO_DEV_UART_1 0x14000 /* UART_1 (16550 w/ ax4 addrs) */ 345 #define RMIXL_IO_DEV_UART_2 0x15000 /* UART_2 (16550 w/ ax4 addrs) */ 346 #define RMIXL_IO_DEV_I2C_1 0x16000 /* I2C_1 */ 347 #define RMIXL_IO_DEV_I2C_2 0x17000 /* I2C_2 */ 348 #define RMIXL_IO_DEV_GPIO 0x18000 /* GPIO */ 349 #define RMIXL_IO_DEV_FLASH 0x19000 /* Flash ROM */ 350 #define RMIXL_IO_DEV_DMA 0x1a000 /* DMA */ 351 #define RMIXL_IO_DEV_L2 0x1b000 /* L2 Cache */ 352 #define RMIXL_IO_DEV_TB 0x1c000 /* Trace Buffer */ 353 #if defined(MIPS64_XLS) 354 #define RMIXL_IO_DEV_CDE 0x1d000 /* Compression/Decompression Engine */ 355 #define RMIXL_IO_DEV_PCIE_BE 0x1e000 /* PCI-Express_BE */ 356 #define RMIXL_IO_DEV_PCIE_LE 0x1f000 /* PCI-Express_LE */ 357 #define RMIXL_IO_DEV_SRIO_BE 0x1e000 /* SRIO_BE */ 358 #define RMIXL_IO_DEV_SRIO_LE 0x1f000 /* SRIO_LE */ 359 #define RMIXL_IO_DEV_XAUI_1 0x20000 /* XAUI Interface_1 */ 360 /* when SGMII Interface_[4-7] are not used */ 361 #define RMIXL_IO_DEV_GMAC_4 0x20000 /* SGMII-Interface_4, Port SGMII4 */ 362 #define RMIXL_IO_DEV_GMAC_5 0x21000 /* SGMII-Interface_5, Port SGMII5 */ 363 #define RMIXL_IO_DEV_GMAC_6 0x22000 /* SGMII-Interface_6, Port SGMII6 */ 364 #define RMIXL_IO_DEV_GMAC_7 0x23000 /* SGMII-Interface_7, Port SGMII7 */ 365 #define RMIXL_IO_DEV_USB_A 0x24000 /* USB Interface Low Address Space */ 366 #define RMIXL_IO_DEV_USB_B 0x25000 /* USB Interface High Address Space */ 367 #endif /* MIPS64_XLS */ 368 369 370 /* 371 * the Programming Reference Manual 372 * lists "Reg ID" values not offsets; 373 * offset = id * 4 374 */ 375 #define _RMIXL_OFFSET(id) ((id) * 4) 376 #define _RMIXL_PCITAG(b,d,f) ((((((b) << 5) | (d)) << 3) | (f)) << 12) 377 #define _RMIXL_PCITAG_BUS(t) (((t) >> 20) & 255) 378 #define _RMIXL_PCITAG_DEV(t) (((t) >> 15) & 31) 379 #define _RMIXL_PCITAG_FUNC(t) (((t) >> 12) & 7) 380 #define _RMIXL_PCITAG_OFFSET(t) (((t) >> 0) & 4095) 381 382 383 /* 384 * System Bridge Controller registers 385 * offsets are relative to RMIXL_IO_DEV_BRIDGE 386 */ 387 #define RMIXL_SBC_DRAM_NBARS 8 388 #define RMIXL_SBC_DRAM_BAR(n) _RMIXL_OFFSET(0x000 + (n)) 389 /* DRAM Region Base Address Regs[0-7] */ 390 #define RMIXL_SBC_DRAM_CHNAC_DTR(n) _RMIXL_OFFSET(0x008 + (n)) 391 /* DRAM Region Channels A,C Address Translation Regs[0-7] */ 392 #define RMIXL_SBC_DRAM_CHNBD_DTR(n) _RMIXL_OFFSET(0x010 + (n)) 393 /* DRAM Region Channels B,D Address Translation Regs[0-7] */ 394 #define RMIXL_SBC_DRAM_BRIDGE_CFG _RMIXL_OFFSET(0x18) /* SBC DRAM config reg */ 395 #define RMIXL_SBC_IO_BAR _RMIXL_OFFSET(0x19) /* I/O Config Base Addr reg */ 396 #define RMIXL_SBC_FLASH_BAR _RMIXL_OFFSET(0x1a) /* Flash Memory Base Addr reg */ 397 #if defined(MIPS64_XLR) 398 #define RMIXLR_SBC_SRAM_BAR _RMIXL_OFFSET(0x1b) /* SRAM Base Addr reg */ 399 #define RMIXLR_SBC_HTMEM_BAR _RMIXL_OFFSET(0x1c) /* HyperTransport Mem Base Addr reg */ 400 #define RMIXLR_SBC_HTINT_BAR _RMIXL_OFFSET(0x1d) /* HyperTransport Interrupt Base Addr reg */ 401 #define RMIXLR_SBC_HTPIC_BAR _RMIXL_OFFSET(0x1e) /* HyperTransport Legacy PIC Base Addr reg */ 402 #define RMIXLR_SBC_HTSM_BAR _RMIXL_OFFSET(0x1f) /* HyperTransport System Management Base Addr reg */ 403 #define RMIXLR_SBC_HTIO_BAR _RMIXL_OFFSET(0x20) /* HyperTransport IO Base Addr reg */ 404 #define RMIXLR_SBC_HTCFG_BAR _RMIXL_OFFSET(0x21) /* HyperTransport Configuration Base Addr reg */ 405 #define RMIXLR_SBC_PCIX_CFG_BAR _RMIXL_OFFSET(0x22) /* PCI-X Configuration Base Addr reg */ 406 #define RMIXLR_SBC_PCIX_MEM_BAR _RMIXL_OFFSET(0x23) /* PCI-X Mem Base Addr reg */ 407 #define RMIXLR_SBC_PCIX_IO_BAR _RMIXL_OFFSET(0x24) /* PCI-X IO Base Addr reg */ 408 #define RMIXLR_SBC_SYS2IO_CREDITS _RMIXL_OFFSET(0x35) /* System Bridge I/O Transaction Credits register */ 409 #endif /* MIPS64_XLR */ 410 #if defined(MIPS64_XLS) 411 #define RMIXLS_SBC_PCIE_CFG_BAR _RMIXL_OFFSET(0x40) /* PCI Configuration BAR */ 412 #define RMIXLS_SBC_PCIE_ECFG_BAR _RMIXL_OFFSET(0x41) /* PCI Extended Configuration BAR */ 413 #define RMIXLS_SBC_PCIE_MEM_BAR _RMIXL_OFFSET(0x42) /* PCI Memory region BAR */ 414 #define RMIXLS_SBC_PCIE_IO_BAR _RMIXL_OFFSET(0x43) /* PCI IO region BAR */ 415 #endif /* MIPS64_XLS */ 416 417 /* 418 * Address Error registers 419 * offsets are relative to RMIXL_IO_DEV_BRIDGE 420 */ 421 #define RMIXL_ADDR_ERR_DEVICE_MASK _RMIXL_OFFSET(0x25) /* Address Error Device Mask */ 422 #define RMIXL_ADDR_ERR_DEVICE_MASK_2 _RMIXL_OFFSET(0x44) /* extension of Device Mask */ 423 #define RMIXL_ADDR_ERR_AERR0_LOG1 _RMIXL_OFFSET(0x26) /* Address Error Set 0 Log 1 */ 424 #define RMIXL_ADDR_ERR_AERR0_LOG2 _RMIXL_OFFSET(0x27) /* Address Error Set 0 Log 2 */ 425 #define RMIXL_ADDR_ERR_AERR0_LOG3 _RMIXL_OFFSET(0x28) /* Address Error Set 0 Log 3 */ 426 #define RMIXL_ADDR_ERR_AERR0_DEVSTAT _RMIXL_OFFSET(0x29) /* Address Error Set 0 irpt status */ 427 #define RMIXL_ADDR_ERR_AERR1_LOG1 _RMIXL_OFFSET(0x2a) /* Address Error Set 1 Log 1 */ 428 #define RMIXL_ADDR_ERR_AERR1_LOG2 _RMIXL_OFFSET(0x2b) /* Address Error Set 1 Log 2 */ 429 #define RMIXL_ADDR_ERR_AERR1_LOG3 _RMIXL_OFFSET(0x2c) /* Address Error Set 1 Log 3 */ 430 #define RMIXL_ADDR_ERR_AERR1_DEVSTAT _RMIXL_OFFSET(0x2d) /* Address Error Set 1 irpt status */ 431 #define RMIXL_ADDR_ERR_AERR0_EN _RMIXL_OFFSET(0x2e) /* Address Error Set 0 irpt enable */ 432 #define RMIXL_ADDR_ERR_AERR0_UPG _RMIXL_OFFSET(0x2f) /* Address Error Set 0 Upgrade */ 433 #define RMIXL_ADDR_ERR_AERR0_CLEAR _RMIXL_OFFSET(0x30) /* Address Error Set 0 irpt clear */ 434 #define RMIXL_ADDR_ERR_AERR1_CLEAR _RMIXL_OFFSET(0x31) /* Address Error Set 1 irpt clear */ 435 #define RMIXL_ADDR_ERR_SBE_COUNTS _RMIXL_OFFSET(0x32) /* Single Bit Error Counts */ 436 #define RMIXL_ADDR_ERR_DBE_COUNTS _RMIXL_OFFSET(0x33) /* Double Bit Error Counts */ 437 #define RMIXL_ADDR_ERR_BITERR_INT_EN _RMIXL_OFFSET(0x33) /* Bit Error intr enable */ 438 439 /* 440 * RMIXL_SBC_FLASH_BAR bit defines 441 */ 442 #define RMIXL_FLASH_BAR_BASE __BITS(31,16) /* phys address bits 39:24 */ 443 #define RMIXL_FLASH_BAR_TO_BA(r) \ 444 (((r) & RMIXL_FLASH_BAR_BASE) << (24 - 16)) 445 #define RMIXL_FLASH_BAR_MASK __BITS(15,5) /* phys address mask bits 34:24 */ 446 #define RMIXL_FLASH_BAR_TO_MASK(r) \ 447 (((((r) & RMIXL_FLASH_BAR_MASK)) << (24 - 5)) | __BITS(23, 0)) 448 #define RMIXL_FLASH_BAR_RESV __BITS(4,1) /* (reserved) */ 449 #define RMIXL_FLASH_BAR_ENB __BIT(0) /* 1=Enable */ 450 #define RMIXL_FLASH_BAR_MASK_MAX RMIXL_FLASH_BAR_TO_MASK(RMIXL_FLASH_BAR_MASK) 451 452 /* 453 * RMIXL_SBC_DRAM_BAR bit defines 454 */ 455 #define RMIXL_DRAM_BAR_BASE_ADDR __BITS(31,16) /* bits 39:24 of Base Address */ 456 #define DRAM_BAR_TO_BASE(r) \ 457 (((r) & RMIXL_DRAM_BAR_BASE_ADDR) << (24 - 16)) 458 #define RMIXL_DRAM_BAR_ADDR_MASK __BITS(15,4) /* bits 35:24 of Address Mask */ 459 #define DRAM_BAR_TO_SIZE(r) \ 460 ((((r) & RMIXL_DRAM_BAR_ADDR_MASK) + __BIT(4)) << (24 - 4)) 461 #define RMIXL_DRAM_BAR_INTERLEAVE __BITS(3,1) /* Interleave Mode */ 462 #define RMIXL_DRAM_BAR_STATUS __BIT(0) /* 1='region enabled' */ 463 464 /* 465 * RMIXL_SBC_DRAM_CHNAC_DTR and 466 * RMIXL_SBC_DRAM_CHNBD_DTR bit defines 467 * insert 'divisions' (0, 1 or 2) bits 468 * of value 'partition' 469 * at 'position' bit location. 470 */ 471 #define RMIXL_DRAM_DTR_RESa __BITS(31,14) 472 #define RMIXL_DRAM_DTR_PARTITION __BITS(13,12) 473 #define RMIXL_DRAM_DTR_RESb __BITS(11,10) 474 #define RMIXL_DRAM_DTR_DIVISIONS __BITS(9,8) 475 #define RMIXL_DRAM_DTR_RESc __BITS(7,6) 476 #define RMIXL_DRAM_DTR_POSITION __BITS(5,0) 477 #define RMIXL_DRAM_DTR_RESV \ 478 (RMIXL_DRAM_DTR_RESa|RMIXL_DRAM_DTR_RESb|RMIXL_DRAM_DTR_RESc) 479 480 /* 481 * RMIXL_SBC_DRAM_BRIDGE_CFG bit defines 482 */ 483 #define RMIXL_DRAM_CFG_RESa __BITS(31,13) 484 #define RMIXL_DRAM_CFG_CHANNEL_MODE __BIT(12) 485 #define RMIXL_DRAM_CFG_RESb __BIT(11) 486 #define RMIXL_DRAM_CFG_INTERLEAVE_MODE __BITS(10,8) 487 #define RMIXL_DRAM_CFG_RESc __BITS(7,5) 488 #define RMIXL_DRAM_CFG_BUS_MODE __BIT(4) 489 #define RMIXL_DRAM_CFG_RESd __BITS(3,2) 490 #define RMIXL_DRAM_CFG_DRAM_MODE __BITS(1,0) /* 1=DDR2 */ 491 492 /* 493 * RMIXL_SBC_XLR_PCIX_CFG_BAR bit defines 494 */ 495 #define RMIXL_PCIX_CFG_BAR_BASE __BITS(31,17) /* phys address bits 39:25 */ 496 #define RMIXL_PCIX_CFG_BAR_BA_SHIFT (25 - 17) 497 #define RMIXL_PCIX_CFG_BAR_TO_BA(r) \ 498 (((r) & RMIXL_PCIX_CFG_BAR_BASE) << RMIXL_PCIX_CFG_BAR_BA_SHIFT) 499 #define RMIXL_PCIX_CFG_BAR_RESV __BITS(16,1) /* (reserved) */ 500 #define RMIXL_PCIX_CFG_BAR_ENB __BIT(0) /* 1=Enable */ 501 #define RMIXL_PCIX_CFG_SIZE __BIT(25) 502 #define RMIXL_PCIX_CFG_BAR(ba, en) \ 503 ((uint32_t)(((ba) >> (25 - 17)) | ((en) ? RMIXL_PCIX_CFG_BAR_ENB : 0))) 504 505 /* 506 * RMIXLR_SBC_PCIX_MEM_BAR bit defines 507 */ 508 #define RMIXL_PCIX_MEM_BAR_BASE __BITS(31,16) /* phys address bits 39:24 */ 509 #define RMIXL_PCIX_MEM_BAR_TO_BA(r) \ 510 (((r) & RMIXL_PCIX_MEM_BAR_BASE) << (24 - 16)) 511 #define RMIXL_PCIX_MEM_BAR_MASK __BITS(15,1) /* phys address mask bits 38:24 */ 512 #define RMIXL_PCIX_MEM_BAR_TO_SIZE(r) \ 513 ((((r) & RMIXL_PCIX_MEM_BAR_MASK) + 2) << (24 - 1)) 514 #define RMIXL_PCIX_MEM_BAR_ENB __BIT(0) /* 1=Enable */ 515 #define RMIXL_PCIX_MEM_BAR(ba, en) \ 516 ((uint32_t)(((ba) >> (24 - 16)) | ((en) ? RMIXL_PCIX_MEM_BAR_ENB : 0))) 517 518 /* 519 * RMIXLR_SBC_PCIX_IO_BAR bit defines 520 */ 521 #define RMIXL_PCIX_IO_BAR_BASE __BITS(31,18) /* phys address bits 39:26 */ 522 #define RMIXL_PCIX_IO_BAR_TO_BA(r) \ 523 (((r) & RMIXL_PCIX_IO_BAR_BASE) << (26 - 18)) 524 #define RMIXL_PCIX_IO_BAR_RESV __BITS(17,7) /* (reserve) */ 525 #define RMIXL_PCIX_IO_BAR_MASK __BITS(6,1) /* phys address mask bits 31:26 */ 526 #define RMIXL_PCIX_IO_BAR_TO_SIZE(r) \ 527 ((((r) & RMIXL_PCIX_IO_BAR_MASK) + 2) << (26 - 1)) 528 #define RMIXL_PCIX_IO_BAR_ENB __BIT(0) /* 1=Enable */ 529 #define RMIXL_PCIX_IO_BAR(ba, en) \ 530 ((uint32_t)(((ba) >> (26 - 18)) | ((en) ? RMIXL_PCIX_IO_BAR_ENB : 0))) 531 532 533 /* 534 * RMIXLS_SBC_PCIE_CFG_BAR bit defines 535 */ 536 #define RMIXL_PCIE_CFG_BAR_BASE __BITS(31,17) /* phys address bits 39:25 */ 537 #define RMIXL_PCIE_CFG_BAR_BA_SHIFT (25 - 17) 538 #define RMIXL_PCIE_CFG_BAR_TO_BA(r) \ 539 (((r) & RMIXL_PCIE_CFG_BAR_BASE) << RMIXL_PCIE_CFG_BAR_BA_SHIFT) 540 #define RMIXL_PCIE_CFG_BAR_RESV __BITS(16,1) /* (reserved) */ 541 #define RMIXL_PCIE_CFG_BAR_ENB __BIT(0) /* 1=Enable */ 542 #define RMIXL_PCIE_CFG_SIZE __BIT(25) 543 #define RMIXL_PCIE_CFG_BAR(ba, en) \ 544 ((uint32_t)(((ba) >> (25 - 17)) | ((en) ? RMIXL_PCIE_CFG_BAR_ENB : 0))) 545 546 /* 547 * RMIXLS_SBC_PCIE_ECFG_BAR bit defines 548 * (PCIe extended config space) 549 */ 550 #define RMIXL_PCIE_ECFG_BAR_BASE __BITS(31,21) /* phys address bits 39:29 */ 551 #define RMIXL_PCIE_ECFG_BAR_BA_SHIFT (29 - 21) 552 #define RMIXL_PCIE_ECFG_BAR_TO_BA(r) \ 553 (((r) & RMIXL_PCIE_ECFG_BAR_BASE) << RMIXL_PCIE_ECFG_BAR_BA_SHIFT) 554 #define RMIXL_PCIE_ECFG_BAR_RESV __BITS(20,1) /* (reserved) */ 555 #define RMIXL_PCIE_ECFG_BAR_ENB __BIT(0) /* 1=Enable */ 556 #define RMIXL_PCIE_ECFG_SIZE __BIT(29) 557 #define RMIXL_PCIE_ECFG_BAR(ba, en) \ 558 ((uint32_t)(((ba) >> (29 - 21)) | ((en) ? RMIXL_PCIE_ECFG_BAR_ENB : 0))) 559 560 /* 561 * RMIXLS_SBC_PCIE_MEM_BAR bit defines 562 */ 563 #define RMIXL_PCIE_MEM_BAR_BASE __BITS(31,16) /* phys address bits 39:24 */ 564 #define RMIXL_PCIE_MEM_BAR_TO_BA(r) \ 565 (((r) & RMIXL_PCIE_MEM_BAR_BASE) << (24 - 16)) 566 #define RMIXL_PCIE_MEM_BAR_MASK __BITS(15,1) /* phys address mask bits 38:24 */ 567 #define RMIXL_PCIE_MEM_BAR_TO_SIZE(r) \ 568 ((((r) & RMIXL_PCIE_MEM_BAR_MASK) + 2) << (24 - 1)) 569 #define RMIXL_PCIE_MEM_BAR_ENB __BIT(0) /* 1=Enable */ 570 #define RMIXL_PCIE_MEM_BAR(ba, en) \ 571 ((uint32_t)(((ba) >> (24 - 16)) | ((en) ? RMIXL_PCIE_MEM_BAR_ENB : 0))) 572 573 /* 574 * RMIXLS_SBC_PCIE_IO_BAR bit defines 575 */ 576 #define RMIXL_PCIE_IO_BAR_BASE __BITS(31,18) /* phys address bits 39:26 */ 577 #define RMIXL_PCIE_IO_BAR_TO_BA(r) \ 578 (((r) & RMIXL_PCIE_IO_BAR_BASE) << (26 - 18)) 579 #define RMIXL_PCIE_IO_BAR_RESV __BITS(17,7) /* (reserve) */ 580 #define RMIXL_PCIE_IO_BAR_MASK __BITS(6,1) /* phys address mask bits 31:26 */ 581 #define RMIXL_PCIE_IO_BAR_TO_SIZE(r) \ 582 ((((r) & RMIXL_PCIE_IO_BAR_MASK) + 2) << (26 - 1)) 583 #define RMIXL_PCIE_IO_BAR_ENB __BIT(0) /* 1=Enable */ 584 #define RMIXL_PCIE_IO_BAR(ba, en) \ 585 ((uint32_t)(((ba) >> (26 - 18)) | ((en) ? RMIXL_PCIE_IO_BAR_ENB : 0))) 586 587 588 /* 589 * Programmable Interrupt Controller registers 590 * the Programming Reference Manual table 10.4 591 * lists "Reg ID" values not offsets 592 * Offsets are relative to RMIXL_IO_DEV_BRIDGE 593 */ 594 #define RMIXL_PIC_CONTROL _RMIXL_OFFSET(0x0) 595 #define RMIXL_PIC_IPIBASE _RMIXL_OFFSET(0x4) 596 #define RMIXL_PIC_INTRACK _RMIXL_OFFSET(0x6) 597 #define RMIXL_PIC_WATCHdOGMAXVALUE0 _RMIXL_OFFSET(0x8) 598 #define RMIXL_PIC_WATCHDOGMAXVALUE1 _RMIXL_OFFSET(0x9) 599 #define RMIXL_PIC_WATCHDOGMASK0 _RMIXL_OFFSET(0xa) 600 #define RMIXL_PIC_WATCHDOGMASK1 _RMIXL_OFFSET(0xb) 601 #define RMIXL_PIC_WATCHDOGHEARTBEAT0 _RMIXL_OFFSET(0xc) 602 #define RMIXL_PIC_WATCHDOGHEARTBEAT1 _RMIXL_OFFSET(0xd) 603 #define RMIXL_PIC_IRTENTRYC0(n) _RMIXL_OFFSET(0x40 + (n)) /* 0<=n<=31 */ 604 #define RMIXL_PIC_IRTENTRYC1(n) _RMIXL_OFFSET(0x80 + (n)) /* 0<=n<=31 */ 605 #define RMIXL_PIC_SYSTMRMAXVALC0(n) _RMIXL_OFFSET(0x100 + (n)) /* 0<=n<=7 */ 606 #define RMIXL_PIC_SYSTMRMAXVALC1(n) _RMIXL_OFFSET(0x110 + (n)) /* 0<=n<=7 */ 607 #define RMIXL_PIC_SYSTMRC0(n) _RMIXL_OFFSET(0x120 + (n)) /* 0<=n<=7 */ 608 #define RMIXL_PIC_SYSTMRC1(n) _RMIXL_OFFSET(0x130 + (n)) /* 0<=n<=7 */ 609 610 /* 611 * RMIXL_PIC_CONTROL bits 612 */ 613 #define RMIXL_PIC_CONTROL_WATCHDOG_ENB __BIT(0) 614 #define RMIXL_PIC_CONTROL_GEN_NMI __BITS(2,1) /* do NMI after n WDog irpts */ 615 #define RMIXL_PIC_CONTROL_GEN_NMIn(n) (((n) << 1) & RMIXL_PIC_CONTROL_GEN_NMI) 616 #define RMIXL_PIC_CONTROL_RESa __BITS(7,3) 617 #define RMIXL_PIC_CONTROL_TIMER_ENB __BITS(15,8) /* per-Timer enable bits */ 618 #define RMIXL_PIC_CONTROL_TIMER_ENBn(n) ((1 << (8 + (n))) & RMIXL_PIC_CONTROL_TIMER_ENB) 619 #define RMIXL_PIC_CONTROL_RESb __BITS(31,16) 620 #define RMIXL_PIC_CONTROL_RESV \ 621 (RMIXL_PIC_CONTROL_RESa|RMIXL_PIC_CONTROL_RESb) 622 623 /* 624 * RMIXL_PIC_IPIBASE bits 625 */ 626 #define RMIXL_PIC_IPIBASE_VECTORNUM __BITS(5,0) 627 #define RMIXL_PIC_IPIBASE_RESa __BIT(6) /* undocumented bit */ 628 #define RMIXL_PIC_IPIBASE_BCAST __BIT(7) 629 #define RMIXL_PIC_IPIBASE_NMI __BIT(8) 630 #define RMIXL_PIC_IPIBASE_ID __BITS(31,16) 631 #define RMIXL_PIC_IPIBASE_ID_RESb __BITS(31,23) 632 #define RMIXL_PIC_IPIBASE_ID_CORE __BITS(22,20) /* Physical CPU ID */ 633 #define RMIXL_PIC_IPIBASE_ID_CORE_SHIFT 20 634 #define RMIXL_PIC_IPIBASE_ID_RESc __BITS(19,18) 635 #define RMIXL_PIC_IPIBASE_ID_THREAD __BITS(17,16) /* Thread ID */ 636 #define RMIXL_PIC_IPIBASE_ID_THREAD_SHIFT 16 637 #define RMIXL_PIC_IPIBASE_ID_RESV \ 638 (RMIXL_PIC_IPIBASE_ID_RESa|RMIXL_PIC_IPIBASE_ID_RESb \ 639 |RMIXL_PIC_IPIBASE_ID_RESc) 640 #define RMIXL_PIC_IPIBASE_MAKE(nmi, core, thread, tag) \ 641 (__SHIFTIN((nmi), RMIXL_PIC_IPIBASE_NMI) \ 642 | __SHIFTIN((core), RMIXL_PIC_IPIBASE_ID_CORE) \ 643 | __SHIFTIN((thread), RMIXL_PIC_IPIBASE_ID_THREAD) \ 644 | __SHIFTIN((tag), RMIXL_PIC_IPIBASE_VECTORNUM)) 645 646 /* 647 * RMIXL_PIC_IRTENTRYC0 bits 648 * IRT Entry low word 649 */ 650 #define RMIXL_PIC_IRTENTRYC0_TMASK __BITS(7,0) /* Thread Mask */ 651 #define RMIXL_PIC_IRTENTRYC0_RESa __BITS(3,2) /* write as 0 */ 652 #define RMIXL_PIC_IRTENTRYC0_RESb __BITS(31,8) /* write as 0 */ 653 #define RMIXL_PIC_IRTENTRYC0_RESV \ 654 (RMIXL_PIC_IRTENTRYC0_RESa | RMIXL_PIC_IRTENTRYC0_RESb) 655 656 /* 657 * RMIXL_PIC_IRTENTRYC1 bits 658 * IRT Entry high word 659 */ 660 #define RMIXL_PIC_IRTENTRYC1_INTVEC __BITS(5,0) /* maps to bit# in CPU's EIRR */ 661 #define RMIXL_PIC_IRTENTRYC1_GL __BIT(6) /* 0=Global; 1=Local */ 662 #define RMIXL_PIC_IRTENTRYC1_NMI __BIT(7) /* 0=Maskable; 1=NMI */ 663 #define RMIXL_PIC_IRTENTRYC1_RESV __BITS(28,8) 664 #define RMIXL_PIC_IRTENTRYC1_P __BIT(29) /* 0=Rising/High; 1=Falling/Low */ 665 #define RMIXL_PIC_IRTENTRYC1_TRG __BIT(30) /* 0=Edge; 1=Level */ 666 #define RMIXL_PIC_IRTENTRYC1_VALID __BIT(31) /* 0=Invalid; 1=Valid IRT Entry */ 667 668 /* 669 * RMI XLP PIC registers (all are 64-bit except when noted) 670 */ 671 #define RMIXLP_PIC_CTRL _RMIXL_OFFSET(0x40) 672 #define RMIXLP_PIC_BYTESWAP _RMIXL_OFFSET(0x42) 673 #define RMIXLP_PIC_STATUS _RMIXL_OFFSET(0x44) 674 #define RMIXLP_PIC_INT_TIMEOUT _RMIXL_OFFSET(0x46) 675 #define RMIXLP_PIC_ICI0_INT_TIMEOUT _RMIXL_OFFSET(0x48) 676 /* nothing at 0x4a */ 677 #define RMIXLP_PIC_IPI_CTRL _RMIXL_OFFSET(0x4e) 678 #define RMIXLP_PIC_INT_ACK _RMIXL_OFFSET(0x50) 679 #define RMIXLP_PIC_INT_PENDING0 _RMIXL_OFFSET(0x52) /* IRT 0..63 */ 680 #define RMIXLP_PIC_INT_PENDING1 _RMIXL_OFFSET(0x54) /* IRT 64..127 */ 681 #define RMIXLP_PIC_INT_PENDING2 _RMIXL_OFFSET(0x56) /* IRT 128..160 */ 682 #define RMIXLP_PIC_WATCHDOG0_MAXVAL _RMIXL_OFFSET(0x58) 683 #define RMIXLP_PIC_WATCHDOG0_COUNT _RMIXL_OFFSET(0x5a) 684 #define RMIXLP_PIC_WATCHDOG0_ENABLE0 _RMIXL_OFFSET(0x5c) 685 /* nothing at 0x5e */ 686 #define RMIXLP_PIC_WATCHDOG0_BEATCMD _RMIXL_OFFSET(0x60) 687 #define RMIXLP_PIC_WATCHDOG0_BEAT0 _RMIXL_OFFSET(0x62) 688 #define RMIXLP_PIC_WATCHDOG0_BEAT1 _RMIXL_OFFSET(0x64) 689 #define RMIXLP_PIC_WATCHDOG1_MAXVAL _RMIXL_OFFSET(0x66) 690 #define RMIXLP_PIC_WATCHDOG1_COUNT _RMIXL_OFFSET(0x68) 691 #define RMIXLP_PIC_WATCHDOG1_ENABLE _RMIXL_OFFSET(0x6a) 692 /* nothing at 0x6c */ 693 #define RMIXLP_PIC_WATCHDOG1_BEATCMD _RMIXL_OFFSET(0x6e) 694 #define RMIXLP_PIC_WATCHDOG1_BEAT _RMIXL_OFFSET(0x70) 695 /* nothing at 0x72 */ 696 #define RMIXLP_PIC_SYSTEMTIMER_MAXVALUE(n) _RMIXL_OFFSET(0x74+2*(n)) 697 #define RMIXLP_PIC_SYSTEMTIMER_COUNT(n) _RMIXL_OFFSET(0x84+2*(n)) 698 #define RMIXLP_PIC_INT_THREAD_ENABLE01(n) _RMIXL_OFFSET(0x94+4*(n)) 699 #define RMIXLP_PIC_INT_THREAD_ENABLE23(n) _RMIXL_OFFSET(0x96+4*(n)) 700 #define RMIXLP_PIC_IRTENTRY(n) _RMIXL_OFFSET(0xb4+2*(n)) 701 #define RMIXLP_PIC_INT_BROADCAST_ENABLE _RMIXL_OFFSET(0x292) /* 32-bit */ 702 #define RMIXLP_PIC_INT_GPIO_PENDING _RMIXL_OFFSET(0x293) /* 32-bit */ 703 704 /* 705 * RMIXLP_PIC_CTRL bits 706 */ 707 #define RMIXLP_PIC_CTRL_ITV __BITS(64,32) /* Interrupt Timeout Value */ 708 #define RMIXLP_PIC_CTRL_STE __BITS(17,10) /* System Timer Enable */ 709 #define RMIXLP_PIC_CTRL_WWR1 __BITS(9,8) /* Watchdog Wraparound Reset1 */ 710 #define RMIXLP_PIC_CTRL_WWR0 __BITS(7,6) /* Watchdog Wraparound Reset0 */ 711 #define RMIXLP_PIC_CTRL_WWN1 __BITS(5,4) /* Watchdog Wraparound NMI1 */ 712 #define RMIXLP_PIC_CTRL_WWN0 __BITS(3,2) /* Watchdog Wraparound NMI0 */ 713 #define RMIXLP_PIC_CTRL_WTE __BITS(1,0) /* Watchdog Timer Enable */ 714 #define RMIXLP_PIC_CTRL_WTE1 __BIT(1) /* Watchdog Timer 1 Enable */ 715 #define RMIXLP_PIC_CTRL_WTE0 __BIT(0) /* Watchdog Timer 0 Enable */ 716 717 /* 718 * RMIXLP_PIC_STATUS bits 719 */ 720 #define RMIXLP_PIC_STATUS_ITE __BIT(32) /* Interrupt Timeout */ 721 #define RMIXLP_PIC_STATUS_STS __BITS(11,4) /* SystemTimer */ 722 #define RMIXLP_PIC_STATUS_WNS __BITS(3,2) /* Watchdog NMI Interrupt */ 723 #define RMIXLP_PIC_STATUS_WIS __BITS(1,0) /* Watchdog Interrupt */ 724 725 /* 726 * RMIXLP_PIC_INT_TIMEOUT and RMIXLP_PIC_ICI0_INT_TIMEOUT bits 727 */ 728 #define RMIXLP_PIC_IPI_TIMEOUT_INTPEND __BITS(51,36) /* ?? */ 729 #define RMIXLP_PIC_IPI_TIMEOUT_INTNUM __BITS(35,28) /* IRT # */ 730 #define RMIXLP_PIC_IPI_TIMEOUT_INTEN __BIT(27) /* Int Enable */ 731 #define RMIXLP_PIC_IPI_TIMEOUT_INTVEC __BITS(25,20) /* Int Vector */ 732 #define RMIXLP_PIC_IPI_TIMEOUT_INTCPU __BITS(19,16) /* Dest CPU */ 733 #define RMIXLP_PIC_IPI_TIMEOUT_INTDEST __BITS(15,0) /* Dest */ 734 735 /* 736 * RMIXLP_PIC_IPI_CTRL bits 737 */ 738 #define RMIXLP_PIC_IPI_CTRL_NMI __BIT(32) /* 1=NMI; 0=Maskable */ 739 #define RMIXLP_PIC_IPI_CTRL_RIV __BITS(25,20) /* Which bit in EIRR */ 740 #define RMIXLP_PIC_IPI_CTRL_DT __BITS(15,0) /* Dest Thread Enbs */ 741 #define RMIXLP_PIC_IPI_CTRL_MAKE(nmi, tmask, tag) \ 742 (__SHIFTIN((nmi), RMIXLP_PIC_IPI_CTRL_NMI) \ 743 | __SHIFTIN((tag), RMIXL_PIC_IPI_CTRL_RIV) \ 744 | __SHIFTIN((tmask), RMIXLP_PIC_IPI_CTRL_DT)) 745 746 /* 747 * RMIXLP_PIC_INT_ACK bits 748 */ 749 #define RMIXLP_PIC_INT_ACK_THREAD __BITS(11,8) /* Thr # if PicIntBrd */ 750 #define RMIXLP_PIC_INT_ACK_ACK __BITS(7,0) /* IRT # */ 751 752 /* 753 * RMIXLP_WATCHDOG_BEATCMD 754 * 755 * write 32 * node + 4 * cpu + thread (e.g. cpu_id) to set heartbeat. 756 */ 757 758 /* 759 * RMIXLP_PIC_INT_THREAD_ENABLE bits 760 */ 761 #define RMIXLP_PIC_INT_ITE __BITS(15,0) 762 763 /* 764 * RMIXLP_PIC_IRTENTRY bits 765 */ 766 767 /* bits 63-32 are reserved */ 768 #define RMIXLP_PIC_IRTENTRY_EN __BIT(31) /* 1=Enable; 0=Disable */ 769 #define RMIXLP_PIC_IRTENTRY_NMI __BIT(29) /* 1=NMI; 0=Maskable */ 770 #define RMIXLP_PIC_IRTENTRY_LOCAL __BIT(28) /* 1=Local; 0=Global */ 771 #define RMIXLP_PIC_IRTENTRY_INTVEC __BITS(25,20) /* maps to bit# in CPU's EIRR */ 772 #define RMIXLP_PIC_IRTENTRY_DT __BIT(19) /* 1=ID; 0=ITE */ 773 #define RMIXLP_PIC_IRTENTRY_DT_ID __SHIFTIN(1, RMIXLP_PIC_IRTENTRY_DT) 774 #define RMIXLP_PIC_IRTENTRY_DT_ITE __SHIFTIN(0, RMIXLP_PIC_IRTENTRY_DT) 775 #define RMIXLP_PIC_IRTENTRY_DB __BITS(18,16) /* NodeId/CpuID[2]; ITE# */ 776 #define RMIXLP_PIC_IRTENTRY_ITE(n) __SHIFTIN((n), RMIXLP_PIC_IRTENTRY_DB) 777 #define RMIXLP_PIC_IRTENTRY_DTE __BITS(15,0) /* Destination Thread Enables */ 778 779 /* 780 * RMIXLP_PIC_INT_BROADCAST_ENABLE bits 781 */ 782 #define RMIXLP_PIC_INT_BROADCAST_ENABLE_PICINTBCMOD __BITS(27,16) 783 #define RMIXLP_PIC_INT_BROADCAST_ENABLE_PICINTBCEN __BITS(11,0) 784 785 /* 786 * RMIXLP_PIC_INT_GPIO_PENDING bits 787 */ 788 #define RMIXLP_PIC_INT_GPIO_PENDING_PICPENDB __BITS(11,0) 789 790 /* 791 * GPIO Controller registers 792 */ 793 /* GPIO Signal Registers */ 794 #define RMIXL_GPIO_INT_ENB _RMIXL_OFFSET(0x0) /* Interrupt Enable register */ 795 #define RMIXL_GPIO_INT_INV _RMIXL_OFFSET(0x1) /* Interrupt Inversion register */ 796 #define RMIXL_GPIO_IO_DIR _RMIXL_OFFSET(0x2) /* I/O Direction register */ 797 #define RMIXL_GPIO_OUTPUT _RMIXL_OFFSET(0x3) /* Output Write register */ 798 #define RMIXL_GPIO_INPUT _RMIXL_OFFSET(0x4) /* Intput Read register */ 799 #define RMIXL_GPIO_INT_CLR _RMIXL_OFFSET(0x5) /* Interrupt Inversion register */ 800 #define RMIXL_GPIO_INT_STS _RMIXL_OFFSET(0x6) /* Interrupt Status register */ 801 #define RMIXL_GPIO_INT_TYP _RMIXL_OFFSET(0x7) /* Interrupt Type register */ 802 #define RMIXL_GPIO_RESET _RMIXL_OFFSET(0x8) /* XLS Soft Reset register */ 803 804 /* 805 * RMIXL_GPIO_RESET bits 806 */ 807 #define RMIXL_GPIO_RESET_RESV __BITS(31,1) 808 #define RMIXL_GPIO_RESET_RESET __BIT(0) 809 810 811 /* GPIO System Control Registers */ 812 #define RMIXL_GPIO_RESET_CFG _RMIXL_OFFSET(0x15) /* Reset Configuration register */ 813 #define RMIXL_GPIO_THERMAL_CSR _RMIXL_OFFSET(0x16) /* Thermal Control/Status register */ 814 #define RMIXL_GPIO_THERMAL_SHFT _RMIXL_OFFSET(0x17) /* Thermal Shift register */ 815 #define RMIXL_GPIO_BIST_ALL_STS _RMIXL_OFFSET(0x18) /* BIST All Status register */ 816 #define RMIXL_GPIO_BIST_EACH_STS _RMIXL_OFFSET(0x19) /* BIST Each Status register */ 817 #define RMIXL_GPIO_SGMII_0_3_PHY_CTL _RMIXL_OFFSET(0x20) /* SGMII #0..3 PHY Control register */ 818 #define RMIXL_GPIO_AUI_0_PHY_CTL _RMIXL_OFFSET(0x20) /* AUI port#0 PHY Control register */ 819 #define RMIXL_GPIO_SGMII_4_7_PLL_CTL _RMIXL_OFFSET(0x21) /* SGMII #4..7 PLL Control register */ 820 #define RMIXL_GPIO_AUI_1_PLL_CTL _RMIXL_OFFSET(0x21) /* AUI port#1 PLL Control register */ 821 #define RMIXL_GPIO_SGMII_4_7_PHY_CTL _RMIXL_OFFSET(0x22) /* SGMII #4..7 PHY Control register */ 822 #define RMIXL_GPIO_AUI_1_PHY_CTL _RMIXL_OFFSET(0x22) /* AUI port#1 PHY Control register */ 823 #define RMIXL_GPIO_INT_MAP _RMIXL_OFFSET(0x25) /* Interrupt Map to PIC, 0=int14, 1=int30 */ 824 #define RMIXL_GPIO_EXT_INT _RMIXL_OFFSET(0x26) /* External Interrupt control register */ 825 #define RMIXL_GPIO_CPU_RST _RMIXL_OFFSET(0x28) /* CPU Reset control register */ 826 #define RMIXL_GPIO_LOW_PWR_DIS _RMIXL_OFFSET(0x29) /* Low Power Dissipation register */ 827 #define RMIXL_GPIO_RANDOM _RMIXL_OFFSET(0x2b) /* Low Power Dissipation register */ 828 #define RMIXL_GPIO_CPU_CLK_DIS _RMIXL_OFFSET(0x2d) /* CPU Clock Disable register */ 829 830 /* 831 * RMIXL_GPIO_RESET_CFG bits 832 */ 833 #define RMIXL_GPIO_RESET_CFG_RESa __BITS(31,28) 834 #define RMIXL_GPIO_RESET_CFG_PCIE_SRIO_SEL __BITS(27,26) /* PCIe or SRIO Select: 835 * 00 = PCIe selected, SRIO not available 836 * 01 = SRIO selected, 1.25 Gbaud (1.0 Gbps) 837 * 10 = SRIO selected, 2.25 Gbaud (2.0 Gbps) 838 * 11 = SRIO selected, 3.125 Gbaud (2.5 Gbps) 839 */ 840 #define RMIXL_GPIO_RESET_CFG_XAUI_PORT1_SEL __BIT(25) /* XAUI Port 1 Select: 841 * 0 = Disabled - Port is SGMII ports 4-7 842 * 1 = Enabled - Port is 4-lane XAUI Port 1 843 */ 844 #define RMIXL_GPIO_RESET_CFG_XAUI_PORT0_SEL __BIT(24) /* XAUI Port 0 Select: 845 * 0 = Disabled - Port is SGMII ports 0-3 846 * 1 = Enabled - Port is 4-lane XAUI Port 0 847 */ 848 #define RMIXL_GPIO_RESET_CFG_RESb __BIT(23) 849 #define RMIXL_GPIO_RESET_CFG_USB_DEV __BIT(22) /* USB Device: 850 * 0 = Device Mode 851 * 1 = Host Mode 852 */ 853 #define RMIXL_GPIO_RESET_CFG_PCIE_CFG __BITS(21,20) /* PCIe or SRIO configuration */ 854 #define RMIXL_GPIO_RESET_CFG_FLASH33_EN __BIT(19) /* Flash 33 MHZ Enable: 855 * 0 = 66.67 MHz 856 * 1 = 33.33 MHz 857 */ 858 #define RMIXL_GPIO_RESET_CFG_BIST_DIAG_EN __BIT(18) /* BIST Diagnostics enable */ 859 #define RMIXL_GPIO_RESET_CFG_BIST_RUN_EN __BIT(18) /* BIST Run enable */ 860 #define RMIXL_GPIO_RESET_CFG_NOOT_NAND __BIT(16) /* Enable boot from NAND Flash */ 861 #define RMIXL_GPIO_RESET_CFG_BOOT_PCMCIA __BIT(15) /* Enable boot from PCMCIA */ 862 #define RMIXL_GPIO_RESET_CFG_FLASH_CFG __BIT(14) /* Flash 32-bit Data Configuration: 863 * 0 = 32-bit address / 16-bit data 864 * 1 = 32-bit address / 32-bit data 865 */ 866 #define RMIXL_GPIO_RESET_CFG_PCMCIA_EN __BIT(13) /* PCMCIA Enable Status */ 867 #define RMIXL_GPIO_RESET_CFG_PARITY_EN __BIT(12) /* Parity Enable Status */ 868 #define RMIXL_GPIO_RESET_CFG_BIGEND __BIT(11) /* Big Endian Mode Enable Status */ 869 #define RMIXL_GPIO_RESET_CFG_PLL1_OUT_DIV __BITS(10,8) /* PLL1 (Core PLL) Output Divider */ 870 #define RMIXL_GPIO_RESET_CFG_PLL1_FB_DIV __BITS(7,0) /* PLL1 Feedback Divider */ 871 872 /* 873 * RMIXL_GPIO_LOW_PWR_DIS bits 874 * except as noted, all bits are: 875 * 0 = feature enable (default) 876 * 1 = feature disable 877 */ 878 /* XXX defines are for XLS6xx, XLS4xx-Lite and XLS4xx Devices */ 879 #define RMIXL_GPIO_LOW_PWR_DIS_LP __BIT(0) /* Low Power disable */ 880 #define RMIXL_GPIO_LOW_PWR_DIS_GMAC_QD_0 __BIT(1) /* GMAC Quad 0 (GMAC 0..3) disable */ 881 #define RMIXL_GPIO_LOW_PWR_DIS_GMAC_QD_1 __BIT(2) /* GMAC Quad 1 (GMAC 4..7) disable */ 882 #define RMIXL_GPIO_LOW_PWR_DIS_USB __BIT(3) /* USB disable */ 883 #define RMIXL_GPIO_LOW_PWR_DIS_PCIE __BIT(4) /* PCIE disable */ 884 #define RMIXL_GPIO_LOW_PWR_DIS_CDE __BIT(5) /* Compression/Decompression Engine disable */ 885 #define RMIXL_GPIO_LOW_PWR_DIS_DMA __BIT(6) /* DMA Engine disable */ 886 #define RMIXL_GPIO_LOW_PWR_DIS_SAE __BITS(8,7) /* Security Acceleration Engine disable: 887 * 00 = enable (default) 888 * 01 = reserved 889 * 10 = reserved 890 * 11 = disable 891 */ 892 #define RMIXL_GPIO_LOW_PWR_DIS_RESV __BITS(31,9) 893 894 #define RMIXLP_GPIO_PADOE(g) _RMIXL_OFFSET(0x40+(g)) // Pad Output Enable Register 0 895 #define RMIXLP_GPIO_PADOE0 _RMIXL_OFFSET(0x40) // Pad Output Enable Register 0 896 #define RMIXLP_GPIO_PADOE1 _RMIXL_OFFSET(0x41) // Pad Output Enable Register 1 897 #define RMIXLP_GPIO_PADDRV(g) _RMIXL_OFFSET(0x42+(g)) // Pad Drive Register 0 898 #define RMIXLP_GPIO_PADDRV0 _RMIXL_OFFSET(0x42) // Pad Drive Register 0 899 #define RMIXLP_GPIO_PADDRV1 _RMIXL_OFFSET(0x43) // Pad Drive Register 1 900 #define RMIXLP_GPIO_PADSAMPLE(g) _RMIXL_OFFSET(0x44+(g)) // Pad Sample Register 0 901 #define RMIXLP_GPIO_PADSAMPLE0 _RMIXL_OFFSET(0x44) // Pad Sample Register 0 902 #define RMIXLP_GPIO_PADSAMPLE1 _RMIXL_OFFSET(0x45) // Pad Sample Register 1 903 #define RMIXLP_GPIO_INTEN(n,g) _RMIXL_OFFSET(0x46+2*(n)+(g)) // Interrupt 0 Enable Register 0 904 #define RMIXLP_GPIO_INTEN0(n) _RMIXL_OFFSET(0x46+2*(n)) // Interrupt 0 Enable Register 0 905 #define RMIXLP_GPIO_INTEN1(n) _RMIXL_OFFSET(0x47+2*(n)) // Interrupt 0 Enable Register 0 906 #define RMIXLP_GPIO_8XX_INTPOL(g) _RMIXL_OFFSET((0x4E)+(g)) // Interrupt Polarity Register 0 907 #define RMIXLP_GPIO_8XX_INTTYPE(g) _RMIXL_OFFSET(0x50+(g)) // Interrupt Type Register 0 908 #define RMIXLP_GPIO_8XX_INTSTAT(g) _RMIXL_OFFSET(0x52+(g)) // Interrupt Status Register 0 909 #define RMIXLP_GPIO_3XX_INTPOL(g) _RMIXL_OFFSET((0x5E)+(g)) // Interrupt Polarity Register 0 910 #define RMIXLP_GPIO_3XX_INTTYPE(g) _RMIXL_OFFSET(0x60+(g)) // Interrupt Type Register 0 911 #define RMIXLP_GPIO_3XX_INTSTAT(g) _RMIXL_OFFSET(0x62+(g)) // Interrupt Status Register 0 912 913 #define RMIXLP_GPIO_8XX_MAXPINS 41 /* 41 GPIO pins */ 914 #define RMIXLP_GPIO_4XX_MAXPINS 41 /* 41 GPIO pins */ 915 #define RMIXLP_GPIO_3XX_MAXPINS 57 /* 41 GPIO pins */ 916 #define RMIXLP_GPIO_3XXL_MAXPINS 44 /* 44 GPIO pins */ 917 918 /* 919 * Peripheral I/O bus (Flash/PCMCIA) controller registers 920 */ 921 #define RMIXL_FLASH_NCS 10 /* number of chip selects */ 922 #define RMIXL_FLASH_CS_BOOT 0 /* CS0 is boot flash */ 923 #define RMIXL_FLASH_CS_PCMCIA_CF 6 /* CS6 is PCMCIA compact flash */ 924 #define RMIXL_FLASH_CSBASE_ADDRn(n) _RMIXL_OFFSET(0x00+(n)) /* CSn Base Address reg */ 925 #define RMIXL_FLASH_CSADDR_MASKn(n) _RMIXL_OFFSET(0x10+(n)) /* CSn Address Mask reg */ 926 #define RMIXL_FLASH_CSDEV_PARMn(n) _RMIXL_OFFSET(0x20+(n)) /* CSn Device Parameter reg */ 927 #define RMIXL_FLASH_CSTIME_PARMAn(n) _RMIXL_OFFSET(0x30+(n)) /* CSn Timing Parameters A reg */ 928 #define RMIXL_FLASH_CSTIME_PARMBn(n) _RMIXL_OFFSET(0x40+(n)) /* CSn Timing Parameters B reg */ 929 #define RMIXL_FLASH_INT_MASK _RMIXL_OFFSET(0x50) /* Flash Interrupt Mask reg */ 930 #define RMIXL_FLASH_INT_STATUS _RMIXL_OFFSET(0x60) /* Flash Interrupt Status reg */ 931 #define RMIXL_FLASH_ERROR_STATUS _RMIXL_OFFSET(0x70) /* Flash Error Status reg */ 932 #define RMIXL_FLASH_ERROR_ADDR _RMIXL_OFFSET(0x80) /* Flash Error Address reg */ 933 934 /* 935 * RMIXL_FLASH_CSDEV_PARMn bits 936 */ 937 #define RMIXL_FLASH_CSDEV_RESV __BITS(31,16) 938 #define RMIXL_FLASH_CSDEV_BFN __BIT(15) /* Boot From Nand 939 * 0=Boot from NOR or 940 * PCCard Type 1 Flash 941 * 1=Boot from NAND 942 */ 943 #define RMIXL_FLASH_CSDEV_NANDEN __BIT(14) /* NAND Flash Enable 944 * 0=NOR 945 * 1=NAND 946 */ 947 #define RMIXL_FLASH_CSDEV_ADVTYPE __BIT(13) /* Add Valid Sensing Type 948 * 0=level 949 * 1=pulse 950 */ 951 #define RMIXL_FLASH_CSDEV_PARITY_TYPE __BIT(12) /* Parity Type 952 * 0=even 953 * 1=odd 954 */ 955 #define RMIXL_FLASH_CSDEV_PARITY_EN __BIT(11) /* Parity Enable */ 956 #define RMIXL_FLASH_CSDEV_GENIF_EN __BIT(10) /* Generic PLD/FPGA interface mode 957 * if this bit is set, then 958 * GPIO[13:10] cannot be used 959 * for interrupts 960 */ 961 #define RMIXL_FLASH_CSDEV_PCMCIA_EN __BIT(9) /* PCMCIA Interface mode */ 962 #define RMIXL_FLASH_CSDEV_DWIDTH __BITS(8,7) /* Data Bus Width: 963 * 00: 8 bit 964 * 01: 16 bit 965 * 10: 32 bit 966 * 11: 8 bit 967 */ 968 #define RMIXL_FLASH_CSDEV_DWIDTH_SHFT 7 969 #define RMIXL_FLASH_CSDEV_MX_ADDR __BIT(6) /* Multiplexed Address 970 * 0: non-muxed 971 * AD[31:24] = Data, 972 * AD[23:0] = Addr 973 * 1: muxed 974 * External latch required 975 */ 976 #define RMIXL_FLASH_CSDEV_WAIT_POL __BIT(5) /* WAIT polarity 977 * 0: Active high 978 * 1: Active low 979 */ 980 #define RMIXL_FLASH_CSDEV_WAIT_EN __BIT(4) /* Enable External WAIT Ack mode */ 981 #define RMIXL_FLASH_CSDEV_BURST __BITS(3,1) /* Burst Length: 982 * 000: 2x 983 * 001: 4x 984 * 010: 8x 985 * 011: 16x 986 * 100: 32x 987 */ 988 #define RMIXL_FLASH_CSDEV_BURST_SHFT 1 989 #define RMIXL_FLASH_CSDEV_BURST_EN __BITS(0) /* Burst Enable */ 990 991 992 /* 993 * NAND Flash Memory Control registers 994 */ 995 #define RMIXL_NAND_CLEn(n) _RMIXL_OFFSET(0x90+(n)) /* CSn 8-bit CLE command value reg */ 996 #define RMIXL_NAND_ALEn(n) _RMIXL_OFFSET(0xa0+(n)) /* CSn 8-bit ALE address phase reg */ 997 998 999 /* 1000 * PCIE Interface Controller registers 1001 */ 1002 #define RMIXL_PCIE_CTRL1 _RMIXL_OFFSET(0x0) 1003 #define RMIXL_PCIE_CTRL2 _RMIXL_OFFSET(0x1) 1004 #define RMIXL_PCIE_CTRL3 _RMIXL_OFFSET(0x2) 1005 #define RMIXL_PCIE_CTRL4 _RMIXL_OFFSET(0x3) 1006 #define RMIXL_PCIE_CTRL _RMIXL_OFFSET(0x4) 1007 #define RMIXL_PCIE_IOBM_TIMER _RMIXL_OFFSET(0x5) 1008 #define RMIXL_PCIE_MSI_CMD _RMIXL_OFFSET(0x6) 1009 #define RMIXL_PCIE_MSI_RESP _RMIXL_OFFSET(0x7) 1010 #define RMIXL_PCIE_DWC_CRTL5 _RMIXL_OFFSET(0x8) /* not on XLS408Lite, XLS404Lite */ 1011 #define RMIXL_PCIE_DWC_CRTL6 _RMIXL_OFFSET(0x9) /* not on XLS408Lite, XLS404Lite */ 1012 #define RMIXL_PCIE_IOBM_SWAP_MEM_BASE _RMIXL_OFFSET(0x10) 1013 #define RMIXL_PCIE_IOBM_SWAP_MEM_LIMIT _RMIXL_OFFSET(0x11) 1014 #define RMIXL_PCIE_IOBM_SWAP_IO_BASE _RMIXL_OFFSET(0x12) 1015 #define RMIXL_PCIE_IOBM_SWAP_IO_LIMIT _RMIXL_OFFSET(0x13) 1016 #define RMIXL_PCIE_TRGT_CHRNT_MEM_BASE _RMIXL_OFFSET(0x14) 1017 #define RMIXL_PCIE_TRGT_CHRNT_MEM_LIMIT _RMIXL_OFFSET(0x15) 1018 #define RMIXL_PCIE_TRGT_L2ALC_MEM_BASE _RMIXL_OFFSET(0x16) 1019 #define RMIXL_PCIE_TRGT_L2ALC_MEM_LIMIT _RMIXL_OFFSET(0x17) 1020 #define RMIXL_PCIE_TRGT_REX_MEM_BASE _RMIXL_OFFSET(0x18) 1021 #define RMIXL_PCIE_TRGT_REX_MEM_LIMIT _RMIXL_OFFSET(0x19) 1022 #define RMIXL_PCIE_EP_MEM_BASE _RMIXL_OFFSET(0x1a) 1023 #define RMIXL_PCIE_EP_MEM_LIMIT _RMIXL_OFFSET(0x1b) 1024 #define RMIXL_PCIE_EP_ADDR_MAP_ENTRY0 _RMIXL_OFFSET(0x1c) 1025 #define RMIXL_PCIE_EP_ADDR_MAP_ENTRY1 _RMIXL_OFFSET(0x1d) 1026 #define RMIXL_PCIE_EP_ADDR_MAP_ENTRY2 _RMIXL_OFFSET(0x1e) 1027 #define RMIXL_PCIE_EP_ADDR_MAP_ENTRY3 _RMIXL_OFFSET(0x1f) 1028 #define RMIXL_PCIE_LINK0_STATE _RMIXL_OFFSET(0x20) 1029 #define RMIXL_PCIE_LINK1_STATE _RMIXL_OFFSET(0x21) 1030 #define RMIXL_PCIE_IOBM_INT_STATUS _RMIXL_OFFSET(0x22) 1031 #define RMIXL_PCIE_IOBM_INT_ENABLE _RMIXL_OFFSET(0x23) 1032 #define RMIXL_PCIE_LINK0_MSI_STATUS _RMIXL_OFFSET(0x24) 1033 #define RMIXL_PCIE_LINK1_MSI_STATUS _RMIXL_OFFSET(0x25) 1034 #define RMIXL_PCIE_LINK0_MSI_ENABLE _RMIXL_OFFSET(0x26) 1035 #define RMIXL_PCIE_LINK1_MSI_ENABLE _RMIXL_OFFSET(0x27) 1036 #define RMIXL_PCIE_LINK0_INT_STATUS0 _RMIXL_OFFSET(0x28) 1037 #define RMIXL_PCIE_LINK1_INT_STATUS0 _RMIXL_OFFSET(0x29) 1038 #define RMIXL_PCIE_LINK0_INT_STATUS1 _RMIXL_OFFSET(0x2a) 1039 #define RMIXL_PCIE_LINK1_INT_STATUS1 _RMIXL_OFFSET(0x2b) 1040 #define RMIXL_PCIE_LINK0_INT_ENABLE0 _RMIXL_OFFSET(0x2c) 1041 #define RMIXL_PCIE_LINK1_INT_ENABLE0 _RMIXL_OFFSET(0x2d) 1042 #define RMIXL_PCIE_LINK0_INT_ENABLE1 _RMIXL_OFFSET(0x2e) 1043 #define RMIXL_PCIE_LINK1_INT_ENABLE1 _RMIXL_OFFSET(0x2f) 1044 #define RMIXL_PCIE_PHY_CR_CMD _RMIXL_OFFSET(0x30) 1045 #define RMIXL_PCIE_PHY_CR_WR_DATA _RMIXL_OFFSET(0x31) 1046 #define RMIXL_PCIE_PHY_CR_RESP _RMIXL_OFFSET(0x32) 1047 #define RMIXL_PCIE_PHY_CR_RD_DATA _RMIXL_OFFSET(0x33) 1048 #define RMIXL_PCIE_IOBM_ERR_CMD _RMIXL_OFFSET(0x34) 1049 #define RMIXL_PCIE_IOBM_ERR_LOWER_ADDR _RMIXL_OFFSET(0x35) 1050 #define RMIXL_PCIE_IOBM_ERR_UPPER_ADDR _RMIXL_OFFSET(0x36) 1051 #define RMIXL_PCIE_IOBM_ERR_BE _RMIXL_OFFSET(0x37) 1052 #define RMIXL_PCIE_LINK2_STATE _RMIXL_OFFSET(0x60) /* not on XLS408Lite, XLS404Lite */ 1053 #define RMIXL_PCIE_LINK3_STATE _RMIXL_OFFSET(0x61) /* not on XLS408Lite, XLS404Lite */ 1054 #define RMIXL_PCIE_LINK2_MSI_STATUS _RMIXL_OFFSET(0x64) /* not on XLS408Lite, XLS404Lite */ 1055 #define RMIXL_PCIE_LINK3_MSI_STATUS _RMIXL_OFFSET(0x65) /* not on XLS408Lite, XLS404Lite */ 1056 #define RMIXL_PCIE_LINK2_MSI_ENABLE _RMIXL_OFFSET(0x66) /* not on XLS408Lite, XLS404Lite */ 1057 #define RMIXL_PCIE_LINK3_MSI_ENABLE _RMIXL_OFFSET(0x67) /* not on XLS408Lite, XLS404Lite */ 1058 #define RMIXL_PCIE_LINK2_INT_STATUS0 _RMIXL_OFFSET(0x68) /* not on XLS408Lite, XLS404Lite */ 1059 #define RMIXL_PCIE_LINK3_INT_STATUS0 _RMIXL_OFFSET(0x69) /* not on XLS408Lite, XLS404Lite */ 1060 #define RMIXL_PCIE_LINK2_INT_STATUS1 _RMIXL_OFFSET(0x6a) /* not on XLS408Lite, XLS404Lite */ 1061 #define RMIXL_PCIE_LINK3_INT_STATUS1 _RMIXL_OFFSET(0x6b) /* not on XLS408Lite, XLS404Lite */ 1062 #define RMIXL_PCIE_LINK2_INT_ENABLE0 _RMIXL_OFFSET(0x6c) /* not on XLS408Lite, XLS404Lite */ 1063 #define RMIXL_PCIE_LINK3_INT_ENABLE0 _RMIXL_OFFSET(0x6d) /* not on XLS408Lite, XLS404Lite */ 1064 #define RMIXL_PCIE_LINK2_INT_ENABLE1 _RMIXL_OFFSET(0x6e) /* not on XLS408Lite, XLS404Lite */ 1065 #define RMIXL_PCIE_LINK3_INT_ENABLE1 _RMIXL_OFFSET(0x6f) /* not on XLS408Lite, XLS404Lite */ 1066 #define RMIXL_VC0_POSTED_RX_QUEUE_CTRL _RMIXL_OFFSET(0x1d2) 1067 #define RMIXL_VC0_POSTED_BUFFER_DEPTH _RMIXL_OFFSET(0x1ea) 1068 #define RMIXL_PCIE_MSG_TX_THRESHOLD _RMIXL_OFFSET(0x308) 1069 #define RMIXL_PCIE_MSG_BUCKET_SIZE_0 _RMIXL_OFFSET(0x320) 1070 #define RMIXL_PCIE_MSG_BUCKET_SIZE_1 _RMIXL_OFFSET(0x321) 1071 #define RMIXL_PCIE_MSG_BUCKET_SIZE_2 _RMIXL_OFFSET(0x322) 1072 #define RMIXL_PCIE_MSG_BUCKET_SIZE_3 _RMIXL_OFFSET(0x323) 1073 #define RMIXL_PCIE_MSG_BUCKET_SIZE_4 _RMIXL_OFFSET(0x324) /* not on XLS408Lite, XLS404Lite */ 1074 #define RMIXL_PCIE_MSG_BUCKET_SIZE_5 _RMIXL_OFFSET(0x325) /* not on XLS408Lite, XLS404Lite */ 1075 #define RMIXL_PCIE_MSG_BUCKET_SIZE_6 _RMIXL_OFFSET(0x326) /* not on XLS408Lite, XLS404Lite */ 1076 #define RMIXL_PCIE_MSG_BUCKET_SIZE_7 _RMIXL_OFFSET(0x327) /* not on XLS408Lite, XLS404Lite */ 1077 #define RMIXL_PCIE_MSG_CREDIT_FIRST _RMIXL_OFFSET(0x380) 1078 #define RMIXL_PCIE_MSG_CREDIT_LAST _RMIXL_OFFSET(0x3ff) 1079 1080 /* 1081 * USB General Interface registers 1082 * these are opffset from REGSPACE selected by __BIT(12) == 1 1083 * RMIXL_IOREG_VADDR(RMIXL_IO_DEV_USB_B + reg) 1084 * see Tables 18-7 and 18-14 in the XLS PRM 1085 */ 1086 #define RMIXL_USB_GEN_CTRL1 0x00 1087 #define RMIXL_USB_GEN_CTRL2 0x04 1088 #define RMIXL_USB_GEN_CTRL3 0x08 1089 #define RMIXL_USB_IOBM_TIMER 0x0C 1090 #define RMIXL_USB_VBUS_TIMER 0x10 1091 #define RMIXL_USB_BYTESWAP_EN 0x14 1092 #define RMIXL_USB_COHERENT_MEM_BASE 0x40 1093 #define RMIXL_USB_COHERENT_MEM_LIMIT 0x44 1094 #define RMIXL_USB_L2ALLOC_MEM_BASE 0x48 1095 #define RMIXL_USB_L2ALLOC_MEM_LIMIT 0x4C 1096 #define RMIXL_USB_READEX_MEM_BASE 0x50 1097 #define RMIXL_USB_READEX_MEM_LIMIT 0x54 1098 #define RMIXL_USB_PHY_STATUS 0xC0 1099 #define RMIXL_USB_INTERRUPT_STATUS 0xC4 1100 #define RMIXL_USB_INTERRUPT_ENABLE 0xC8 1101 1102 /* 1103 * RMIXL_USB_GEN_CTRL1 bits 1104 */ 1105 #define RMIXL_UG_CTRL1_RESV __BITS(31,2) 1106 #define RMIXL_UG_CTRL1_HOST_RST __BIT(1) /* Resets the Host Controller 1107 * 0: reset 1108 * 1: normal operation 1109 */ 1110 #define RMIXL_UG_CTRL1_DEV_RST __BIT(0) /* Resets the Device Controller 1111 * 0: reset 1112 * 1: normal operation 1113 */ 1114 1115 /* 1116 * RMIXL_USB_GEN_CTRL2 bits 1117 */ 1118 #define RMIXL_UG_CTRL2_RESa __BITS(31,20) 1119 #define RMIXL_UG_CTRL2_TX_TUNE_1 __BITS(19,18) /* Port_1 Transmitter Tuning for High-Speed Operation. 1120 * 00: ~-4.5% 1121 * 01: Design default 1122 * 10: ~+4.5% 1123 * 11: ~+9% = Recommended Operating setting 1124 */ 1125 #define RMIXL_UG_CTRL2_TX_TUNE_0 __BITS(17,16) /* Port_0 Transmitter Tuning for High-Speed Operation 1126 * 11: Recommended Operating condition 1127 */ 1128 #define RMIXL_UG_CTRL2_RESb __BIT(15) 1129 #define RMIXL_UG_CTRL2_WEAK_PDEN __BIT(14) /* 500kOhm Pull-Down Resistor on D+ and D- Enable */ 1130 #define RMIXL_UG_CTRL2_DP_PULLUP_ESD __BIT(13) /* D+ Pull-Up Resistor Enable */ 1131 #define RMIXL_UG_CTRL2_ESD_TEST_MODE __BIT(12) /* D+ Pull-Up Resistor Control Select */ 1132 #define RMIXL_UG_CTRL2_TX_BIT_STUFF_EN_H_1 \ 1133 __BIT(11) /* Port_1 High-Byte Transmit Bit-Stuffing Enable */ 1134 #define RMIXL_UG_CTRL2_TX_BIT_STUFF_EN_H_0 \ 1135 __BIT(10) /* Port_0 High-Byte Transmit Bit-Stuffing Enable */ 1136 #define RMIXL_UG_CTRL2_TX_BIT_STUFF_EN_L_1 \ 1137 __BIT(9) /* Port_1 Low-Byte Transmit Bit-Stuffing Enable */ 1138 #define RMIXL_UG_CTRL2_TX_BIT_STUFF_EN_L_0 \ 1139 __BIT(8) /* Port_0 Low-Byte Transmit Bit-Stuffing Enable */ 1140 #define RMIXL_UG_CTRL2_RESc __BITS(7,6) 1141 #define RMIXL_UG_CTRL2_LOOPBACK_ENB_1 __BIT(5) /* Port_1 Loopback Test Enable */ 1142 #define RMIXL_UG_CTRL2_LOOPBACK_ENB_0 __BIT(4) /* Port_0 Loopback Test Enable */ 1143 #define RMIXL_UG_CTRL2_DEVICE_VBUS __BIT(3) /* VBUS detected (Device mode only) */ 1144 #define RMIXL_UG_CTRL2_PHY_PORT_RST_1 __BIT(2) /* Resets Port_1 of the PHY 1145 * 1: normal operation 1146 * 0: reset 1147 */ 1148 #define RMIXL_UG_CTRL2_PHY_PORT_RST_0 __BIT(1) /* Resets Port_0 of the PHY 1149 * 1: normal operation 1150 * 0: reset 1151 */ 1152 #define RMIXL_UG_CTRL2_PHY_RST __BIT(0) /* Resets the PHY 1153 * 1: normal operation 1154 * 0: reset 1155 */ 1156 #define RMIXL_UG_CTRL2_RESV \ 1157 (RMIXL_UG_CTRL2_RESa | RMIXL_UG_CTRL2_RESb | RMIXL_UG_CTRL2_RESc) 1158 1159 1160 /* 1161 * RMIXL_USB_GEN_CTRL3 bits 1162 */ 1163 #define RMIXL_UG_CTRL3_RESa __BITS(31,11) 1164 #define RMIXL_UG_CTRL3_PREFETCH_SIZE __BITS(10,8) /* The pre-fetch size for a memory read transfer 1165 * between USB Interface and DI station. 1166 * Valid value ranges is from 1 to 4. 1167 */ 1168 #define RMIXL_UG_CTRL3_RESb __BIT(7) 1169 #define RMIXL_UG_CTRL3_DEV_UPPERADDR __BITS(6,1) /* Device controller address space selector */ 1170 #define RMIXL_UG_CTRL3_USB_FLUSH __BIT(0) /* Flush the USB interface */ 1171 1172 /* 1173 * RMIXL_USB_PHY_STATUS bits 1174 */ 1175 #define RMIXL_UB_PHY_STATUS_RESV __BITS(31,1) 1176 #define RMIXL_UB_PHY_STATUS_VBUS __BIT(0) /* USB VBUS status */ 1177 1178 /* 1179 * RMIXL_USB_INTERRUPT_STATUS and RMIXL_USB_INTERRUPT_ENABLE bits 1180 */ 1181 #define RMIXL_UB_INTERRUPT_RESV __BITS(31,6) 1182 #define RMIXL_UB_INTERRUPT_FORCE __BIT(5) /* USB force interrupt */ 1183 #define RMIXL_UB_INTERRUPT_PHY __BIT(4) /* USB PHY interrupt */ 1184 #define RMIXL_UB_INTERRUPT_DEV __BIT(3) /* USB Device Controller interrupt */ 1185 #define RMIXL_UB_INTERRUPT_EHCI __BIT(2) /* USB EHCI interrupt */ 1186 #define RMIXL_UB_INTERRUPT_OHCI_1 __BIT(1) /* USB OHCI #1 interrupt */ 1187 #define RMIXL_UB_INTERRUPT_OHCI_0 __BIT(0) /* USB OHCI #0 interrupt */ 1188 #define RMIXL_UB_INTERRUPT_MAX 5 1189 1190 1191 /* 1192 * USB Device Controller registers 1193 * these are opffset from REGSPACE selected by __BIT(12) == 0 1194 * RMIXL_IOREG_VADDR(RMIXL_IO_DEV_USB_A + reg) 1195 * see Table 18-7 in the XLS PRM 1196 */ 1197 #define RMIXL_USB_UDC_GAHBCFG 0x008 /* UDC Configuration A (UDC_GAHBCFG) */ 1198 #define RMIXL_USB_UDC_GUSBCFG 0x00C /* UDC Configuration B (UDC_GUSBCFG) */ 1199 #define RMIXL_USB_UDC_GRSTCTL 0x010 /* UDC Reset */ 1200 #define RMIXL_USB_UDC_GINTSTS 0x014 /* UDC Interrupt Register */ 1201 #define RMIXL_USB_UDC_GINTMSK 0x018 /* UDC Interrupt Mask Register */ 1202 #define RMIXL_USB_UDC_GRXSTSP 0x020 /* UDC Receive Status Read /Pop Register (Read Only) */ 1203 #define RMIXL_USB_UDC_GRXFSIZ 0x024 /* UDC Receive FIFO Size Register */ 1204 #define RMIXL_USB_UDC_GNPTXFSIZ 0x028 /* UDC Non-periodic Transmit FIFO Size Register */ 1205 #define RMIXL_USB_UDC_GUID 0x03C /* UDC User ID Register (UDC_GUID) */ 1206 #define RMIXL_USB_UDC_GSNPSID 0x040 /* UDC ID Register (Read Only) */ 1207 #define RMIXL_USB_UDC_GHWCFG1 0x044 /* UDC User HW Config1 Register (Read Only) */ 1208 #define RMIXL_USB_UDC_GHWCFG2 0x048 /* UDC User HW Config2 Register (Read Only) */ 1209 #define RMIXL_USB_UDC_GHWCFG3 0x04C /* UDC User HW Config3 Register (Read Only) */ 1210 #define RMIXL_USB_UDC_GHWCFG4 0x050 /* UDC User HW Config4 Register (Read Only) */ 1211 #define RMIXL_USB_UDC_DPTXFSIZ0 0x104 1212 #define RMIXL_USB_UDC_DPTXFSIZ1 0x108 1213 #define RMIXL_USB_UDC_DPTXFSIZ2 0x10c 1214 #define RMIXL_USB_UDC_DPTXFSIZn(n) (0x104 + (4 * (n))) 1215 /* UDC Device IN Endpoint Transmit FIFO-n 1216 Size Registers (UDC_DPTXFSIZn) */ 1217 #define RMIXL_USB_UDC_DCFG 0x800 /* UDC Configuration C */ 1218 #define RMIXL_USB_UDC_DCTL 0x804 /* UDC Control Register */ 1219 #define RMIXL_USB_UDC_DSTS 0x808 /* UDC Status Register (Read Only) */ 1220 #define RMIXL_USB_UDC_DIEPMSK 0x810 /* UDC Device IN Endpoint Common 1221 Interrupt Mask Register (UDC_DIEPMSK) */ 1222 #define RMIXL_USB_UDC_DOEPMSK 0x814 /* UDC Device OUT Endpoint Common Interrupt Mask register */ 1223 #define RMIXL_USB_UDC_DAINT 0x818 /* UDC Device All Endpoints Interrupt Register */ 1224 #define RMIXL_USB_UDC_DAINTMSK 0x81C /* UDC Device All Endpoints Interrupt Mask Register */ 1225 #define RMIXL_USB_UDC_DTKNQR3 0x830 /* Device Threshold Control Register */ 1226 #define RMIXL_USB_UDC_DTKNQR4 0x834 /* Device IN Endpoint FIFO Empty Interrupt Mask Register */ 1227 #define RMIXL_USB_UDC_DIEPCTL 0x900 /* Device Control IN Endpoint 0 Control Register */ 1228 #define RMIXL_USB_UDC_DIEPINT 0x908 /* Device IN Endpoint 0 Interrupt Register */ 1229 #define RMIXL_USB_UDC_DIEPTSIZ 0x910 /* Device IN Endpoint 0 Transfer Size Register */ 1230 #define RMIXL_USB_UDC_DIEPDMA 0x914 /* Device IN Endpoint 0 DMA Address Register */ 1231 #define RMIXL_USB_UDC_DTXFSTS 0x918 /* Device IN Endpoint Transmit FIFO Status Register */ 1232 #define RMIXL_USB_DEV_IN_ENDPT(d,n) (0x920 + ((d) * 0x20) + ((n) * 4)) 1233 /* Device IN Endpoint #d Register #n */ 1234 1235 /* 1236 * USB Host Controller register base addrs 1237 * these are offset from REGSPACE selected by __BIT(12) == 0 1238 * RMIXL_IOREG_VADDR(RMIXL_IO_DEV_USB_A + reg) 1239 * see Table 18-14 in the XLS PRM 1240 * specific Host Controller is selected by __BITS(11,10) 1241 */ 1242 #define RMIXL_USB_HOST_EHCI_BASE 0x000 1243 #define RMIXL_USB_HOST_0HCI0_BASE 0x400 1244 #define RMIXL_USB_HOST_0HCI1_BASE 0x800 1245 #define RMIXL_USB_HOST_RESV 0xc00 1246 #define RMIXL_USB_HOST_MASK 0xc00 1247 1248 /* 1249 * XLP PCIe Host Bridge Registers 1250 */ 1251 #ifndef RMIXLP_SBC_PCIE_ECFG_PBASE 1252 #define RMIXLP_SBC_PCIE_ECFG_PBASE 0x18000000 1253 #endif 1254 #define RMIXLP_SBC_PCIE_ECFG_VBASE MIPS_PHYS_TO_KSEG1(RMIXLP_SBC_PCIE_ECFG_PBASE) 1255 #define RMIXLP_SBC_NBU_MODE _RMIXL_OFFSET(0x40) /* Memory I/O mode */ 1256 #define RMIXLP_SBC_PCIE_CFG_BASE _RMIXL_OFFSET(0x41) /* PCI Configuration BAR */ 1257 #define RMIXLP_SBC_PCIE_CFG_LIMIT _RMIXL_OFFSET(0x42) /* PCI Configuration Limit */ 1258 #define RMIXLP_SBC_PCIE_ECFG_BASE _RMIXL_OFFSET(0x43) /* PCI Extended Configuration BAR */ 1259 #define RMIXLP_SBC_PCIE_ECFG_LIMIT _RMIXL_OFFSET(0x44) /* PCI Extended Configuration Limit */ 1260 #define RMIXLP_SBC_BUSNUM_BARn(n) _RMIXL_OFFSET(0x45+(n)) /* Bus Number BAR reg */ 1261 #define RMIXLP_SBC_NBUSNUM_BAR 7 /* PCIe: 0-3, ICI: 4-7 */ 1262 #define RMIXLP_SBC_FLASH_BASEn(n) _RMIXL_OFFSET(0x4c+(n)) /* Flash Memory BAR */ 1263 #define RMIXLP_SBC_FLASH_LIMITn(n) _RMIXL_OFFSET(0x50+(n)) /* Flash Memory Limit reg */ 1264 #define RMIXLP_SBC_NFLASH 4 1265 #define RMIXLP_SBC_DRAM_BASEn(n) _RMIXL_OFFSET(0x54+(n)) /* DRAM[n] BAR */ 1266 #define RMIXLP_SBC_DRAM_LIMITn(n) _RMIXL_OFFSET(0x5c+(n)) /* DRAM[n] Limit */ 1267 #define RMIXLP_SBC_DRAM_XLATIONn(n) _RMIXL_OFFSET(0x6c+(n)) /* DRAM[n] Translation */ 1268 #define RMIXLP_SBC_NDRAM 8 1269 #define RMIXLP_SBC_PCIE_MEM_BASEn(n) _RMIXL_OFFSET(0x74+(n)) /* PCI Memory region BAR */ 1270 #define RMIXLP_SBC_PCIE_MEM_LIMITn(n) _RMIXL_OFFSET(0x78+(n)) /* PCI Memory region Limit */ 1271 #define RMIXLP_SBC_NPCIE_MEM 4 1272 #define RMIXLP_SBC_PCIE_IO_BASEn(n) _RMIXL_OFFSET(0x7c+(n)) /* PCI IO region BAR */ 1273 #define RMIXLP_SBC_PCIE_IO_LIMITn(n) _RMIXL_OFFSET(0x80+(n)) /* PCI IO region LimitAR */ 1274 #define RMIXLP_SBC_NPCIE_IO 4 1275 1276 #define _RMIXLP_SBC_X_TO_PA(x,r) \ 1277 ((uint64_t)((r) & RMIXLP_SBC_##x##_MASK) << 8) 1278 #define _RMIXLP_SBC_PA_TO_X(x,r) \ 1279 (((uint64_t)(r) >> 8) & RMIXLP_SBC_##x##_MASK) 1280 #define _RMIXLP_SBC_X_SIZE(x,b,l) \ 1281 ((l)-(b)+(__LOWEST_SET_BIT(RMIXLP_SBC_##x##_MASK) << 8)) 1282 1283 #define RMIXLP_SBC_DRAM_MASK __BITS(31,12) /* phys address bits 39:20 */ 1284 #define RMIXLP_SBC_PCIE_CFG_MASK __BITS(31,16) /* phys address bits 39:24 */ 1285 #define RMIXLP_SBC_PCIE_ECFG_MASK __BITS(31,12) /* phys address bits 39:20 */ 1286 #define RMIXLP_SBC_PCIE_MEM_MASK __BITS(31,12) /* phys address bits 39:20 */ 1287 #define RMIXLP_SBC_PCIE_IO_MASK __BITS(31,12) /* phys address bits 39:20 */ 1288 #define RMIXLP_SBC_SRIO_MEM_MASK __BITS(31,12) /* phys address bits 39:20 */ 1289 1290 #define RMIXLP_SBC_DRAM_SIZE(b,l) _RMIXLP_SBC_X_SIZE(DRAM,b,l) 1291 #define RMIXLP_SBC_PCIE_CFG_SIZE(b,l) _RMIXLP_SBC_X_SIZE(PCIE_CFG,b,l) 1292 #define RMIXLP_SBC_PCIE_ECFG_SIZE(b,l) _RMIXLP_SBC_X_SIZE(PCIE_ECFG,b,l) 1293 #define RMIXLP_SBC_PCIE_MEM_SIZE(b,l) _RMIXLP_SBC_X_SIZE(PCIE_MEM,b,l) 1294 #define RMIXLP_SBC_PCIE_IO_SIZE(b,l) _RMIXLP_SBC_X_SIZE(PCIE_IO,b,l) 1295 #define RMIXLP_SBC_SRIO_MEM_SIZE(b,l) _RMIXLP_SBC_X_SIZE(SRIO_MEM,b,l) 1296 1297 #define RMIXLP_SBC_DRAM_TO_PA(r) _RMIXLP_SBC_X_TO_PA(DRAM,r) 1298 #define RMIXLP_SBC_PCIE_CFG_TO_PA(r) _RMIXLP_SBC_X_TO_PA(PCIE_CFG,r) 1299 #define RMIXLP_SBC_PCIE_ECFG_TO_PA(r) _RMIXLP_SBC_X_TO_PA(PCIE_ECFG,r) 1300 #define RMIXLP_SBC_PCIE_MEM_TO_PA(r) _RMIXLP_SBC_X_TO_PA(PCIE_MEM,r) 1301 #define RMIXLP_SBC_PCIE_IO_TO_PA(r) _RMIXLP_SBC_X_TO_PA(PCIE_IO,r) 1302 #define RMIXLP_SBC_SRIO_MEM_TO_PA(r) _RMIXLP_SBC_X_TO_PA(SRIO_MEM,r) 1303 1304 #define RMIXLP_SBC_PA_TO_DRAM(r) _RMIXLP_SBC_PA_TO_X(DRAM,r) 1305 #define RMIXLP_SBC_PA_TO_PCIE_CFG(r) _RMIXLP_SBC_PA_TO_X(PCIE_CFG,r) 1306 #define RMIXLP_SBC_PA_TO_PCIE_ECFG(r) _RMIXLP_SBC_PA_TO_X(PCIE_ECFG,r) 1307 #define RMIXLP_SBC_PA_TO_PCIE_MEM(r) _RMIXLP_SBC_PA_TO_X(PCIE_MEM,r) 1308 #define RMIXLP_SBC_PA_TO_PCIE_IO(r) _RMIXLP_SBC_PA_TO_X(PCIE_IO,r) 1309 #define RMIXLP_SBC_PA_TO_SRIO_MEM(r) _RMIXLP_SBC_PA_TO_X(SRIO_MEM,r) 1310 1311 /* 1312 * For each PCIe link, its subordinate buses must be programed into its 1313 * BusNum_BAR register. This is in addition to the normal PCIe registers 1314 * on the PCIe link device itself. 1315 */ 1316 #define RMIXLP_SBC_BUSNUM_BAR_ENABLE __BIT(0) 1317 #define RMIXLP_SBC_BUSNUM_BAR_SECBUS __BITS(15,8) 1318 #define RMIXLP_SBC_BUSNUM_BAR_SUBBUS __BITS(23,16) 1319 #define RMIXLP_SBC_BUSNUM_BAR_MASK __BITS(23,8) 1320 1321 #define RMIXLP_SBC_EVCNT_CTRL1 _RMIXL_OFFSET(0x90) /* Event Counter 1 Control Register */ 1322 #define RMIXLP_SBC_EVCNT_LOW1 _RMIXL_OFFSET(0x91) /* Event Counter 1 Low Register */ 1323 #define RMIXLP_SBC_EVCNT_HIGH1 _RMIXL_OFFSET(0x92) /* Event Counter 1 High Register */ 1324 #define RMIXLP_SBC_EVCNT_CTRL2 _RMIXL_OFFSET(0x93) /* Event Counter 2 Control Register */ 1325 #define RMIXLP_SBC_EVCNT_LOW2 _RMIXL_OFFSET(0x94) /* Event Counter 2 Low Register */ 1326 #define RMIXLP_SBC_EVCNT_HIGH2 _RMIXL_OFFSET(0x95) /* Event Counter 2 High Register */ 1327 1328 #define RMIXLP_SBC_TRCBUF_MATCH_RQST0 _RMIXL_OFFSET(0x96) /* Trace Buffer Match Request Register 0 */ 1329 #define RMIXLP_SBC_TRCBUF_MATCH_RQST1 _RMIXL_OFFSET(0x97) /* Trace Buffer MAtch Request Register 1 */ 1330 #define RMIXLP_SBC_TRCBUF_MATCH_ADDRLO _RMIXL_OFFSET(0x98) /* Trace Buffer Match Request Address Low Register */ 1331 #define RMIXLP_SBC_TRCBUF_MATCH_ADDRHI _RMIXL_OFFSET(0x99) /* Trace Buffer Match Request Address High Register */ 1332 #define RMIXLP_SBC_TRCBUF_CTRL _RMIXL_OFFSET(0x9A) /* Trace Buffer Control Register */ 1333 #define RMIXLP_SBC_TRCBUF_INIT _RMIXL_OFFSET(0x9B) /* Trace Buffer Initialization Register */ 1334 #define RMIXLP_SBC_TRCBUF_ACCESS _RMIXL_OFFSET(0x9C) /* Trace Buffer Access Register */ 1335 #define RMIXLP_SBC_TRCBUF_READDATA(n) _RMIXL_OFFSET(0x9D+(n)) /* Trace Buffer Read Data Registers <0-3> */ 1336 #define RMIXLP_SBC_NTRCBUF_READDATA 4 1337 #define RMIXLP_SBC_TRCBUF_STATUS _RMIXL_OFFSET(0xA1) /* Trace Buffer Status Register */ 1338 1339 #define RMIXLP_SBC_ADDR_ERROR0 _RMIXL_OFFSET(0xA2) /* Address Error Register 0 */ 1340 #define RMIXLP_SBC_ADDR_ERROR1 _RMIXL_OFFSET(0xA3) /* Address Error Register 1 */ 1341 #define RMIXLP_SBC_ADDR_ERROR2 _RMIXL_OFFSET(0xA4) /* Address Error Register 2 */ 1342 #define RMIXLP_SBC_TAGECC_ADDR_ERROR0 _RMIXL_OFFSET(0xA5) /* Tag ECC Address Error Register 0 */ 1343 #define RMIXLP_SBC_TAGECC_ADDR_ERROR1 _RMIXL_OFFSET(0xA6) /* Tag ECC Address Error Register 1 */ 1344 #define RMIXLP_SBC_TAGECC_ADDR_ERROR2 _RMIXL_OFFSET(0xA7) /* Tag ECC Address Error Register 2 */ 1345 #define RMIXLP_SBC_LINE_FLUSH_LOW _RMIXL_OFFSET(0xA8) /* Line Flush Low Register */ 1346 #define RMIXLP_SBC_LINE_FLUSH_HIGH _RMIXL_OFFSET(0xA9) /* Line Flush High Register */ 1347 #define RMIXLP_SBC_NODE_ID _RMIXL_OFFSET(0xAA) /* Node ID Register */ 1348 #define RMIXLP_SBC_ERROR_INT_ENABLE _RMIXL_OFFSET(0xAB) /* Error Interrupt Enable Register */ 1349 #define RMIXLP_SBC_TIMEOUT_ERROR0 _RMIXL_OFFSET(0xAC) /* Timeout Error Register 0 */ 1350 #define RMIXLP_SBC_TIMEOUT_ERROR1 _RMIXL_OFFSET(0xAD) /* Timeout Error Register 1 */ 1351 #define RMIXLP_SBC_TIMEOUT_ERROR2 _RMIXL_OFFSET(0xAE) /* Timeout Error Register 2 */ 1352 #define RMIXLP_SBC_SRIO_MEM_BASE _RMIXL_OFFSET(0xAF) /* SRIO Memory Base Address Register */ 1353 #define RMIXLP_SBC_SRIO_MEM_LIMIT _RMIXL_OFFSET(0xB0) /* SRIO Memory Limit Address Register */ 1354 1355 /* 1356 * XLP L3 Cache Registers 1357 */ 1358 #define RMIXLP_SBC_L3_LINE_LCK0 _RMIXL_OFFSET(0xC0) 1359 #define RMIXLP_SBC_L3_LINE_LCK1 _RMIXL_OFFSET(0xC1) 1360 #define RMIXLP_SBC_L3_ACCESS_CMD _RMIXL_OFFSET(0xC2) 1361 #define RMIXLP_SBC_L3_ACCESS_ADDR _RMIXL_OFFSET(0xC3) 1362 #define RMIXLP_SBC_L3_ACCESS_DATA0 _RMIXL_OFFSET(0xC4) 1363 #define RMIXLP_SBC_L3_ACCESS_DATA1 _RMIXL_OFFSET(0xC5) 1364 #define RMIXLP_SBC_L3_ACCESS_DATA2 _RMIXL_OFFSET(0xC6) 1365 #define RMIXLP_SBC_L3_WAY_PART0 _RMIXL_OFFSET(0xC7) 1366 #define RMIXLP_SBC_L3_WAY_PART1 _RMIXL_OFFSET(0xC8) 1367 #define RMIXLP_SBC_L3_WAY_PART4 _RMIXL_OFFSET(0xCB) 1368 #define RMIXLP_SBC_L3_WAY_PART5 _RMIXL_OFFSET(0xCC) 1369 #define RMIXLP_SBC_L3_WAY_PART6 _RMIXL_OFFSET(0xCD) 1370 #define RMIXLP_SBC_L3_PERF_CTL_REG0 _RMIXL_OFFSET(0xCE) 1371 #define RMIXLP_SBC_L3_PERF_CNT_REG0 _RMIXL_OFFSET(0xCF) 1372 #define RMIXLP_SBC_L3_PERF_CTL_REG1 _RMIXL_OFFSET(0xD0) 1373 #define RMIXLP_SBC_L3_PERF_CNT_REG1 _RMIXL_OFFSET(0xD1) 1374 #define RMIXLP_SBC_L3_PERF_CTL_REG2 _RMIXL_OFFSET(0xD2) 1375 #define RMIXLP_SBC_L3_PERF_CNT_REG2 _RMIXL_OFFSET(0xD3) 1376 #define RMIXLP_SBC_L3_PERF_CTL_REG3 _RMIXL_OFFSET(0xD4) 1377 #define RMIXLP_SBC_L3_PERF_CNT_REG3 _RMIXL_OFFSET(0xD5) 1378 #define RMIXLP_SBC_L3_ERROR_INJ_CTL_REG0 _RMIXL_OFFSET(0xD6) 1379 #define RMIXLP_SBC_L3_ERROR_INJ_CTL_REG1 _RMIXL_OFFSET(0xD7) 1380 #define RMIXLP_SBC_L3_ERROR_INJ_CTL_REG2 _RMIXL_OFFSET(0xD8) 1381 #define RMIXLP_SBC_L3_ERROR_LOG_REG0 _RMIXL_OFFSET(0xD9) 1382 #define RMIXLP_SBC_L3_ERROR_LOG_REG1 _RMIXL_OFFSET(0xDA) 1383 #define RMIXLP_SBC_L3_ERROR_LOG_REG2 _RMIXL_OFFSET(0xDB) 1384 #define RMIXLP_SBC_L3_INTERRUPT_EN_REG _RMIXL_OFFSET(0xDC) 1385 1386 /* 1387 * XLP Time Slot Weight Registers 1388 */ 1389 #define RMIXLP_SBC_PCIE_LINK_TSW(n) _RMIXL_OFFSET(0x300+(n)) /* PCIe Link 0 Time Slot Weight Register */ 1390 #define RMIXLP_SBC_NPCIE_LINK_TSW 4 1391 #define RMIXLP_SBC_USB_TSW _RMIXL_OFFSET(0x304) /* USB Time Slot Weight Register */ 1392 #define RMIXLP_SBC_POE_TSW _RMIXL_OFFSET(0x305) /* Packet Ordering Engine Time Slot Weight Register */ 1393 #define RMIXLP_SBC_SATA_TSW _RMIXL_OFFSET(0x306) /* SATA Weight Register */ 1394 #define RMIXLP_SBC_SRIO_TSW _RMIXL_OFFSET(0x307) /* SRIO Weight Register */ 1395 #define RMIXLP_SBC_REGEX_TSW _RMIXL_OFFSET(0x308) /* RegEx Weight Register */ 1396 #define RMIXLP_SBC_GPIO_TSW _RMIXL_OFFSET(0x309) /* General I/O Time Slot Weight Register */ 1397 #define RMIXLP_SBC_FLASH_TSW _RMIXL_OFFSET(0x30A) /* Flash Time Slot Weight Register (NAND/NOR/SPI/MMC/SD) */ 1398 #define RMIXLP_SBC_NAE_TSW _RMIXL_OFFSET(0x30B) /* Network Acceleration Engine Time Slot Weight Register */ 1399 #define RMIXLP_SBC_FMN_TSW _RMIXL_OFFSET(0x30C) /* Fast Messaging Network Time Slot Weight Register */ 1400 #define RMIXLP_SBC_DMAENG_TSW _RMIXL_OFFSET(0x30D) /* Data Transfer and RAID Engine Slot Weight Register */ 1401 #define RMIXLP_SBC_SEC_TSW _RMIXL_OFFSET(0x30E) /* Security Engine Slot Weight Register */ 1402 #define RMIXLP_SBC_RSAECC_TSW _RMIXL_OFFSET(0x30F) /* RSA/ECC Engine Slot Weight Register */ 1403 #define RMIXLP_SBC_BRIDGE_DATA_COUNTER _RMIXL_OFFSET(0x310) /* Bridge Data Counter Register */ 1404 #define RMIXLP_SBC_BYTE_SWAP _RMIXL_OFFSET(0x311) /* Byte Swap Register */ 1405 1406 #define RMIXLP_USB_CTL0 _RMIXL_OFFSET(0x41) 1407 #define RMIXLP_USB_BYTE_SWAP_DIS _RMIXL_OFFSET(0x49) 1408 #define RMIXLP_USB_PHY0 _RMIXL_OFFSET(0x4A) 1409 1410 #define RMIXLP_USB_CTL0_BIUTOEN __BIT(8) 1411 #define RMIXLP_USB_CTL0_INCR4 __BIT(7) 1412 #define RMIXLP_USB_CTL0_INCR8 __BIT(6) 1413 #define RMIXLP_USB_CTL0_INCR16 __BIT(5) 1414 #define RMIXLP_USB_CTL0_0HCIINT12 __BIT(4) 1415 #define RMIXLP_USB_CTL0_0HCIINT1 __BIT(3) 1416 #define RMIXLP_USB_CTL0_0HCISTRTCLK __BIT(2) 1417 #define RMIXLP_USB_CTL0_EHCI64BEN __BIT(1) 1418 #define RMIXLP_USB_CTL0_USBCTLRRST __BIT(0) 1419 1420 #define RMIXLP_USB_PHY0_PHYTXBSENH1 __BIT(11) 1421 #define RMIXLP_USB_PHY0_PHYTXBSTENH0 __BIT(10) 1422 #define RMIXLP_USB_PHY0_PHYTXBSENL1 __BIT(9) 1423 #define RMIXLP_USB_PHY0_PHYTXBSENL0 __BIT(8) 1424 #define RMIXLP_USB_PHY0_PHYLBEN1 __BIT(7) 1425 #define RMIXLP_USB_PHY0_PHYLBEN0 __BIT(6) 1426 #define RMIXLP_USB_PHY0_PHYPORTRST1 __BIT(5) 1427 #define RMIXLP_USB_PHY0_PHYPORTRST0 __BIT(4) 1428 #define RMIXLP_USB_PHY0_PHYREFCLKFREQ __BITS(3,2) 1429 #define RMIXLP_USB_PHY0_PHYDETVBUS __BIT(1) 1430 #define RMIXLP_USB_PHY0_USBPHYRESET __BIT(0) 1431 1432 #define RMIXLP_SBC_PCITAG _RMIXL_PCITAG(0,0,0) 1433 #define RMIXLP_ICI1_PCITAG _RMIXL_PCITAG(0,0,1) 1434 #define RMIXLP_ICI2_PCITAG _RMIXL_PCITAG(0,0,2) 1435 #define RMIXLP_ICI3_PCITAG _RMIXL_PCITAG(0,0,3) 1436 #define RMIXLP_PIC_PCITAG _RMIXL_PCITAG(0,0,4) 1437 1438 #define RMIXLP_PCIPORT0_PCITAG _RMIXL_PCITAG(0,0,0) 1439 #define RMIXLP_PCIPORT1_PCITAG _RMIXL_PCITAG(0,1,0) 1440 #define RMIXLP_PCIPORT2_PCITAG _RMIXL_PCITAG(0,2,0) 1441 #define RMIXLP_PCIPORT3_PCITAG _RMIXL_PCITAG(0,3,0) 1442 1443 #define RMIXLP_EHCI0_PCITAG _RMIXL_PCITAG(0,2,0) 1444 #define RMIXLP_OHCI0_PCITAG _RMIXL_PCITAG(0,2,1) 1445 #define RMIXLP_OHCI1_PCITAG _RMIXL_PCITAG(0,2,2) 1446 #define RMIXLP_EHCI1_PCITAG _RMIXL_PCITAG(0,2,3) 1447 #define RMIXLP_OHCI2_PCITAG _RMIXL_PCITAG(0,2,4) 1448 #define RMIXLP_OHCI3_PCITAG _RMIXL_PCITAG(0,2,5) 1449 1450 #define RMIXLP_NAE_PCITAG _RMIXL_PCITAG(0,3,0) 1451 #define RMIXLP_POE_PCITAG _RMIXL_PCITAG(0,3,1) 1452 #define RMIXLP_AHCI_PCITAG _RMIXL_PCITAG(0,3,2) 1453 1454 #define RMIXLP_FMN_PCITAG _RMIXL_PCITAG(0,4,0) 1455 1456 #define RMIXLP_DMA_PCITAG _RMIXL_PCITAG(0,5,0) 1457 #define RMIXLP_SAE_PCITAG _RMIXL_PCITAG(0,5,1) 1458 #define RMIXLP_PKE_PCITAG _RMIXL_PCITAG(0,5,2) 1459 #define RMIXLP_SRIO_PCITAG _RMIXL_PCITAG(0,5,3) 1460 #define RMIXLP_RXE_PCITAG _RMIXL_PCITAG(0,5,4) 1461 1462 #define RMIXLP_UART1_PCITAG _RMIXL_PCITAG(0,6,0) 1463 #define RMIXLP_UART2_PCITAG _RMIXL_PCITAG(0,6,1) 1464 #define RMIXLP_I2C1_PCITAG _RMIXL_PCITAG(0,6,2) 1465 #define RMIXLP_I2C2_PCITAG _RMIXL_PCITAG(0,6,3) 1466 #define RMIXLP_GPIO_PCITAG _RMIXL_PCITAG(0,6,4) 1467 #define RMIXLP_SM_PCITAG _RMIXL_PCITAG(0,6,5) 1468 #define RMIXLP_JTAG_PCITAG _RMIXL_PCITAG(0,6,6) 1469 1470 #define RMIXLP_NOR_PCITAG _RMIXL_PCITAG(0,7,0) 1471 #define RMIXLP_NAND_PCITAG _RMIXL_PCITAG(0,7,1) 1472 #define RMIXLP_SPI_PCITAG _RMIXL_PCITAG(0,7,2) 1473 #define RMIXLP_MMC_PCITAG _RMIXL_PCITAG(0,7,3) 1474 /* 1475 * PCI PCIe control (contains the IRT info) 1476 */ 1477 #define PCI_RMIXLP_STATID _RMIXL_OFFSET(0x3c) 1478 #define PCI_RMIXLP_IRTINFO _RMIXL_OFFSET(0x3d) 1479 1480 #define PCI_RMIXLP_STATID_BASE(x) (((x) >> 0) & 0xfff) 1481 #define PCI_RMIXLP_STATID_COUNT(x) (((x) >> 16) & 0xfff) 1482 1483 #define PCI_RMIXLP_IRTINFO_BASE(x) (((x) >> 0) & 0xfff) 1484 #define PCI_RMIXLP_IRTINFO_COUNT(x) (((x) >> 16) & 0xfff) 1485 1486 /* 1487 * XLP System Management Registers 1488 */ 1489 #define RMIXLP_SM_CHIP_RESET _RMIXL_OFFSET(0x40) 1490 #define RMIXLP_SM_POWER_ON_RESET_CFG _RMIXL_OFFSET(0x41) 1491 #define RMIXLP_SM_EFUSE_DEVICE_CFG_STATUS0 _RMIXL_OFFSET(0x42) 1492 #define RMIXLP_SM_EFUSE_DEVICE_CFG_STATUS1 _RMIXL_OFFSET(0x43) 1493 1494 #define RMIXLP_SM_POWER_ON_RESET_CFG_CPLL_DFS __BITS(31,30) 1495 #define RMIXLP_SM_POWER_ON_RESET_CFG_I2LR __BIT(29) 1496 #define RMIXLP_SM_POWER_ON_RESET_CFG_I1LR __BIT(28) 1497 #define RMIXLP_SM_POWER_ON_RESET_CFG_I0LR __BIT(27) 1498 #define RMIXLP_SM_POWER_ON_RESET_CFG_TS __BIT(26) 1499 #define RMIXLP_SM_POWER_ON_RESET_CFG_UM __BIT(25) 1500 #define RMIXLP_SM_POWER_ON_RESET_CFG_PLC __BITS(24,23) 1501 #define RMIXLP_SM_POWER_ON_RESET_CFG_PM __BITS(22,19) 1502 #define RMIXLP_SM_POWER_ON_RESET_CFG_CDV __BITS(18,17) 1503 #define RMIXLP_SM_POWER_ON_RESET_CFG_CDF __BITS(16,10) 1504 #define RMIXLP_SM_POWER_ON_RESET_CFG_CDR __BITS(9,8) 1505 #define RMIXLP_SM_POWER_ON_RESET_CFG_MC __BIT(7) 1506 #define RMIXLP_SM_POWER_ON_RESET_CFG_RB __BIT(6) 1507 #define RMIXLP_SM_POWER_ON_RESET_CFG_BE __BIT(5) 1508 #define RMIXLP_SM_POWER_ON_RESET_CFG_NORSP __BIT(4) 1509 #define RMIXLP_SM_POWER_ON_RESET_CFG_BD __BITS(3,0) 1510 1511 #define RMIXLP_NOR_NCS 8 1512 #define RMIXLP_NOR_CS_BASEADDRESSn(n) _RMIXL_OFFSET(0x40+(n)) 1513 #define RMIXLP_NOR_CS_BASELIMITn(n) _RMIXL_OFFSET(0x48+(n)) 1514 #define RMIXLP_NOR_CS_DEVPARMn(n) _RMIXL_OFFSET(0x50+(n)) 1515 #define RMIXLP_NOR_CS_DEVTIME0n(n) _RMIXL_OFFSET(0x58+2*(n)) 1516 #define RMIXLP_NOR_CS_DEVTIME1n(n) _RMIXL_OFFSET(0x59+2*(n)) 1517 #define RMIXLP_NOR_SYSCTRL _RMIXL_OFFSET(0x68) 1518 #define RMIXLP_NOR_BYTESWAP _RMIXL_OFFSET(0x69) 1519 #define RMIXLP_NOR_ERRLOG0 _RMIXL_OFFSET(0x6a) 1520 #define RMIXLP_NOR_ERRLOG1 _RMIXL_OFFSET(0x6b) 1521 #define RMIXLP_NOR_ERRLOG2 _RMIXL_OFFSET(0x6c) 1522 #define RMIXLP_NOR_ID_TIMEOUT_VAL _RMIXL_OFFSET(0x6d) 1523 #define RMIXLP_NOR_INSTAT _RMIXL_OFFSET(0x6e) 1524 #define RMIXLP_NOR_INTEN _RMIXL_OFFSET(0x6f) 1525 #define RMIXLP_NOR_STATUS _RMIXL_OFFSET(0x70) 1526 1527 #define RMIXLP_NOR_CS_ADDRESS_TO_PA(r) ((uint64_t)(r) << 8) 1528 #define RMIXLP_NOR_PA_TO_CS_ADDRESS(r) ((uint64_t)(r) >> 8) 1529 #define RMIXLP_NOR_CS_SIZE(b,l) ((l)-(b)+256) 1530 1531 // Interface Byte signal Enable. 1532 // 0: Disables programmable data width selection 1533 // 1: Enables programmable data width selection 1534 #define RMIXLP_NOR_CS_DEVPARM_BE __BIT(16) 1535 // Little Endian. 1536 // 0:Big Endian 1537 // 1:Little Endian 1538 #define RMIXLP_NOR_CS_DEVPARM_LE __BIT(13) 1539 #define RMIXLP_NOR_CS_DEVPARM_DW __BITS(12,11) // Device Data Width 1540 #define RMIXLP_NOR_CS_DEVPARM_DW_8_BITS 0 1541 #define RMIXLP_NOR_CS_DEVPARM_DW_16_BITS 1 1542 #define RMIXLP_NOR_CS_DEVPARM_DW_32_BITS 2 1543 // Multiplexed/non-multiplexed device data/address mode 1544 // 0:Non-multiplexed (only valid if field DW is set to 0) 1545 // 1:Multiplexed data and address bus 1546 #define RMIXLP_NOR_CS_DEVPARM_MUX __BIT(10) 1547 // Wait/Ready signal Polarity 1548 // 0:Wait active high 1549 // 1:Wait active low 1550 #define RMIXLP_NOR_CS_DEVPARM_WRP __BIT(9) 1551 // Wait/ready signal Write interface Enable. 1552 // Enables/disables wait-acknowledge mode during write cycles. 1553 // 0: Enable device Wait mode. External IO_WAIT_L signal is used. 1554 // 1: Disable Wait mode; external IO_WAIT_L signal is not used. 1555 #define RMIXLP_NOR_CS_DEVPARM_WWE __BIT(8) 1556 // Wait/Ready signal Read interface Enable. 1557 // Enables/disables wait-acknowledge mode during read cycles. 1558 // 0: Enable device Wait mode. External IO_WAIT_L signal is used. 1559 // 1: Disable Wait mode; external IO_WAIT_L signal is not used. 1560 // This signal is distinct from the RYBY (Ready/Busy) signal, 1561 // which is shared by all Flash devices. 1562 #define RMIXLP_NOR_CS_DEVPARM_WRE __BIT(7) 1563 // Synchronous Read Data Burst Enabled (when set to 1). 1564 #define RMIXLP_NOR_CS_DEVPARM_SRDBE __BIT(5) 1565 // Word-align Address. 1566 // If set to 1, address bits are word-aligned. 1567 // This allows address bits of a 16-bit Flash device to connect to XLP 1568 // address bits [24:1] instead of [23:0] or the address bits of a 32-bit 1569 // Flash device to connect to XLP address bits [25:2] instead of [23:0]. 1570 #define RMIXLP_NOR_CS_DEVPARM_WA __BIT(2) 1571 #define RMIXLP_NOR_CS_DEVPARM_FLASH_TYPE __BITS(1,0) // Flash Type 1572 #define RMIXLP_NOR_CS_DEVPARM_FLASH_TYPE_NOR 0 // NOR Flash 1573 #define RMIXLP_NOR_CS_DEVPARM_FLASH_TYPE_ONCHIP 1 // On-chip ROM 1574 1575 // CS to CS timing. 1576 // This field indicates the number of clock cycles from the falling 1577 // edge of IO_CSn to the next falling edge of IO_CSn, where n = 0-7. 1578 #define RMIXLP_NOR_DEVTIME0_CS_TO_CS __BITS(31,28) 1579 1580 // WE to CS timing. 1581 // This field indicates the number of clock cycles from the rising 1582 // edge of IO_WE_L to the rising edge of IO_CSn_L. 1583 #define RMIXLP_NOR_DEVTIME0_WE_TO_CS __BITS(27,24) 1584 1585 // OE to CS timing. 1586 // This field indicates the number of clock cycles from the rising 1587 // edge of IO_OE_L to the rising edge of IO_CSn_L. 1588 #define RMIXLP_NOR_DEVTIME0_OE_TO_CS __BITS(23,22) 1589 1590 // CS to WE timing. 1591 // This field indicates the number of clock cycles from the falling 1592 // edge of IO_CSn_L to the falling edge of IO_WE_L 1593 #define RMIXLP_NOR_DEVTIME0_CS_TO_WE __BITS(21,19) 1594 1595 // CS to OE timing. 1596 // This field indicates the number of clock cycles from the falling 1597 // edge of IO_CSn_L to the falling edge of IO_OE_L. 1598 #define RMIXLP_NOR_DEVTIME0_CS_TO_OE __BITS(18,16) 1599 1600 // Wait/Ready to Data timing. 1601 // This field indicates the number of clock cycles from the falling 1602 // edge of IO_WE_L to when data is available on a write, or the 1603 // falling edge of IO_OE_L to when date is available on a read. 1604 #define RMIXLP_NOR_DEVTIME0_WAIT_TO_DATA __BITS(15,11) 1605 1606 // OE to Wait timing. 1607 // This field indicates the IO_WE_L to wait time on a write, 1608 // or the IO_OE_L to wait time on a read. 1609 #define RMIXLP_NOR_DEVTIME0_OE_TO_WAIT __BITS(10,6) 1610 1611 // ALE to CS timing. 1612 // This field indicates the number of clock cycles from the falling 1613 // edge of IO_ALE to the falling edge of IO_CSn_L. This field is 1614 // encoded as follows: 1615 #define RMIXLP_NOR_DEVTIME0_ALE_TO_CS ___BITS(5,3) 1616 // 000: IO_CSn_L is one cycle ahead of IO_ALE. 1617 #define RMIXLP_NOR_DEVTIME0_ALE_TO_CS_AHEAD1 0 1618 // 001: IO_CSn_L is aligned with IO_ALE. 1619 #define RMIXLP_NOR_DEVTIME0_ALE_TO_CS_ALIGNED 1 1620 // 010-111: IO_ALE is ahead of IO_CSn_L. 1621 #define RMIXLP_NOR_DEVTIME0_ALE_TO_CS_BEHIND1 2 1622 #define RMIXLP_NOR_DEVTIME0_ALE_TO_CS_BEHIND2 3 1623 #define RMIXLP_NOR_DEVTIME0_ALE_TO_CS_BEHIND3 4 1624 #define RMIXLP_NOR_DEVTIME0_ALE_TO_CS_BEHIND4 5 1625 #define RMIXLP_NOR_DEVTIME0_ALE_TO_CS_BEHIND5 6 1626 #define RMIXLP_NOR_DEVTIME0_ALE_TO_CS_BEHIND6 7 1627 1628 // ALE pulse width. 1629 // This field indicates the number of clock cycles from the falling 1630 // edge of IO_ALE to the rising edge of IO_ALE. 1631 #define RMIXLP_NOR_DEVTIME0_ALE_WIDTH __BITS(2,0) 1632 1633 #define RMIXLP_NOR_DEVTIME1_WAIT_TIMEOUT __BITS(26,12) 1634 // Wait Timeout. 1635 // If the Interrupt is an error, the Enable bit is set. 1636 1637 // RDY/BSY signal Polarity: 1638 // 0:Ready low, busy high 1639 // 1:Ready high, busy low 1640 // This signal is shared by all Flash devices. If any of the devices 1641 // puts the signal into the busy state, this signal will indicate 1642 // not-ready (busy) status. 1643 #define RMIXLP_NOR_SYSCTRL_RDYBSY_POL __BIT(1) 1644 1645 // Interconnect Timeout Enable (if set to 1). 1646 #define RMIXLP_NOR_SYSCTRL_ITE __BIT(0) 1647 1648 // RDY/BSY pin transition, if set to 1. 1649 #define RMIXLP_NOR_INTSTAT_RDYBSY __BIT(0) 1650 1651 // Error Log. Setting this bit enables error logging. 1652 #define RMIXLP_NOR_INTEN_EL __BIT(1) 1653 // RYBY Interrupt Enable. Setting this bit enables NOR Flash interrupts. 1654 #define RMIXLP_NOR_INTEN_RDYBSY __BIT(0) 1655 1656 // RDY/BSY Status. 1: NOR device is ready. 1657 #define RMIXLP_NOR_STATUS_RDYBSY __BIT(0) 1658 1659 #define RMIXLP_NAND_RDYBSY_SEL _RMIXL_OFFSET(0x81) 1660 1661 1662 #define RMIXLP_SPI_CS_CONFIG(n) _RMIXL_OFFSET(0x40+0x10*(n)) 1663 #define RMIXLP_SPI_CS_FDIV(n) _RMIXL_OFFSET(0x41+0x10*(n)) 1664 #define RMIXLP_SPI_CS_CMD(n) _RMIXL_OFFSET(0x42+0x10*(n)) 1665 #define RMIXLP_SPI_CS_STATUS(n) _RMIXL_OFFSET(0x43+0x10*(n)) 1666 #define RMIXLP_SPI_CS_INTEN(n) _RMIXL_OFFSET(0x44+0x10*(n)) 1667 #define RMIXLP_SPI_CS_FIFO_THRESH(n) _RMIXL_OFFSET(0x45+0x10*(n)) 1668 #define RMIXLP_SPI_CS_FIFO_WCNT(n) _RMIXL_OFFSET(0x46+0x10*(n)) 1669 #define RMIXLP_SPI_CS_TXDATA_FIFO(n) _RMIXL_OFFSET(0x47+0x10*(n)) 1670 #define RMIXLP_SPI_CS_RXDATA_FIFO(n) _RMIXL_OFFSET(0x48+0x10*(n)) 1671 #define RMIXLP_SPI_SYSCNTRL _RMIXL_OFFSET(0x80) 1672 1673 #define RMIXLP_SPI_CS_CONFIG_RXCAP __BIT(11) // RX capture on phase drive 1674 #define RMIXLP_SPI_CS_CONFIG_LSBFE __BIT(10) // LSB first enable 1675 #define RMIXLP_SPI_CS_CONFIG_CSTODATA __BITS(9,8) // chip select polarity 1:high 1676 #define RMIXLP_SPI_CS_CONFIG_SBPOL __BIT(6) // start bit polarity 1:high 1677 #define RMIXLP_SPI_CS_CONFIG_SBE __BIT(6) // start bit enable 1:enabled 1678 #define RMIXLP_SPI_CS_CONFIG_RXMISO __BIT(5) // 0: RX MOSI, 1: RX MISO 1679 #define RMIXLP_SPI_CS_CONFIG_TXMOSI __BIT(4) // 1: TX enable for MOSI pin 1680 #define RMIXLP_SPI_CS_CONFIG_TXMISO __BIT(3) // 1: TX enable for MISO pin 1681 #define RMIXLP_SPI_CS_CONFIG_CSPOL __BIT(2) // chip select polarity 1:high 1682 #define RMIXLP_SPI_CS_CONFIG_CPOL __BIT(1) // clock polarity 1:high 1683 #define RMIXLP_SPI_CS_CONFIG_CPHA __BIT(0) // SPI_CLK clock phase select 1684 1685 #define RMIXLP_SPI_CS_FDIV_CNT __BITS(15,0) // divisor (min of 16) 1686 1687 #define RMIXLP_SPI_CS_CMD_XFERBITCNT __BITS(31,16) // total # of bits - 1 1688 #define RMIXLP_SPI_CS_CMD_CONT __BIT(4) 1689 #define RMIXLP_SPI_CS_CMD_CMD __BITS(3,0) 1690 #define RMIXLP_SPI_CS_CMD_IDLE 0 1691 #define RMIXLP_SPI_CS_CMD_TX 1 1692 #define RMIXLP_SPI_CS_CMD_RX 2 1693 #define RMIXLP_SPI_CS_CMD_TXRX 3 1694 1695 #define RMIXLP_SPI_CS_STATUS_RXOF __BIT(5) // RX FIFO overflow 1696 #define RMIXLP_SPI_CS_STATUS_TXUF __BIT(4) // TX FIFO underflow 1697 #define RMIXLP_SPI_CS_STATUS_RXTHRESH __BIT(3) // RX FIFO threshold crossed 1698 #define RMIXLP_SPI_CS_STATUS_TXTHRESH __BIT(2) // TX FIFO threshold crossed 1699 #define RMIXLP_SPI_CS_STATUS_XFERDONE __BIT(1) // Transfer is complete (RO) 1700 #define RMIXLP_SPI_CS_STATUS_XFERPEND __BIT(1) // Transfer is pending (RO) 1701 1702 #define RMIXLP_SPI_CS_INTEN_RXOF __BIT(4) // RX FIFO overflow 1703 #define RMIXLP_SPI_CS_INTEN_TXUF __BIT(3) // TX FIFO underflow 1704 #define RMIXLP_SPI_CS_INTEN_RXTHRESH __BIT(2) // RX FIFO threshold crossed 1705 #define RMIXLP_SPI_CS_INTEN_TXTHRESH __BIT(1) // TX FIFO threshold crossed 1706 #define RMIXLP_SPI_CS_INTEN_XFERDONE __BIT(0) // Transfer is complete 1707 1708 #define RMIXLP_SPI_CS_FIFO_THRESH_TXFIFO __BITS(7,4) 1709 #define RMIXLP_SPI_CS_FIFO_THRESH_RXFIFO __BITS(3,0) 1710 1711 #define RMIXLP_SPI_CS_FIFO_WCNT_TXFIFO __BITS(7,4) 1712 #define RMIXLP_SPI_CS_FIFO_WCNT_RXFIFO __BITS(3,0) 1713 1714 #define RMIXLP_SPI_SYSCNTRL_PMEN __BIT(8) // Pin muxing enable 1715 #define RMIXLP_SPI_SYSCNTRL_CLKDSI(n) __BIT(4+(n)) // Clock disable for chan 1716 #define RMIXLP_SPI_SYSCNTRL_RESET(n) __BIT(0+(n)) // Reset SPI channel n 1717 1718 #define RMIXLP_SPI_GPIO_PINS __BITS(28,22) 1719 1720 #define RMIXLP_MMC_SLOTSIZE _RMIXL_OFFSET(0x40) 1721 1722 #define RMIXLP_MMC_SLOT0 _RMIXL_OFFSET(0x40) 1723 #define RMIXLP_MMC_SLOT1 _RMIXL_OFFSET(0x80) 1724 #define RMIXLP_MMC_SYSCTRL _RMIXL_OFFSET(0xC0) 1725 #define RMIXLP_MMC_CAPCFG0_S(n) _RMIXL_OFFSET(0xC1+5*(n)) 1726 #define RMIXLP_MMC_CAPCFG1_S(n) _RMIXL_OFFSET(0xC2+5*(n)) 1727 #define RMIXLP_MMC_INIT_PRESET_S(n) _RMIXL_OFFSET(0xC3+5*(n)) 1728 #define RMIXLP_MMC_DEF_PRESET_S(n) _RMIXL_OFFSET(0xC4+5*(n)) 1729 1730 #define RMIXLP_MMC_SYSCTRL_DELAY __BITS(21,19) 1731 #define RMIXLP_MMC_SYSCTRL_RT __BIT(8) 1732 #define RMIXLP_MMC_SYSCTRL_WP1 __BIT(7) 1733 #define RMIXLP_MMC_SYSCTRL_WP0 __BIT(6) 1734 #define RMIXLP_MMC_SYSCTRL_RD_EX __BIT(5) 1735 #define RMIXLP_MMC_SYSCTRL_CA __BIT(4) 1736 #define RMIXLP_MMC_SYSCTRL_EN1 __BIT(3) 1737 #define RMIXLP_MMC_SYSCTRL_EN0 __BIT(2) 1738 #define RMIXLP_MMC_SYSCTRL_EN(n) __BIT(2+(n)) 1739 #define RMIXLP_MMC_SYSCTRL_CLK_DIS __BIT(1) 1740 #define RMIXLP_MMC_SYSCTRL_RST __BIT(0) 1741 1742 #define RMIXLP_MMC_CAPCFG0_S_EMB __BIT(17) // Extended Media Bus 1743 1744 #define RMIXLP_MMC_GPIO_PINS0 \ 1745 (__BITS(10,0) | __BIT(29) | __BIT(31)) 1746 #define RMIXLP_MMC_GPIO_PINS1 \ 1747 (__BITS(21,11) | __BIT(28) | __BIT(30)) 1748 #define RMIXLP_MMC_GPIO_PINS(slot) \ 1749 (slot == 0 ? RMIXLP_MMC_GPIO_PINS0 : RMIXLP_MMC_GPIO_PINS1) 1750 1751 /* 1752 * FMN non-core station configuration registers 1753 */ 1754 #define RMIXL_FMN_BS_FIRST _RMIXL_OFFSET(0x320) 1755 1756 /* 1757 * SGMII bucket size regs 1758 */ 1759 #define RMIXL_FMN_BS_SGMII_UNUSED0 _RMIXL_OFFSET(0x320) /* initialize as 0 */ 1760 #define RMIXL_FMN_BS_SGMII_FCB _RMIXL_OFFSET(0x321) /* Free Credit Bucket size */ 1761 #define RMIXL_FMN_BS_SGMII_TX0 _RMIXL_OFFSET(0x322) 1762 #define RMIXL_FMN_BS_SGMII_TX1 _RMIXL_OFFSET(0x323) 1763 #define RMIXL_FMN_BS_SGMII_TX2 _RMIXL_OFFSET(0x324) 1764 #define RMIXL_FMN_BS_SGMII_TX3 _RMIXL_OFFSET(0x325) 1765 #define RMIXL_FMN_BS_SGMII_UNUSED1 _RMIXL_OFFSET(0x326) /* initialize as 0 */ 1766 #define RMIXL_FMN_BS_SGMII_FCB1 _RMIXL_OFFSET(0x327) /* Free Credit Bucket1 size */ 1767 1768 /* 1769 * SAE bucket size regs 1770 */ 1771 #define RMIXL_FMN_BS_SAE_PIPE0 _RMIXL_OFFSET(0x320) 1772 #define RMIXL_FMN_BS_SAE_RSA_PIPE _RMIXL_OFFSET(0x321) 1773 1774 /* 1775 * DMA bucket size regs 1776 */ 1777 #define RMIXL_FMN_BS_DMA_CHAN0 _RMIXL_OFFSET(0x320) 1778 #define RMIXL_FMN_BS_DMA_CHAN1 _RMIXL_OFFSET(0x321) 1779 #define RMIXL_FMN_BS_DMA_CHAN2 _RMIXL_OFFSET(0x322) 1780 #define RMIXL_FMN_BS_DMA_CHAN3 _RMIXL_OFFSET(0x323) 1781 1782 /* 1783 * CDE bucket size regs 1784 */ 1785 #define RMIXL_FMN_BS_CDE_FREE_DESC _RMIXL_OFFSET(0x320) 1786 #define RMIXL_FMN_BS_CDE_COMPDECOMP _RMIXL_OFFSET(0x321) 1787 1788 /* 1789 * PCIe bucket size regs 1790 */ 1791 #define RMIXL_FMN_BS_PCIE_TX0 _RMIXL_OFFSET(0x320) 1792 #define RMIXL_FMN_BS_PCIE_RX0 _RMIXL_OFFSET(0x321) 1793 #define RMIXL_FMN_BS_PCIE_TX1 _RMIXL_OFFSET(0x322) 1794 #define RMIXL_FMN_BS_PCIE_RX1 _RMIXL_OFFSET(0x323) 1795 #define RMIXL_FMN_BS_PCIE_TX2 _RMIXL_OFFSET(0x324) 1796 #define RMIXL_FMN_BS_PCIE_RX2 _RMIXL_OFFSET(0x325) 1797 #define RMIXL_FMN_BS_PCIE_TX3 _RMIXL_OFFSET(0x326) 1798 #define RMIXL_FMN_BS_PCIE_RX3 _RMIXL_OFFSET(0x327) 1799 1800 /* 1801 * non-core Credit Counter offsets 1802 */ 1803 #define RMIXL_FMN_CC_FIRST _RMIXL_OFFSET(0x380) 1804 #define RMIXL_FMN_CC_LAST _RMIXL_OFFSET(0x3ff) 1805 1806 /* 1807 * non-core Credit Counter bit defines 1808 */ 1809 #define RMIXL_FMN_CC_RESV __BITS(31,8) 1810 #define RMIXL_FMN_CC_COUNT __BITS(7,0) 1811 1812 #endif /* _MIPS_RMI_RMIXLREG_H_ */ 1813
Indexes created Sat Oct 25 16:10:12 GMT 2025