rmixlreg.h revision 1.1.2.21
1 /* rmixlreg.h,v 1.1.2.20 2012/01/19 08:06:54 matt Exp */ 2 3 /*- 4 * Copyright (c) 2009 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Cliff Neighbors 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 33 #ifndef _MIPS_RMI_RMIXLREG_H_ 34 #define _MIPS_RMI_RMIXLREG_H_ 35 36 #include <sys/endian.h> 37 38 /* 39 * on chip I/O register byte order is 40 * BIG ENDIAN regardless of code model 41 */ 42 #define RMIXL_IOREG_VADDR(o) \ 43 (volatile uint32_t *)MIPS_PHYS_TO_KSEG1( \ 44 rmixl_configuration.rc_io.r_pbase + (o)) 45 #define RMIXL_IOREG_READ(o) be32toh(*RMIXL_IOREG_VADDR(o)) 46 #define RMIXL_IOREG_WRITE(o,v) *RMIXL_IOREG_VADDR(o) = htobe32(v) 47 48 49 /* 50 * RMIXL Coprocessor 2 registers: 51 */ 52 #ifdef _LOCORE 53 #define _(n) __CONCAT($,n) 54 #else 55 #define _(n) n 56 #endif 57 /* 58 * Note CP2 FMN register scope or "context" 59 * L : Local : per thread register 60 * G : Global : per FMN Station (per core) register 61 * L/G : "partly global" : ??? 62 * Global regs should be managed by a single thread 63 * (see XLS PRM "Coprocessor 2 Register Summary") 64 */ 65 /* context ---------------+ */ 66 /* #sels --------------+ | */ 67 /* #regs -----------+ | | */ 68 /* What: #bits --+ | | | */ 69 /* v v v v */ 70 #define RMIXL_COP_2_TXBUF _(0) /* Transmit Buffers 64 [1][4] L */ 71 #define RMIXL_COP_2_RXBUF _(1) /* Receive Buffers 64 [1][4] L */ 72 #define RMIXL_COP_2_MSG_STS _(2) /* Mesage Status 32 [1][2] L/G */ 73 #define RMIXL_COP_2_MSG_CFG _(3) /* Message Config 32 [1][2] G */ 74 #define RMIXL_COP_2_MSG_BSZ _(4) /* Message Bucket Size 32 [1][8] G */ 75 #define RMIXL_COP_2_CREDITS _(16) /* Credit Counters 8 [16][8] G */ 76 77 #define RMIXLP_COP_2_MSG_TX_STS _(2) /* Tx Mesage Status 32 [1][1] L */ 78 #define RMIXLP_COP_2_MSG_RX_STS _(3) /* Rx Mesage Status 32 [1][1] L */ 79 #define RMIXLP_COP_2_MSG_STS1 _(4) /* Mesage Queue Status 32 [1][1] G */ 80 #define RMIXLP_COP_2_MSG_CFG _(5) /* Mesage Intr Config 32 [1][1] L */ 81 #define RMIXLP_COP_2_MSG_ERR _(6) /* Mesage Error 32 [1][4] G */ 82 #define RMIXLP_COP_2_CREDITS _(9) /* Output/Input Credits 64/32 [1][2] G */ 83 84 /* 85 * MsgStatus: RMIXL_COP_2_MSG_STS (CP2 Reg 2, Select 0) bits 86 */ 87 #define RMIXL_MSG_STS0_RFBE __BITS(31,24) /* RX FIFO Buckets bit mask 88 * 0=not empty 89 * 1=empty 90 */ 91 #define RMIXL_MSG_STS0_RESV __BIT(23) 92 #define RMIXL_MSG_STS0_RMSID __BITS(22,16) /* Source ID */ 93 #define RMIXL_MSG_STS0_RMSC __BITS(15,8) /* RX Message Software Code */ 94 #define RMIXL_MSG_STS0_RMS __BITS(7,6) /* RX Message Size (minus 1) */ 95 #define RMIXL_MSG_STS0_LEF __BIT(5) /* Load Empty Fail */ 96 #define RMIXL_MSG_STS0_LPF __BIT(4) /* Load Pending Fail */ 97 #define RMIXL_MSG_STS0_LMP __BIT(3) /* Load Message Pending */ 98 #define RMIXL_MSG_STS0_SCF __BIT(2) /* Send Credit Fail */ 99 #define RMIXL_MSG_STS0_SPF __BIT(1) /* Send Pending Fail */ 100 #define RMIXL_MSG_STS0_SMP __BIT(0) /* Send Message Pending */ 101 #define RMIXL_MSG_STS0_ERRS \ 102 (RMIXL_MSG_STS0_LEF|RMIXL_MSG_STS0_LPF|RMIXL_MSG_STS0_LMP \ 103 |RMIXL_MSG_STS0_SCF|RMIXL_MSG_STS0_SPF|RMIXL_MSG_STS0_SMP) 104 105 /* 106 * MsgStatus1: RMIXL_COP_2_MSG_STS (CP2 Reg 2, Select 1) bits 107 */ 108 #define RMIXL_MSG_STS1_RESV __BIT(31) 109 #define RMIXL_MSG_STS1_C __BIT(30) /* Credit Overrun Error */ 110 #define RMIXL_MSG_STS1_CCFCME __BITS(29,23) /* Credit Counter of Free Credit Message with Error */ 111 #define RMIXL_MSG_STS1_SIDFCME __BITS(22,16) /* Source ID of Free Credit Message with Error */ 112 #define RMIXL_MSG_STS1_T __BIT(15) /* Invalid Target Error */ 113 #define RMIXL_MSG_STS1_F __BIT(14) /* Receive Queue "Write When Full" Error */ 114 #define RMIXL_MSG_STS1_SIDE __BITS(13,7) /* Source ID of incoming msg with Error */ 115 #define RMIXL_MSG_STS1_DIDE __BITS(6,0) /* Destination ID of the incoming message Message with Error */ 116 #define RMIXL_MSG_STS1_ERRS \ 117 (RMIXL_MSG_STS1_C|RMIXL_MSG_STS1_T|RMIXL_MSG_STS1_F) 118 119 /* 120 * MsgConfig: RMIXL_COP_2_MSG_CFG (CP2 Reg 3, Select 0) bits 121 */ 122 #define RMIXL_MSG_CFG0_WM __BITS(31,24) /* Watermark level */ 123 #define RMIXL_MSG_CFG0_RESa __BITS(23,22) 124 #define RMIXL_MSG_CFG0_IV __BITS(21,16) /* Interrupt Vector */ 125 #define RMIXL_MSG_CFG0_RESb __BITS(15,12) 126 #define RMIXL_MSG_CFG0_ITM __BITS(11,8) /* Interrupt Thread Mask */ 127 #define RMIXL_MSG_CFG0_RESc __BITS(7,2) 128 #define RMIXL_MSG_CFG0_WIE __BIT(1) /* Watermark Interrupt Enable */ 129 #define RMIXL_MSG_CFG0_EIE __BIT(0) /* Receive Queue Not Empty Enable */ 130 #define RMIXL_MSG_CFG0_RESV \ 131 (RMIXL_MSG_CFG0_RESa|RMIXL_MSG_CFG0_RESb|RMIXL_MSG_CFG0_RESc) 132 133 /* 134 * MsgConfig1: RMIXL_COP_2_MSG_CFG (CP2 Reg 3, Select 1) bits 135 * Note: reg width is 64 bits in PRM reg description, but 32 bits in reg summary 136 */ 137 #define RMIXL_MSG_CFG1_RESV __BITS(63,3) 138 #define RMIXL_MSG_CFG1_T __BIT(2) /* Trace Mode Enable */ 139 #define RMIXL_MSG_CFG1_C __BIT(1) /* Credit Over-run Interrupt Enable */ 140 #define RMIXL_MSG_CFG1_M __BIT(0) /* Messaging Errors Interrupt Enable */ 141 142 143 /* 144 * MsgBucketSize: RMIXL_COP_2_MSG_BSZ (CP2 Reg 4, Select [0..7]) bits 145 * Note: reg width is 64 bits in PRM reg description, but 32 bits in reg summary 146 * Size: 147 * - 0 means bucket disabled, else 148 * - must be power of 2 149 * - must be >=4 150 */ 151 #define RMIXL_MSG_BSZ_RESV __BITS(63,8) 152 #define RMIXL_MSG_BSZ_SIZE __BITS(7,0) 153 154 /* 155 * RMIXLP COP0 Registers 156 */ 157 #define RMIXLP_MSG_TX_STS_TQF __BIT(24) // Transmit Queue Full 158 #define RMIXLP_MSG_TX_STS_DCF __BITS(19,4) // Destination Flow Control Count 159 #define RMIXLP_MSG_TX_STS_DFCF __BIT(3) // ECC error during OQ credit read 160 #define RMIXLP_MSG_TX_STS_PS __BIT(2) // Failed for Pending Synchronization 161 #define RMIXLP_MSG_TX_STS_IQC __BIT(1) // Insufficient input queue credits 162 #define RMIXLP_MSG_TX_STS_OQC __BIT(0) // Insufficient output queue credits 163 164 #define RMIXLP_MSG_RX_STS_RXQVCE __BITS(31,28) // Receive Queue VC[0-3] Empty. 165 #define RMIXLP_MSG_RX_STS_RXQVC3E __BIT(31) // Receive Queue VC[3] Empty. 166 #define RMIXLP_MSG_RX_STS_RXQVC2E __BIT(30) // Receive Queue VC[2] Empty. 167 #define RMIXLP_MSG_RX_STS_RXQVC1E __BIT(29) // Receive Queue VC[1] Empty. 168 #define RMIXLP_MSG_RX_STS_RXQVC0E __BIT(28) // Receive Queue VC[0] Empty. 169 #define RMIXLP_MSG_RX_STS_SM1 __BITS(27,26) // Receive message Size (DW) Minus 1 170 #define RMIXLP_MSG_RX_STS_SC __BITS(25,18) // Software Code sent by the MSGSND 171 #define RMIXLP_MSG_RX_STS_MLFE __BIT(17) // MSGLD ECC fatal error 172 #define RMIXLP_MSG_RX_STS_SID __BITS(15,4) // Source ID of the sending station. 173 #define RMIXLP_MSG_RX_STS_PRF __BIT(1) // 1: MSGLD Pop Request Failure 174 #define RMIXLP_MSG_RX_STS_LMEF __BIT(0) // 1: MSGLD Fail 175 176 #define RMIXLP_MSG_STS1_VCE __BITS(27,24) // VCE[3:0] indicates the active status of VC[3:0], where a bit set to 1 indicates the corresponding VC is empty. 177 #define RMIXLP_MSG_STS1_RWF __BIT(23) // CPU Receive Queue Written when Full (if set to 1). 178 #define RMIXLP_MSG_STS1_ICO __BIT(22) // FMN Input Credit Overflow hardware error. Message source queue ID unusable. 179 #define RMIXLP_MSG_STS1_OCO __BIT(21) // FMN Output Credit Overflow hardware error. Message destination queue ID unusable. 180 #define RMIXLP_MSG_STS1_ME __BIT(20) // 1: Message Error 181 #define RMIXLP_MSG_STS1_VC_PEND __BITS(19,16) // Interrupt pending for vectors 0 to 3 on a thread. Once the message is asserted, a bit corresponding to the VC is cleared by hardware. Software must set this bit once the message is handled; else no further interrupts would be generated for this VC. 182 #define RMIXLP_MSG_STS1_MSGSTA __BIT(12) // During the output queue credit return process, if a single or multi bit ECC error happens in the COP2 RAM, then COP2 sets the MSGSTA bit of each thread. Msgsnd from any thread will check respective MSGSTA and it fails the msgsnd if it is set to 1. The MSGSTA bit of each thread must be cleared by a system reset or MTC2 instruction before the next msgsnd successfully executes. 183 #define RMIXLP_MSG_STS1_OQID __BITS(11,0) // Output Queue ID that caused the OCO field to be set. 184 185 #define RMIXLP_MSG_CFG_INTVEC __BITS(21,16) // Interrupt Vector Number 186 #define RMIXLP_MSG_CFG_ECC_EN __BIT(8) // Enabled COP2 Output Queue RAM ECC 187 #define RMIXLP_MSG_CFG_VC3POP_EN __BIT(4) // 1: VC3 Pop Msg Request Mode Enable 188 #define RMIXLP_MSG_CFG_VC2POP_EN __BIT(3) // 1: VC2 Pop Msg Request Mode Enable 189 #define RMIXLP_MSG_CFG_VC1POP_EN __BIT(2) // 1: VC1 Pop Msg Request Mode Enable 190 #define RMIXLP_MSG_CFG_VC0POP_EN __BIT(1) // 1: VC0 Pop Msg Request Mode Enable 191 #define RMIXLP_MSG_CFG_VCPOP_EN(n) __BIT(1+(n)) // 1: VCn Pop Msg Request Mode Enable 192 193 #define RMIXLP_MSG_IQ_CNT_STS_T3POPQ __BITS(31,28) // PopQ credit available for thread 3 194 #define RMIXLP_MSG_IQ_CNT_STS_T2POPQ __BITS(27,24) // PopQ credit available for thread 2 195 #define RMIXLP_MSG_IQ_CNT_STS_T1POPQ __BITS(23,20) // PopQ credit available for thread 1 196 #define RMIXLP_MSG_IQ_CNT_STS_T0POPQ __BITS(19,16) // PopQ credit available for thread 0 197 #define RMIXLP_MSG_IQ_CNT_STS_TPOPQ(n) __BITS(19+4*(n),16+4*(n)) 198 #define RMIXLP_MSG_IQ_CNT_STS_T3PUSHQ __BITS(15,12) // PushQ credit available for thread 3 199 #define RMIXLP_MSG_IQ_CNT_STS_T2PUSHQ __BITS(11, 8) // PushQ credit available for thread 2 200 #define RMIXLP_MSG_IQ_CNT_STS_T1PUSHQ __BITS( 7, 4) // PushQ credit available for thread 1 201 #define RMIXLP_MSG_IQ_CNT_STS_T0PUSHQ __BITS( 3, 0) // PushQ credit available for thread 0 202 #define RMIXLP_MSG_IQ_CNT_STS_TPUSHQ(n) __BITS( 3+4*(n), 0+4*(n)) 203 204 /* 205 * RMIXL Processor Control Register addresses 206 * - Offset in bits 7..0 207 * - BlockID in bits 15..8 208 */ 209 #define RMIXL_PCR_THREADEN 0x0000 210 #define RMIXL_PCR_SOFTWARE_SLEEP 0x0001 211 #define RMIXL_PCR_SCHEDULING 0x0002 212 #define RMIXL_PCR_SCHEDULING_COUNTERS 0x0003 213 #define RMIXL_PCR_BHRPM 0x0004 214 #define RMIXL_PCR_IFU_DEFEATURE 0x0006 215 #define RMIXL_PCR_ICU_DEFEATURE 0x0100 216 #define RMIXL_PCR_ICU_ERROR_LOGGING 0x0101 217 #define RMIXL_PCR_ICU_DEBUG_ACCESS_ADDR 0x0102 218 #define RMIXL_PCR_ICU_DEBUG_ACCESS_DATALO 0x0103 219 #define RMIXL_PCR_ICU_DEBUG_ACCESS_DATAHI 0x0104 220 #define RMIXL_PCR_ICU_SAMPLING_LFSR 0x0105 221 #define RMIXL_PCR_ICU_SAMPLING_PC 0x0106 222 #define RMIXL_PCR_ICU_SAMPLING_SETUP 0x0107 223 #define RMIXL_PCR_ICU_SAMPLING_TIMER 0x0108 224 #define RMIXL_PCR_ICU_SAMPLING_PC_UPPER 0x0109 225 #define RMIXL_PCR_IEU_DEFEATURE 0x0200 226 #define RMIXL_PCR_TARGET_PC_REGISTER 0x0207 227 #define RMIXL_PCR_L1D_CONFIG0 0x0300 228 #define RMIXL_PCR_L1D_CONFIG1 0x0301 229 #define RMIXL_PCR_L1D_CONFIG2 0x0302 230 #define RMIXL_PCR_L1D_CONFIG3 0x0303 231 #define RMIXL_PCR_L1D_CONFIG4 0x0304 232 #define RMIXL_PCR_L1D_STATUS 0x0305 233 #define RMIXL_PCR_L1D_DEFEATURE 0x0306 234 #define RMIXL_PCR_L1D_DEBUG0 0x0307 235 #define RMIXL_PCR_L1D_DEBUG1 0x0308 236 #define RMIXL_PCR_L1D_CACHE_ERROR_LOG 0x0309 237 #define RMIXL_PCR_L1D_CACHE_ERROR_OVF_LO 0x030A 238 #define RMIXL_PCR_L1D_CACHE_INTERRUPT 0x030B 239 #define RMIXL_PCR_MMU_SETUP 0x0400 240 #define RMIXL_PCR_PRF_SMP_EVENT 0x0500 241 #define RMIXL_PCR_RF_SMP_RPLY_BUF 0x0501 242 243 /* PCR bit defines TBD */ 244 245 /* XLP Instruction Fetch Unit Registers */ 246 #define RMIXLP_PCR_IFU_THREAD_EN 0x0000 247 #define RMIXLP_PCR_IFU_SW_SLEEP 0x0001 248 #define RMIXLP_PCR_IFU_THREAD_SCHED_MODE 0x0002 249 #define RMIXLP_PCR_IFU_THREAD_SCHED_COUNTER 0x0003 250 #define RMIXLP_PCR_IFU_BHR_PROG_MASK 0x0004 251 #define RMIXLP_PCR_IFU_SLEEP_STATE 0x0006 252 #define RMIXLP_PCR_IFU_BRUB_RESERVE 0x0007 253 254 /* XLP Instruction Cache Unit Registers */ 255 #define RMIXLP_PCR_ICU_DEFEATURE 0x0100 256 #define RMIXLP_PCR_ICU_CACHE_ERR_INT 0x0101 /* RW1C */ 257 #define RMIXLP_PCR_ICU_ERR_LOG0 0x0110 258 #define RMIXLP_PCR_ICU_ERR_LOG1 0x0111 259 #define RMIXLP_PCR_ICU_ERR_LOG2 0x0112 260 #define RMIXLP_PCR_ICU_ERR_INJECT0 0x0113 261 #define RMIXLP_PCR_ICU_ERR_INJECT1 0x0114 262 263 /* XLP Load Store Unit Registers */ 264 #define RMIXLP_PCR_LSU_CONFIG0 0x0300 265 #define RMIXLP_PCR_LSU_CONFIG1 0x0301 266 #define RMIXLP_PCR_LSU_DEFEATURE 0x0304 267 #define RMIXLP_PCR_LSU_DEBUG_ADDR 0x0305 268 #define RMIXLP_PCR_LSU_DEBUG_DATA 0x0306 269 #define RMIXLP_PCR_LSU_CERR_LOG0 0x0308 270 #define RMIXLP_PCR_LSU_CERR_LOG1 0x0309 271 #define RMIXLP_PCR_LSU_CERR_INJ0 0x030a 272 #define RMIXLP_PCR_LSU_CERR_INJ1 0x030b 273 #define RMIXLP_PCR_LSU_CERR_INT 0x030c 274 275 #define RMIXLP_PCR_LSE_DEFEATURE_EUL __BIT(30) 276 277 /* XLP MMU Registers */ 278 #define RMIXLP_PCR_MMU_SETUP 0x0400 279 #define RMIXLP_PCR_LFSRSEED 0x0401 280 #define RMIXLP_PCR_HPW_NUM_PAGE_LVL 0x0410 281 #define RMIXLP_PCR_PGWKR_PGDBASE 0x0411 282 #define RMIXLP_PCR_PGWKR_PGDSHIFT 0x0412 283 #define RMIXLP_PCR_PGWKR_PGDMASK 0x0413 284 #define RMIXLP_PCR_PGWKR_PUDSHIFT 0x0414 285 #define RMIXLP_PCR_PGWKR_PUDMASK 0x0415 286 #define RMIXLP_PCR_PGWKR_PMDSHIFT 0x0416 287 #define RMIXLP_PCR_PGWKR_PMDMASK 0x0417 288 #define RMIXLP_PCR_PGWKR_PTESHIFT 0x0418 289 #define RMIXLP_PCR_PGWKR_PTEMASK 0x0419 290 291 #define RMIXLP_PCR_MMU_SETUP_CACHEOFF __BIT(14) 292 #define RMIXLP_PCR_MMU_SETUP_HASHFUNCTIONEN __BIT(13) 293 #define RMIXLP_PCR_MMU_SETUP_XLP1PTESTYLE __BIT(4) 294 #define RMIXLP_PCR_MMU_SETUP_2XX_EET __BIT(3) 295 #define RMIXLP_PCR_MMU_SETUP_LOCCLKGATE __BIT(3) 296 #define RMIXLP_PCR_MMU_SETUP_TLB_GLOBAL __BIT(0) 297 #define RMIXLP_PCR_PGWKR_PxxSHIFT_MASK __BITS(5,0) 298 #define RMIXLP_PCR_PGWKR_PxxMASK_MASK __BITS(31,0) 299 300 /* XLP L2 Cache Registers */ 301 #define RMIXLP_PCR_L2_FTR_CTL0 0x800 302 #define RMIXLP_PCR_L2_FTR_CTL1 0x801 303 #define RMIXLP_PCR_L2_CRERR_INT_VID 0x802 304 #define RMIXLP_PCR_L2_DIS_WAY 0x803 305 #define RMIXLP_PCR_L2_ERR_LOG0 0x810 306 #define RMIXLP_PCR_L2_ERR_LOG1 0x811 307 #define RMIXLP_PCR_L2_ERR_LOG2 0x812 308 #define RMIXLP_PCR_L2_ERR_INJ0 0x813 309 #define RMIXLP_PCR_L2_ERR_INJ1 0x814 310 311 /* XLP Mapping Unit Registers */ 312 #define RMIXLP_PCR_MAP_T0_LRQ_MASK 0x0602 313 #define RMIXLP_PCR_MAP_T1_LRQ_MASK 0x0603 314 #define RMIXLP_PCR_MAP_T2_LRQ_MASK 0x0604 315 #define RMIXLP_PCR_MAP_T3_LRQ_MASK 0x0605 316 #define RMIXLP_PCR_MAP_T0_SRQ_MASK 0x0606 317 #define RMIXLP_PCR_MAP_T1_SRQ_MASK 0x0607 318 #define RMIXLP_PCR_MAP_T2_SRQ_MASK 0x0608 319 #define RMIXLP_PCR_MAP_T3_SRQ_MASK 0x0609 320 #define RMIXLP_PCR_MAP_THREAD_MODE 0x0a00 321 #define RMIXLP_PCR_MAP_EXT_EBASE_ENABLE 0x0a02 322 #define RMIXLP_PCR_MAP_CCD_CONFIG 0x0a02 323 #define RMIXLP_PCR_MAP_T0_DEBUG_MODE 0x0a03 324 #define RMIXLP_PCR_MAP_T1_DEBUG_MODE 0x0a04 325 #define RMIXLP_PCR_MAP_T2_DEBUG_MODE 0x0a05 326 #define RMIXLP_PCR_MAP_T3_DEBUG_MODE 0x0a06 327 #define RMIXLP_PCR_MAP_THREAD_STATE 0x0a10 328 #define RMIXLP_PCR_MAP_T0_CCD_STATUS 0x0a11 329 #define RMIXLP_PCR_MAP_T1_CCD_STATUS 0x0a12 330 #define RMIXLP_PCR_MAP_T2_CCD_STATUS 0x0a13 331 #define RMIXLP_PCR_MAP_T3_CCD_STATUS 0x0a14 332 333 /* 334 * Memory Distributed Interconnect (MDI) System Memory Map 335 */ 336 #define RMIXL_PHYSADDR_MAX 0xffffffffffLL /* 1TB Physical Address space */ 337 #define RMIXL_IO_DEV_PBASE 0x1ef00000 /* default phys. from XL[RS]_IO_BAR */ 338 #define RMIXL_IO_DEV_VBASE MIPS_PHYS_TO_KSEG1(RMIXL_IO_DEV_PBASE) 339 /* default virtual base address */ 340 #define RMIXL_IO_DEV_SIZE 0x100000 /* I/O Conf. space is 1MB region */ 341 342 343 344 /* 345 * Peripheral and I/O Configuration Region of Memory 346 * 347 * These are relocatable; we run using the reset value defaults, 348 * and we expect to inherit those intact from the boot firmware. 349 * 350 * Many of these overlap between XLR and XLS, exceptions are ifdef'ed. 351 * 352 * Device region offsets are relative to RMIXL_IO_DEV_PBASE. 353 */ 354 #define RMIXL_IO_DEV_BRIDGE 0x00000 /* System Bridge Controller (SBC) */ 355 #define RMIXL_IO_DEV_DDR_CHNA 0x01000 /* DDR1/DDR2 DRAM_A Channel, Port MA */ 356 #define RMIXL_IO_DEV_DDR_CHNB 0x02000 /* DDR1/DDR2 DRAM_B Channel, Port MB */ 357 #define RMIXL_IO_DEV_DDR_CHNC 0x03000 /* DDR1/DDR2 DRAM_C Channel, Port MC */ 358 #define RMIXL_IO_DEV_DDR_CHND 0x04000 /* DDR1/DDR2 DRAM_D Channel, Port MD */ 359 #if defined(MIPS64_XLR) 360 #define RMIXL_IO_DEV_SRAM 0x07000 /* SRAM Controller, Port SA */ 361 #endif /* MIPS64_XLR */ 362 #define RMIXL_IO_DEV_PIC 0x08000 /* Programmable Interrupt Controller */ 363 #if defined(MIPS64_XLR) 364 #define RMIXL_IO_DEV_PCIX 0x09000 /* PCI-X */ 365 #define RMIXL_IO_DEV_PCIX_EL \ 366 RMIXL_IO_DEV_PCIX /* PXI-X little endian */ 367 #define RMIXL_IO_DEV_PCIX_EB \ 368 (RMIXL_IO_DEV_PCIX | __BIT(11)) /* PXI-X big endian */ 369 #define RMIXL_IO_DEV_HT 0x0a000 /* HyperTransport */ 370 #endif /* MIPS64_XLR */ 371 #define RMIXL_IO_DEV_SAE 0x0b000 /* Security Acceleration Engine */ 372 #if defined(MIPS64_XLS) 373 #define XAUI_INTERFACE_0 0x0c000 /* XAUI Interface_0 */ 374 /* when SGMII Interface_[0-3] are not used */ 375 #define RMIXL_IO_DEV_GMAC_0 0x0c000 /* SGMII-Interface_0, Port SGMII0 */ 376 #define RMIXL_IO_DEV_GMAC_1 0x0d000 /* SGMII-Interface_1, Port SGMII1 */ 377 #define RMIXL_IO_DEV_GMAC_2 0x0e000 /* SGMII-Interface_2, Port SGMII2 */ 378 #define RMIXL_IO_DEV_GMAC_3 0x0f000 /* SGMII-Interface_3, Port SGMII3 */ 379 #endif /* MIPS64_XLS */ 380 #if defined(MIPS64_XLR) 381 #define RMIXL_IO_DEV_GMAC_A 0x0c000 /* RGMII-Interface_0, Port RA */ 382 #define RMIXL_IO_DEV_GMAC_B 0x0d000 /* RGMII-Interface_1, Port RB */ 383 #define RMIXL_IO_DEV_GMAC_C 0x0e000 /* RGMII-Interface_2, Port RC */ 384 #define RMIXL_IO_DEV_GMAC_D 0x0f000 /* RGMII-Interface_3, Port RD */ 385 #define RMIXL_IO_DEV_SPI4_A 0x10000 /* SPI-4.2-Interface_A, Port XA */ 386 #define RMIXL_IO_DEV_XGMAC_A 0x11000 /* XGMII-Interface_A, Port XA */ 387 #define RMIXL_IO_DEV_SPI4_B 0x12000 /* SPI-4.2-Interface_B, Port XB */ 388 #define RMIXL_IO_DEV_XGMAC_B 0x13000 /* XGMII-Interface_B, Port XB */ 389 #endif /* MIPS64_XLR */ 390 #define RMIXL_IO_DEV_UART_1 0x14000 /* UART_1 (16550 w/ ax4 addrs) */ 391 #define RMIXL_IO_DEV_UART_2 0x15000 /* UART_2 (16550 w/ ax4 addrs) */ 392 #define RMIXL_IO_DEV_I2C_1 0x16000 /* I2C_1 */ 393 #define RMIXL_IO_DEV_I2C_2 0x17000 /* I2C_2 */ 394 #define RMIXL_IO_DEV_GPIO 0x18000 /* GPIO */ 395 #define RMIXL_IO_DEV_FLASH 0x19000 /* Flash ROM */ 396 #define RMIXL_IO_DEV_DMA 0x1a000 /* DMA */ 397 #define RMIXL_IO_DEV_L2 0x1b000 /* L2 Cache */ 398 #define RMIXL_IO_DEV_TB 0x1c000 /* Trace Buffer */ 399 #if defined(MIPS64_XLS) 400 #define RMIXL_IO_DEV_CDE 0x1d000 /* Compression/Decompression Engine */ 401 #define RMIXL_IO_DEV_PCIE_BE 0x1e000 /* PCI-Express_BE */ 402 #define RMIXL_IO_DEV_PCIE_LE 0x1f000 /* PCI-Express_LE */ 403 #define RMIXL_IO_DEV_SRIO_BE 0x1e000 /* SRIO_BE */ 404 #define RMIXL_IO_DEV_SRIO_LE 0x1f000 /* SRIO_LE */ 405 #define RMIXL_IO_DEV_XAUI_1 0x20000 /* XAUI Interface_1 */ 406 /* when SGMII Interface_[4-7] are not used */ 407 #define RMIXL_IO_DEV_GMAC_4 0x20000 /* SGMII-Interface_4, Port SGMII4 */ 408 #define RMIXL_IO_DEV_GMAC_5 0x21000 /* SGMII-Interface_5, Port SGMII5 */ 409 #define RMIXL_IO_DEV_GMAC_6 0x22000 /* SGMII-Interface_6, Port SGMII6 */ 410 #define RMIXL_IO_DEV_GMAC_7 0x23000 /* SGMII-Interface_7, Port SGMII7 */ 411 #define RMIXL_IO_DEV_USB_A 0x24000 /* USB Interface Low Address Space */ 412 #define RMIXL_IO_DEV_USB_B 0x25000 /* USB Interface High Address Space */ 413 #endif /* MIPS64_XLS */ 414 415 416 /* 417 * the Programming Reference Manual 418 * lists "Reg ID" values not offsets; 419 * offset = id * 4 420 */ 421 #define _RMIXL_OFFSET(id) ((id) * 4) 422 #define _RMIXL_PCITAG(b,d,f) ((((((b) << 5) | (d)) << 3) | (f)) << 12) 423 #define _RMIXL_PCITAG_BUS(t) (((t) >> 20) & 255) 424 #define _RMIXL_PCITAG_DEV(t) (((t) >> 15) & 31) 425 #define _RMIXL_PCITAG_FUNC(t) (((t) >> 12) & 7) 426 #define _RMIXL_PCITAG_OFFSET(t) (((t) >> 0) & 4095) 427 428 429 /* 430 * System Bridge Controller registers 431 * offsets are relative to RMIXL_IO_DEV_BRIDGE 432 */ 433 #define RMIXL_SBC_DRAM_NBARS 8 434 #define RMIXL_SBC_DRAM_BAR(n) _RMIXL_OFFSET(0x000 + (n)) 435 /* DRAM Region Base Address Regs[0-7] */ 436 #define RMIXL_SBC_DRAM_CHNAC_DTR(n) _RMIXL_OFFSET(0x008 + (n)) 437 /* DRAM Region Channels A,C Address Translation Regs[0-7] */ 438 #define RMIXL_SBC_DRAM_CHNBD_DTR(n) _RMIXL_OFFSET(0x010 + (n)) 439 /* DRAM Region Channels B,D Address Translation Regs[0-7] */ 440 #define RMIXL_SBC_DRAM_BRIDGE_CFG _RMIXL_OFFSET(0x18) /* SBC DRAM config reg */ 441 #define RMIXL_SBC_IO_BAR _RMIXL_OFFSET(0x19) /* I/O Config Base Addr reg */ 442 #define RMIXL_SBC_FLASH_BAR _RMIXL_OFFSET(0x1a) /* Flash Memory Base Addr reg */ 443 #if defined(MIPS64_XLR) 444 #define RMIXLR_SBC_SRAM_BAR _RMIXL_OFFSET(0x1b) /* SRAM Base Addr reg */ 445 #define RMIXLR_SBC_HTMEM_BAR _RMIXL_OFFSET(0x1c) /* HyperTransport Mem Base Addr reg */ 446 #define RMIXLR_SBC_HTINT_BAR _RMIXL_OFFSET(0x1d) /* HyperTransport Interrupt Base Addr reg */ 447 #define RMIXLR_SBC_HTPIC_BAR _RMIXL_OFFSET(0x1e) /* HyperTransport Legacy PIC Base Addr reg */ 448 #define RMIXLR_SBC_HTSM_BAR _RMIXL_OFFSET(0x1f) /* HyperTransport System Management Base Addr reg */ 449 #define RMIXLR_SBC_HTIO_BAR _RMIXL_OFFSET(0x20) /* HyperTransport IO Base Addr reg */ 450 #define RMIXLR_SBC_HTCFG_BAR _RMIXL_OFFSET(0x21) /* HyperTransport Configuration Base Addr reg */ 451 #define RMIXLR_SBC_PCIX_CFG_BAR _RMIXL_OFFSET(0x22) /* PCI-X Configuration Base Addr reg */ 452 #define RMIXLR_SBC_PCIX_MEM_BAR _RMIXL_OFFSET(0x23) /* PCI-X Mem Base Addr reg */ 453 #define RMIXLR_SBC_PCIX_IO_BAR _RMIXL_OFFSET(0x24) /* PCI-X IO Base Addr reg */ 454 #define RMIXLR_SBC_SYS2IO_CREDITS _RMIXL_OFFSET(0x35) /* System Bridge I/O Transaction Credits register */ 455 #endif /* MIPS64_XLR */ 456 #if defined(MIPS64_XLS) 457 #define RMIXLS_SBC_PCIE_CFG_BAR _RMIXL_OFFSET(0x40) /* PCI Configuration BAR */ 458 #define RMIXLS_SBC_PCIE_ECFG_BAR _RMIXL_OFFSET(0x41) /* PCI Extended Configuration BAR */ 459 #define RMIXLS_SBC_PCIE_MEM_BAR _RMIXL_OFFSET(0x42) /* PCI Memory region BAR */ 460 #define RMIXLS_SBC_PCIE_IO_BAR _RMIXL_OFFSET(0x43) /* PCI IO region BAR */ 461 #endif /* MIPS64_XLS */ 462 463 /* 464 * Address Error registers 465 * offsets are relative to RMIXL_IO_DEV_BRIDGE 466 */ 467 #define RMIXL_ADDR_ERR_DEVICE_MASK _RMIXL_OFFSET(0x25) /* Address Error Device Mask */ 468 #define RMIXL_ADDR_ERR_DEVICE_MASK_2 _RMIXL_OFFSET(0x44) /* extension of Device Mask */ 469 #define RMIXL_ADDR_ERR_AERR0_LOG1 _RMIXL_OFFSET(0x26) /* Address Error Set 0 Log 1 */ 470 #define RMIXL_ADDR_ERR_AERR0_LOG2 _RMIXL_OFFSET(0x27) /* Address Error Set 0 Log 2 */ 471 #define RMIXL_ADDR_ERR_AERR0_LOG3 _RMIXL_OFFSET(0x28) /* Address Error Set 0 Log 3 */ 472 #define RMIXL_ADDR_ERR_AERR0_DEVSTAT _RMIXL_OFFSET(0x29) /* Address Error Set 0 irpt status */ 473 #define RMIXL_ADDR_ERR_AERR1_LOG1 _RMIXL_OFFSET(0x2a) /* Address Error Set 1 Log 1 */ 474 #define RMIXL_ADDR_ERR_AERR1_LOG2 _RMIXL_OFFSET(0x2b) /* Address Error Set 1 Log 2 */ 475 #define RMIXL_ADDR_ERR_AERR1_LOG3 _RMIXL_OFFSET(0x2c) /* Address Error Set 1 Log 3 */ 476 #define RMIXL_ADDR_ERR_AERR1_DEVSTAT _RMIXL_OFFSET(0x2d) /* Address Error Set 1 irpt status */ 477 #define RMIXL_ADDR_ERR_AERR0_EN _RMIXL_OFFSET(0x2e) /* Address Error Set 0 irpt enable */ 478 #define RMIXL_ADDR_ERR_AERR0_UPG _RMIXL_OFFSET(0x2f) /* Address Error Set 0 Upgrade */ 479 #define RMIXL_ADDR_ERR_AERR0_CLEAR _RMIXL_OFFSET(0x30) /* Address Error Set 0 irpt clear */ 480 #define RMIXL_ADDR_ERR_AERR1_CLEAR _RMIXL_OFFSET(0x31) /* Address Error Set 1 irpt clear */ 481 #define RMIXL_ADDR_ERR_SBE_COUNTS _RMIXL_OFFSET(0x32) /* Single Bit Error Counts */ 482 #define RMIXL_ADDR_ERR_DBE_COUNTS _RMIXL_OFFSET(0x33) /* Double Bit Error Counts */ 483 #define RMIXL_ADDR_ERR_BITERR_INT_EN _RMIXL_OFFSET(0x33) /* Bit Error intr enable */ 484 485 /* 486 * RMIXL_SBC_FLASH_BAR bit defines 487 */ 488 #define RMIXL_FLASH_BAR_BASE __BITS(31,16) /* phys address bits 39:24 */ 489 #define RMIXL_FLASH_BAR_TO_BA(r) \ 490 (((r) & RMIXL_FLASH_BAR_BASE) << (24 - 16)) 491 #define RMIXL_FLASH_BAR_MASK __BITS(15,5) /* phys address mask bits 34:24 */ 492 #define RMIXL_FLASH_BAR_TO_MASK(r) \ 493 (((((r) & RMIXL_FLASH_BAR_MASK)) << (24 - 5)) | __BITS(23, 0)) 494 #define RMIXL_FLASH_BAR_RESV __BITS(4,1) /* (reserved) */ 495 #define RMIXL_FLASH_BAR_ENB __BIT(0) /* 1=Enable */ 496 #define RMIXL_FLASH_BAR_MASK_MAX RMIXL_FLASH_BAR_TO_MASK(RMIXL_FLASH_BAR_MASK) 497 498 /* 499 * RMIXL_SBC_DRAM_BAR bit defines 500 */ 501 #define RMIXL_DRAM_BAR_BASE_ADDR __BITS(31,16) /* bits 39:24 of Base Address */ 502 #define DRAM_BAR_TO_BASE(r) \ 503 (((r) & RMIXL_DRAM_BAR_BASE_ADDR) << (24 - 16)) 504 #define RMIXL_DRAM_BAR_ADDR_MASK __BITS(15,4) /* bits 35:24 of Address Mask */ 505 #define DRAM_BAR_TO_SIZE(r) \ 506 ((((r) & RMIXL_DRAM_BAR_ADDR_MASK) + __BIT(4)) << (24 - 4)) 507 #define RMIXL_DRAM_BAR_INTERLEAVE __BITS(3,1) /* Interleave Mode */ 508 #define RMIXL_DRAM_BAR_STATUS __BIT(0) /* 1='region enabled' */ 509 510 /* 511 * RMIXL_SBC_DRAM_CHNAC_DTR and 512 * RMIXL_SBC_DRAM_CHNBD_DTR bit defines 513 * insert 'divisions' (0, 1 or 2) bits 514 * of value 'partition' 515 * at 'position' bit location. 516 */ 517 #define RMIXL_DRAM_DTR_RESa __BITS(31,14) 518 #define RMIXL_DRAM_DTR_PARTITION __BITS(13,12) 519 #define RMIXL_DRAM_DTR_RESb __BITS(11,10) 520 #define RMIXL_DRAM_DTR_DIVISIONS __BITS(9,8) 521 #define RMIXL_DRAM_DTR_RESc __BITS(7,6) 522 #define RMIXL_DRAM_DTR_POSITION __BITS(5,0) 523 #define RMIXL_DRAM_DTR_RESV \ 524 (RMIXL_DRAM_DTR_RESa|RMIXL_DRAM_DTR_RESb|RMIXL_DRAM_DTR_RESc) 525 526 /* 527 * RMIXL_SBC_DRAM_BRIDGE_CFG bit defines 528 */ 529 #define RMIXL_DRAM_CFG_RESa __BITS(31,13) 530 #define RMIXL_DRAM_CFG_CHANNEL_MODE __BIT(12) 531 #define RMIXL_DRAM_CFG_RESb __BIT(11) 532 #define RMIXL_DRAM_CFG_INTERLEAVE_MODE __BITS(10,8) 533 #define RMIXL_DRAM_CFG_RESc __BITS(7,5) 534 #define RMIXL_DRAM_CFG_BUS_MODE __BIT(4) 535 #define RMIXL_DRAM_CFG_RESd __BITS(3,2) 536 #define RMIXL_DRAM_CFG_DRAM_MODE __BITS(1,0) /* 1=DDR2 */ 537 538 /* 539 * RMIXL_SBC_XLR_PCIX_CFG_BAR bit defines 540 */ 541 #define RMIXL_PCIX_CFG_BAR_BASE __BITS(31,17) /* phys address bits 39:25 */ 542 #define RMIXL_PCIX_CFG_BAR_BA_SHIFT (25 - 17) 543 #define RMIXL_PCIX_CFG_BAR_TO_BA(r) \ 544 (((r) & RMIXL_PCIX_CFG_BAR_BASE) << RMIXL_PCIX_CFG_BAR_BA_SHIFT) 545 #define RMIXL_PCIX_CFG_BAR_RESV __BITS(16,1) /* (reserved) */ 546 #define RMIXL_PCIX_CFG_BAR_ENB __BIT(0) /* 1=Enable */ 547 #define RMIXL_PCIX_CFG_SIZE __BIT(25) 548 #define RMIXL_PCIX_CFG_BAR(ba, en) \ 549 ((uint32_t)(((ba) >> (25 - 17)) | ((en) ? RMIXL_PCIX_CFG_BAR_ENB : 0))) 550 551 /* 552 * RMIXLR_SBC_PCIX_MEM_BAR bit defines 553 */ 554 #define RMIXL_PCIX_MEM_BAR_BASE __BITS(31,16) /* phys address bits 39:24 */ 555 #define RMIXL_PCIX_MEM_BAR_TO_BA(r) \ 556 (((r) & RMIXL_PCIX_MEM_BAR_BASE) << (24 - 16)) 557 #define RMIXL_PCIX_MEM_BAR_MASK __BITS(15,1) /* phys address mask bits 38:24 */ 558 #define RMIXL_PCIX_MEM_BAR_TO_SIZE(r) \ 559 ((((r) & RMIXL_PCIX_MEM_BAR_MASK) + 2) << (24 - 1)) 560 #define RMIXL_PCIX_MEM_BAR_ENB __BIT(0) /* 1=Enable */ 561 #define RMIXL_PCIX_MEM_BAR(ba, en) \ 562 ((uint32_t)(((ba) >> (24 - 16)) | ((en) ? RMIXL_PCIX_MEM_BAR_ENB : 0))) 563 564 /* 565 * RMIXLR_SBC_PCIX_IO_BAR bit defines 566 */ 567 #define RMIXL_PCIX_IO_BAR_BASE __BITS(31,18) /* phys address bits 39:26 */ 568 #define RMIXL_PCIX_IO_BAR_TO_BA(r) \ 569 (((r) & RMIXL_PCIX_IO_BAR_BASE) << (26 - 18)) 570 #define RMIXL_PCIX_IO_BAR_RESV __BITS(17,7) /* (reserve) */ 571 #define RMIXL_PCIX_IO_BAR_MASK __BITS(6,1) /* phys address mask bits 31:26 */ 572 #define RMIXL_PCIX_IO_BAR_TO_SIZE(r) \ 573 ((((r) & RMIXL_PCIX_IO_BAR_MASK) + 2) << (26 - 1)) 574 #define RMIXL_PCIX_IO_BAR_ENB __BIT(0) /* 1=Enable */ 575 #define RMIXL_PCIX_IO_BAR(ba, en) \ 576 ((uint32_t)(((ba) >> (26 - 18)) | ((en) ? RMIXL_PCIX_IO_BAR_ENB : 0))) 577 578 579 /* 580 * RMIXLS_SBC_PCIE_CFG_BAR bit defines 581 */ 582 #define RMIXL_PCIE_CFG_BAR_BASE __BITS(31,17) /* phys address bits 39:25 */ 583 #define RMIXL_PCIE_CFG_BAR_BA_SHIFT (25 - 17) 584 #define RMIXL_PCIE_CFG_BAR_TO_BA(r) \ 585 (((r) & RMIXL_PCIE_CFG_BAR_BASE) << RMIXL_PCIE_CFG_BAR_BA_SHIFT) 586 #define RMIXL_PCIE_CFG_BAR_RESV __BITS(16,1) /* (reserved) */ 587 #define RMIXL_PCIE_CFG_BAR_ENB __BIT(0) /* 1=Enable */ 588 #define RMIXL_PCIE_CFG_SIZE __BIT(25) 589 #define RMIXL_PCIE_CFG_BAR(ba, en) \ 590 ((uint32_t)(((ba) >> (25 - 17)) | ((en) ? RMIXL_PCIE_CFG_BAR_ENB : 0))) 591 592 /* 593 * RMIXLS_SBC_PCIE_ECFG_BAR bit defines 594 * (PCIe extended config space) 595 */ 596 #define RMIXL_PCIE_ECFG_BAR_BASE __BITS(31,21) /* phys address bits 39:29 */ 597 #define RMIXL_PCIE_ECFG_BAR_BA_SHIFT (29 - 21) 598 #define RMIXL_PCIE_ECFG_BAR_TO_BA(r) \ 599 (((r) & RMIXL_PCIE_ECFG_BAR_BASE) << RMIXL_PCIE_ECFG_BAR_BA_SHIFT) 600 #define RMIXL_PCIE_ECFG_BAR_RESV __BITS(20,1) /* (reserved) */ 601 #define RMIXL_PCIE_ECFG_BAR_ENB __BIT(0) /* 1=Enable */ 602 #define RMIXL_PCIE_ECFG_SIZE __BIT(29) 603 #define RMIXL_PCIE_ECFG_BAR(ba, en) \ 604 ((uint32_t)(((ba) >> (29 - 21)) | ((en) ? RMIXL_PCIE_ECFG_BAR_ENB : 0))) 605 606 /* 607 * RMIXLS_SBC_PCIE_MEM_BAR bit defines 608 */ 609 #define RMIXL_PCIE_MEM_BAR_BASE __BITS(31,16) /* phys address bits 39:24 */ 610 #define RMIXL_PCIE_MEM_BAR_TO_BA(r) \ 611 (((r) & RMIXL_PCIE_MEM_BAR_BASE) << (24 - 16)) 612 #define RMIXL_PCIE_MEM_BAR_MASK __BITS(15,1) /* phys address mask bits 38:24 */ 613 #define RMIXL_PCIE_MEM_BAR_TO_SIZE(r) \ 614 ((((r) & RMIXL_PCIE_MEM_BAR_MASK) + 2) << (24 - 1)) 615 #define RMIXL_PCIE_MEM_BAR_ENB __BIT(0) /* 1=Enable */ 616 #define RMIXL_PCIE_MEM_BAR(ba, en) \ 617 ((uint32_t)(((ba) >> (24 - 16)) | ((en) ? RMIXL_PCIE_MEM_BAR_ENB : 0))) 618 619 /* 620 * RMIXLS_SBC_PCIE_IO_BAR bit defines 621 */ 622 #define RMIXL_PCIE_IO_BAR_BASE __BITS(31,18) /* phys address bits 39:26 */ 623 #define RMIXL_PCIE_IO_BAR_TO_BA(r) \ 624 (((r) & RMIXL_PCIE_IO_BAR_BASE) << (26 - 18)) 625 #define RMIXL_PCIE_IO_BAR_RESV __BITS(17,7) /* (reserve) */ 626 #define RMIXL_PCIE_IO_BAR_MASK __BITS(6,1) /* phys address mask bits 31:26 */ 627 #define RMIXL_PCIE_IO_BAR_TO_SIZE(r) \ 628 ((((r) & RMIXL_PCIE_IO_BAR_MASK) + 2) << (26 - 1)) 629 #define RMIXL_PCIE_IO_BAR_ENB __BIT(0) /* 1=Enable */ 630 #define RMIXL_PCIE_IO_BAR(ba, en) \ 631 ((uint32_t)(((ba) >> (26 - 18)) | ((en) ? RMIXL_PCIE_IO_BAR_ENB : 0))) 632 633 634 /* 635 * Programmable Interrupt Controller registers 636 * the Programming Reference Manual table 10.4 637 * lists "Reg ID" values not offsets 638 * Offsets are relative to RMIXL_IO_DEV_BRIDGE 639 */ 640 #define RMIXL_PIC_CONTROL _RMIXL_OFFSET(0x0) 641 #define RMIXL_PIC_IPIBASE _RMIXL_OFFSET(0x4) 642 #define RMIXL_PIC_INTRACK _RMIXL_OFFSET(0x6) 643 #define RMIXL_PIC_WATCHdOGMAXVALUE0 _RMIXL_OFFSET(0x8) 644 #define RMIXL_PIC_WATCHDOGMAXVALUE1 _RMIXL_OFFSET(0x9) 645 #define RMIXL_PIC_WATCHDOGMASK0 _RMIXL_OFFSET(0xa) 646 #define RMIXL_PIC_WATCHDOGMASK1 _RMIXL_OFFSET(0xb) 647 #define RMIXL_PIC_WATCHDOGHEARTBEAT0 _RMIXL_OFFSET(0xc) 648 #define RMIXL_PIC_WATCHDOGHEARTBEAT1 _RMIXL_OFFSET(0xd) 649 #define RMIXL_PIC_IRTENTRYC0(n) _RMIXL_OFFSET(0x40 + (n)) /* 0<=n<=31 */ 650 #define RMIXL_PIC_IRTENTRYC1(n) _RMIXL_OFFSET(0x80 + (n)) /* 0<=n<=31 */ 651 #define RMIXL_PIC_SYSTMRMAXVALC0(n) _RMIXL_OFFSET(0x100 + (n)) /* 0<=n<=7 */ 652 #define RMIXL_PIC_SYSTMRMAXVALC1(n) _RMIXL_OFFSET(0x110 + (n)) /* 0<=n<=7 */ 653 #define RMIXL_PIC_SYSTMRC0(n) _RMIXL_OFFSET(0x120 + (n)) /* 0<=n<=7 */ 654 #define RMIXL_PIC_SYSTMRC1(n) _RMIXL_OFFSET(0x130 + (n)) /* 0<=n<=7 */ 655 656 /* 657 * RMIXL_PIC_CONTROL bits 658 */ 659 #define RMIXL_PIC_CONTROL_WATCHDOG_ENB __BIT(0) 660 #define RMIXL_PIC_CONTROL_GEN_NMI __BITS(2,1) /* do NMI after n WDog irpts */ 661 #define RMIXL_PIC_CONTROL_GEN_NMIn(n) (((n) << 1) & RMIXL_PIC_CONTROL_GEN_NMI) 662 #define RMIXL_PIC_CONTROL_RESa __BITS(7,3) 663 #define RMIXL_PIC_CONTROL_TIMER_ENB __BITS(15,8) /* per-Timer enable bits */ 664 #define RMIXL_PIC_CONTROL_TIMER_ENBn(n) ((1 << (8 + (n))) & RMIXL_PIC_CONTROL_TIMER_ENB) 665 #define RMIXL_PIC_CONTROL_RESb __BITS(31,16) 666 #define RMIXL_PIC_CONTROL_RESV \ 667 (RMIXL_PIC_CONTROL_RESa|RMIXL_PIC_CONTROL_RESb) 668 669 /* 670 * RMIXL_PIC_IPIBASE bits 671 */ 672 #define RMIXL_PIC_IPIBASE_VECTORNUM __BITS(5,0) 673 #define RMIXL_PIC_IPIBASE_RESa __BIT(6) /* undocumented bit */ 674 #define RMIXL_PIC_IPIBASE_BCAST __BIT(7) 675 #define RMIXL_PIC_IPIBASE_NMI __BIT(8) 676 #define RMIXL_PIC_IPIBASE_ID __BITS(31,16) 677 #define RMIXL_PIC_IPIBASE_ID_RESb __BITS(31,23) 678 #define RMIXL_PIC_IPIBASE_ID_CORE __BITS(22,20) /* Physical CPU ID */ 679 #define RMIXL_PIC_IPIBASE_ID_CORE_SHIFT 20 680 #define RMIXL_PIC_IPIBASE_ID_RESc __BITS(19,18) 681 #define RMIXL_PIC_IPIBASE_ID_THREAD __BITS(17,16) /* Thread ID */ 682 #define RMIXL_PIC_IPIBASE_ID_THREAD_SHIFT 16 683 #define RMIXL_PIC_IPIBASE_ID_RESV \ 684 (RMIXL_PIC_IPIBASE_ID_RESa|RMIXL_PIC_IPIBASE_ID_RESb \ 685 |RMIXL_PIC_IPIBASE_ID_RESc) 686 #define RMIXL_PIC_IPIBASE_MAKE(nmi, core, thread, tag) \ 687 (__SHIFTIN((nmi), RMIXL_PIC_IPIBASE_NMI) \ 688 | __SHIFTIN((core), RMIXL_PIC_IPIBASE_ID_CORE) \ 689 | __SHIFTIN((thread), RMIXL_PIC_IPIBASE_ID_THREAD) \ 690 | __SHIFTIN((tag), RMIXL_PIC_IPIBASE_VECTORNUM)) 691 692 /* 693 * RMIXL_PIC_IRTENTRYC0 bits 694 * IRT Entry low word 695 */ 696 #define RMIXL_PIC_IRTENTRYC0_TMASK __BITS(7,0) /* Thread Mask */ 697 #define RMIXL_PIC_IRTENTRYC0_RESa __BITS(3,2) /* write as 0 */ 698 #define RMIXL_PIC_IRTENTRYC0_RESb __BITS(31,8) /* write as 0 */ 699 #define RMIXL_PIC_IRTENTRYC0_RESV \ 700 (RMIXL_PIC_IRTENTRYC0_RESa | RMIXL_PIC_IRTENTRYC0_RESb) 701 702 /* 703 * RMIXL_PIC_IRTENTRYC1 bits 704 * IRT Entry high word 705 */ 706 #define RMIXL_PIC_IRTENTRYC1_INTVEC __BITS(5,0) /* maps to bit# in CPU's EIRR */ 707 #define RMIXL_PIC_IRTENTRYC1_GL __BIT(6) /* 0=Global; 1=Local */ 708 #define RMIXL_PIC_IRTENTRYC1_NMI __BIT(7) /* 0=Maskable; 1=NMI */ 709 #define RMIXL_PIC_IRTENTRYC1_RESV __BITS(28,8) 710 #define RMIXL_PIC_IRTENTRYC1_P __BIT(29) /* 0=Rising/High; 1=Falling/Low */ 711 #define RMIXL_PIC_IRTENTRYC1_TRG __BIT(30) /* 0=Edge; 1=Level */ 712 #define RMIXL_PIC_IRTENTRYC1_VALID __BIT(31) /* 0=Invalid; 1=Valid IRT Entry */ 713 714 /* 715 * GPIO Controller registers 716 */ 717 /* GPIO Signal Registers */ 718 #define RMIXL_GPIO_INT_ENB _RMIXL_OFFSET(0x0) /* Interrupt Enable register */ 719 #define RMIXL_GPIO_INT_INV _RMIXL_OFFSET(0x1) /* Interrupt Inversion register */ 720 #define RMIXL_GPIO_IO_DIR _RMIXL_OFFSET(0x2) /* I/O Direction register */ 721 #define RMIXL_GPIO_OUTPUT _RMIXL_OFFSET(0x3) /* Output Write register */ 722 #define RMIXL_GPIO_INPUT _RMIXL_OFFSET(0x4) /* Intput Read register */ 723 #define RMIXL_GPIO_INT_CLR _RMIXL_OFFSET(0x5) /* Interrupt Inversion register */ 724 #define RMIXL_GPIO_INT_STS _RMIXL_OFFSET(0x6) /* Interrupt Status register */ 725 #define RMIXL_GPIO_INT_TYP _RMIXL_OFFSET(0x7) /* Interrupt Type register */ 726 #define RMIXL_GPIO_RESET _RMIXL_OFFSET(0x8) /* XLS Soft Reset register */ 727 728 /* 729 * RMIXL_GPIO_RESET bits 730 */ 731 #define RMIXL_GPIO_RESET_RESV __BITS(31,1) 732 #define RMIXL_GPIO_RESET_RESET __BIT(0) 733 734 735 /* GPIO System Control Registers */ 736 #define RMIXL_GPIO_RESET_CFG _RMIXL_OFFSET(0x15) /* Reset Configuration register */ 737 #define RMIXL_GPIO_THERMAL_CSR _RMIXL_OFFSET(0x16) /* Thermal Control/Status register */ 738 #define RMIXL_GPIO_THERMAL_SHFT _RMIXL_OFFSET(0x17) /* Thermal Shift register */ 739 #define RMIXL_GPIO_BIST_ALL_STS _RMIXL_OFFSET(0x18) /* BIST All Status register */ 740 #define RMIXL_GPIO_BIST_EACH_STS _RMIXL_OFFSET(0x19) /* BIST Each Status register */ 741 #define RMIXL_GPIO_SGMII_0_3_PHY_CTL _RMIXL_OFFSET(0x20) /* SGMII #0..3 PHY Control register */ 742 #define RMIXL_GPIO_AUI_0_PHY_CTL _RMIXL_OFFSET(0x20) /* AUI port#0 PHY Control register */ 743 #define RMIXL_GPIO_SGMII_4_7_PLL_CTL _RMIXL_OFFSET(0x21) /* SGMII #4..7 PLL Control register */ 744 #define RMIXL_GPIO_AUI_1_PLL_CTL _RMIXL_OFFSET(0x21) /* AUI port#1 PLL Control register */ 745 #define RMIXL_GPIO_SGMII_4_7_PHY_CTL _RMIXL_OFFSET(0x22) /* SGMII #4..7 PHY Control register */ 746 #define RMIXL_GPIO_AUI_1_PHY_CTL _RMIXL_OFFSET(0x22) /* AUI port#1 PHY Control register */ 747 #define RMIXL_GPIO_INT_MAP _RMIXL_OFFSET(0x25) /* Interrupt Map to PIC, 0=int14, 1=int30 */ 748 #define RMIXL_GPIO_EXT_INT _RMIXL_OFFSET(0x26) /* External Interrupt control register */ 749 #define RMIXL_GPIO_CPU_RST _RMIXL_OFFSET(0x28) /* CPU Reset control register */ 750 #define RMIXL_GPIO_LOW_PWR_DIS _RMIXL_OFFSET(0x29) /* Low Power Dissipation register */ 751 #define RMIXL_GPIO_RANDOM _RMIXL_OFFSET(0x2b) /* Low Power Dissipation register */ 752 #define RMIXL_GPIO_CPU_CLK_DIS _RMIXL_OFFSET(0x2d) /* CPU Clock Disable register */ 753 754 /* 755 * RMIXL_GPIO_RESET_CFG bits 756 */ 757 #define RMIXL_GPIO_RESET_CFG_RESa __BITS(31,28) 758 #define RMIXL_GPIO_RESET_CFG_PCIE_SRIO_SEL __BITS(27,26) /* PCIe or SRIO Select: 759 * 00 = PCIe selected, SRIO not available 760 * 01 = SRIO selected, 1.25 Gbaud (1.0 Gbps) 761 * 10 = SRIO selected, 2.25 Gbaud (2.0 Gbps) 762 * 11 = SRIO selected, 3.125 Gbaud (2.5 Gbps) 763 */ 764 #define RMIXL_GPIO_RESET_CFG_XAUI_PORT1_SEL __BIT(25) /* XAUI Port 1 Select: 765 * 0 = Disabled - Port is SGMII ports 4-7 766 * 1 = Enabled - Port is 4-lane XAUI Port 1 767 */ 768 #define RMIXL_GPIO_RESET_CFG_XAUI_PORT0_SEL __BIT(24) /* XAUI Port 0 Select: 769 * 0 = Disabled - Port is SGMII ports 0-3 770 * 1 = Enabled - Port is 4-lane XAUI Port 0 771 */ 772 #define RMIXL_GPIO_RESET_CFG_RESb __BIT(23) 773 #define RMIXL_GPIO_RESET_CFG_USB_DEV __BIT(22) /* USB Device: 774 * 0 = Device Mode 775 * 1 = Host Mode 776 */ 777 #define RMIXL_GPIO_RESET_CFG_PCIE_CFG __BITS(21,20) /* PCIe or SRIO configuration */ 778 #define RMIXL_GPIO_RESET_CFG_FLASH33_EN __BIT(19) /* Flash 33 MHZ Enable: 779 * 0 = 66.67 MHz 780 * 1 = 33.33 MHz 781 */ 782 #define RMIXL_GPIO_RESET_CFG_BIST_DIAG_EN __BIT(18) /* BIST Diagnostics enable */ 783 #define RMIXL_GPIO_RESET_CFG_BIST_RUN_EN __BIT(18) /* BIST Run enable */ 784 #define RMIXL_GPIO_RESET_CFG_NOOT_NAND __BIT(16) /* Enable boot from NAND Flash */ 785 #define RMIXL_GPIO_RESET_CFG_BOOT_PCMCIA __BIT(15) /* Enable boot from PCMCIA */ 786 #define RMIXL_GPIO_RESET_CFG_FLASH_CFG __BIT(14) /* Flash 32-bit Data Configuration: 787 * 0 = 32-bit address / 16-bit data 788 * 1 = 32-bit address / 32-bit data 789 */ 790 #define RMIXL_GPIO_RESET_CFG_PCMCIA_EN __BIT(13) /* PCMCIA Enable Status */ 791 #define RMIXL_GPIO_RESET_CFG_PARITY_EN __BIT(12) /* Parity Enable Status */ 792 #define RMIXL_GPIO_RESET_CFG_BIGEND __BIT(11) /* Big Endian Mode Enable Status */ 793 #define RMIXL_GPIO_RESET_CFG_PLL1_OUT_DIV __BITS(10,8) /* PLL1 (Core PLL) Output Divider */ 794 #define RMIXL_GPIO_RESET_CFG_PLL1_FB_DIV __BITS(7,0) /* PLL1 Feedback Divider */ 795 796 /* 797 * RMIXL_GPIO_LOW_PWR_DIS bits 798 * except as noted, all bits are: 799 * 0 = feature enable (default) 800 * 1 = feature disable 801 */ 802 /* XXX defines are for XLS6xx, XLS4xx-Lite and XLS4xx Devices */ 803 #define RMIXL_GPIO_LOW_PWR_DIS_LP __BIT(0) /* Low Power disable */ 804 #define RMIXL_GPIO_LOW_PWR_DIS_GMAC_QD_0 __BIT(1) /* GMAC Quad 0 (GMAC 0..3) disable */ 805 #define RMIXL_GPIO_LOW_PWR_DIS_GMAC_QD_1 __BIT(2) /* GMAC Quad 1 (GMAC 4..7) disable */ 806 #define RMIXL_GPIO_LOW_PWR_DIS_USB __BIT(3) /* USB disable */ 807 #define RMIXL_GPIO_LOW_PWR_DIS_PCIE __BIT(4) /* PCIE disable */ 808 #define RMIXL_GPIO_LOW_PWR_DIS_CDE __BIT(5) /* Compression/Decompression Engine disable */ 809 #define RMIXL_GPIO_LOW_PWR_DIS_DMA __BIT(6) /* DMA Engine disable */ 810 #define RMIXL_GPIO_LOW_PWR_DIS_SAE __BITS(8,7) /* Security Acceleration Engine disable: 811 * 00 = enable (default) 812 * 01 = reserved 813 * 10 = reserved 814 * 11 = disable 815 */ 816 #define RMIXL_GPIO_LOW_PWR_DIS_RESV __BITS(31,9) 817 818 /* 819 * Peripheral I/O bus (Flash/PCMCIA) controller registers 820 */ 821 #define RMIXL_FLASH_NCS 10 /* number of chip selects */ 822 #define RMIXL_FLASH_CS_BOOT 0 /* CS0 is boot flash */ 823 #define RMIXL_FLASH_CS_PCMCIA_CF 6 /* CS6 is PCMCIA compact flash */ 824 #define RMIXL_FLASH_CSBASE_ADDRn(n) _RMIXL_OFFSET(0x00+(n)) /* CSn Base Address reg */ 825 #define RMIXL_FLASH_CSADDR_MASKn(n) _RMIXL_OFFSET(0x10+(n)) /* CSn Address Mask reg */ 826 #define RMIXL_FLASH_CSDEV_PARMn(n) _RMIXL_OFFSET(0x20+(n)) /* CSn Device Parameter reg */ 827 #define RMIXL_FLASH_CSTIME_PARMAn(n) _RMIXL_OFFSET(0x30+(n)) /* CSn Timing Parameters A reg */ 828 #define RMIXL_FLASH_CSTIME_PARMBn(n) _RMIXL_OFFSET(0x40+(n)) /* CSn Timing Parameters B reg */ 829 #define RMIXL_FLASH_INT_MASK _RMIXL_OFFSET(0x50) /* Flash Interrupt Mask reg */ 830 #define RMIXL_FLASH_INT_STATUS _RMIXL_OFFSET(0x60) /* Flash Interrupt Status reg */ 831 #define RMIXL_FLASH_ERROR_STATUS _RMIXL_OFFSET(0x70) /* Flash Error Status reg */ 832 #define RMIXL_FLASH_ERROR_ADDR _RMIXL_OFFSET(0x80) /* Flash Error Address reg */ 833 834 /* 835 * RMIXL_FLASH_CSDEV_PARMn bits 836 */ 837 #define RMIXL_FLASH_CSDEV_RESV __BITS(31,16) 838 #define RMIXL_FLASH_CSDEV_BFN __BIT(15) /* Boot From Nand 839 * 0=Boot from NOR or 840 * PCCard Type 1 Flash 841 * 1=Boot from NAND 842 */ 843 #define RMIXL_FLASH_CSDEV_NANDEN __BIT(14) /* NAND Flash Enable 844 * 0=NOR 845 * 1=NAND 846 */ 847 #define RMIXL_FLASH_CSDEV_ADVTYPE __BIT(13) /* Add Valid Sensing Type 848 * 0=level 849 * 1=pulse 850 */ 851 #define RMIXL_FLASH_CSDEV_PARITY_TYPE __BIT(12) /* Parity Type 852 * 0=even 853 * 1=odd 854 */ 855 #define RMIXL_FLASH_CSDEV_PARITY_EN __BIT(11) /* Parity Enable */ 856 #define RMIXL_FLASH_CSDEV_GENIF_EN __BIT(10) /* Generic PLD/FPGA interface mode 857 * if this bit is set, then 858 * GPIO[13:10] cannot be used 859 * for interrupts 860 */ 861 #define RMIXL_FLASH_CSDEV_PCMCIA_EN __BIT(9) /* PCMCIA Interface mode */ 862 #define RMIXL_FLASH_CSDEV_DWIDTH __BITS(8,7) /* Data Bus Width: 863 * 00: 8 bit 864 * 01: 16 bit 865 * 10: 32 bit 866 * 11: 8 bit 867 */ 868 #define RMIXL_FLASH_CSDEV_DWIDTH_SHFT 7 869 #define RMIXL_FLASH_CSDEV_MX_ADDR __BIT(6) /* Multiplexed Address 870 * 0: non-muxed 871 * AD[31:24] = Data, 872 * AD[23:0] = Addr 873 * 1: muxed 874 * External latch required 875 */ 876 #define RMIXL_FLASH_CSDEV_WAIT_POL __BIT(5) /* WAIT polarity 877 * 0: Active high 878 * 1: Active low 879 */ 880 #define RMIXL_FLASH_CSDEV_WAIT_EN __BIT(4) /* Enable External WAIT Ack mode */ 881 #define RMIXL_FLASH_CSDEV_BURST __BITS(3,1) /* Burst Length: 882 * 000: 2x 883 * 001: 4x 884 * 010: 8x 885 * 011: 16x 886 * 100: 32x 887 */ 888 #define RMIXL_FLASH_CSDEV_BURST_SHFT 1 889 #define RMIXL_FLASH_CSDEV_BURST_EN __BITS(0) /* Burst Enable */ 890 891 892 /* 893 * NAND Flash Memory Control registers 894 */ 895 #define RMIXL_NAND_CLEn(n) _RMIXL_OFFSET(0x90+(n)) /* CSn 8-bit CLE command value reg */ 896 #define RMIXL_NAND_ALEn(n) _RMIXL_OFFSET(0xa0+(n)) /* CSn 8-bit ALE address phase reg */ 897 898 899 /* 900 * PCIE Interface Controller registers 901 */ 902 #define RMIXL_PCIE_CTRL1 _RMIXL_OFFSET(0x0) 903 #define RMIXL_PCIE_CTRL2 _RMIXL_OFFSET(0x1) 904 #define RMIXL_PCIE_CTRL3 _RMIXL_OFFSET(0x2) 905 #define RMIXL_PCIE_CTRL4 _RMIXL_OFFSET(0x3) 906 #define RMIXL_PCIE_CTRL _RMIXL_OFFSET(0x4) 907 #define RMIXL_PCIE_IOBM_TIMER _RMIXL_OFFSET(0x5) 908 #define RMIXL_PCIE_MSI_CMD _RMIXL_OFFSET(0x6) 909 #define RMIXL_PCIE_MSI_RESP _RMIXL_OFFSET(0x7) 910 #define RMIXL_PCIE_DWC_CRTL5 _RMIXL_OFFSET(0x8) /* not on XLS408Lite, XLS404Lite */ 911 #define RMIXL_PCIE_DWC_CRTL6 _RMIXL_OFFSET(0x9) /* not on XLS408Lite, XLS404Lite */ 912 #define RMIXL_PCIE_IOBM_SWAP_MEM_BASE _RMIXL_OFFSET(0x10) 913 #define RMIXL_PCIE_IOBM_SWAP_MEM_LIMIT _RMIXL_OFFSET(0x11) 914 #define RMIXL_PCIE_IOBM_SWAP_IO_BASE _RMIXL_OFFSET(0x12) 915 #define RMIXL_PCIE_IOBM_SWAP_IO_LIMIT _RMIXL_OFFSET(0x13) 916 #define RMIXL_PCIE_TRGT_CHRNT_MEM_BASE _RMIXL_OFFSET(0x14) 917 #define RMIXL_PCIE_TRGT_CHRNT_MEM_LIMIT _RMIXL_OFFSET(0x15) 918 #define RMIXL_PCIE_TRGT_L2ALC_MEM_BASE _RMIXL_OFFSET(0x16) 919 #define RMIXL_PCIE_TRGT_L2ALC_MEM_LIMIT _RMIXL_OFFSET(0x17) 920 #define RMIXL_PCIE_TRGT_REX_MEM_BASE _RMIXL_OFFSET(0x18) 921 #define RMIXL_PCIE_TRGT_REX_MEM_LIMIT _RMIXL_OFFSET(0x19) 922 #define RMIXL_PCIE_EP_MEM_BASE _RMIXL_OFFSET(0x1a) 923 #define RMIXL_PCIE_EP_MEM_LIMIT _RMIXL_OFFSET(0x1b) 924 #define RMIXL_PCIE_EP_ADDR_MAP_ENTRY0 _RMIXL_OFFSET(0x1c) 925 #define RMIXL_PCIE_EP_ADDR_MAP_ENTRY1 _RMIXL_OFFSET(0x1d) 926 #define RMIXL_PCIE_EP_ADDR_MAP_ENTRY2 _RMIXL_OFFSET(0x1e) 927 #define RMIXL_PCIE_EP_ADDR_MAP_ENTRY3 _RMIXL_OFFSET(0x1f) 928 #define RMIXL_PCIE_LINK0_STATE _RMIXL_OFFSET(0x20) 929 #define RMIXL_PCIE_LINK1_STATE _RMIXL_OFFSET(0x21) 930 #define RMIXL_PCIE_IOBM_INT_STATUS _RMIXL_OFFSET(0x22) 931 #define RMIXL_PCIE_IOBM_INT_ENABLE _RMIXL_OFFSET(0x23) 932 #define RMIXL_PCIE_LINK0_MSI_STATUS _RMIXL_OFFSET(0x24) 933 #define RMIXL_PCIE_LINK1_MSI_STATUS _RMIXL_OFFSET(0x25) 934 #define RMIXL_PCIE_LINK0_MSI_ENABLE _RMIXL_OFFSET(0x26) 935 #define RMIXL_PCIE_LINK1_MSI_ENABLE _RMIXL_OFFSET(0x27) 936 #define RMIXL_PCIE_LINK0_INT_STATUS0 _RMIXL_OFFSET(0x28) 937 #define RMIXL_PCIE_LINK1_INT_STATUS0 _RMIXL_OFFSET(0x29) 938 #define RMIXL_PCIE_LINK0_INT_STATUS1 _RMIXL_OFFSET(0x2a) 939 #define RMIXL_PCIE_LINK1_INT_STATUS1 _RMIXL_OFFSET(0x2b) 940 #define RMIXL_PCIE_LINK0_INT_ENABLE0 _RMIXL_OFFSET(0x2c) 941 #define RMIXL_PCIE_LINK1_INT_ENABLE0 _RMIXL_OFFSET(0x2d) 942 #define RMIXL_PCIE_LINK0_INT_ENABLE1 _RMIXL_OFFSET(0x2e) 943 #define RMIXL_PCIE_LINK1_INT_ENABLE1 _RMIXL_OFFSET(0x2f) 944 #define RMIXL_PCIE_PHY_CR_CMD _RMIXL_OFFSET(0x30) 945 #define RMIXL_PCIE_PHY_CR_WR_DATA _RMIXL_OFFSET(0x31) 946 #define RMIXL_PCIE_PHY_CR_RESP _RMIXL_OFFSET(0x32) 947 #define RMIXL_PCIE_PHY_CR_RD_DATA _RMIXL_OFFSET(0x33) 948 #define RMIXL_PCIE_IOBM_ERR_CMD _RMIXL_OFFSET(0x34) 949 #define RMIXL_PCIE_IOBM_ERR_LOWER_ADDR _RMIXL_OFFSET(0x35) 950 #define RMIXL_PCIE_IOBM_ERR_UPPER_ADDR _RMIXL_OFFSET(0x36) 951 #define RMIXL_PCIE_IOBM_ERR_BE _RMIXL_OFFSET(0x37) 952 #define RMIXL_PCIE_LINK2_STATE _RMIXL_OFFSET(0x60) /* not on XLS408Lite, XLS404Lite */ 953 #define RMIXL_PCIE_LINK3_STATE _RMIXL_OFFSET(0x61) /* not on XLS408Lite, XLS404Lite */ 954 #define RMIXL_PCIE_LINK2_MSI_STATUS _RMIXL_OFFSET(0x64) /* not on XLS408Lite, XLS404Lite */ 955 #define RMIXL_PCIE_LINK3_MSI_STATUS _RMIXL_OFFSET(0x65) /* not on XLS408Lite, XLS404Lite */ 956 #define RMIXL_PCIE_LINK2_MSI_ENABLE _RMIXL_OFFSET(0x66) /* not on XLS408Lite, XLS404Lite */ 957 #define RMIXL_PCIE_LINK3_MSI_ENABLE _RMIXL_OFFSET(0x67) /* not on XLS408Lite, XLS404Lite */ 958 #define RMIXL_PCIE_LINK2_INT_STATUS0 _RMIXL_OFFSET(0x68) /* not on XLS408Lite, XLS404Lite */ 959 #define RMIXL_PCIE_LINK3_INT_STATUS0 _RMIXL_OFFSET(0x69) /* not on XLS408Lite, XLS404Lite */ 960 #define RMIXL_PCIE_LINK2_INT_STATUS1 _RMIXL_OFFSET(0x6a) /* not on XLS408Lite, XLS404Lite */ 961 #define RMIXL_PCIE_LINK3_INT_STATUS1 _RMIXL_OFFSET(0x6b) /* not on XLS408Lite, XLS404Lite */ 962 #define RMIXL_PCIE_LINK2_INT_ENABLE0 _RMIXL_OFFSET(0x6c) /* not on XLS408Lite, XLS404Lite */ 963 #define RMIXL_PCIE_LINK3_INT_ENABLE0 _RMIXL_OFFSET(0x6d) /* not on XLS408Lite, XLS404Lite */ 964 #define RMIXL_PCIE_LINK2_INT_ENABLE1 _RMIXL_OFFSET(0x6e) /* not on XLS408Lite, XLS404Lite */ 965 #define RMIXL_PCIE_LINK3_INT_ENABLE1 _RMIXL_OFFSET(0x6f) /* not on XLS408Lite, XLS404Lite */ 966 #define RMIXL_VC0_POSTED_RX_QUEUE_CTRL _RMIXL_OFFSET(0x1d2) 967 #define RMIXL_VC0_POSTED_BUFFER_DEPTH _RMIXL_OFFSET(0x1ea) 968 #define RMIXL_PCIE_MSG_TX_THRESHOLD _RMIXL_OFFSET(0x308) 969 #define RMIXL_PCIE_MSG_BUCKET_SIZE_0 _RMIXL_OFFSET(0x320) 970 #define RMIXL_PCIE_MSG_BUCKET_SIZE_1 _RMIXL_OFFSET(0x321) 971 #define RMIXL_PCIE_MSG_BUCKET_SIZE_2 _RMIXL_OFFSET(0x322) 972 #define RMIXL_PCIE_MSG_BUCKET_SIZE_3 _RMIXL_OFFSET(0x323) 973 #define RMIXL_PCIE_MSG_BUCKET_SIZE_4 _RMIXL_OFFSET(0x324) /* not on XLS408Lite, XLS404Lite */ 974 #define RMIXL_PCIE_MSG_BUCKET_SIZE_5 _RMIXL_OFFSET(0x325) /* not on XLS408Lite, XLS404Lite */ 975 #define RMIXL_PCIE_MSG_BUCKET_SIZE_6 _RMIXL_OFFSET(0x326) /* not on XLS408Lite, XLS404Lite */ 976 #define RMIXL_PCIE_MSG_BUCKET_SIZE_7 _RMIXL_OFFSET(0x327) /* not on XLS408Lite, XLS404Lite */ 977 #define RMIXL_PCIE_MSG_CREDIT_FIRST _RMIXL_OFFSET(0x380) 978 #define RMIXL_PCIE_MSG_CREDIT_LAST _RMIXL_OFFSET(0x3ff) 979 980 /* 981 * USB General Interface registers 982 * these are opffset from REGSPACE selected by __BIT(12) == 1 983 * RMIXL_IOREG_VADDR(RMIXL_IO_DEV_USB_B + reg) 984 * see Tables 18-7 and 18-14 in the XLS PRM 985 */ 986 #define RMIXL_USB_GEN_CTRL1 0x00 987 #define RMIXL_USB_GEN_CTRL2 0x04 988 #define RMIXL_USB_GEN_CTRL3 0x08 989 #define RMIXL_USB_IOBM_TIMER 0x0C 990 #define RMIXL_USB_VBUS_TIMER 0x10 991 #define RMIXL_USB_BYTESWAP_EN 0x14 992 #define RMIXL_USB_COHERENT_MEM_BASE 0x40 993 #define RMIXL_USB_COHERENT_MEM_LIMIT 0x44 994 #define RMIXL_USB_L2ALLOC_MEM_BASE 0x48 995 #define RMIXL_USB_L2ALLOC_MEM_LIMIT 0x4C 996 #define RMIXL_USB_READEX_MEM_BASE 0x50 997 #define RMIXL_USB_READEX_MEM_LIMIT 0x54 998 #define RMIXL_USB_PHY_STATUS 0xC0 999 #define RMIXL_USB_INTERRUPT_STATUS 0xC4 1000 #define RMIXL_USB_INTERRUPT_ENABLE 0xC8 1001 1002 /* 1003 * RMIXL_USB_GEN_CTRL1 bits 1004 */ 1005 #define RMIXL_UG_CTRL1_RESV __BITS(31,2) 1006 #define RMIXL_UG_CTRL1_HOST_RST __BIT(1) /* Resets the Host Controller 1007 * 0: reset 1008 * 1: normal operation 1009 */ 1010 #define RMIXL_UG_CTRL1_DEV_RST __BIT(0) /* Resets the Device Controller 1011 * 0: reset 1012 * 1: normal operation 1013 */ 1014 1015 /* 1016 * RMIXL_USB_GEN_CTRL2 bits 1017 */ 1018 #define RMIXL_UG_CTRL2_RESa __BITS(31,20) 1019 #define RMIXL_UG_CTRL2_TX_TUNE_1 __BITS(19,18) /* Port_1 Transmitter Tuning for High-Speed Operation. 1020 * 00: ~-4.5% 1021 * 01: Design default 1022 * 10: ~+4.5% 1023 * 11: ~+9% = Recommended Operating setting 1024 */ 1025 #define RMIXL_UG_CTRL2_TX_TUNE_0 __BITS(17,16) /* Port_0 Transmitter Tuning for High-Speed Operation 1026 * 11: Recommended Operating condition 1027 */ 1028 #define RMIXL_UG_CTRL2_RESb __BIT(15) 1029 #define RMIXL_UG_CTRL2_WEAK_PDEN __BIT(14) /* 500kOhm Pull-Down Resistor on D+ and D- Enable */ 1030 #define RMIXL_UG_CTRL2_DP_PULLUP_ESD __BIT(13) /* D+ Pull-Up Resistor Enable */ 1031 #define RMIXL_UG_CTRL2_ESD_TEST_MODE __BIT(12) /* D+ Pull-Up Resistor Control Select */ 1032 #define RMIXL_UG_CTRL2_TX_BIT_STUFF_EN_H_1 \ 1033 __BIT(11) /* Port_1 High-Byte Transmit Bit-Stuffing Enable */ 1034 #define RMIXL_UG_CTRL2_TX_BIT_STUFF_EN_H_0 \ 1035 __BIT(10) /* Port_0 High-Byte Transmit Bit-Stuffing Enable */ 1036 #define RMIXL_UG_CTRL2_TX_BIT_STUFF_EN_L_1 \ 1037 __BIT(9) /* Port_1 Low-Byte Transmit Bit-Stuffing Enable */ 1038 #define RMIXL_UG_CTRL2_TX_BIT_STUFF_EN_L_0 \ 1039 __BIT(8) /* Port_0 Low-Byte Transmit Bit-Stuffing Enable */ 1040 #define RMIXL_UG_CTRL2_RESc __BITS(7,6) 1041 #define RMIXL_UG_CTRL2_LOOPBACK_ENB_1 __BIT(5) /* Port_1 Loopback Test Enable */ 1042 #define RMIXL_UG_CTRL2_LOOPBACK_ENB_0 __BIT(4) /* Port_0 Loopback Test Enable */ 1043 #define RMIXL_UG_CTRL2_DEVICE_VBUS __BIT(3) /* VBUS detected (Device mode only) */ 1044 #define RMIXL_UG_CTRL2_PHY_PORT_RST_1 __BIT(2) /* Resets Port_1 of the PHY 1045 * 1: normal operation 1046 * 0: reset 1047 */ 1048 #define RMIXL_UG_CTRL2_PHY_PORT_RST_0 __BIT(1) /* Resets Port_0 of the PHY 1049 * 1: normal operation 1050 * 0: reset 1051 */ 1052 #define RMIXL_UG_CTRL2_PHY_RST __BIT(0) /* Resets the PHY 1053 * 1: normal operation 1054 * 0: reset 1055 */ 1056 #define RMIXL_UG_CTRL2_RESV \ 1057 (RMIXL_UG_CTRL2_RESa | RMIXL_UG_CTRL2_RESb | RMIXL_UG_CTRL2_RESc) 1058 1059 1060 /* 1061 * RMIXL_USB_GEN_CTRL3 bits 1062 */ 1063 #define RMIXL_UG_CTRL3_RESa __BITS(31,11) 1064 #define RMIXL_UG_CTRL3_PREFETCH_SIZE __BITS(10,8) /* The pre-fetch size for a memory read transfer 1065 * between USB Interface and DI station. 1066 * Valid value ranges is from 1 to 4. 1067 */ 1068 #define RMIXL_UG_CTRL3_RESb __BIT(7) 1069 #define RMIXL_UG_CTRL3_DEV_UPPERADDR __BITS(6,1) /* Device controller address space selector */ 1070 #define RMIXL_UG_CTRL3_USB_FLUSH __BIT(0) /* Flush the USB interface */ 1071 1072 /* 1073 * RMIXL_USB_PHY_STATUS bits 1074 */ 1075 #define RMIXL_UB_PHY_STATUS_RESV __BITS(31,1) 1076 #define RMIXL_UB_PHY_STATUS_VBUS __BIT(0) /* USB VBUS status */ 1077 1078 /* 1079 * RMIXL_USB_INTERRUPT_STATUS and RMIXL_USB_INTERRUPT_ENABLE bits 1080 */ 1081 #define RMIXL_UB_INTERRUPT_RESV __BITS(31,6) 1082 #define RMIXL_UB_INTERRUPT_FORCE __BIT(5) /* USB force interrupt */ 1083 #define RMIXL_UB_INTERRUPT_PHY __BIT(4) /* USB PHY interrupt */ 1084 #define RMIXL_UB_INTERRUPT_DEV __BIT(3) /* USB Device Controller interrupt */ 1085 #define RMIXL_UB_INTERRUPT_EHCI __BIT(2) /* USB EHCI interrupt */ 1086 #define RMIXL_UB_INTERRUPT_OHCI_1 __BIT(1) /* USB OHCI #1 interrupt */ 1087 #define RMIXL_UB_INTERRUPT_OHCI_0 __BIT(0) /* USB OHCI #0 interrupt */ 1088 #define RMIXL_UB_INTERRUPT_MAX 5 1089 1090 1091 /* 1092 * USB Device Controller registers 1093 * these are opffset from REGSPACE selected by __BIT(12) == 0 1094 * RMIXL_IOREG_VADDR(RMIXL_IO_DEV_USB_A + reg) 1095 * see Table 18-7 in the XLS PRM 1096 */ 1097 #define RMIXL_USB_UDC_GAHBCFG 0x008 /* UDC Configuration A (UDC_GAHBCFG) */ 1098 #define RMIXL_USB_UDC_GUSBCFG 0x00C /* UDC Configuration B (UDC_GUSBCFG) */ 1099 #define RMIXL_USB_UDC_GRSTCTL 0x010 /* UDC Reset */ 1100 #define RMIXL_USB_UDC_GINTSTS 0x014 /* UDC Interrupt Register */ 1101 #define RMIXL_USB_UDC_GINTMSK 0x018 /* UDC Interrupt Mask Register */ 1102 #define RMIXL_USB_UDC_GRXSTSP 0x020 /* UDC Receive Status Read /Pop Register (Read Only) */ 1103 #define RMIXL_USB_UDC_GRXFSIZ 0x024 /* UDC Receive FIFO Size Register */ 1104 #define RMIXL_USB_UDC_GNPTXFSIZ 0x028 /* UDC Non-periodic Transmit FIFO Size Register */ 1105 #define RMIXL_USB_UDC_GUID 0x03C /* UDC User ID Register (UDC_GUID) */ 1106 #define RMIXL_USB_UDC_GSNPSID 0x040 /* UDC ID Register (Read Only) */ 1107 #define RMIXL_USB_UDC_GHWCFG1 0x044 /* UDC User HW Config1 Register (Read Only) */ 1108 #define RMIXL_USB_UDC_GHWCFG2 0x048 /* UDC User HW Config2 Register (Read Only) */ 1109 #define RMIXL_USB_UDC_GHWCFG3 0x04C /* UDC User HW Config3 Register (Read Only) */ 1110 #define RMIXL_USB_UDC_GHWCFG4 0x050 /* UDC User HW Config4 Register (Read Only) */ 1111 #define RMIXL_USB_UDC_DPTXFSIZ0 0x104 1112 #define RMIXL_USB_UDC_DPTXFSIZ1 0x108 1113 #define RMIXL_USB_UDC_DPTXFSIZ2 0x10c 1114 #define RMIXL_USB_UDC_DPTXFSIZn(n) (0x104 + (4 * (n))) 1115 /* UDC Device IN Endpoint Transmit FIFO-n 1116 Size Registers (UDC_DPTXFSIZn) */ 1117 #define RMIXL_USB_UDC_DCFG 0x800 /* UDC Configuration C */ 1118 #define RMIXL_USB_UDC_DCTL 0x804 /* UDC Control Register */ 1119 #define RMIXL_USB_UDC_DSTS 0x808 /* UDC Status Register (Read Only) */ 1120 #define RMIXL_USB_UDC_DIEPMSK 0x810 /* UDC Device IN Endpoint Common 1121 Interrupt Mask Register (UDC_DIEPMSK) */ 1122 #define RMIXL_USB_UDC_DOEPMSK 0x814 /* UDC Device OUT Endpoint Common Interrupt Mask register */ 1123 #define RMIXL_USB_UDC_DAINT 0x818 /* UDC Device All Endpoints Interrupt Register */ 1124 #define RMIXL_USB_UDC_DAINTMSK 0x81C /* UDC Device All Endpoints Interrupt Mask Register */ 1125 #define RMIXL_USB_UDC_DTKNQR3 0x830 /* Device Threshold Control Register */ 1126 #define RMIXL_USB_UDC_DTKNQR4 0x834 /* Device IN Endpoint FIFO Empty Interrupt Mask Register */ 1127 #define RMIXL_USB_UDC_DIEPCTL 0x900 /* Device Control IN Endpoint 0 Control Register */ 1128 #define RMIXL_USB_UDC_DIEPINT 0x908 /* Device IN Endpoint 0 Interrupt Register */ 1129 #define RMIXL_USB_UDC_DIEPTSIZ 0x910 /* Device IN Endpoint 0 Transfer Size Register */ 1130 #define RMIXL_USB_UDC_DIEPDMA 0x914 /* Device IN Endpoint 0 DMA Address Register */ 1131 #define RMIXL_USB_UDC_DTXFSTS 0x918 /* Device IN Endpoint Transmit FIFO Status Register */ 1132 #define RMIXL_USB_DEV_IN_ENDPT(d,n) (0x920 + ((d) * 0x20) + ((n) * 4)) 1133 /* Device IN Endpoint #d Register #n */ 1134 1135 /* 1136 * FMN non-core station configuration registers 1137 */ 1138 #define RMIXL_FMN_BS_FIRST _RMIXL_OFFSET(0x320) 1139 1140 /* 1141 * SGMII bucket size regs 1142 */ 1143 #define RMIXL_FMN_BS_SGMII_UNUSED0 _RMIXL_OFFSET(0x320) /* initialize as 0 */ 1144 #define RMIXL_FMN_BS_SGMII_FCB _RMIXL_OFFSET(0x321) /* Free Credit Bucket size */ 1145 #define RMIXL_FMN_BS_SGMII_TX0 _RMIXL_OFFSET(0x322) 1146 #define RMIXL_FMN_BS_SGMII_TX1 _RMIXL_OFFSET(0x323) 1147 #define RMIXL_FMN_BS_SGMII_TX2 _RMIXL_OFFSET(0x324) 1148 #define RMIXL_FMN_BS_SGMII_TX3 _RMIXL_OFFSET(0x325) 1149 #define RMIXL_FMN_BS_SGMII_UNUSED1 _RMIXL_OFFSET(0x326) /* initialize as 0 */ 1150 #define RMIXL_FMN_BS_SGMII_FCB1 _RMIXL_OFFSET(0x327) /* Free Credit Bucket1 size */ 1151 1152 /* 1153 * SAE bucket size regs 1154 */ 1155 #define RMIXL_FMN_BS_SAE_PIPE0 _RMIXL_OFFSET(0x320) 1156 #define RMIXL_FMN_BS_SAE_RSA_PIPE _RMIXL_OFFSET(0x321) 1157 1158 /* 1159 * DMA bucket size regs 1160 */ 1161 #define RMIXL_FMN_BS_DMA_CHAN0 _RMIXL_OFFSET(0x320) 1162 #define RMIXL_FMN_BS_DMA_CHAN1 _RMIXL_OFFSET(0x321) 1163 #define RMIXL_FMN_BS_DMA_CHAN2 _RMIXL_OFFSET(0x322) 1164 #define RMIXL_FMN_BS_DMA_CHAN3 _RMIXL_OFFSET(0x323) 1165 1166 /* 1167 * CDE bucket size regs 1168 */ 1169 #define RMIXL_FMN_BS_CDE_FREE_DESC _RMIXL_OFFSET(0x320) 1170 #define RMIXL_FMN_BS_CDE_COMPDECOMP _RMIXL_OFFSET(0x321) 1171 1172 /* 1173 * PCIe bucket size regs 1174 */ 1175 #define RMIXL_FMN_BS_PCIE_TX0 _RMIXL_OFFSET(0x320) 1176 #define RMIXL_FMN_BS_PCIE_RX0 _RMIXL_OFFSET(0x321) 1177 #define RMIXL_FMN_BS_PCIE_TX1 _RMIXL_OFFSET(0x322) 1178 #define RMIXL_FMN_BS_PCIE_RX1 _RMIXL_OFFSET(0x323) 1179 #define RMIXL_FMN_BS_PCIE_TX2 _RMIXL_OFFSET(0x324) 1180 #define RMIXL_FMN_BS_PCIE_RX2 _RMIXL_OFFSET(0x325) 1181 #define RMIXL_FMN_BS_PCIE_TX3 _RMIXL_OFFSET(0x326) 1182 #define RMIXL_FMN_BS_PCIE_RX3 _RMIXL_OFFSET(0x327) 1183 1184 /* 1185 * non-core Credit Counter offsets 1186 */ 1187 #define RMIXL_FMN_CC_FIRST _RMIXL_OFFSET(0x380) 1188 #define RMIXL_FMN_CC_LAST _RMIXL_OFFSET(0x3ff) 1189 1190 /* 1191 * non-core Credit Counter bit defines 1192 */ 1193 #define RMIXL_FMN_CC_RESV __BITS(31,8) 1194 #define RMIXL_FMN_CC_COUNT __BITS(7,0) 1195 1196 /* 1197 * USB Host Controller register base addrs 1198 * these are offset from REGSPACE selected by __BIT(12) == 0 1199 * RMIXL_IOREG_VADDR(RMIXL_IO_DEV_USB_A + reg) 1200 * see Table 18-14 in the XLS PRM 1201 * specific Host Controller is selected by __BITS(11,10) 1202 */ 1203 #define RMIXL_USB_HOST_EHCI_BASE 0x000 1204 #define RMIXL_USB_HOST_0HCI0_BASE 0x400 1205 #define RMIXL_USB_HOST_0HCI1_BASE 0x800 1206 #define RMIXL_USB_HOST_RESV 0xc00 1207 #define RMIXL_USB_HOST_MASK 0xc00 1208 1209 #define RMIXLP_SBC_PCITAG _RMIXL_PCITAG(0,0,0) 1210 #define RMIXLP_ICI1_PCITAG _RMIXL_PCITAG(0,0,1) 1211 #define RMIXLP_ICI2_PCITAG _RMIXL_PCITAG(0,0,2) 1212 #define RMIXLP_ICI3_PCITAG _RMIXL_PCITAG(0,0,3) 1213 #define RMIXLP_PIC_PCITAG _RMIXL_PCITAG(0,0,4) 1214 1215 #define RMIXLP_PCIPORT0_PCITAG _RMIXL_PCITAG(0,1,0) 1216 #define RMIXLP_PCIPORT1_PCITAG _RMIXL_PCITAG(0,1,1) 1217 #define RMIXLP_PCIPORT2_PCITAG _RMIXL_PCITAG(0,1,2) 1218 #define RMIXLP_PCIPORT3_PCITAG _RMIXL_PCITAG(0,1,3) 1219 1220 #define RMIXLP_EHCI0_PCITAG _RMIXL_PCITAG(0,2,0) 1221 #define RMIXLP_OHCI0_PCITAG _RMIXL_PCITAG(0,2,1) 1222 #define RMIXLP_OHCI1_PCITAG _RMIXL_PCITAG(0,2,2) 1223 #define RMIXLP_EHCI1_PCITAG _RMIXL_PCITAG(0,2,3) 1224 #define RMIXLP_OHCI2_PCITAG _RMIXL_PCITAG(0,2,4) 1225 #define RMIXLP_OHCI3_PCITAG _RMIXL_PCITAG(0,2,5) 1226 1227 #define RMIXLP_NAE_PCITAG _RMIXL_PCITAG(0,3,0) 1228 #define RMIXLP_POE_PCITAG _RMIXL_PCITAG(0,3,1) 1229 #define RMIXLP_AHCI_PCITAG _RMIXL_PCITAG(0,3,2) 1230 1231 #define RMIXLP_FMN_PCITAG _RMIXL_PCITAG(0,4,0) 1232 1233 #define RMIXLP_DMA_PCITAG _RMIXL_PCITAG(0,5,0) 1234 #define RMIXLP_SAE_PCITAG _RMIXL_PCITAG(0,5,1) 1235 #define RMIXLP_PKE_PCITAG _RMIXL_PCITAG(0,5,2) 1236 #define RMIXLP_CDE_PCITAG _RMIXL_PCITAG(0,5,3) 1237 #define RMIXLP_SRIO_PCITAG _RMIXL_PCITAG(0,5,4) 1238 #define RMIXLP_RXE_PCITAG _RMIXL_PCITAG(0,5,5) 1239 1240 #define RMIXLP_UART1_PCITAG _RMIXL_PCITAG(0,6,0) 1241 #define RMIXLP_UART2_PCITAG _RMIXL_PCITAG(0,6,1) 1242 #define RMIXLP_I2C1_PCITAG _RMIXL_PCITAG(0,6,2) 1243 #define RMIXLP_I2C2_PCITAG _RMIXL_PCITAG(0,6,3) 1244 #define RMIXLP_GPIO_PCITAG _RMIXL_PCITAG(0,6,4) 1245 #define RMIXLP_SM_PCITAG _RMIXL_PCITAG(0,6,5) 1246 #define RMIXLP_JTAG_PCITAG _RMIXL_PCITAG(0,6,6) 1247 1248 #define RMIXLP_NOR_PCITAG _RMIXL_PCITAG(0,7,0) 1249 #define RMIXLP_NAND_PCITAG _RMIXL_PCITAG(0,7,1) 1250 #define RMIXLP_SPI_PCITAG _RMIXL_PCITAG(0,7,2) 1251 #define RMIXLP_MMC_PCITAG _RMIXL_PCITAG(0,7,3) 1252 /* 1253 * PCI PCIe control (contains the IRT info) 1254 */ 1255 #define PCI_RMIXLP_OQCOUNT _RMIXL_OFFSET(0x30) 1256 #define PCI_RMIXLP_POE_FLOWS _RMIXL_OFFSET(0x30) 1257 #define PCI_RMIXLP_ONCHIP _RMIXL_OFFSET(0x31) 1258 #define PCI_RMIXLP_OFFCHIP _RMIXL_OFFSET(0x32) 1259 #define PCI_RMIXLP_CONTEXTS _RMIXL_OFFSET(0x35) 1260 #define PCI_RMIXLP_STATID _RMIXL_OFFSET(0x3c) 1261 #define PCI_RMIXLP_IRTINFO _RMIXL_OFFSET(0x3d) 1262 1263 #define PCI_RMIXLP_STATID_BASE(x) (((x) >> 0) & 0xfff) 1264 #define PCI_RMIXLP_STATID_COUNT(x) (((x) >> 16) & 0xfff) 1265 1266 #define PCI_RMIXLP_IRTINFO_BASE(x) (((x) >> 0) & 0xfff) 1267 #define PCI_RMIXLP_IRTINFO_COUNT(x) (((x) >> 16) & 0xfff) 1268 1269 /* 1270 * XLP PCIe Host Bridge (Device 0 Function 0) Registers 1271 */ 1272 #ifndef RMIXLP_SBC_PCIE_ECFG_PBASE 1273 #define RMIXLP_SBC_PCIE_ECFG_PBASE 0x18000000 1274 #endif 1275 #define RMIXLP_SBC_PCIE_ECFG_VBASE MIPS_PHYS_TO_KSEG1(RMIXLP_SBC_PCIE_ECFG_PBASE) 1276 #define RMIXLP_SBC_NBU_MODE _RMIXL_OFFSET(0x40) /* Memory I/O mode */ 1277 #define RMIXLP_SBC_PCIE_CFG_BASE _RMIXL_OFFSET(0x41) /* PCI Configuration BAR */ 1278 #define RMIXLP_SBC_PCIE_CFG_LIMIT _RMIXL_OFFSET(0x42) /* PCI Configuration Limit */ 1279 #define RMIXLP_SBC_PCIE_ECFG_BASE _RMIXL_OFFSET(0x43) /* PCI Extended Configuration BAR */ 1280 #define RMIXLP_SBC_PCIE_ECFG_LIMIT _RMIXL_OFFSET(0x44) /* PCI Extended Configuration Limit */ 1281 #define RMIXLP_SBC_BUSNUM_BARn(n) _RMIXL_OFFSET(0x45+(n)) /* Bus Number BAR reg */ 1282 #define RMIXLP_SBC_NBUSNUM_BAR 7 /* PCIe: 0-3, ICI: 4-7 */ 1283 #define RMIXLP_SBC_FLASH_BASEn(n) _RMIXL_OFFSET(0x4c+(n)) /* Flash Memory BAR */ 1284 #define RMIXLP_SBC_FLASH_LIMITn(n) _RMIXL_OFFSET(0x50+(n)) /* Flash Memory Limit reg */ 1285 #define RMIXLP_SBC_NFLASH 4 1286 #define RMIXLP_SBC_DRAM_BASEn(n) _RMIXL_OFFSET(0x54+(n)) /* DRAM[n] BAR */ 1287 #define RMIXLP_SBC_DRAM_LIMITn(n) _RMIXL_OFFSET(0x5c+(n)) /* DRAM[n] Limit */ 1288 #define RMIXLP_SBC_DRAM_XLATIONn(n) _RMIXL_OFFSET(0x6c+(n)) /* DRAM[n] Translation */ 1289 #define RMIXLP_SBC_NDRAM 8 1290 #define RMIXLP_SBC_PCIE_MEM_BASEn(n) _RMIXL_OFFSET(0x74+(n)) /* PCI Memory region BAR */ 1291 #define RMIXLP_SBC_PCIE_MEM_LIMITn(n) _RMIXL_OFFSET(0x78+(n)) /* PCI Memory region Limit */ 1292 #define RMIXLP_SBC_NPCIE_MEM 4 1293 #define RMIXLP_SBC_PCIE_IO_BASEn(n) _RMIXL_OFFSET(0x7c+(n)) /* PCI IO region BAR */ 1294 #define RMIXLP_SBC_PCIE_IO_LIMITn(n) _RMIXL_OFFSET(0x80+(n)) /* PCI IO region LimitAR */ 1295 #define RMIXLP_SBC_NPCIE_IO 4 1296 1297 #define _RMIXLP_SBC_X_TO_PA(x,r) \ 1298 ((uint64_t)((r) & RMIXLP_SBC_##x##_MASK) << 8) 1299 #define _RMIXLP_SBC_PA_TO_X(x,r) \ 1300 (((uint64_t)(r) >> 8) & RMIXLP_SBC_##x##_MASK) 1301 #define _RMIXLP_SBC_X_SIZE(x,b,l) \ 1302 ((l)-(b)+(__LOWEST_SET_BIT(RMIXLP_SBC_##x##_MASK) << 8)) 1303 1304 #define RMIXLP_SBC_DRAM_MASK __BITS(31,12) /* phys address bits 39:20 */ 1305 #define RMIXLP_SBC_PCIE_CFG_MASK __BITS(31,16) /* phys address bits 39:24 */ 1306 #define RMIXLP_SBC_PCIE_ECFG_MASK __BITS(31,12) /* phys address bits 39:20 */ 1307 #define RMIXLP_SBC_PCIE_MEM_MASK __BITS(31,12) /* phys address bits 39:20 */ 1308 #define RMIXLP_SBC_PCIE_IO_MASK __BITS(31,12) /* phys address bits 39:20 */ 1309 #define RMIXLP_SBC_SRIO_MEM_MASK __BITS(31,12) /* phys address bits 39:20 */ 1310 1311 #define RMIXLP_SBC_DRAM_SIZE(b,l) _RMIXLP_SBC_X_SIZE(DRAM,b,l) 1312 #define RMIXLP_SBC_PCIE_CFG_SIZE(b,l) _RMIXLP_SBC_X_SIZE(PCIE_CFG,b,l) 1313 #define RMIXLP_SBC_PCIE_ECFG_SIZE(b,l) _RMIXLP_SBC_X_SIZE(PCIE_ECFG,b,l) 1314 #define RMIXLP_SBC_PCIE_MEM_SIZE(b,l) _RMIXLP_SBC_X_SIZE(PCIE_MEM,b,l) 1315 #define RMIXLP_SBC_PCIE_IO_SIZE(b,l) _RMIXLP_SBC_X_SIZE(PCIE_IO,b,l) 1316 #define RMIXLP_SBC_SRIO_MEM_SIZE(b,l) _RMIXLP_SBC_X_SIZE(SRIO_MEM,b,l) 1317 1318 #define RMIXLP_SBC_DRAM_TO_PA(r) _RMIXLP_SBC_X_TO_PA(DRAM,r) 1319 #define RMIXLP_SBC_PCIE_CFG_TO_PA(r) _RMIXLP_SBC_X_TO_PA(PCIE_CFG,r) 1320 #define RMIXLP_SBC_PCIE_ECFG_TO_PA(r) _RMIXLP_SBC_X_TO_PA(PCIE_ECFG,r) 1321 #define RMIXLP_SBC_PCIE_MEM_TO_PA(r) _RMIXLP_SBC_X_TO_PA(PCIE_MEM,r) 1322 #define RMIXLP_SBC_PCIE_IO_TO_PA(r) _RMIXLP_SBC_X_TO_PA(PCIE_IO,r) 1323 #define RMIXLP_SBC_SRIO_MEM_TO_PA(r) _RMIXLP_SBC_X_TO_PA(SRIO_MEM,r) 1324 1325 #define RMIXLP_SBC_PA_TO_DRAM(r) _RMIXLP_SBC_PA_TO_X(DRAM,r) 1326 #define RMIXLP_SBC_PA_TO_PCIE_CFG(r) _RMIXLP_SBC_PA_TO_X(PCIE_CFG,r) 1327 #define RMIXLP_SBC_PA_TO_PCIE_ECFG(r) _RMIXLP_SBC_PA_TO_X(PCIE_ECFG,r) 1328 #define RMIXLP_SBC_PA_TO_PCIE_MEM(r) _RMIXLP_SBC_PA_TO_X(PCIE_MEM,r) 1329 #define RMIXLP_SBC_PA_TO_PCIE_IO(r) _RMIXLP_SBC_PA_TO_X(PCIE_IO,r) 1330 #define RMIXLP_SBC_PA_TO_SRIO_MEM(r) _RMIXLP_SBC_PA_TO_X(SRIO_MEM,r) 1331 1332 /* 1333 * For each PCIe link, its subordinate buses must be programed into its 1334 * BusNum_BAR register. This is in addition to the normal PCIe registers 1335 * on the PCIe link device itself. 1336 */ 1337 #define RMIXLP_SBC_BUSNUM_BAR_ENABLE __BIT(0) 1338 #define RMIXLP_SBC_BUSNUM_BAR_SECBUS __BITS(15,8) 1339 #define RMIXLP_SBC_BUSNUM_BAR_SUBBUS __BITS(23,16) 1340 #define RMIXLP_SBC_BUSNUM_BAR_MASK __BITS(23,8) 1341 1342 #define RMIXLP_SBC_EVCNT_CTRL1 _RMIXL_OFFSET(0x90) /* Event Counter 1 Control Register */ 1343 #define RMIXLP_SBC_EVCNT_LOW1 _RMIXL_OFFSET(0x91) /* Event Counter 1 Low Register */ 1344 #define RMIXLP_SBC_EVCNT_HIGH1 _RMIXL_OFFSET(0x92) /* Event Counter 1 High Register */ 1345 #define RMIXLP_SBC_EVCNT_CTRL2 _RMIXL_OFFSET(0x93) /* Event Counter 2 Control Register */ 1346 #define RMIXLP_SBC_EVCNT_LOW2 _RMIXL_OFFSET(0x94) /* Event Counter 2 Low Register */ 1347 #define RMIXLP_SBC_EVCNT_HIGH2 _RMIXL_OFFSET(0x95) /* Event Counter 2 High Register */ 1348 1349 #define RMIXLP_SBC_TRCBUF_MATCH_RQST0 _RMIXL_OFFSET(0x96) /* Trace Buffer Match Request Register 0 */ 1350 #define RMIXLP_SBC_TRCBUF_MATCH_RQST1 _RMIXL_OFFSET(0x97) /* Trace Buffer MAtch Request Register 1 */ 1351 #define RMIXLP_SBC_TRCBUF_MATCH_ADDRLO _RMIXL_OFFSET(0x98) /* Trace Buffer Match Request Address Low Register */ 1352 #define RMIXLP_SBC_TRCBUF_MATCH_ADDRHI _RMIXL_OFFSET(0x99) /* Trace Buffer Match Request Address High Register */ 1353 #define RMIXLP_SBC_TRCBUF_CTRL _RMIXL_OFFSET(0x9A) /* Trace Buffer Control Register */ 1354 #define RMIXLP_SBC_TRCBUF_INIT _RMIXL_OFFSET(0x9B) /* Trace Buffer Initialization Register */ 1355 #define RMIXLP_SBC_TRCBUF_ACCESS _RMIXL_OFFSET(0x9C) /* Trace Buffer Access Register */ 1356 #define RMIXLP_SBC_TRCBUF_READDATA(n) _RMIXL_OFFSET(0x9D+(n)) /* Trace Buffer Read Data Registers <0-3> */ 1357 #define RMIXLP_SBC_NTRCBUF_READDATA 4 1358 #define RMIXLP_SBC_TRCBUF_STATUS _RMIXL_OFFSET(0xA1) /* Trace Buffer Status Register */ 1359 1360 #define RMIXLP_SBC_ADDR_ERROR0 _RMIXL_OFFSET(0xA2) /* Address Error Register 0 */ 1361 #define RMIXLP_SBC_ADDR_ERROR1 _RMIXL_OFFSET(0xA3) /* Address Error Register 1 */ 1362 #define RMIXLP_SBC_ADDR_ERROR2 _RMIXL_OFFSET(0xA4) /* Address Error Register 2 */ 1363 #define RMIXLP_SBC_TAGECC_ADDR_ERROR0 _RMIXL_OFFSET(0xA5) /* Tag ECC Address Error Register 0 */ 1364 #define RMIXLP_SBC_TAGECC_ADDR_ERROR1 _RMIXL_OFFSET(0xA6) /* Tag ECC Address Error Register 1 */ 1365 #define RMIXLP_SBC_TAGECC_ADDR_ERROR2 _RMIXL_OFFSET(0xA7) /* Tag ECC Address Error Register 2 */ 1366 #define RMIXLP_SBC_LINE_FLUSH_LOW _RMIXL_OFFSET(0xA8) /* Line Flush Low Register */ 1367 #define RMIXLP_SBC_LINE_FLUSH_HIGH _RMIXL_OFFSET(0xA9) /* Line Flush High Register */ 1368 #define RMIXLP_SBC_NODE_ID _RMIXL_OFFSET(0xAA) /* Node ID Register */ 1369 #define RMIXLP_SBC_ERROR_INT_ENABLE _RMIXL_OFFSET(0xAB) /* Error Interrupt Enable Register */ 1370 #define RMIXLP_SBC_TIMEOUT_ERROR0 _RMIXL_OFFSET(0xAC) /* Timeout Error Register 0 */ 1371 #define RMIXLP_SBC_TIMEOUT_ERROR1 _RMIXL_OFFSET(0xAD) /* Timeout Error Register 1 */ 1372 #define RMIXLP_SBC_TIMEOUT_ERROR2 _RMIXL_OFFSET(0xAE) /* Timeout Error Register 2 */ 1373 #define RMIXLP_SBC_SRIO_MEM_BASE _RMIXL_OFFSET(0xAF) /* SRIO Memory Base Address Register */ 1374 #define RMIXLP_SBC_SRIO_MEM_LIMIT _RMIXL_OFFSET(0xB0) /* SRIO Memory Limit Address Register */ 1375 1376 /* 1377 * XLP L3 Cache Registers 1378 */ 1379 #define RMIXLP_SBC_L3_LINE_LCK0 _RMIXL_OFFSET(0xC0) 1380 #define RMIXLP_SBC_L3_LINE_LCK1 _RMIXL_OFFSET(0xC1) 1381 #define RMIXLP_SBC_L3_ACCESS_CMD _RMIXL_OFFSET(0xC2) 1382 #define RMIXLP_SBC_L3_ACCESS_ADDR _RMIXL_OFFSET(0xC3) 1383 #define RMIXLP_SBC_L3_ACCESS_DATA0 _RMIXL_OFFSET(0xC4) 1384 #define RMIXLP_SBC_L3_ACCESS_DATA1 _RMIXL_OFFSET(0xC5) 1385 #define RMIXLP_SBC_L3_ACCESS_DATA2 _RMIXL_OFFSET(0xC6) 1386 #define RMIXLP_SBC_L3_WAY_PART0 _RMIXL_OFFSET(0xC7) 1387 #define RMIXLP_SBC_L3_WAY_PART1 _RMIXL_OFFSET(0xC8) 1388 #define RMIXLP_SBC_L3_WAY_PART4 _RMIXL_OFFSET(0xCB) 1389 #define RMIXLP_SBC_L3_WAY_PART5 _RMIXL_OFFSET(0xCC) 1390 #define RMIXLP_SBC_L3_WAY_PART6 _RMIXL_OFFSET(0xCD) 1391 #define RMIXLP_SBC_L3_PERF_CTL_REG0 _RMIXL_OFFSET(0xCE) 1392 #define RMIXLP_SBC_L3_PERF_CNT_REG0 _RMIXL_OFFSET(0xCF) 1393 #define RMIXLP_SBC_L3_PERF_CTL_REG1 _RMIXL_OFFSET(0xD0) 1394 #define RMIXLP_SBC_L3_PERF_CNT_REG1 _RMIXL_OFFSET(0xD1) 1395 #define RMIXLP_SBC_L3_PERF_CTL_REG2 _RMIXL_OFFSET(0xD2) 1396 #define RMIXLP_SBC_L3_PERF_CNT_REG2 _RMIXL_OFFSET(0xD3) 1397 #define RMIXLP_SBC_L3_PERF_CTL_REG3 _RMIXL_OFFSET(0xD4) 1398 #define RMIXLP_SBC_L3_PERF_CNT_REG3 _RMIXL_OFFSET(0xD5) 1399 #define RMIXLP_SBC_L3_ERROR_INJ_CTL_REG0 _RMIXL_OFFSET(0xD6) 1400 #define RMIXLP_SBC_L3_ERROR_INJ_CTL_REG1 _RMIXL_OFFSET(0xD7) 1401 #define RMIXLP_SBC_L3_ERROR_INJ_CTL_REG2 _RMIXL_OFFSET(0xD8) 1402 #define RMIXLP_SBC_L3_ERROR_LOG_REG0 _RMIXL_OFFSET(0xD9) 1403 #define RMIXLP_SBC_L3_ERROR_LOG_REG1 _RMIXL_OFFSET(0xDA) 1404 #define RMIXLP_SBC_L3_ERROR_LOG_REG2 _RMIXL_OFFSET(0xDB) 1405 #define RMIXLP_SBC_L3_INTERRUPT_EN_REG _RMIXL_OFFSET(0xDC) 1406 1407 /* 1408 * XLP Time Slot Weight Registers 1409 */ 1410 #define RMIXLP_SBC_PCIE_LINK_TSW(n) _RMIXL_OFFSET(0x300+(n)) /* PCIe Link 0 Time Slot Weight Register */ 1411 #define RMIXLP_SBC_NPCIE_LINK_TSW 4 1412 #define RMIXLP_SBC_USB_TSW _RMIXL_OFFSET(0x304) /* USB Time Slot Weight Register */ 1413 #define RMIXLP_SBC_POE_TSW _RMIXL_OFFSET(0x305) /* Packet Ordering Engine Time Slot Weight Register */ 1414 #define RMIXLP_SBC_SATA_TSW _RMIXL_OFFSET(0x306) /* SATA Weight Register */ 1415 #define RMIXLP_SBC_SRIO_TSW _RMIXL_OFFSET(0x307) /* SRIO Weight Register */ 1416 #define RMIXLP_SBC_REGEX_TSW _RMIXL_OFFSET(0x308) /* RegEx Weight Register */ 1417 #define RMIXLP_SBC_GPIO_TSW _RMIXL_OFFSET(0x309) /* General I/O Time Slot Weight Register */ 1418 #define RMIXLP_SBC_FLASH_TSW _RMIXL_OFFSET(0x30A) /* Flash Time Slot Weight Register (NAND/NOR/SPI/MMC/SD) */ 1419 #define RMIXLP_SBC_NAE_TSW _RMIXL_OFFSET(0x30B) /* Network Acceleration Engine Time Slot Weight Register */ 1420 #define RMIXLP_SBC_FMN_TSW _RMIXL_OFFSET(0x30C) /* Fast Messaging Network Time Slot Weight Register */ 1421 #define RMIXLP_SBC_DMAENG_TSW _RMIXL_OFFSET(0x30D) /* Data Transfer and RAID Engine Slot Weight Register */ 1422 #define RMIXLP_SBC_SEC_TSW _RMIXL_OFFSET(0x30E) /* Security Engine Slot Weight Register */ 1423 #define RMIXLP_SBC_RSAECC_TSW _RMIXL_OFFSET(0x30F) /* RSA/ECC Engine Slot Weight Register */ 1424 #define RMIXLP_SBC_BRIDGE_DATA_COUNTER _RMIXL_OFFSET(0x310) /* Bridge Data Counter Register */ 1425 #define RMIXLP_SBC_BYTE_SWAP _RMIXL_OFFSET(0x311) /* Byte Swap Register */ 1426 1427 /* 1428 * RMIXLP PIC (device 0 function 4) registers 1429 * (all are 64-bit except when noted) 1430 */ 1431 #define RMIXLP_PIC_CTRL _RMIXL_OFFSET(0x40) 1432 #define RMIXLP_PIC_BYTESWAP _RMIXL_OFFSET(0x42) 1433 #define RMIXLP_PIC_STATUS _RMIXL_OFFSET(0x44) 1434 #define RMIXLP_PIC_INT_TIMEOUT _RMIXL_OFFSET(0x46) 1435 #define RMIXLP_PIC_ICI0_INT_TIMEOUT _RMIXL_OFFSET(0x48) 1436 /* nothing at 0x4a */ 1437 #define RMIXLP_PIC_IPI_CTRL _RMIXL_OFFSET(0x4e) 1438 #define RMIXLP_PIC_INT_ACK _RMIXL_OFFSET(0x50) 1439 #define RMIXLP_PIC_INT_PENDING0 _RMIXL_OFFSET(0x52) /* IRT 0..63 */ 1440 #define RMIXLP_PIC_INT_PENDING1 _RMIXL_OFFSET(0x54) /* IRT 64..127 */ 1441 #define RMIXLP_PIC_INT_PENDING2 _RMIXL_OFFSET(0x56) /* IRT 128..160 */ 1442 #define RMIXLP_PIC_WATCHDOG0_MAXVAL _RMIXL_OFFSET(0x58) 1443 #define RMIXLP_PIC_WATCHDOG0_COUNT _RMIXL_OFFSET(0x5a) 1444 #define RMIXLP_PIC_WATCHDOG0_ENABLE0 _RMIXL_OFFSET(0x5c) 1445 /* nothing at 0x5e */ 1446 #define RMIXLP_PIC_WATCHDOG0_BEATCMD _RMIXL_OFFSET(0x60) 1447 #define RMIXLP_PIC_WATCHDOG0_BEAT0 _RMIXL_OFFSET(0x62) 1448 #define RMIXLP_PIC_WATCHDOG0_BEAT1 _RMIXL_OFFSET(0x64) 1449 #define RMIXLP_PIC_WATCHDOG1_MAXVAL _RMIXL_OFFSET(0x66) 1450 #define RMIXLP_PIC_WATCHDOG1_COUNT _RMIXL_OFFSET(0x68) 1451 #define RMIXLP_PIC_WATCHDOG1_ENABLE _RMIXL_OFFSET(0x6a) 1452 /* nothing at 0x6c */ 1453 #define RMIXLP_PIC_WATCHDOG1_BEATCMD _RMIXL_OFFSET(0x6e) 1454 #define RMIXLP_PIC_WATCHDOG1_BEAT _RMIXL_OFFSET(0x70) 1455 /* nothing at 0x72 */ 1456 #define RMIXLP_PIC_SYSTEMTIMER_MAXVALUE(n) _RMIXL_OFFSET(0x74+2*(n)) 1457 #define RMIXLP_PIC_SYSTEMTIMER_COUNT(n) _RMIXL_OFFSET(0x84+2*(n)) 1458 #define RMIXLP_PIC_INT_THREAD_ENABLE01(n) _RMIXL_OFFSET(0x94+4*(n)) 1459 #define RMIXLP_PIC_INT_THREAD_ENABLE23(n) _RMIXL_OFFSET(0x96+4*(n)) 1460 #define RMIXLP_PIC_IRTENTRY(n) _RMIXL_OFFSET(0xb4+2*(n)) 1461 #define RMIXLP_PIC_INT_BROADCAST_ENABLE _RMIXL_OFFSET(0x292) /* 32-bit */ 1462 #define RMIXLP_PIC_INT_GPIO_PENDING _RMIXL_OFFSET(0x293) /* 32-bit */ 1463 1464 /* 1465 * RMIXLP_PIC_CTRL bits 1466 */ 1467 #define RMIXLP_PIC_CTRL_ITV __BITS(64,32) /* Interrupt Timeout Value */ 1468 #define RMIXLP_PIC_CTRL_STE __BITS(17,10) /* System Timer Enable */ 1469 #define RMIXLP_PIC_CTRL_WWR1 __BITS(9,8) /* Watchdog Wraparound Reset1 */ 1470 #define RMIXLP_PIC_CTRL_WWR0 __BITS(7,6) /* Watchdog Wraparound Reset0 */ 1471 #define RMIXLP_PIC_CTRL_WWN1 __BITS(5,4) /* Watchdog Wraparound NMI1 */ 1472 #define RMIXLP_PIC_CTRL_WWN0 __BITS(3,2) /* Watchdog Wraparound NMI0 */ 1473 #define RMIXLP_PIC_CTRL_WTE __BITS(1,0) /* Watchdog Timer Enable */ 1474 #define RMIXLP_PIC_CTRL_WTE1 __BIT(1) /* Watchdog Timer 1 Enable */ 1475 #define RMIXLP_PIC_CTRL_WTE0 __BIT(0) /* Watchdog Timer 0 Enable */ 1476 1477 /* 1478 * RMIXLP_PIC_STATUS bits 1479 */ 1480 #define RMIXLP_PIC_STATUS_ITE __BIT(32) /* Interrupt Timeout */ 1481 #define RMIXLP_PIC_STATUS_STS __BITS(11,4) /* SystemTimer */ 1482 #define RMIXLP_PIC_STATUS_WNS __BITS(3,2) /* Watchdog NMI Interrupt */ 1483 #define RMIXLP_PIC_STATUS_WIS __BITS(1,0) /* Watchdog Interrupt */ 1484 1485 /* 1486 * RMIXLP_PIC_INT_TIMEOUT and RMIXLP_PIC_ICI0_INT_TIMEOUT bits 1487 */ 1488 #define RMIXLP_PIC_IPI_TIMEOUT_INTPEND __BITS(51,36) /* ?? */ 1489 #define RMIXLP_PIC_IPI_TIMEOUT_INTNUM __BITS(35,28) /* IRT # */ 1490 #define RMIXLP_PIC_IPI_TIMEOUT_INTEN __BIT(27) /* Int Enable */ 1491 #define RMIXLP_PIC_IPI_TIMEOUT_INTVEC __BITS(25,20) /* Int Vector */ 1492 #define RMIXLP_PIC_IPI_TIMEOUT_INTCPU __BITS(19,16) /* Dest CPU */ 1493 #define RMIXLP_PIC_IPI_TIMEOUT_INTDEST __BITS(15,0) /* Dest */ 1494 1495 /* 1496 * RMIXLP_PIC_IPI_CTRL bits 1497 */ 1498 #define RMIXLP_PIC_IPI_CTRL_NMI __BIT(32) /* 1=NMI; 0=Maskable */ 1499 #define RMIXLP_PIC_IPI_CTRL_RIV __BITS(25,20) /* Which bit in EIRR */ 1500 #define RMIXLP_PIC_IPI_CTRL_DT __BITS(15,0) /* Dest Thread Enbs */ 1501 #define RMIXLP_PIC_IPI_CTRL_MAKE(nmi, tmask, tag) \ 1502 (__SHIFTIN((nmi), RMIXLP_PIC_IPI_CTRL_NMI) \ 1503 | __SHIFTIN((tag), RMIXLP_PIC_IPI_CTRL_RIV) \ 1504 | __SHIFTIN((tmask), RMIXLP_PIC_IPI_CTRL_DT)) 1505 1506 /* 1507 * RMIXLP_PIC_INT_ACK bits 1508 */ 1509 #define RMIXLP_PIC_INT_ACK_THREAD __BITS(11,8) /* Thr # if PicIntBrd */ 1510 #define RMIXLP_PIC_INT_ACK_ACK __BITS(7,0) /* IRT # */ 1511 1512 /* 1513 * RMIXLP_WATCHDOG_BEATCMD 1514 * 1515 * write 32 * node + 4 * cpu + thread (e.g. cpu_id) to set heartbeat. 1516 */ 1517 1518 /* 1519 * RMIXLP_PIC_INT_THREAD_ENABLE bits 1520 */ 1521 #define RMIXLP_PIC_INT_ITE __BITS(15,0) 1522 1523 /* 1524 * RMIXLP_PIC_IRTENTRY bits 1525 */ 1526 1527 /* bits 63-32 are reserved */ 1528 #define RMIXLP_PIC_IRTENTRY_EN __BIT(31) /* 1=Enable; 0=Disable */ 1529 #define RMIXLP_PIC_IRTENTRY_NMI __BIT(29) /* 1=NMI; 0=Maskable */ 1530 #define RMIXLP_PIC_IRTENTRY_LOCAL __BIT(28) /* 1=Local; 0=Global */ 1531 #define RMIXLP_PIC_IRTENTRY_INTVEC __BITS(25,20) /* maps to bit# in CPU's EIRR */ 1532 #define RMIXLP_PIC_IRTENTRY_DT __BIT(19) /* 1=ID; 0=ITE */ 1533 #define RMIXLP_PIC_IRTENTRY_DT_ID __SHIFTIN(1, RMIXLP_PIC_IRTENTRY_DT) 1534 #define RMIXLP_PIC_IRTENTRY_DT_ITE __SHIFTIN(0, RMIXLP_PIC_IRTENTRY_DT) 1535 #define RMIXLP_PIC_IRTENTRY_DB __BITS(18,16) /* NodeId/CpuID[2]; ITE# */ 1536 #define RMIXLP_PIC_IRTENTRY_ITE(n) __SHIFTIN((n), RMIXLP_PIC_IRTENTRY_DB) 1537 #define RMIXLP_PIC_IRTENTRY_DTE __BITS(15,0) /* Destination Thread Enables */ 1538 1539 /* 1540 * RMIXLP_PIC_INT_BROADCAST_ENABLE bits 1541 */ 1542 #define RMIXLP_PIC_INT_BROADCAST_ENABLE_PICINTBCMOD __BITS(27,16) 1543 #define RMIXLP_PIC_INT_BROADCAST_ENABLE_PICINTBCEN __BITS(11,0) 1544 1545 /* 1546 * RMIXLP_PIC_INT_GPIO_PENDING bits 1547 */ 1548 #define RMIXLP_PIC_INT_GPIO_PENDING_PICPENDB __BITS(11,0) 1549 1550 /* 1551 * PCIe Link (Device 1) Registers 1552 */ 1553 #define RMIXLP_PCIE_GEN2_CTL _RMIXL_OFFSET(0x203) 1554 #define RMIXLP_PCIE_CTL0 _RMIXL_OFFSET(0x240) 1555 #define RMIXLP_PCIE_CTL1 _RMIXL_OFFSET(0x241) 1556 #define RMIXLP_PCIE_PHY_ACC_CTL _RMIXL_OFFSET(0x242) 1557 #define RMIXLP_PCIE_PHY_ACC_DATA _RMIXL_OFFSET(0x243) 1558 #define RMIXLP_PCIE_PHY_BMI_TIMEOUT _RMIXL_OFFSET(0x244) 1559 #define RMIXLP_PCIE_PHY_BSI_TIMEOUT _RMIXL_OFFSET(0x245) 1560 #define RMIXLP_PCIE_BYTE_SWAP _RMIXL_OFFSET(0x246) 1561 #define RMIXLP_PCIE_BYTE_SWAP_MEM_BASE _RMIXL_OFFSET(0x247) 1562 #define RMIXLP_PCIE_BYTE_SWAP_MEM_LIMIT _RMIXL_OFFSET(0x248) 1563 #define RMIXLP_PCIE_BYTE_SWAP_IO_BASE _RMIXL_OFFSET(0x249) 1564 #define RMIXLP_PCIE_BYTE_SWAP_IO_LIMIT _RMIXL_OFFSET(0x24a) 1565 #define RMIXLP_PCIE_RDEX_MEM_BASE _RMIXL_OFFSET(0x24b) 1566 #define RMIXLP_PCIE_RDEX_MEM_LIMIT _RMIXL_OFFSET(0x24c) 1567 #define RMIXLP_PCIE_CACHE_ALLOC_BASE _RMIXL_OFFSET(0x24d) 1568 #define RMIXLP_PCIE_CACHE_ALLOC_LIMIT _RMIXL_OFFSET(0x24e) 1569 #define RMIXLP_PCIE_MSIX_BASE _RMIXL_OFFSET(0x24f) // EP 1570 #define RMIXLP_PCIE_MSIX_LIMIT _RMIXL_OFFSET(0x250) // EP 1571 #define RMIXLP_PCIE_ENTRY_0 _RMIXL_OFFSET(0x251) // EP 1572 #define RMIXLP_PCIE_ENTRY_1 _RMIXL_OFFSET(0x252) // EP 1573 #define RMIXLP_PCIE_ENTRY_2 _RMIXL_OFFSET(0x253) // EP 1574 #define RMIXLP_PCIE_ENTRY_3 _RMIXL_OFFSET(0x254) // EP 1575 #define RMIXLP_PCIE_ZERO_BYTE_READ _RMIXL_OFFSET(0x255) 1576 #define RMIXLP_PCIE_ZERO_BYTE_ADDR_LO _RMIXL_OFFSET(0x256) 1577 #define RMIXLP_PCIE_ZERO_BYTE_ADDR_HI _RMIXL_OFFSET(0x257) 1578 #define RMIXLP_PCIE_MSI_CMD _RMIXL_OFFSET(0x258) // EP 1579 #define RMIXLP_PCIE_MSI_ACK _RMIXL_OFFSET(0x259) // EP 1580 #define RMIXLP_PCIE_MSI_STAT _RMIXL_OFFSET(0x25a) // RC 1581 #define RMIXLP_PCIE_MSI_ENABLE _RMIXL_OFFSET(0x25b) // RC 1582 #define RMIXLP_PCIE_MSIX_PBA _RMIXL_OFFSET(0x25c) // EP 1583 #define RMIXLP_PCIE_MSIX_STAT _RMIXL_OFFSET(0x25d) // EP 1584 #define RMIXLP_PCIE_LTSSM _RMIXL_OFFSET(0x25e) 1585 #define RMIXLP_PCIE_INT_STAT0 _RMIXL_OFFSET(0x25f) 1586 #define RMIXLP_PCIE_INT_STAT1 _RMIXL_OFFSET(0x260) 1587 #define RMIXLP_PCIE_INT_ENAB0 _RMIXL_OFFSET(0x261) 1588 #define RMIXLP_PCIE_INT_ENAB1 _RMIXL_OFFSET(0x262) 1589 1590 #define RMIXLP_PCIE_GEN2_CTL_SPEED_CHNG __BIT(17) 1591 // Indicates to the LTSSM whether or not to initialize a speed change 1592 // to Gen2speed after the link is initialized at Gen1 speed. 1593 1594 #define RMIXLP_PCIE_CTL0_REL_ORD __BIT(31) 1595 #define RMIXLP_PCIE_CTL0_FAST_INIT __BIT(30) 1596 #define RMIXLP_PCIE_CTL0_ST_FLUSH __BIT(28) 1597 #define RMIXLP_PCIE_CTL0_LD_FLUSH __BIT(27) 1598 #define RMIXLP_PCIE_CTL0_ECC_DIS __BIT(26) 1599 #define RMIXLP_PCIE_CTL0_ADDR_MAP_EN __BIT(25) 1600 #define RMIXLP_PCIE_CTL0_BSI_TO __BIT(24) 1601 #define RMIXLP_PCIE_CTL0_BMI_TO __BIT(23) 1602 #define RMIXLP_PCIE_CTL0_SYS_INT __BIT(22) 1603 #define RMIXLP_PCIE_CTL0_CORE_CFG_MSG __BIT(21) 1604 #define RMIXLP_PCIE_CTL0_TO_EN __BIT(20) 1605 #define RMIXLP_PCIE_CTL0_PM_OFF __BIT(19) 1606 #define RMIXLP_PCIE_CTL0_EMIL __BIT(18) 1607 #define RMIXLP_PCIE_CTL0_CMD_COMP __BIT(17) 1608 #define RMIXLP_PCIE_CTL0_PRES_DET_CH __BIT(16) 1609 #define RMIXLP_PCIE_CTL0_MRL_SENSE_CH __BIT(15) 1610 #define RMIXLP_PCIE_CTL0_PWR_FIT_DET __BIT(14) 1611 #define RMIXLP_PCIE_CTL0_MRL_SENSE __BIT(13) 1612 #define RMIXLP_PCIE_CTL0_PRES_DET __BIT(12) 1613 #define RMIXLP_PCIE_CTL0_ATTN_BTN __BIT(11) 1614 #define RMIXLP_PCIE_CTL0_L1_EXIT __BIT(10) 1615 #define RMIXLP_PCIE_CTL0_L1_ENTR __BIT( 9) 1616 #define RMIXLP_PCIE_CTL0_AUX_PWR_DET __BIT( 8) 1617 #define RMIXLP_PCIE_CTL0_XMT_OME __BIT( 7) 1618 #define RMIXLP_PCIE_CTL0_PWR_UP_CMD __BIT( 6) 1619 #define RMIXLP_PCIE_CTL0_TX_FLIP __BIT( 5) 1620 #define RMIXLP_PCIE_CTL0_RX_FLIP __BIT( 4) 1621 #define RMIXLP_PCIE_CTL0_LTSS_EN __BIT( 3) 1622 #define RMIXLP_PCIE_CTL0_RET_EN __BIT( 2) 1623 #define RMIXLP_PCIE_CTL0_IRST __BIT( 1) 1624 #define RMIXLP_PCIE_CTL0_COR_EN __BIT( 0) 1625 1626 #define RMIXLP_PCIE_CTL1_PHY_RST __BIT(17) 1627 #define RMIXLP_PCIE_CTL1_LANE_7_CALIB __BITS(15,13) 1628 #define RMIXLP_PCIE_CTL1_LANE_6_CALIB __BITS(13,12) 1629 #define RMIXLP_PCIE_CTL1_LANE_5_CALIB __BITS(11,10) 1630 #define RMIXLP_PCIE_CTL1_LANE_4_CALIB __BITS( 9, 8) 1631 #define RMIXLP_PCIE_CTL1_LANE_3_CALIB __BITS( 7, 6) 1632 #define RMIXLP_PCIE_CTL1_LANE_2_CALIB __BITS( 5, 4) 1633 #define RMIXLP_PCIE_CTL1_LANE_1_CALIB __BITS( 3, 2) 1634 #define RMIXLP_PCIE_CTL1_LANE_0_CALIB __BITS( 1, 0) 1635 1636 #define RMIXLP_PCIE_PHY_ACC_CTL_PHYADDR __BITS(15, 8) 1637 #define RMIXLP_PCIE_PHY_ACC_CTL_PHYLANE __BITS( 7, 0) 1638 1639 #define RMIXLP_PCIE_LTSSM_STATE __BITS(23,18) 1640 #define RMIXLP_PCIE_LTSSM_PWR_STATE __BITS(17,15) 1641 #define RMIXLP_PCIE_LTSSM_DLL_UP __BITS(14) 1642 #define RMIXLP_PCIE_LTSSM_PHY_UP __BITS(13) 1643 #define RMIXLP_PCIE_LTSSM_BUS_DEV_NUM __BITS(12,8) // EP 1644 #define RMIXLP_PCIE_LTSSM_BUS_NUM __BITS(7,0) // EP 1645 1646 #define RMIXLP_PCIE_INT0_CLK_LOS __BIT(10) // loss of clock 1647 #define RMIXLP_PCIE_INT0_MSI __BIT( 9) // MSI interrupt 1648 #define RMIXLP_PCIE_INT0_BMI __BIT( 8) // bandwidth mgmt int 1649 #define RMIXLP_PCIE_INT0_ABSI __BIT( 7) // auto band mgmt int 1650 #define RMIXLP_PCIE_INT0_HPI __BIT( 6) // hot plug int 1651 #define RMIXLP_PCIE_INT0_PMEI __BIT( 5) // pme int 1652 #define RMIXLP_PCIE_INT0_AEI __BIT( 4) // advanced error int 1653 #define RMIXLP_PCIE_INT0_INTD __BIT( 3) // int d 1654 #define RMIXLP_PCIE_INT0_INTC __BIT( 2) // int c 1655 #define RMIXLP_PCIE_INT0_INTB __BIT( 1) // int b 1656 #define RMIXLP_PCIE_INT0_INTA __BIT( 0) // int a 1657 1658 #define RMIXLP_PCIE_INT1_BMI __BIT(23) // link down reset 1659 #define RMIXLP_PCIE_INT1_ABSI __BIT(22) // link down reset 1660 #define RMIXLP_PCIE_INT1_MBE_STORE __BIT(21) // link down reset 1661 #define RMIXLP_PCIE_INT1_MBE_LOAD __BIT(20) // link down reset 1662 #define RMIXLP_PCIE_INT1_SBE_STORE __BIT(19) // link down reset 1663 #define RMIXLP_PCIE_INT1_SBE_LOAD __BIT(18) // link down reset 1664 #define RMIXLP_PCIE_INT1_DMA_STORE __BIT(17) // link down reset 1665 #define RMIXLP_PCIE_INT1_DMA_LOAD __BIT(16) // link down reset 1666 #define RMIXLP_PCIE_INT1_BSIC2 __BIT(15) // link down reset 1667 #define RMIXLP_PCIE_INT1_BSIC1 __BIT(14) // link down reset 1668 #define RMIXLP_PCIE_INT1_BSIC0 __BIT(13) // link down reset 1669 #define RMIXLP_PCIE_INT1_BMIC __BIT(12) // link down reset 1670 #define RMIXLP_PCIE_INT1_TO_RX __BIT(11) // link down reset 1671 #define RMIXLP_PCIE_INT1_TO_ACK __BIT(10) // link down reset 1672 #define RMIXLP_PCIE_INT1_PME_RX __BIT( 9) // link down reset 1673 #define RMIXLP_PCIE_INT1_FATAL __BIT( 8) // link down reset 1674 #define RMIXLP_PCIE_INT1_NON_FATAL __BIT( 7) // link down reset 1675 #define RMIXLP_PCIE_INT1_CORE __BIT( 6) // link down reset 1676 #define RMIXLP_PCIE_INT1_PME_MSI __BIT( 5) // link down reset 1677 #define RMIXLP_PCIE_INT1_AE_MSI __BIT( 4) // link down reset 1678 #define RMIXLP_PCIE_INT1_HP_MSI __BIT( 3) // link down reset 1679 #define RMIXLP_PCIE_INT1_HP_PME __BIT( 2) // link down reset 1680 #define RMIXLP_PCIE_INT1_SYS __BIT( 1) // system error 1681 #define RMIXLP_PCIE_INT1_RST __BIT( 0) // link down reset 1682 1683 /* 1684 * RMIXLP USB (Device 2) Registers 1685 */ 1686 1687 #define RMIXLP_USB_CTL0 _RMIXL_OFFSET(0x41) 1688 #define RMIXLP_USB_BYTE_SWAP_DIS _RMIXL_OFFSET(0x49) 1689 #define RMIXLP_USB_PHY0 _RMIXL_OFFSET(0x4A) 1690 1691 #define RMIXLP_USB_CTL0_BIUTOEN __BIT(8) 1692 #define RMIXLP_USB_CTL0_INCR4 __BIT(7) 1693 #define RMIXLP_USB_CTL0_INCR8 __BIT(6) 1694 #define RMIXLP_USB_CTL0_INCR16 __BIT(5) 1695 #define RMIXLP_USB_CTL0_0HCIINT12 __BIT(4) 1696 #define RMIXLP_USB_CTL0_0HCIINT1 __BIT(3) 1697 #define RMIXLP_USB_CTL0_0HCISTRTCLK __BIT(2) 1698 #define RMIXLP_USB_CTL0_EHCI64BEN __BIT(1) 1699 #define RMIXLP_USB_CTL0_USBCTLRRST __BIT(0) 1700 1701 #define RMIXLP_USB_PHY0_PHYTXBSENH1 __BIT(11) 1702 #define RMIXLP_USB_PHY0_PHYTXBSTENH0 __BIT(10) 1703 #define RMIXLP_USB_PHY0_PHYTXBSENL1 __BIT(9) 1704 #define RMIXLP_USB_PHY0_PHYTXBSENL0 __BIT(8) 1705 #define RMIXLP_USB_PHY0_PHYLBEN1 __BIT(7) 1706 #define RMIXLP_USB_PHY0_PHYLBEN0 __BIT(6) 1707 #define RMIXLP_USB_PHY0_PHYPORTRST1 __BIT(5) 1708 #define RMIXLP_USB_PHY0_PHYPORTRST0 __BIT(4) 1709 #define RMIXLP_USB_PHY0_PHYREFCLKFREQ __BITS(3,2) 1710 #define RMIXLP_USB_PHY0_PHYDETVBUS __BIT(1) 1711 #define RMIXLP_USB_PHY0_USBPHYRESET __BIT(0) 1712 1713 #define RMIXLP_USB_INTERRUPTEN _RMIXL_OFFSET(0x4f) 1714 #define RMIXLP_USB_INTERRUPTEN_BIUTO1_INTEN \ 1715 __BIT(6) 1716 #define RMIXLP_USB_INTERRUPTEN_BIUTO0_INTEN \ 1717 __BIT(5) 1718 #define RMIXLP_USB_INTERRUPTEN_INTEN __BIT(4) 1719 #define RMIXLP_USB_INTERRUPTEN_OHCIINT12_EN \ 1720 __BIT(3) 1721 #define RMIXLP_USB_INTERRUPTEN_OHCIINT1_EN \ 1722 __BIT(2) 1723 #define RMIXLP_USB_INTERRUPTEN_OHCIEMUL_INTEN \ 1724 __BIT(1) 1725 #define RMIXLP_USB_INTERRUPTEN_PHY_INTEN \ 1726 __BIT(0) 1727 1728 /* 1729 * XLP AHCI (deivce 3 function 2) 1730 */ 1731 #define RMIXLP_SATA_BYTE_SWAP_DIS _RMIXL_OFFSET(0x25D) 1732 1733 /* 1734 * XLP FMN (device 4 function 0) BAR0 register space 1735 */ 1736 #define RMIXLP_FMN_OQ_CONFIG(n) _RMIXL_OFFSET(2*(n)) 1737 #define RMIXLP_FMN_OQ_CREDIT_CONFIG _RMIXL_OFFSET(0x800) 1738 #define RMIXLP_FMN_MSG_CONF _RMIXL_OFFSET(0x801) 1739 #define RMIXLP_FMN_MSG_ERR _RMIXL_OFFSET(0x802) 1740 #define RMIXLP_FMN_TRACE_CONF _RMIXL_OFFSET(0x803) 1741 #define RMIXLP_FMN_TRACE_ADDR_CONF0 _RMIXL_OFFSET(0x804) 1742 #define RMIXLP_FMN_TRACE_ADDR_CONF1 _RMIXL_OFFSET(0x805) 1743 #define RMIXLP_FMN_TRACE_ADDR_CONF2 _RMIXL_OFFSET(0x806) 1744 #define RMIXLP_FMN_MSG_SWAP _RMIXL_OFFSET(0x807) 1745 #define RMIXLP_FMN_MSG_TIMEOUT _RMIXL_OFFSET(0x808) 1746 #define RMIXLP_FMN_MSG_OQ_RESET _RMIXL_OFFSET(0x809) 1747 #define RMIXLP_FMN_MSG_OQ_ERR_INJECT _RMIXL_OFFSET(0x80a) 1748 #define RMIXLP_FMN_MSG_OQ_EVENT_CTL _RMIXL_OFFSET(0x80b) 1749 #define RMIXLP_FMN_MSG_OQ_EVENT_CNT _RMIXL_OFFSET(0x80c) 1750 1751 #define RMIXLP_FMN_OQ_CONFIG_OE __BIT(63) // 1: Output Enable 1752 #define RMIXLP_FMN_OQ_CONFIG_SE __BIT(62) // 1: Spill Enable 1753 /* INT, LV, LT, TV, TT are valid only for OQ[0..255] */ 1754 #define RMIXLP_FMN_OQ_CONFIG_INT __BIT(59) // 1: Interrupt generated 1755 #define RMIXLP_FMN_OQ_CONFIG_LV __BITS(58,56) // Level Interrupt Value 1756 #define RMIXLP_FMN_OQ_CONFIG_LV_EMTPY 0 // On-chip queue empty 1757 #define RMIXLP_FMN_OQ_CONFIG_LV_1QTR 1 // On-chip queue 1/4 full 1758 #define RMIXLP_FMN_OQ_CONFIG_LV_HALF 2 // On-chip queue half full 1759 #define RMIXLP_FMN_OQ_CONFIG_LV_3QTR 3 // On-chip queue 3/4 full 1760 #define RMIXLP_FMN_OQ_CONFIG_LV_FULL 4 // On-chip queue full 1761 #define RMIXLP_FMN_OQ_CONFIG_LT __BITS(55,54) // Level Interrupt Type 1762 #define RMIXLP_FMN_OQ_CONFIG_LT_DISABLE 0 // Disable 1763 #define RMIXLP_FMN_OQ_CONFIG_LT_LOW 1 // Low watermark 1764 #define RMIXLP_FMN_OQ_CONFIG_LT_HIGH 2 // High watermark 1765 #define RMIXLP_FMN_OQ_CONFIG_TV __BITS(53,51) // Timer Interrupt Value 1766 #define RMIXLP_FMN_OQ_CONFIG_TV_256 0 // 2^8 clock cycles 1767 #define RMIXLP_FMN_OQ_CONFIG_TV_1K 1 // 2^10 clock cycles 1768 #define RMIXLP_FMN_OQ_CONFIG_TV_4K 2 // 2^12 clock cycles 1769 #define RMIXLP_FMN_OQ_CONFIG_TV_16K 3 // 2^14 clock cycles 1770 #define RMIXLP_FMN_OQ_CONFIG_TV_64K 4 // 2^16 clock cycles 1771 #define RMIXLP_FMN_OQ_CONFIG_TV_256K 5 // 2^18 clock cycles 1772 #define RMIXLP_FMN_OQ_CONFIG_TV_1M 6 // 2^20 clock cycles 1773 #define RMIXLP_FMN_OQ_CONFIG_TV_4M 7 // 2^22 clock cycles 1774 #define RMIXLP_FMN_OQ_CONFIG_TT __BITS(50,49) // Timer Interrupt Type 1775 #define RMIXLP_FMN_OQ_CONFIG_TT_DISABLE 0 // Disable 1776 #define RMIXLP_FMN_OQ_CONFIG_TT_CONSUMER 1 // Since last dequeue 1777 #define RMIXLP_FMN_OQ_CONFIG_TT_PRODUCER 2 // Since last enqueue 1778 /* These are valid for all output-queues */ 1779 /* Min/Max of 64B/256KB per queue */ 1780 #define RMIXLP_FMN_OQ_CONFIG_SB __BITS(48,27) // Spill Base PA[39:18] 1781 #define RMIXLP_FMN_OQ_CONFIG_SL __BITS(26,21) // Spill Last PA[17:12] 1782 #define RMIXLP_FMN_OQ_CONFIG_SS __BITS(20,15) // Spill Start PA[17:12] 1783 /* Min/Max of 32B/1KB per queue */ 1784 #define RMIXLP_FMN_OQ_CONFIG_OB __BITS(14,10) // OQ Base SRAM[14:10] 1785 #define RMIXLP_FMN_OQ_CONFIG_OL __BITS( 9, 5) // OQ Last SRAM[9:5] 1786 #define RMIXLP_FMN_OQ_CONFIG_OS __BITS( 4, 0) // OQ Start SRAM[9:5] 1787 1788 #define RMIXLP_FMN_OQ_CREDIT_CONFIG_UNCR_ECC_ERR \ 1789 __BIT(41) // Error Inject 1790 #define RMIXLP_FMN_OQ_CREDIT_CONFIG_CR_ECC_ERR \ 1791 __BIT(40) // Error Inject 1792 #define RMIXLP_FMN_OQ_CREDIT_CONFIG_CC __BITS(39,24) // Credit Count 1793 // The number of output-queue credits to assign to the source 1794 // identified by the SID field, where the output queue is identified 1795 // by the DID field. 1796 #define RMIXLP_FMN_OQ_CREDIT_CONFIG_DID __BITS(23,12) // Destination ID 1797 // Identifies the output queue for which credits are being allocated. 1798 #define RMIXLP_FMN_OQ_CREDIT_CONFIG_SID __BITS(9,0) // Source ID 1799 // Identifies the agent on the local node to be allocated credits. 1800 // Bits corresponding to Thread-Id and VC-Id are ignored for CPUs. 1801 // For I/O blocks, only the base ID can be allocated credits. 1802 // The user must make sure that the programmed source ID is legal. 1803 1804 #define RMIXLP_FMN_MSG_CONF_SH __BIT(63) // 1: Switch Halt 1805 #define RMIXLP_FMN_MSG_CONF_DAS __BITS(62,60) // Debug Address Space 1806 #define RMIXLP_FMN_MSG_CONF_DAS_OQ_STATUS 0 1807 #define RMIXLP_FMN_MSG_CONF_DAS_OQ_RAM 1 1808 #define RMIXLP_FMN_MSG_CONF_DAS_SPILL_FILL_ADDR_RAM 2 1809 #define RMIXLP_FMN_MSG_CONF_OMR __BITS(59,54) // OqRamAddr[18:13] 1810 #define RMIXLP_FMN_MSG_CONF_L3TW __BIT(18) // L3 on Trace Writes 1811 #define RMIXLP_FMN_MSG_CONF_L3S __BIT(17) // L3 on Spill 1812 #define RMIXLP_FMN_MSG_CONF_PS __BIT(16) // 1: Switch Halt 1813 #define RMIXLP_FMN_MSG_CONF_FF __BIT(9) // Fill FIFO Error IntEn 1814 #define RMIXLP_FMN_MSG_CONF_ID __BIT(8) // Ill Dest Error IntEn 1815 #define RMIXLP_FMN_MSG_CONF_BT __BIT(7) // BIU Timeout Error IntEn 1816 #define RMIXLP_FMN_MSG_CONF_BE __BIT(6) // BIU Error Response IntEn 1817 #define RMIXLP_FMN_MSG_CONF_SU __BIT(5) // SpillFillAddrRAM UnECC IntEn 1818 #define RMIXLP_FMN_MSG_CONF_SC __BIT(4) // SpillFillAddrRAM CorECC IntE 1819 #define RMIXLP_FMN_MSG_CONF_BU __BIT(3) // SpillBuffer UnECC IntEn 1820 #define RMIXLP_FMN_MSG_CONF_BC __BIT(2) // SpillBuffer CorECC IntEn 1821 #define RMIXLP_FMN_MSG_CONF_OU __BIT(1) // OqRAM UnECC IntEn 1822 #define RMIXLP_FMN_MSG_CONF_OC __BIT(0) // OqRAM CorECC IntEn 1823 #define RMIXLP_RMN_MSG_CONF_FATAL \ 1824 (RMIXLP_FMN_MSG_CONF_OU | RMIXLP_FMN_MSG_CONF_BU \ 1825 | RMIXLP_FMN_MSG_CONF_SU | RMIXLP_FMN_MSG_CONF_BT \ 1826 | RMIXLP_FMN_MSG_CONF_BE) 1827 1828 #define RMIXLP_FMN_MSG_ERR_RI __BITS(58,44) // 1829 #define RMIXLP_FMN_MSG_ERR_RI_OQ_RAM_INDEX \ 1830 __BITS(58,47) // 1831 #define RMIXLP_FMN_MSG_ERR_RI_OQ_RAM_BANK \ 1832 __BITS(46,44) // 1833 #define RMIXLP_FMN_MSG_ERR_RI_SPILL_FILL_ADDR_RAM_INDEX \ 1834 __BITS(53,44) // 1835 #define RMIXLP_FMN_MSG_ERR_RI_SPILL_BUFFER_RAM_INDEX \ 1836 __BITS(53,46) // 1837 #define RMIXLP_FMN_MSG_ERR_RI_SPILL_BUFFER_RAM_BANK \ 1838 __BITS(45,44) // 1839 #define RMIXLP_FMN_MSG_ERR_SD_OQ_RAM __BITS(40,32) // 1840 #define RMIXLP_FMN_MSG_ERR_SD_SPILL_FILL_ADDR_RAM \ 1841 __BITS(39,32) // 1842 #define RMIXLP_FMN_MSG_ERR_SD_SPILL_BUFFER_RAM \ 1843 __BITS(28,32) // 1844 #define RMIXLP_FMN_MSG_ERR_OQID __BITS(27,16) // OutputQueue ID 1845 #define RMIXLP_FMN_MSG_ERR_EC __BITS(15,12) // Error Code [ID..OC] 1846 #define RMIXLP_FMN_MSG_ERR_FF __BIT(9) // Fill FIFO Error Error 1847 #define RMIXLP_FMN_MSG_ERR_ID __BIT(8) // Ill Dest Error Error 1848 #define RMIXLP_FMN_MSG_ERR_BT __BIT(7) // BIU Timeout Error Error 1849 #define RMIXLP_FMN_MSG_ERR_BE __BIT(6) // BIU Error Response Error 1850 #define RMIXLP_FMN_MSG_ERR_SU __BIT(5) // SpillFillAddrRAM UnECC Error 1851 #define RMIXLP_FMN_MSG_ERR_SC __BIT(4) // SpillFillAddrRAM CorECC Err 1852 #define RMIXLP_FMN_MSG_ERR_BU __BIT(3) // SpillBuffer UnECC Error 1853 #define RMIXLP_FMN_MSG_ERR_BC __BIT(2) // SpillBuffer CorECC Error 1854 #define RMIXLP_FMN_MSG_ERR_OU __BIT(1) // OqRAM UnECC Error 1855 #define RMIXLP_FMN_MSG_ERR_OC __BIT(0) // OqRAM CorECC Error 1856 1857 /* 1858 * RMIXLP GPIO (device 6 function 4) registers 1859 */ 1860 #define RMIXLP_GPIO_PADOE(g) _RMIXL_OFFSET(0x40+(g)) // Pad Output Enable Register 0 1861 #define RMIXLP_GPIO_PADOE0 _RMIXL_OFFSET(0x40) // Pad Output Enable Register 0 1862 #define RMIXLP_GPIO_PADOE1 _RMIXL_OFFSET(0x41) // Pad Output Enable Register 1 1863 #define RMIXLP_GPIO_PADDRV(g) _RMIXL_OFFSET(0x42+(g)) // Pad Drive Register 0 1864 #define RMIXLP_GPIO_PADDRV0 _RMIXL_OFFSET(0x42) // Pad Drive Register 0 1865 #define RMIXLP_GPIO_PADDRV1 _RMIXL_OFFSET(0x43) // Pad Drive Register 1 1866 #define RMIXLP_GPIO_PADSAMPLE(g) _RMIXL_OFFSET(0x44+(g)) // Pad Sample Register 0 1867 #define RMIXLP_GPIO_PADSAMPLE0 _RMIXL_OFFSET(0x44) // Pad Sample Register 0 1868 #define RMIXLP_GPIO_PADSAMPLE1 _RMIXL_OFFSET(0x45) // Pad Sample Register 1 1869 #define RMIXLP_GPIO_INTEN(n,g) _RMIXL_OFFSET(0x46+2*(n)+(g)) // Interrupt 0 Enable Register 0 1870 #define RMIXLP_GPIO_INTEN0(n) _RMIXL_OFFSET(0x46+2*(n)) // Interrupt 0 Enable Register 0 1871 #define RMIXLP_GPIO_INTEN1(n) _RMIXL_OFFSET(0x47+2*(n)) // Interrupt 0 Enable Register 0 1872 #define RMIXLP_GPIO_8XX_INTPOL(g) _RMIXL_OFFSET((0x4E)+(g)) // Interrupt Polarity Register 0 1873 #define RMIXLP_GPIO_8XX_INTTYPE(g) _RMIXL_OFFSET(0x50+(g)) // Interrupt Type Register 0 1874 #define RMIXLP_GPIO_8XX_INTSTAT(g) _RMIXL_OFFSET(0x52+(g)) // Interrupt Status Register 0 1875 #define RMIXLP_GPIO_3XX_INTPOL(g) _RMIXL_OFFSET((0x5E)+(g)) // Interrupt Polarity Register 0 1876 #define RMIXLP_GPIO_3XX_INTTYPE(g) _RMIXL_OFFSET(0x60+(g)) // Interrupt Type Register 0 1877 #define RMIXLP_GPIO_3XX_INTSTAT(g) _RMIXL_OFFSET(0x62+(g)) // Interrupt Status Register 0 1878 1879 #define RMIXLP_GPIO_8XX_MAXPINS 41 /* 41 GPIO pins */ 1880 #define RMIXLP_GPIO_4XX_MAXPINS 41 /* 41 GPIO pins */ 1881 #define RMIXLP_GPIO_3XX_MAXPINS 57 /* 41 GPIO pins */ 1882 #define RMIXLP_GPIO_3XXL_MAXPINS 44 /* 44 GPIO pins */ 1883 #define RMIXLP_GPIO_2XXL_MAXPINS 42 /* 42 GPIO pins */ 1884 1885 /* 1886 * XLP System Management (device 6 function 5) Registers 1887 */ 1888 #define RMIXLP_SM_CHIP_RESET _RMIXL_OFFSET(0x40) 1889 #define RMIXLP_SM_POWER_ON_RESET_CFG _RMIXL_OFFSET(0x41) 1890 #define RMIXLP_SM_EFUSE_DEVICE_CFG_STATUS0 _RMIXL_OFFSET(0x42) 1891 #define RMIXLP_SM_EFUSE_DEVICE_CFG_STATUS1 _RMIXL_OFFSET(0x43) 1892 1893 #define RMIXLP_SM_POWER_ON_RESET_CFG_CPLL_DFS __BITS(31,30) 1894 #define RMIXLP_SM_POWER_ON_RESET_CFG_I2LR __BIT(29) 1895 #define RMIXLP_SM_POWER_ON_RESET_CFG_I1LR __BIT(28) 1896 #define RMIXLP_SM_POWER_ON_RESET_CFG_I0LR __BIT(27) 1897 #define RMIXLP_SM_POWER_ON_RESET_CFG_TS __BIT(26) 1898 #define RMIXLP_SM_POWER_ON_RESET_CFG_CPM_2XX __BITS(31,26) /* 2XX */ 1899 #define RMIXLP_SM_POWER_ON_RESET_CFG_UM __BIT(25) 1900 #define RMIXLP_SM_POWER_ON_RESET_CFG_PLC __BITS(24,23) 1901 #define RMIXLP_SM_POWER_ON_RESET_CFG_PM __BITS(22,19) 1902 #define RMIXLP_SM_POWER_ON_RESET_CFG_SPM_2XX __BITS(25,20) /* 2XX */ 1903 #define RMIXLP_SM_POWER_ON_RESET_CFG_RCS_2XX __BITS(19,18) /* 2XX */ 1904 #define RMIXLP_SM_POWER_ON_RESET_CFG_CDV __BITS(18,17) 1905 #define RMIXLP_SM_POWER_ON_RESET_CFG_CDF __BITS(16,10) 1906 #define RMIXLP_SM_POWER_ON_RESET_CFG_PM_2XX __BITS(13,8) /* 2XX */ 1907 #define RMIXLP_SM_POWER_ON_RESET_CFG_CDR __BITS(9,8) 1908 #define RMIXLP_SM_POWER_ON_RESET_CFG_MC __BIT(7) 1909 #define RMIXLP_SM_POWER_ON_RESET_CFG_RB __BIT(6) 1910 #define RMIXLP_SM_POWER_ON_RESET_CFG_BE __BIT(5) 1911 #define RMIXLP_SM_POWER_ON_RESET_CFG_NORSP __BIT(4) 1912 #define RMIXLP_SM_POWER_ON_RESET_CFG_BD __BITS(3,0) 1913 1914 /* 1915 * RMIXLP NOR (device 7 function 0) 1916 */ 1917 #define RMIXLP_NOR_NCS 8 1918 #define RMIXLP_NOR_CS_BASEADDRESSn(n) _RMIXL_OFFSET(0x40+(n)) 1919 #define RMIXLP_NOR_CS_BASELIMITn(n) _RMIXL_OFFSET(0x48+(n)) 1920 #define RMIXLP_NOR_CS_DEVPARMn(n) _RMIXL_OFFSET(0x50+(n)) 1921 #define RMIXLP_NOR_CS_DEVTIME0n(n) _RMIXL_OFFSET(0x58+2*(n)) 1922 #define RMIXLP_NOR_CS_DEVTIME1n(n) _RMIXL_OFFSET(0x59+2*(n)) 1923 #define RMIXLP_NOR_SYSCTRL _RMIXL_OFFSET(0x68) 1924 #define RMIXLP_NOR_BYTESWAP _RMIXL_OFFSET(0x69) 1925 #define RMIXLP_NOR_ERRLOG0 _RMIXL_OFFSET(0x6a) 1926 #define RMIXLP_NOR_ERRLOG1 _RMIXL_OFFSET(0x6b) 1927 #define RMIXLP_NOR_ERRLOG2 _RMIXL_OFFSET(0x6c) 1928 #define RMIXLP_NOR_ID_TIMEOUT_VAL _RMIXL_OFFSET(0x6d) 1929 #define RMIXLP_NOR_INSTAT _RMIXL_OFFSET(0x6e) 1930 #define RMIXLP_NOR_INTEN _RMIXL_OFFSET(0x6f) 1931 #define RMIXLP_NOR_STATUS _RMIXL_OFFSET(0x70) 1932 1933 #define RMIXLP_NOR_CS_ADDRESS_TO_PA(r) ((uint64_t)(r) << 8) 1934 #define RMIXLP_NOR_PA_TO_CS_ADDRESS(r) ((uint64_t)(r) >> 8) 1935 #define RMIXLP_NOR_CS_SIZE(b,l) ((l)-(b)+256) 1936 1937 // Interface Byte signal Enable. 1938 // 0: Disables programmable data width selection 1939 // 1: Enables programmable data width selection 1940 #define RMIXLP_NOR_CS_DEVPARM_BE __BIT(16) 1941 // Little Endian. 1942 // 0:Big Endian 1943 // 1:Little Endian 1944 #define RMIXLP_NOR_CS_DEVPARM_LE __BIT(13) 1945 #define RMIXLP_NOR_CS_DEVPARM_DW __BITS(12,11) // Device Data Width 1946 #define RMIXLP_NOR_CS_DEVPARM_DW_8_BITS 0 1947 #define RMIXLP_NOR_CS_DEVPARM_DW_16_BITS 1 1948 #define RMIXLP_NOR_CS_DEVPARM_DW_32_BITS 2 1949 // Multiplexed/non-multiplexed device data/address mode 1950 // 0:Non-multiplexed (only valid if field DW is set to 0) 1951 // 1:Multiplexed data and address bus 1952 #define RMIXLP_NOR_CS_DEVPARM_MUX __BIT(10) 1953 // Wait/Ready signal Polarity 1954 // 0:Wait active high 1955 // 1:Wait active low 1956 #define RMIXLP_NOR_CS_DEVPARM_WRP __BIT(9) 1957 // Wait/ready signal Write interface Enable. 1958 // Enables/disables wait-acknowledge mode during write cycles. 1959 // 0: Enable device Wait mode. External IO_WAIT_L signal is used. 1960 // 1: Disable Wait mode; external IO_WAIT_L signal is not used. 1961 #define RMIXLP_NOR_CS_DEVPARM_WWE __BIT(8) 1962 // Wait/Ready signal Read interface Enable. 1963 // Enables/disables wait-acknowledge mode during read cycles. 1964 // 0: Enable device Wait mode. External IO_WAIT_L signal is used. 1965 // 1: Disable Wait mode; external IO_WAIT_L signal is not used. 1966 // This signal is distinct from the RYBY (Ready/Busy) signal, 1967 // which is shared by all Flash devices. 1968 #define RMIXLP_NOR_CS_DEVPARM_WRE __BIT(7) 1969 // Synchronous Read Data Burst Enabled (when set to 1). 1970 #define RMIXLP_NOR_CS_DEVPARM_SRDBE __BIT(5) 1971 // Word-align Address. 1972 // If set to 1, address bits are word-aligned. 1973 // This allows address bits of a 16-bit Flash device to connect to XLP 1974 // address bits [24:1] instead of [23:0] or the address bits of a 32-bit 1975 // Flash device to connect to XLP address bits [25:2] instead of [23:0]. 1976 #define RMIXLP_NOR_CS_DEVPARM_WA __BIT(2) 1977 #define RMIXLP_NOR_CS_DEVPARM_FLASH_TYPE __BITS(1,0) // Flash Type 1978 #define RMIXLP_NOR_CS_DEVPARM_FLASH_TYPE_NOR 0 // NOR Flash 1979 #define RMIXLP_NOR_CS_DEVPARM_FLASH_TYPE_ONCHIP 1 // On-chip ROM 1980 1981 // CS to CS timing. 1982 // This field indicates the number of clock cycles from the falling 1983 // edge of IO_CSn to the next falling edge of IO_CSn, where n = 0-7. 1984 #define RMIXLP_NOR_DEVTIME0_CS_TO_CS __BITS(31,28) 1985 1986 // WE to CS timing. 1987 // This field indicates the number of clock cycles from the rising 1988 // edge of IO_WE_L to the rising edge of IO_CSn_L. 1989 #define RMIXLP_NOR_DEVTIME0_WE_TO_CS __BITS(27,24) 1990 1991 // OE to CS timing. 1992 // This field indicates the number of clock cycles from the rising 1993 // edge of IO_OE_L to the rising edge of IO_CSn_L. 1994 #define RMIXLP_NOR_DEVTIME0_OE_TO_CS __BITS(23,22) 1995 1996 // CS to WE timing. 1997 // This field indicates the number of clock cycles from the falling 1998 // edge of IO_CSn_L to the falling edge of IO_WE_L 1999 #define RMIXLP_NOR_DEVTIME0_CS_TO_WE __BITS(21,19) 2000 2001 // CS to OE timing. 2002 // This field indicates the number of clock cycles from the falling 2003 // edge of IO_CSn_L to the falling edge of IO_OE_L. 2004 #define RMIXLP_NOR_DEVTIME0_CS_TO_OE __BITS(18,16) 2005 2006 // Wait/Ready to Data timing. 2007 // This field indicates the number of clock cycles from the falling 2008 // edge of IO_WE_L to when data is available on a write, or the 2009 // falling edge of IO_OE_L to when date is available on a read. 2010 #define RMIXLP_NOR_DEVTIME0_WAIT_TO_DATA __BITS(15,11) 2011 2012 // OE to Wait timing. 2013 // This field indicates the IO_WE_L to wait time on a write, 2014 // or the IO_OE_L to wait time on a read. 2015 #define RMIXLP_NOR_DEVTIME0_OE_TO_WAIT __BITS(10,6) 2016 2017 // ALE to CS timing. 2018 // This field indicates the number of clock cycles from the falling 2019 // edge of IO_ALE to the falling edge of IO_CSn_L. This field is 2020 // encoded as follows: 2021 #define RMIXLP_NOR_DEVTIME0_ALE_TO_CS ___BITS(5,3) 2022 // 000: IO_CSn_L is one cycle ahead of IO_ALE. 2023 #define RMIXLP_NOR_DEVTIME0_ALE_TO_CS_AHEAD1 0 2024 // 001: IO_CSn_L is aligned with IO_ALE. 2025 #define RMIXLP_NOR_DEVTIME0_ALE_TO_CS_ALIGNED 1 2026 // 010-111: IO_ALE is ahead of IO_CSn_L. 2027 #define RMIXLP_NOR_DEVTIME0_ALE_TO_CS_BEHIND1 2 2028 #define RMIXLP_NOR_DEVTIME0_ALE_TO_CS_BEHIND2 3 2029 #define RMIXLP_NOR_DEVTIME0_ALE_TO_CS_BEHIND3 4 2030 #define RMIXLP_NOR_DEVTIME0_ALE_TO_CS_BEHIND4 5 2031 #define RMIXLP_NOR_DEVTIME0_ALE_TO_CS_BEHIND5 6 2032 #define RMIXLP_NOR_DEVTIME0_ALE_TO_CS_BEHIND6 7 2033 2034 // ALE pulse width. 2035 // This field indicates the number of clock cycles from the falling 2036 // edge of IO_ALE to the rising edge of IO_ALE. 2037 #define RMIXLP_NOR_DEVTIME0_ALE_WIDTH __BITS(2,0) 2038 2039 #define RMIXLP_NOR_DEVTIME1_WAIT_TIMEOUT __BITS(26,12) 2040 // Wait Timeout. 2041 // If the Interrupt is an error, the Enable bit is set. 2042 2043 // RDY/BSY signal Polarity: 2044 // 0:Ready low, busy high 2045 // 1:Ready high, busy low 2046 // This signal is shared by all Flash devices. If any of the devices 2047 // puts the signal into the busy state, this signal will indicate 2048 // not-ready (busy) status. 2049 #define RMIXLP_NOR_SYSCTRL_RDYBSY_POL __BIT(1) 2050 2051 // Interconnect Timeout Enable (if set to 1). 2052 #define RMIXLP_NOR_SYSCTRL_ITE __BIT(0) 2053 2054 // RDY/BSY pin transition, if set to 1. 2055 #define RMIXLP_NOR_INTSTAT_RDYBSY __BIT(0) 2056 2057 // Error Log. Setting this bit enables error logging. 2058 #define RMIXLP_NOR_INTEN_EL __BIT(1) 2059 // RYBY Interrupt Enable. Setting this bit enables NOR Flash interrupts. 2060 #define RMIXLP_NOR_INTEN_RDYBSY __BIT(0) 2061 2062 // RDY/BSY Status. 1: NOR device is ready. 2063 #define RMIXLP_NOR_STATUS_RDYBSY __BIT(0) 2064 2065 /* 2066 * RMIXLP NAND (device 7 function 1) 2067 */ 2068 #define RMIXLP_NAND_RDYBSY_SEL _RMIXL_OFFSET(0x81) 2069 2070 /* 2071 * RMIXLP SPI (device 7 function 2) 2072 */ 2073 #define RMIXLP_SPI_CS_CONFIG(n) _RMIXL_OFFSET(0x40+0x10*(n)) 2074 #define RMIXLP_SPI_CS_FDIV(n) _RMIXL_OFFSET(0x41+0x10*(n)) 2075 #define RMIXLP_SPI_CS_CMD(n) _RMIXL_OFFSET(0x42+0x10*(n)) 2076 #define RMIXLP_SPI_CS_STATUS(n) _RMIXL_OFFSET(0x43+0x10*(n)) 2077 #define RMIXLP_SPI_CS_INTEN(n) _RMIXL_OFFSET(0x44+0x10*(n)) 2078 #define RMIXLP_SPI_CS_FIFO_THRESH(n) _RMIXL_OFFSET(0x45+0x10*(n)) 2079 #define RMIXLP_SPI_CS_FIFO_WCNT(n) _RMIXL_OFFSET(0x46+0x10*(n)) 2080 #define RMIXLP_SPI_CS_TXDATA_FIFO(n) _RMIXL_OFFSET(0x47+0x10*(n)) 2081 #define RMIXLP_SPI_CS_RXDATA_FIFO(n) _RMIXL_OFFSET(0x48+0x10*(n)) 2082 #define RMIXLP_SPI_SYSCNTRL _RMIXL_OFFSET(0x80) 2083 2084 #define RMIXLP_SPI_CS_CONFIG_RXCAP __BIT(11) // RX capture on phase drive 2085 #define RMIXLP_SPI_CS_CONFIG_LSBFE __BIT(10) // LSB first enable 2086 #define RMIXLP_SPI_CS_CONFIG_CSTODATA __BITS(9,8) // chip select polarity 1:high 2087 #define RMIXLP_SPI_CS_CONFIG_SBPOL __BIT(6) // start bit polarity 1:high 2088 #define RMIXLP_SPI_CS_CONFIG_SBE __BIT(6) // start bit enable 1:enabled 2089 #define RMIXLP_SPI_CS_CONFIG_RXMISO __BIT(5) // 0: RX MOSI, 1: RX MISO 2090 #define RMIXLP_SPI_CS_CONFIG_TXMOSI __BIT(4) // 1: TX enable for MOSI pin 2091 #define RMIXLP_SPI_CS_CONFIG_TXMISO __BIT(3) // 1: TX enable for MISO pin 2092 #define RMIXLP_SPI_CS_CONFIG_CSPOL __BIT(2) // chip select polarity 1:high 2093 #define RMIXLP_SPI_CS_CONFIG_CPOL __BIT(1) // clock polarity 1:high 2094 #define RMIXLP_SPI_CS_CONFIG_CPHA __BIT(0) // SPI_CLK clock phase select 2095 2096 #define RMIXLP_SPI_CS_FDIV_CNT __BITS(15,0) // divisor (min of 16) 2097 2098 #define RMIXLP_SPI_CS_CMD_XFERBITCNT __BITS(31,16) // total # of bits - 1 2099 #define RMIXLP_SPI_CS_CMD_CONT __BIT(4) 2100 #define RMIXLP_SPI_CS_CMD_CMD __BITS(3,0) 2101 #define RMIXLP_SPI_CS_CMD_IDLE 0 2102 #define RMIXLP_SPI_CS_CMD_TX 1 2103 #define RMIXLP_SPI_CS_CMD_RX 2 2104 #define RMIXLP_SPI_CS_CMD_TXRX 3 2105 2106 #define RMIXLP_SPI_CS_STATUS_RXOF __BIT(5) // RX FIFO overflow 2107 #define RMIXLP_SPI_CS_STATUS_TXUF __BIT(4) // TX FIFO underflow 2108 #define RMIXLP_SPI_CS_STATUS_RXTHRESH __BIT(3) // RX FIFO threshold crossed 2109 #define RMIXLP_SPI_CS_STATUS_TXTHRESH __BIT(2) // TX FIFO threshold crossed 2110 #define RMIXLP_SPI_CS_STATUS_XFERDONE __BIT(1) // Transfer is complete (RO) 2111 #define RMIXLP_SPI_CS_STATUS_XFERPEND __BIT(1) // Transfer is pending (RO) 2112 2113 #define RMIXLP_SPI_CS_INTEN_RXOF __BIT(4) // RX FIFO overflow 2114 #define RMIXLP_SPI_CS_INTEN_TXUF __BIT(3) // TX FIFO underflow 2115 #define RMIXLP_SPI_CS_INTEN_RXTHRESH __BIT(2) // RX FIFO threshold crossed 2116 #define RMIXLP_SPI_CS_INTEN_TXTHRESH __BIT(1) // TX FIFO threshold crossed 2117 #define RMIXLP_SPI_CS_INTEN_XFERDONE __BIT(0) // Transfer is complete 2118 2119 #define RMIXLP_SPI_CS_FIFO_THRESH_TXFIFO __BITS(7,4) 2120 #define RMIXLP_SPI_CS_FIFO_THRESH_RXFIFO __BITS(3,0) 2121 2122 #define RMIXLP_SPI_CS_FIFO_WCNT_TXFIFO __BITS(7,4) 2123 #define RMIXLP_SPI_CS_FIFO_WCNT_RXFIFO __BITS(3,0) 2124 2125 #define RMIXLP_SPI_SYSCNTRL_PMEN __BIT(8) // Pin muxing enable 2126 #define RMIXLP_SPI_SYSCNTRL_CLKDSI(n) __BIT(4+(n)) // Clock disable for chan 2127 #define RMIXLP_SPI_SYSCNTRL_RESET(n) __BIT(0+(n)) // Reset SPI channel n 2128 2129 #define RMIXLP_SPI_GPIO_PINS __BITS(28,22) 2130 2131 /* 2132 * RMIXLP SD/MMC (device 7 function 3) 2133 */ 2134 #define RMIXLP_MMC_SLOTSIZE _RMIXL_OFFSET(0x40) 2135 2136 #define RMIXLP_MMC_SLOT0 _RMIXL_OFFSET(0x40) 2137 #define RMIXLP_MMC_SLOT1 _RMIXL_OFFSET(0x80) 2138 #define RMIXLP_MMC_SYSCTRL _RMIXL_OFFSET(0xC0) 2139 #define RMIXLP_MMC_CAPCFG0_S(n) _RMIXL_OFFSET(0xC1+5*(n)) 2140 #define RMIXLP_MMC_CAPCFG1_S(n) _RMIXL_OFFSET(0xC2+5*(n)) 2141 #define RMIXLP_MMC_INIT_PRESET_S(n) _RMIXL_OFFSET(0xC3+5*(n)) 2142 #define RMIXLP_MMC_DEF_PRESET_S(n) _RMIXL_OFFSET(0xC4+5*(n)) 2143 2144 #define RMIXLP_MMC_SYSCTRL_DELAY __BITS(21,19) 2145 #define RMIXLP_MMC_SYSCTRL_RT __BIT(8) 2146 #define RMIXLP_MMC_SYSCTRL_WP1 __BIT(7) 2147 #define RMIXLP_MMC_SYSCTRL_WP0 __BIT(6) 2148 #define RMIXLP_MMC_SYSCTRL_RD_EX __BIT(5) 2149 #define RMIXLP_MMC_SYSCTRL_CA __BIT(4) 2150 #define RMIXLP_MMC_SYSCTRL_EN1 __BIT(3) 2151 #define RMIXLP_MMC_SYSCTRL_EN0 __BIT(2) 2152 #define RMIXLP_MMC_SYSCTRL_EN(n) __BIT(2+(n)) 2153 #define RMIXLP_MMC_SYSCTRL_CLK_DIS __BIT(1) 2154 #define RMIXLP_MMC_SYSCTRL_RST __BIT(0) 2155 2156 #define RMIXLP_MMC_CAPCFG0_S_EMB __BIT(17) // Extended Media Bus 2157 2158 #define RMIXLP_MMC_GPIO_PINS0 \ 2159 (__BITS(10,0) | __BIT(29) | __BIT(31)) 2160 #define RMIXLP_MMC_GPIO_PINS1 \ 2161 (__BITS(21,11) | __BIT(28) | __BIT(30)) 2162 #define RMIXLP_MMC_GPIO_PINS(slot) \ 2163 (slot == 0 ? RMIXLP_MMC_GPIO_PINS0 : RMIXLP_MMC_GPIO_PINS1) 2164 2165 #endif /* _MIPS_RMI_RMIXLREG_H_ */ 2166
Indexes created Wed Oct 29 18:09:52 GMT 2025