rmixlreg.h revision 1.2
1 /* $NetBSD: rmixlreg.h,v 1.2 2009/12/14 00:46:08 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by CCCCCCCC NNNNNNNNNN 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 33 #ifndef _MIPS_RMI_RMIXLREGS_H_ 34 #define _MIPS_RMI_RMIXLREGS_H_ 35 36 #include <sys/endian.h> 37 38 /* 39 * on chip I/O register byte order is 40 * BIG ENDIAN regardless of code model 41 */ 42 #define RMIXL_IOREG_VADDR(o) \ 43 (volatile uint32_t *)MIPS_PHYS_TO_KSEG1( \ 44 rmixl_configuration.rc_io_pbase + (o)) 45 #define RMIXL_IOREG_READ(o) be32toh(*RMIXL_IOREG_VADDR(o)) 46 #define RMIXL_IOREG_WRITE(o,v) *RMIXL_IOREG_VADDR(o) = htobe32(v) 47 48 49 /* 50 * RMIXL Coprocessor 2 registers: 51 */ 52 #ifdef _LOCORE 53 #define _(n) __CONCAT($,n) 54 #else 55 #define _(n) n 56 #endif 57 /* #sels --------------+ */ 58 /* #regs -----------+ | */ 59 /* What: #bits --+ | | */ 60 /* v v v */ 61 #define RMIXL_COP_2_TXBUF _(0) /* Transmit Buffers 64 [1][4] */ 62 #define RMIXL_COP_2_RXBUF _(1) /* Receive Buffers 64 [1][4] */ 63 #define RMIXL_COP_2_MSG_STS _(2) /* Mesage Status 32 [1][2] */ 64 #define RMIXL_COP_2_MSG_CFG _(3) /* MEssage Config 32 [1][2] */ 65 #define RMIXL_COP_2_MSG_BSZ _(4) /* Message Bucket Size 32 [1][8] */ 66 #define RMIXL_COP_2_CREDITS _(16) /* Credit Counters 32 [16][8] */ 67 68 /* CP2 bit defines TBD */ 69 70 /* 71 * RMIXL Processor Control Register addresses 72 * - Offset in bits 7..0 73 * - BlockID in bits 15..8 74 */ 75 #define RMIXL_PCR_THREADEN 0x0000 76 #define RMIXL_PCR_SOFTWARE_SLEEP 0x0001 77 #define RMIXL_PCR_SCHEDULING 0x0002 78 #define RMIXL_PCR_SCHEDULING_COUNTERS 0x0003 79 #define RMIXL_PCR_BHRPM 0x0004 80 #define RMIXL_PCR_IFU_DEFEATURE 0x0006 81 #define RMIXL_PCR_ICU_DEFEATURE 0x0100 82 #define RMIXL_PCR_ICU_ERROR_LOGGING 0x0101 83 #define RMIXL_PCR_ICU_DEBUG_ACCESS_ADDR 0x0102 84 #define RMIXL_PCR_ICU_DEBUG_ACCESS_DATALO 0x0103 85 #define RMIXL_PCR_ICU_DEBUG_ACCESS_DATAHI 0x0104 86 #define RMIXL_PCR_ICU_SAMPLING_LFSR 0x0105 87 #define RMIXL_PCR_ICU_SAMPLING_PC 0x0106 88 #define RMIXL_PCR_ICU_SAMPLING_SETUP 0x0107 89 #define RMIXL_PCR_ICU_SAMPLING_TIMER 0x0108 90 #define RMIXL_PCR_ICU_SAMPLING_PC_UPPER 0x0109 91 #define RMIXL_PCR_IEU_DEFEATURE 0x0200 92 #define RMIXL_PCR_TARGET_PC_REGISTER 0x0207 93 #define RMIXL_PCR_L1D_CONFIG0 0x0300 94 #define RMIXL_PCR_L1D_CONFIG1 0x0301 95 #define RMIXL_PCR_L1D_CONFIG2 0x0302 96 #define RMIXL_PCR_L1D_CONFIG3 0x0303 97 #define RMIXL_PCR_L1D_CONFIG4 0x0304 98 #define RMIXL_PCR_L1D_STATUS 0x0305 99 #define RMIXL_PCR_L1D_DEFEATURE 0x0306 100 #define RMIXL_PCR_L1D_DEBUG0 0x0307 101 #define RMIXL_PCR_L1D_DEBUG1 0x0308 102 #define RMIXL_PCR_L1D_CACHE_ERROR_LOG 0x0309 103 #define RMIXL_PCR_L1D_CACHE_ERROR_OVF_LO 0x030A 104 #define RMIXL_PCR_L1D_CACHE_INTERRUPT 0x030B 105 #define RMIXL_PCR_MMU_SETUP 0x0400 106 #define RMIXL_PCR_PRF_SMP_EVENT 0x0500 107 #define RMIXL_PCR_RF_SMP_RPLY_BUF 0x0501 108 109 /* PCR bit defines TBD */ 110 111 112 /* 113 * Memory Distributed Interconnect (MDI) System Memory Map 114 */ 115 #define RMIXL_PHYSADDR_MAX 0xffffffffffLL /* 1TB Physical Address space */ 116 #define RMIXL_IO_DEV_PBASE 0x1ef00000 /* default phys. from XL[RS]_IO_BAR */ 117 #define RMIXL_IO_DEV_VBASE MIPS_PHYS_TO_KSEG1(RMIXL_IO_DEV_PBASE) 118 /* default virtual base address */ 119 #define RMIXL_IO_DEV_SIZE 0x100000 /* I/O Conf. space is 1MB region */ 120 121 122 123 /* 124 * Peripheral and I/O Configuration Region of Memory 125 * 126 * These are relocatable; we run using the reset value defaults, 127 * and we expect to inherit those intact from the boot firmware. 128 * 129 * Many of these overlap between XLR and XLS, exceptions are ifdef'ed. 130 * 131 * Device region offsets are relative to RMIXL_IO_DEV_PBASE. 132 */ 133 #define RMIXL_IO_DEV_BRIDGE 0x00000 /* System Bridge Controller (SBC) */ 134 #define RMIXL_IO_DEV_DDR_CHNA 0x01000 /* DDR1/DDR2 DRAM_A Channel, Port MA */ 135 #define RMIXL_IO_DEV_DDR_CHNB 0x02000 /* DDR1/DDR2 DRAM_B Channel, Port MB */ 136 #define RMIXL_IO_DEV_DDR_CHNC 0x03000 /* DDR1/DDR2 DRAM_C Channel, Port MC */ 137 #define RMIXL_IO_DEV_DDR_CHND 0x04000 /* DDR1/DDR2 DRAM_D Channel, Port MD */ 138 #if defined(MIPS64_XLR) 139 #define RMIXL_IO_DEV_SRAM 0x07000 /* SRAM Controller, Port SA */ 140 #endif /* MIPS64_XLR */ 141 #define RMIXL_IO_DEV_PIC 0x08000 /* Programmable Interrupt Controller */ 142 #if defined(MIPS64_XLR) 143 #define RMIXL_IO_DEV_PCIX 0x09000 /* PCI-X */ 144 #define RMIXL_IO_DEV_HT 0x0a000 /* HyperTransport */ 145 #endif /* MIPS64_XLR */ 146 #define RMIXL_IO_DEV_SAE 0x0b000 /* Security Acceleration Engine */ 147 #if defined(MIPS64_XLS) 148 #define XAUI Interface_0 0x0c000 /* XAUI Interface_0 */ 149 /* when SGMII Interface_[0-3] are not used */ 150 #endif /* MIPS64_XLS */ 151 #define RMIXL_IO_DEV_GMAC_A 0x0c000 /* RGMII-Interface_A, Port RA */ 152 #define RMIXL_IO_DEV_GMAC_B 0x0d000 /* RGMII-Interface_B, Port RB */ 153 #define RMIXL_IO_DEV_GMAC_C 0x0e000 /* RGMII-Interface_C, Port RC */ 154 #define RMIXL_IO_DEV_GMAC_D 0x0f000 /* RGMII-Interface_D, Port RD */ 155 #if defined(MIPS64_XLR) 156 #define RMIXL_IO_DEV_SPI4_A 0x10000 /* SPI-4.2-Interface_A, Port XA */ 157 #define RMIXL_IO_DEV_XGMAC_A 0x11000 /* XGMII-Interface_A, Port XA */ 158 #define RMIXL_IO_DEV_SPI4_B 0x12000 /* SPI-4.2-Interface_B, Port XB */ 159 #define RMIXL_IO_DEV_XGMAC_B 0x13000 /* XGMII-Interface_B, Port XB */ 160 #endif /* MIPS64_XLR */ 161 #define RMIXL_IO_DEV_UART_1 0x14000 /* UART_1 (16550 w/ ax4 addrs) */ 162 #define RMIXL_IO_DEV_UART_2 0x15000 /* UART_2 (16550 w/ ax4 addrs) */ 163 #define RMIXL_IO_DEV_I2C_1 0x16000 /* I2C_1 */ 164 #define RMIXL_IO_DEV_I2C_2 0x17000 /* I2C_2 */ 165 #define RMIXL_IO_DEV_GPIO 0x18000 /* GPIO */ 166 #define RMIXL_IO_DEV_FLASH 0x19000 /* Flash ROM */ 167 #define RMIXL_IO_DEV_DMA 0x1a000 /* DMA */ 168 #define RMIXL_IO_DEV_L2 0x1b000 /* L2 Cache */ 169 #define RMIXL_IO_DEV_TB 0x1c000 /* Trace Buffer */ 170 #if defined(MIPS64_XLS) 171 #define RMIXL_IO_DEV_CMP 0x1d000 /* Compression/Decompression */ 172 #define RMIXL_IO_DEV_PCIE_BE 0x1e000 /* PCI-Express_BE */ 173 #define RMIXL_IO_DEV_PCIE_LE 0x1f000 /* PCI-Express_LE */ 174 #define RMIXL_IO_DEV_SRIO_BE 0x1e000 /* SRIO_BE */ 175 #define RMIXL_IO_DEV_SRIO_LE 0x1f000 /* SRIO_LE */ 176 #define RMIXL_IO_DEV_XAUI_1 0x20000 /* XAUI Interface_1 */ 177 /* when SGMII Interface_[4-7] are not used */ 178 #define RMIXL_IO_DEV_GMAC_4 0x20000 /* SGMII-Interface_4, Port SGMII4 */ 179 #define RMIXL_IO_DEV_GMAC_5 0x21000 /* SGMII-Interface_5, Port SGMII5 */ 180 #define RMIXL_IO_DEV_GMAC_6 0x22000 /* SGMII-Interface_6, Port SGMII6 */ 181 #define RMIXL_IO_DEV_GMAC_7 0x23000 /* SGMII-Interface_7, Port SGMII7 */ 182 #define RMIXL_IO_DEV_USB_A 0x24000 /* USB Interface Low Address Space */ 183 #define RMIXL_IO_DEV_USB_B 0x25000 /* USB Interface High Address Space */ 184 #endif /* MIPS64_XLS */ 185 186 187 /* 188 * the Programming Reference Manual 189 * lists "Reg ID" values not offsets; 190 * offset = id * 4 191 */ 192 #define _RMIXL_OFFSET(id) ((id) * 4) 193 194 195 /* 196 * System Bridge Controller registers 197 * offsets are relative to RMIXL_IO_DEV_BRIDGE 198 */ 199 #define RMIXL_SBC_DRAM_NBARS 8 200 #define RMIXL_SBC_DRAM_BAR(n) _RMIXL_OFFSET(0x000 + (n)) 201 /* DRAM Region Base Address Regs[0-7] */ 202 #define RMIXL_SBC_DRAM_CHNAC_DTR(n) _RMIXL_OFFSET(0x008 + (n)) 203 /* DRAM Region Channels A,C Address Translation Regs[0-7] */ 204 #define RMIXL_SBC_DRAM_CHNBD_DTR(n) _RMIXL_OFFSET(0x010 + (n)) 205 /* DRAM Region Channels B,D Address Translation Regs[0-7] */ 206 #define RMIXL_SBC_DRAM_BRIDGE_CFG _RMIXL_OFFSET(0x18) /* SBC DRAM config reg */ 207 #define RMIXL_SBC_XLS_IO_BAR _RMIXL_OFFSET(0x19) /* I/O Config Base Addr reg */ 208 #define RMIXL_SBC_XLS_FLASH_BAR _RMIXL_OFFSET(0x20) /* Flash Memory Base Addr reg */ 209 #define RMIXL_SBC_PCIE_CFG_BAR _RMIXL_OFFSET(0x40) /* PCI Configuration BAR */ 210 #define RMIXL_SBC_PCIE_ECFG_BAR _RMIXL_OFFSET(0x41) /* PCI Extended Configuration BAR */ 211 #define RMIXL_SBC_PCIE_MEM_BAR _RMIXL_OFFSET(0x42) /* PCI Memory region BAR */ 212 #define RMIXL_SBC_PCIE_IO_BAR _RMIXL_OFFSET(0x43) /* PCI IO region BAR */ 213 214 /* 215 * Address Error registers 216 * offsets are relative to RMIXL_IO_DEV_BRIDGE 217 */ 218 #define RMIXL_ADDR_ERR_DEVICE_MASK _RMIXL_OFFSET(0x25) /* Address Error Device Mask */ 219 #define RMIXL_ADDR_ERR_AERR0_LOG1 _RMIXL_OFFSET(0x26) /* Address Error Set 0 Log 1 */ 220 #define RMIXL_ADDR_ERR_AERR0_LOG2 _RMIXL_OFFSET(0x27) /* Address Error Set 0 Log 2 */ 221 #define RMIXL_ADDR_ERR_AERR0_LOG3 _RMIXL_OFFSET(0x28) /* Address Error Set 0 Log 3 */ 222 #define RMIXL_ADDR_ERR_AERR0_DEVSTAT _RMIXL_OFFSET(0x29) /* Address Error Set 0 irpt status */ 223 #define RMIXL_ADDR_ERR_AERR1_LOG1 _RMIXL_OFFSET(0x2a) /* Address Error Set 1 Log 1 */ 224 #define RMIXL_ADDR_ERR_AERR1_LOG2 _RMIXL_OFFSET(0x2b) /* Address Error Set 1 Log 2 */ 225 #define RMIXL_ADDR_ERR_AERR1_LOG3 _RMIXL_OFFSET(0x2c) /* Address Error Set 1 Log 3 */ 226 #define RMIXL_ADDR_ERR_AERR1_DEVSTAT _RMIXL_OFFSET(0x2d) /* Address Error Set 1 irpt status */ 227 #define RMIXL_ADDR_ERR_AERR0_EN _RMIXL_OFFSET(0x2e) /* Address Error Set 0 irpt enable */ 228 #define RMIXL_ADDR_ERR_AERR0_UPG _RMIXL_OFFSET(0x2f) /* Address Error Set 0 Upgrade */ 229 #define RMIXL_ADDR_ERR_AERR0_CLEAR _RMIXL_OFFSET(0x30) /* Address Error Set 0 irpt clear */ 230 #define RMIXL_ADDR_ERR_AERR1_CLEAR _RMIXL_OFFSET(0x31) /* Address Error Set 1 irpt clear */ 231 #define RMIXL_ADDR_ERR_SBE_COUNTS _RMIXL_OFFSET(0x32) /* Single Bit Error Counts */ 232 #define RMIXL_ADDR_ERR_DBE_COUNTS _RMIXL_OFFSET(0x33) /* Double Bit Error Counts */ 233 #define RMIXL_ADDR_ERR_BITERR_INT_EN _RMIXL_OFFSET(0x33) /* Bit Error intr enable */ 234 235 /* 236 * RMIXL_SBC_DRAM_BAR bit defines 237 */ 238 #define RMIXL_DRAM_BAR_BASE_ADDR __BITS(31,16) /* bits 39:24 of Base Address */ 239 #define DRAM_BAR_TO_BASE(r) \ 240 (((r) & RMIXL_DRAM_BAR_BASE_ADDR) << (24 - 16)) 241 #define RMIXL_DRAM_BAR_ADDR_MASK __BITS(15,4) /* bits 35:24 of Address Mask */ 242 #define DRAM_BAR_TO_SIZE(r) \ 243 ((((r) & RMIXL_DRAM_BAR_ADDR_MASK) + __BIT(4)) << (24 - 4)) 244 #define RMIXL_DRAM_BAR_INTERLEAVE __BITS(3,1) /* Interleave Mode */ 245 #define RMIXL_DRAM_BAR_STATUS __BIT(0) /* 1='region enabled' */ 246 247 /* 248 * RMIXL_SBC_DRAM_CHNAC_DTR and 249 * RMIXL_SBC_DRAM_CHNBD_DTR bit defines 250 * insert 'divisions' (0, 1 or 2) bits 251 * of value 'partition' 252 * at 'position' bit location. 253 */ 254 #define RMIXL_DRAM_DTR_RESa __BITS(31,14) 255 #define RMIXL_DRAM_DTR_PARTITION __BITS(13,12) 256 #define RMIXL_DRAM_DTR_RESb __BITS(11,10) 257 #define RMIXL_DRAM_DTR_DIVISIONS __BITS(9,8) 258 #define RMIXL_DRAM_DTR_RESc __BITS(7,6) 259 #define RMIXL_DRAM_DTR_POSITION __BITS(5,0) 260 #define RMIXL_DRAM_DTR_RESV \ 261 (RMIXL_DRAM_DTR_RESa|RMIXL_DRAM_DTR_RESb|RMIXL_DRAM_DTR_RESc) 262 263 /* 264 * RMIXL_SBC_DRAM_BRIDGE_CFG bit defines 265 */ 266 #define RMIXL_DRAM_CFG_RESa __BITS(31,13) 267 #define RMIXL_DRAM_CFG_CHANNEL_MODE __BIT(12) 268 #define RMIXL_DRAM_CFG_RESb __BIT(11) 269 #define RMIXL_DRAM_CFG_INTERLEAVE_MODE __BITS(10,8) 270 #define RMIXL_DRAM_CFG_RESc __BITS(7,5) 271 #define RMIXL_DRAM_CFG_BUS_MODE __BIT(4) 272 #define RMIXL_DRAM_CFG_RESd __BITS(3,2) 273 #define RMIXL_DRAM_CFG_DRAM_MODE __BITS(1,0) /* 1=DDR2 */ 274 275 /* 276 * RMIXL_SBC_PCIE_CFG_BAR bit defines 277 */ 278 #define RMIXL_PCIE_CFG_BAR_BASE __BITS(31,17) /* phys address bits 39:25 */ 279 #define RMIXL_PCIE_CFG_BAR_BA_SHIFT (25 - 17) 280 #define RMIXL_PCIE_CFG_BAR_TO_BA(r) \ 281 (((r) & RMIXL_PCIE_CFG_BAR_BASE) << RMIXL_PCIE_CFG_BAR_BA_SHIFT) 282 #define RMIXL_PCIE_CFG_BAR_RESV __BITS(16,1) /* (reserved) */ 283 #define RMIXL_PCIE_CFG_BAR_ENB __BIT(0) /* 1=Enable */ 284 #define RMIXL_PCIE_CFG_SIZE __BIT(25) 285 #define RMIXL_PCIE_CFG_BAR(ba, en) \ 286 ((uint32_t)(((ba) >> (25 - 17)) | ((en) ? RMIXL_PCIE_CFG_BAR_ENB : 0))) 287 288 /* 289 * RMIXL_SBC_PCIE_ECFG_BAR bit defines 290 * (PCIe extended config space) 291 */ 292 #define RMIXL_PCIE_ECFG_BAR_BASE __BITS(31,21) /* phys address bits 39:29 */ 293 #define RMIXL_PCIE_ECFG_BAR_BA_SHIFT (29 - 21) 294 #define RMIXL_PCIE_ECFG_BAR_TO_BA(r) \ 295 (((r) & RMIXL_PCIE_ECFG_BAR_BASE) << RMIXL_PCIE_ECFG_BAR_BA_SHIFT) 296 #define RMIXL_PCIE_ECFG_BAR_RESV __BITS(20,1) /* (reserved) */ 297 #define RMIXL_PCIE_ECFG_BAR_ENB __BIT(0) /* 1=Enable */ 298 #define RMIXL_PCIE_ECFG_SIZE __BIT(29) 299 #define RMIXL_PCIE_ECFG_BAR(ba, en) \ 300 ((uint32_t)(((ba) >> (29 - 21)) | ((en) ? RMIXL_PCIE_ECFG_BAR_ENB : 0))) 301 302 /* 303 * RMIXL_SBC_PCIE_MEM_BAR bit defines 304 */ 305 #define RMIXL_PCIE_MEM_BAR_BASE __BITS(31,16) /* phys address bits 39:24 */ 306 #define RMIXL_PCIE_MEM_BAR_TO_BA(r) \ 307 (((r) & RMIXL_PCIE_MEM_BAR_BASE) << (24 - 16)) 308 #define RMIXL_PCIE_MEM_BAR_MASK __BITS(15,1) /* phys address mask bits 38:24 */ 309 #define RMIXL_PCIE_MEM_BAR_TO_SIZE(r) \ 310 ((((r) & RMIXL_PCIE_MEM_BAR_MASK) + 2) << (24 - 1)) 311 #define RMIXL_PCIE_MEM_BAR_ENB __BIT(0) /* 1=Enable */ 312 #define RMIXL_PCIE_MEM_BAR(ba, en) \ 313 ((uint32_t)(((ba) >> (24 - 16)) | ((en) ? RMIXL_PCIE_MEM_BAR_ENB : 0))) 314 315 /* 316 * RMIXL_SBC_PCIE_IO_BAR bit defines 317 */ 318 #define RMIXL_PCIE_IO_BAR_BASE __BITS(31,18) /* phys address bits 39:26 */ 319 #define RMIXL_PCIE_IO_BAR_TO_BA(r) \ 320 (((r) & RMIXL_PCIE_IO_BAR_BASE) << (26 - 18)) 321 #define RMIXL_PCIE_IO_BAR_RESV __BITS(17,7) /* (reserve) */ 322 #define RMIXL_PCIE_IO_BAR_MASK __BITS(6,1) /* phys address mask bits 31:26 */ 323 #define RMIXL_PCIE_IO_BAR_TO_SIZE(r) \ 324 ((((r) & RMIXL_PCIE_IO_BAR_MASK) + 2) << (26 - 1)) 325 #define RMIXL_PCIE_IO_BAR_ENB __BIT(0) /* 1=Enable */ 326 #define RMIXL_PCIE_IO_BAR(ba, en) \ 327 ((uint32_t)(((ba) >> (26 - 18)) | ((en) ? RMIXL_PCIE_IO_BAR_ENB : 0))) 328 329 330 /* 331 * Programmable Interrupt Controller registers 332 * the Programming Reference Manual table 10.4 333 * lists "Reg ID" values not offsets 334 * Offsets are relative to RMIXL_IO_DEV_BRIDGE 335 */ 336 #define RMIXL_PIC_CONTROL _RMIXL_OFFSET(0x0) 337 #define RMIXL_PIC_IPIBASE _RMIXL_OFFSET(0x4) 338 #define RMIXL_PIC_INTRACK _RMIXL_OFFSET(0x6) 339 #define RMIXL_PIC_WATCHdOGMAXVALUE0 _RMIXL_OFFSET(0x8) 340 #define RMIXL_PIC_WATCHDOGMAXVALUE1 _RMIXL_OFFSET(0x9) 341 #define RMIXL_PIC_WATCHDOGMASK0 _RMIXL_OFFSET(0xa) 342 #define RMIXL_PIC_WATCHDOGMASK1 _RMIXL_OFFSET(0xb) 343 #define RMIXL_PIC_WATCHDOGHEARTBEAT0 _RMIXL_OFFSET(0xc) 344 #define RMIXL_PIC_WATCHDOGHEARTBEAT1 _RMIXL_OFFSET(0xd) 345 #define RMIXL_PIC_IRTENTRYC0(n) _RMIXL_OFFSET(0x40 + (n)) /* 0<=n<=31 */ 346 #define RMIXL_PIC_IRTENTRYC1(n) _RMIXL_OFFSET(0x80 + (n)) /* 0<=n<=31 */ 347 #define RMIXL_PIC_SYSTMRMAXVALC0(n) _RMIXL_OFFSET(0x100 + (n)) /* 0<=n<=7 */ 348 #define RMIXL_PIC_SYSTMRMAXVALC1(n) _RMIXL_OFFSET(0x110 + (n)) /* 0<=n<=7 */ 349 #define RMIXL_PIC_SYSTMRC0(n) _RMIXL_OFFSET(0x120 + (n)) /* 0<=n<=7 */ 350 #define RMIXL_PIC_SYSTMRC1(n) _RMIXL_OFFSET(0x130 + (n)) /* 0<=n<=7 */ 351 352 /* 353 * RMIXL_PIC_CONTROL bits 354 */ 355 #define RMIXL_PIC_CONTROL_WATCHDOG_ENB __BIT(0) 356 #define RMIXL_PIC_CONTROL_GEN_NMI __BITS(2,1) /* do NMI after n WDog irpts */ 357 #define RMIXL_PIC_CONTROL_GEN_NMIn(n) (((n) << 1) & RMIXL_PIC_CONTROL_GEN_NMI) 358 #define RMIXL_PIC_CONTROL_RESa __BITS(7,3) 359 #define RMIXL_PIC_CONTROL_TIMER_ENB __BITS(15,8) /* per-Timer enable bits */ 360 #define RMIXL_PIC_CONTROL_TIMER_ENBn(n) ((1 << (n)) & RMIXL_PIC_CONTROL_TIMER_ENB) 361 #define RMIXL_PIC_CONTROL_RESb __BITS(31,16) 362 #define RMIXL_PIC_CONTROL_RESV \ 363 (RMIXL_PIC_CONTROL_RESa|RMIXL_PIC_CONTROL_RESb) 364 365 /* 366 * RMIXL_PIC_IPIBASE bits 367 */ 368 #define RMIXL_PIC_IPIBASE_VECTORNUM __BITS(5,0) 369 #define RMIXL_PIC_IPIBASE_RESa __BIT(6) /* undocumented bit */ 370 #define RMIXL_PIC_IPIBASE_BCAST __BIT(7) 371 #define RMIXL_PIC_IPIBASE_NMI __BIT(8) 372 #define RMIXL_PIC_IPIBASE_ID __BITS(31,16) 373 #define RMIXL_PIC_IPIBASE_ID_RESb __BITS(31,23) 374 #define RMIXL_PIC_IPIBASE_ID_CPU __BITS(22,20) /* Physical CPU ID */ 375 #define RMIXL_PIC_IPIBASE_ID_RESc __BITS(19,18) 376 #define RMIXL_PIC_IPIBASE_ID_THREAD __BITS(22,20) /* Thread ID */ 377 #define RMIXL_PIC_IPIBASE_ID_RESV \ 378 (RMIXL_PIC_IPIBASE_ID_RESa|RMIXL_PIC_IPIBASE_ID_RESb \ 379 |RMIXL_PIC_IPIBASE_ID_RESc) 380 381 /* 382 * RMIXL_PIC_IRTENTRYC0 bits 383 * IRT Entry low word 384 */ 385 #define RMIXL_PIC_IRTENTRYC0_TMASK __BITS(7,0) /* Thread Mask */ 386 #define RMIXL_PIC_IRTENTRYC0_RESa __BITS(3,2) /* write as 0 */ 387 #define RMIXL_PIC_IRTENTRYC0_RESb __BITS(31,8) /* write as 0 */ 388 #define RMIXL_PIC_IRTENTRYC0_RESV \ 389 (RMIXL_PIC_IRTENTRYC0_RESa | RMIXL_PIC_IRTENTRYC0_RESb) 390 391 /* 392 * RMIXL_PIC_IRTENTRYC1 bits 393 * IRT Entry high word 394 */ 395 #define RMIXL_PIC_IRTENTRYC1_INTVEC __BITS(5,0) /* maps to bit# in CPU's EIRR */ 396 #define RMIXL_PIC_IRTENTRYC1_GL __BIT(6) /* 0=Global; 1=Local */ 397 #define RMIXL_PIC_IRTENTRYC1_NMI __BIT(7) /* 0=Maskable; 1=NMI */ 398 #define RMIXL_PIC_IRTENTRYC1_RESV __BITS(28,8) 399 #define RMIXL_PIC_IRTENTRYC1_P __BIT(29) /* 0=Rising/High; 1=Falling/Low */ 400 #define RMIXL_PIC_IRTENTRYC1_TRG __BIT(30) /* 0=Edge; 1=Level */ 401 #define RMIXL_PIC_IRTENTRYC1_VALID __BIT(31) /* 0=Invalid; 1=Valid IRT Entry */ 402 403 404 /* 405 * GPIO Controller registers 406 */ 407 408 /* GPIO Signal Registers */ 409 #define RMIXL_GPIO_INT_ENB _RMIXL_OFFSET(0x0) /* Interrupt Enable register */ 410 #define RMIXL_GPIO_INT_INV _RMIXL_OFFSET(0x1) /* Interrupt Inversion register */ 411 #define RMIXL_GPIO_IO_DIR _RMIXL_OFFSET(0x2) /* I/O Direction register */ 412 #define RMIXL_GPIO_OUTPUT _RMIXL_OFFSET(0x3) /* Output Write register */ 413 #define RMIXL_GPIO_INPUT _RMIXL_OFFSET(0x4) /* Intput Read register */ 414 #define RMIXL_GPIO_INT_CLR _RMIXL_OFFSET(0x5) /* Interrupt Inversion register */ 415 #define RMIXL_GPIO_INT_STS _RMIXL_OFFSET(0x6) /* Interrupt Status register */ 416 #define RMIXL_GPIO_INT_TYP _RMIXL_OFFSET(0x7) /* Interrupt Type register */ 417 #define RMIXL_GPIO_RESET _RMIXL_OFFSET(0x8) /* XLS Soft Reset register */ 418 419 /* GPIO System Control Registers */ 420 #define RMIXL_GPIO_RESET_CFG _RMIXL_OFFSET(0x15) /* Reset Configuration register */ 421 #define RMIXL_GPIO_THERMAL_CSR _RMIXL_OFFSET(0x16) /* Thermal Control/Status register */ 422 #define RMIXL_GPIO_THERMAL_SHFT _RMIXL_OFFSET(0x17) /* Thermal Shift register */ 423 #define RMIXL_GPIO_BIST_ALL_STS _RMIXL_OFFSET(0x18) /* BIST All Status register */ 424 #define RMIXL_GPIO_BIST_EACH_STS _RMIXL_OFFSET(0x19) /* BIST Each Status register */ 425 #define RMIXL_GPIO_SGMII_0_3_PHY_CTL _RMIXL_OFFSET(0x20) /* SGMII #0..3 PHY Control register */ 426 #define RMIXL_GPIO_AUI_0_PHY_CTL _RMIXL_OFFSET(0x20) /* AUI port#0 PHY Control register */ 427 #define RMIXL_GPIO_SGMII_4_7_PLL_CTL _RMIXL_OFFSET(0x21) /* SGMII #4..7 PLL Control register */ 428 #define RMIXL_GPIO_AUI_1_PLL_CTL _RMIXL_OFFSET(0x21) /* AUI port#1 PLL Control register */ 429 #define RMIXL_GPIO_SGMII_4_7_PHY_CTL _RMIXL_OFFSET(0x22) /* SGMII #4..7 PHY Control register */ 430 #define RMIXL_GPIO_AUI_1_PHY_CTL _RMIXL_OFFSET(0x22) /* AUI port#1 PHY Control register */ 431 #define RMIXL_GPIO_INT_MAP _RMIXL_OFFSET(0x25) /* Interrupt Map to PIC, 0=int14, 1=int30 */ 432 #define RMIXL_GPIO_EXT_INT _RMIXL_OFFSET(0x26) /* External Interrupt control register */ 433 #define RMIXL_GPIO_CPU_RST _RMIXL_OFFSET(0x28) /* CPU Reset control register */ 434 #define RMIXL_GPIO_LOW_PWR_DIS _RMIXL_OFFSET(0x29) /* Low Power Dissipation register */ 435 #define RMIXL_GPIO_RANDOM _RMIXL_OFFSET(0x2b) /* Low Power Dissipation register */ 436 #define RMIXL_GPIO_CPU_CLK_DIS _RMIXL_OFFSET(0x2d) /* CPU Clock Disable register */ 437 438 /* 439 * PCIE Interface Controller registers 440 */ 441 #define RMIXL_PCIE_CTRL1 _RMIXL_OFFSET(0x0) 442 #define RMIXL_PCIE_CTRL2 _RMIXL_OFFSET(0x1) 443 #define RMIXL_PCIE_CTRL3 _RMIXL_OFFSET(0x2) 444 #define RMIXL_PCIE_CTRL4 _RMIXL_OFFSET(0x3) 445 #define RMIXL_PCIE_CTRL _RMIXL_OFFSET(0x4) 446 #define RMIXL_PCIE_IOBM_TIMER _RMIXL_OFFSET(0x5) 447 #define RMIXL_PCIE_MSI_CMD _RMIXL_OFFSET(0x6) 448 #define RMIXL_PCIE_MSI_RESP _RMIXL_OFFSET(0x7) 449 #define RMIXL_PCIE_DWC_CRTL5 _RMIXL_OFFSET(0x8) /* not on XLS408Lite, XLS404Lite */ 450 #define RMIXL_PCIE_DWC_CRTL6 _RMIXL_OFFSET(0x9) /* not on XLS408Lite, XLS404Lite */ 451 #define RMIXL_PCIE_IOBM_SWAP_MEM_BASE _RMIXL_OFFSET(0x10) 452 #define RMIXL_PCIE_IOBM_SWAP_MEM_LIMIT _RMIXL_OFFSET(0x11) 453 #define RMIXL_PCIE_IOBM_SWAP_IO_BASE _RMIXL_OFFSET(0x12) 454 #define RMIXL_PCIE_IOBM_SWAP_IO_LIMIT _RMIXL_OFFSET(0x13) 455 #define RMIXL_PCIE_TRGT_CHRNT_MEM_BASE _RMIXL_OFFSET(0x14) 456 #define RMIXL_PCIE_TRGT_CHRNT_MEM_LIMIT _RMIXL_OFFSET(0x15) 457 #define RMIXL_PCIE_TRGT_L2ALC_MEM_BASE _RMIXL_OFFSET(0x16) 458 #define RMIXL_PCIE_TRGT_L2ALC_MEM_LIMIT _RMIXL_OFFSET(0x17) 459 #define RMIXL_PCIE_TRGT_REX_MEM_BASE _RMIXL_OFFSET(0x18) 460 #define RMIXL_PCIE_TRGT_REX_MEM_LIMIT _RMIXL_OFFSET(0x19) 461 #define RMIXL_PCIE_EP_MEM_BASE _RMIXL_OFFSET(0x1a) 462 #define RMIXL_PCIE_EP_MEM_LIMIT _RMIXL_OFFSET(0x1b) 463 #define RMIXL_PCIE_EP_ADDR_MAP_ENTRY0 _RMIXL_OFFSET(0x1c) 464 #define RMIXL_PCIE_EP_ADDR_MAP_ENTRY1 _RMIXL_OFFSET(0x1d) 465 #define RMIXL_PCIE_EP_ADDR_MAP_ENTRY2 _RMIXL_OFFSET(0x1e) 466 #define RMIXL_PCIE_EP_ADDR_MAP_ENTRY3 _RMIXL_OFFSET(0x1f) 467 #define RMIXL_PCIE_LINK0_STATE _RMIXL_OFFSET(0x20) 468 #define RMIXL_PCIE_LINK1_STATE _RMIXL_OFFSET(0x21) 469 #define RMIXL_PCIE_IOBM_INT_STATUS _RMIXL_OFFSET(0x22) 470 #define RMIXL_PCIE_IOBM_INT_ENABLE _RMIXL_OFFSET(0x23) 471 #define RMIXL_PCIE_LINK0_MSI_STATUS _RMIXL_OFFSET(0x24) 472 #define RMIXL_PCIE_LINK1_MSI_STATUS _RMIXL_OFFSET(0x25) 473 #define RMIXL_PCIE_LINK0_MSI_ENABLE _RMIXL_OFFSET(0x26) 474 #define RMIXL_PCIE_LINK1_MSI_ENABLE _RMIXL_OFFSET(0x27) 475 #define RMIXL_PCIE_LINK0_INT_STATUS0 _RMIXL_OFFSET(0x28) 476 #define RMIXL_PCIE_LINK1_INT_STATUS0 _RMIXL_OFFSET(0x29) 477 #define RMIXL_PCIE_LINK0_INT_STATUS1 _RMIXL_OFFSET(0x2a) 478 #define RMIXL_PCIE_LINK1_INT_STATUS1 _RMIXL_OFFSET(0x2b) 479 #define RMIXL_PCIE_LINK0_INT_ENABLE0 _RMIXL_OFFSET(0x2c) 480 #define RMIXL_PCIE_LINK1_INT_ENABLE0 _RMIXL_OFFSET(0x2d) 481 #define RMIXL_PCIE_LINK0_INT_ENABLE1 _RMIXL_OFFSET(0x2e) 482 #define RMIXL_PCIE_LINK1_INT_ENABLE1 _RMIXL_OFFSET(0x2f) 483 #define RMIXL_PCIE_PHY_CR_CMD _RMIXL_OFFSET(0x30) 484 #define RMIXL_PCIE_PHY_CR_WR_DATA _RMIXL_OFFSET(0x31) 485 #define RMIXL_PCIE_PHY_CR_RESP _RMIXL_OFFSET(0x32) 486 #define RMIXL_PCIE_PHY_CR_RD_DATA _RMIXL_OFFSET(0x33) 487 #define RMIXL_PCIE_IOBM_ERR_CMD _RMIXL_OFFSET(0x34) 488 #define RMIXL_PCIE_IOBM_ERR_LOWER_ADDR _RMIXL_OFFSET(0x35) 489 #define RMIXL_PCIE_IOBM_ERR_UPPER_ADDR _RMIXL_OFFSET(0x36) 490 #define RMIXL_PCIE_IOBM_ERR_BE _RMIXL_OFFSET(0x37) 491 #define RMIXL_PCIE_LINK2_STATE _RMIXL_OFFSET(0x60) /* not on XLS408Lite, XLS404Lite */ 492 #define RMIXL_PCIE_LINK3_STATE _RMIXL_OFFSET(0x61) /* not on XLS408Lite, XLS404Lite */ 493 #define RMIXL_PCIE_LINK2_MSI_STATUS _RMIXL_OFFSET(0x64) /* not on XLS408Lite, XLS404Lite */ 494 #define RMIXL_PCIE_LINK3_MSI_STATUS _RMIXL_OFFSET(0x65) /* not on XLS408Lite, XLS404Lite */ 495 #define RMIXL_PCIE_LINK2_MSI_ENABLE _RMIXL_OFFSET(0x66) /* not on XLS408Lite, XLS404Lite */ 496 #define RMIXL_PCIE_LINK3_MSI_ENABLE _RMIXL_OFFSET(0x67) /* not on XLS408Lite, XLS404Lite */ 497 #define RMIXL_PCIE_LINK2_INT_STATUS0 _RMIXL_OFFSET(0x68) /* not on XLS408Lite, XLS404Lite */ 498 #define RMIXL_PCIE_LINK3_INT_STATUS0 _RMIXL_OFFSET(0x69) /* not on XLS408Lite, XLS404Lite */ 499 #define RMIXL_PCIE_LINK2_INT_STATUS1 _RMIXL_OFFSET(0x6a) /* not on XLS408Lite, XLS404Lite */ 500 #define RMIXL_PCIE_LINK3_INT_STATUS1 _RMIXL_OFFSET(0x6b) /* not on XLS408Lite, XLS404Lite */ 501 #define RMIXL_PCIE_LINK2_INT_ENABLE0 _RMIXL_OFFSET(0x6c) /* not on XLS408Lite, XLS404Lite */ 502 #define RMIXL_PCIE_LINK3_INT_ENABLE0 _RMIXL_OFFSET(0x6d) /* not on XLS408Lite, XLS404Lite */ 503 #define RMIXL_PCIE_LINK2_INT_ENABLE1 _RMIXL_OFFSET(0x6e) /* not on XLS408Lite, XLS404Lite */ 504 #define RMIXL_PCIE_LINK3_INT_ENABLE1 _RMIXL_OFFSET(0x6f) /* not on XLS408Lite, XLS404Lite */ 505 #define RMIXL_VC0_POSTED_RX_QUEUE_CTRL _RMIXL_OFFSET(0x1d2) 506 #define RMIXL_VC0_POSTED_BUFFER_DEPTH _RMIXL_OFFSET(0x1ea) 507 #define RMIXL_PCIE_MSG_TX_THRESHOLD _RMIXL_OFFSET(0x308) 508 #define RMIXL_PCIE_MSG_BUCKET_SIZE_0 _RMIXL_OFFSET(0x320) 509 #define RMIXL_PCIE_MSG_BUCKET_SIZE_1 _RMIXL_OFFSET(0x321) 510 #define RMIXL_PCIE_MSG_BUCKET_SIZE_2 _RMIXL_OFFSET(0x322) 511 #define RMIXL_PCIE_MSG_BUCKET_SIZE_3 _RMIXL_OFFSET(0x323) 512 #define RMIXL_PCIE_MSG_BUCKET_SIZE_4 _RMIXL_OFFSET(0x324) /* not on XLS408Lite, XLS404Lite */ 513 #define RMIXL_PCIE_MSG_BUCKET_SIZE_5 _RMIXL_OFFSET(0x325) /* not on XLS408Lite, XLS404Lite */ 514 #define RMIXL_PCIE_MSG_BUCKET_SIZE_6 _RMIXL_OFFSET(0x326) /* not on XLS408Lite, XLS404Lite */ 515 #define RMIXL_PCIE_MSG_BUCKET_SIZE_7 _RMIXL_OFFSET(0x327) /* not on XLS408Lite, XLS404Lite */ 516 #define RMIXL_PCIE_MSG_CREDIT_FIRST _RMIXL_OFFSET(0x380) 517 #define RMIXL_PCIE_MSG_CREDIT_LAST _RMIXL_OFFSET(0x3ff) 518 519 #endif /* _MIPS_RMI_RMIRMIXLEGS_H_ */ 520 521
Indexes created Tue Sep 30 20:09:53 GMT 2025