rmixlreg.h revision 1.6
1 /* $NetBSD: rmixlreg.h,v 1.6 2025/05/03 02:00:46 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Cliff Neighbors 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 33 #ifndef _MIPS_RMI_RMIXLREGS_H_ 34 #define _MIPS_RMI_RMIXLREGS_H_ 35 36 #ifdef _KERNEL_OPT 37 #include "opt_cputype.h" 38 #endif 39 40 #include <sys/endian.h> 41 42 /* 43 * on chip I/O register byte order is 44 * BIG ENDIAN regardless of code model 45 */ 46 #define RMIXL_IOREG_VADDR(o) \ 47 (volatile uint32_t *)MIPS_PHYS_TO_KSEG1( \ 48 rmixl_configuration.rc_io_pbase + (o)) 49 #define RMIXL_IOREG_READ(o) be32toh(*RMIXL_IOREG_VADDR(o)) 50 #define RMIXL_IOREG_WRITE(o,v) *RMIXL_IOREG_VADDR(o) = htobe32(v) 51 52 53 /* 54 * RMIXL Coprocessor 2 registers: 55 */ 56 #ifdef _LOCORE 57 #define _(n) __CONCAT($,n) 58 #else 59 #define _(n) n 60 #endif 61 /* 62 * Note CP2 FMN register scope or "context" 63 * L : Local : per thread register 64 * G : Global : per FMN Station (per core) register 65 * L/G : "partly global" : ??? 66 * Global regs should be managed by a single thread 67 * (see XLS PRM "Coprocessor 2 Register Summary") 68 */ 69 /* context ---------------+ */ 70 /* #sels --------------+ | */ 71 /* #regs -----------+ | | */ 72 /* What: #bits --+ | | | */ 73 /* v v v v */ 74 #define RMIXL_COP_2_TXBUF _(0) /* Transmit Buffers 64 [1][4] L */ 75 #define RMIXL_COP_2_RXBUF _(1) /* Receive Buffers 64 [1][4] L */ 76 #define RMIXL_COP_2_MSG_STS _(2) /* Message Status 32 [1][2] L/G */ 77 #define RMIXL_COP_2_MSG_CFG _(3) /* Message Config 32 [1][2] G */ 78 #define RMIXL_COP_2_MSG_BSZ _(4) /* Message Bucket Size 32 [1][8] G */ 79 #define RMIXL_COP_2_CREDITS _(16) /* Credit Counters 8 [16][8] G */ 80 81 /* 82 * MsgStatus: RMIXL_COP_2_MSG_STS (CP2 Reg 2, Select 0) bits 83 */ 84 #define RMIXL_MSG_STS0_RFBE __BITS(31,24) /* RX FIFO Buckets bit mask 85 * 0=not empty 86 * 1=empty 87 */ 88 #define RMIXL_MSG_STS0_RFBE_SHIFT 24 89 #define RMIXL_MSG_STS0_RESV __BIT(23) 90 #define RMIXL_MSG_STS0_RMSID __BITS(22,16) /* Source ID */ 91 #define RMIXL_MSG_STS0_RMSID_SHIFT 16 92 #define RMIXL_MSG_STS0_RMSC __BITS(15,8) /* RX Message Software Code */ 93 #define RMIXL_MSG_STS0_RMSC_SHIFT 8 94 #define RMIXL_MSG_STS0_RMS __BITS(7,6) /* RX Message Size (minus 1) */ 95 #define RMIXL_MSG_STS0_RMS_SHIFT 6 96 #define RMIXL_MSG_STS0_LEF __BIT(5) /* Load Empty Fail */ 97 #define RMIXL_MSG_STS0_LPF __BIT(4) /* Load Pending Fail */ 98 #define RMIXL_MSG_STS0_LMP __BIT(3) /* Load Message Pending */ 99 #define RMIXL_MSG_STS0_SCF __BIT(2) /* Send Credit Fail */ 100 #define RMIXL_MSG_STS0_SPF __BIT(1) /* Send Pending Fail */ 101 #define RMIXL_MSG_STS0_SMP __BIT(0) /* Send Message Pending */ 102 #define RMIXL_MSG_STS0_ERRS \ 103 (RMIXL_MSG_STS0_LEF|RMIXL_MSG_STS0_LPF|RMIXL_MSG_STS0_LMP \ 104 |RMIXL_MSG_STS0_SCF|RMIXL_MSG_STS0_SPF|RMIXL_MSG_STS0_SMP) 105 106 /* 107 * MsgStatus1: RMIXL_COP_2_MSG_STS (CP2 Reg 2, Select 1) bits 108 */ 109 #define RMIXL_MSG_STS1_RESV __BIT(31) 110 #define RMIXL_MSG_STS1_C __BIT(30) /* Credit Overrun Error */ 111 #define RMIXL_MSG_STS1_CCFCME __BITS(29,23) /* Credit Counter of Free Credit Message with Error */ 112 #define RMIXL_MSG_STS1_CCFCME_SHIFT 23 113 #define RMIXL_MSG_STS1_SIDFCME __BITS(22,16) /* Source ID of Free Credit Message with Error */ 114 #define RMIXL_MSG_STS1_SIDFCME_SHIFT 16 115 #define RMIXL_MSG_STS1_T __BIT(15) /* Invalid Target Error */ 116 #define RMIXL_MSG_STS1_F __BIT(14) /* Receive Queue "Write When Full" Error */ 117 #define RMIXL_MSG_STS1_SIDE __BITS(13,7) /* Source ID of incoming msg with Error */ 118 #define RMIXL_MSG_STS1_SIDE_SHIFT 7 119 #define RMIXL_MSG_STS1_DIDE __BITS(6,0) /* Destination ID of the incoming message Message with Error */ 120 #define RMIXL_MSG_STS1_DIDE_SHIFT 0 121 #define RMIXL_MSG_STS1_ERRS \ 122 (RMIXL_MSG_STS1_C|RMIXL_MSG_STS1_T|RMIXL_MSG_STS1_F) 123 124 /* 125 * MsgConfig: RMIXL_COP_2_MSG_CFG (CP2 Reg 3, Select 0) bits 126 */ 127 #define RMIXL_MSG_CFG0_WM __BITS(31,24) /* Watermark level */ 128 #define RMIXL_MSG_CFG0_WMSHIFT 24 129 #define RMIXL_MSG_CFG0_RESa __BITS(23,22) 130 #define RMIXL_MSG_CFG0_IV __BITS(21,16) /* Interrupt Vector */ 131 #define RMIXL_MSG_CFG0_IV_SHIFT 16 132 #define RMIXL_MSG_CFG0_RESb __BITS(15,12) 133 #define RMIXL_MSG_CFG0_ITM __BITS(11,8) /* Interrupt Thread Mask */ 134 #define RMIXL_MSG_CFG0_ITM_SHIFT 8 135 #define RMIXL_MSG_CFG0_RESc __BITS(7,2) 136 #define RMIXL_MSG_CFG0_WIE __BIT(1) /* Watermark Interrupt Enable */ 137 #define RMIXL_MSG_CFG0_EIE __BIT(0) /* Receive Queue Not Empty Enable */ 138 #define RMIXL_MSG_CFG0_RESV \ 139 (RMIXL_MSG_CFG0_RESa|RMIXL_MSG_CFG0_RESb|RMIXL_MSG_CFG0_RESc) 140 141 /* 142 * MsgConfig1: RMIXL_COP_2_MSG_CFG (CP2 Reg 3, Select 1) bits 143 * Note: reg width is 64 bits in PRM reg description, but 32 bits in reg summary 144 */ 145 #define RMIXL_MSG_CFG1_RESV __BITS(63,3) 146 #define RMIXL_MSG_CFG1_T __BIT(2) /* Trace Mode Enable */ 147 #define RMIXL_MSG_CFG1_C __BIT(1) /* Credit Over-run Interrupt Enable */ 148 #define RMIXL_MSG_CFG1_M __BIT(0) /* Messaging Errors Interrupt Enable */ 149 150 151 /* 152 * MsgBucketSize: RMIXL_COP_2_MSG_BSZ (CP2 Reg 4, Select [0..7]) bits 153 * Note: reg width is 64 bits in PRM reg description, but 32 bits in reg summary 154 * Size: 155 * - 0 means bucket disabled, else 156 * - must be power of 2 157 * - must be >=4 158 */ 159 #define RMIXL_MSG_BSZ_RESV __BITS(63,8) 160 #define RMIXL_MSG_BSZ_SIZE __BITS(7,0) 161 162 163 164 165 /* 166 * RMIXL Processor Control Register addresses 167 * - Offset in bits 7..0 168 * - BlockID in bits 15..8 169 */ 170 #define RMIXL_PCR_THREADEN 0x0000 171 #define RMIXL_PCR_SOFTWARE_SLEEP 0x0001 172 #define RMIXL_PCR_SCHEDULING 0x0002 173 #define RMIXL_PCR_SCHEDULING_COUNTERS 0x0003 174 #define RMIXL_PCR_BHRPM 0x0004 175 #define RMIXL_PCR_IFU_DEFEATURE 0x0006 176 #define RMIXL_PCR_ICU_DEFEATURE 0x0100 177 #define RMIXL_PCR_ICU_ERROR_LOGGING 0x0101 178 #define RMIXL_PCR_ICU_DEBUG_ACCESS_ADDR 0x0102 179 #define RMIXL_PCR_ICU_DEBUG_ACCESS_DATALO 0x0103 180 #define RMIXL_PCR_ICU_DEBUG_ACCESS_DATAHI 0x0104 181 #define RMIXL_PCR_ICU_SAMPLING_LFSR 0x0105 182 #define RMIXL_PCR_ICU_SAMPLING_PC 0x0106 183 #define RMIXL_PCR_ICU_SAMPLING_SETUP 0x0107 184 #define RMIXL_PCR_ICU_SAMPLING_TIMER 0x0108 185 #define RMIXL_PCR_ICU_SAMPLING_PC_UPPER 0x0109 186 #define RMIXL_PCR_IEU_DEFEATURE 0x0200 187 #define RMIXL_PCR_TARGET_PC_REGISTER 0x0207 188 #define RMIXL_PCR_L1D_CONFIG0 0x0300 189 #define RMIXL_PCR_L1D_CONFIG1 0x0301 190 #define RMIXL_PCR_L1D_CONFIG2 0x0302 191 #define RMIXL_PCR_L1D_CONFIG3 0x0303 192 #define RMIXL_PCR_L1D_CONFIG4 0x0304 193 #define RMIXL_PCR_L1D_STATUS 0x0305 194 #define RMIXL_PCR_L1D_DEFEATURE 0x0306 195 #define RMIXL_PCR_L1D_DEBUG0 0x0307 196 #define RMIXL_PCR_L1D_DEBUG1 0x0308 197 #define RMIXL_PCR_L1D_CACHE_ERROR_LOG 0x0309 198 #define RMIXL_PCR_L1D_CACHE_ERROR_OVF_LO 0x030A 199 #define RMIXL_PCR_L1D_CACHE_INTERRUPT 0x030B 200 #define RMIXL_PCR_MMU_SETUP 0x0400 201 #define RMIXL_PCR_PRF_SMP_EVENT 0x0500 202 #define RMIXL_PCR_RF_SMP_RPLY_BUF 0x0501 203 204 /* PCR bit defines TBD */ 205 206 207 /* 208 * Memory Distributed Interconnect (MDI) System Memory Map 209 */ 210 #define RMIXL_PHYSADDR_MAX 0xffffffffffLL /* 1TB Physical Address space */ 211 #define RMIXL_IO_DEV_PBASE 0x1ef00000 /* default phys. from XL[RS]_IO_BAR */ 212 #define RMIXL_IO_DEV_VBASE MIPS_PHYS_TO_KSEG1(RMIXL_IO_DEV_PBASE) 213 /* default virtual base address */ 214 #define RMIXL_IO_DEV_SIZE 0x100000 /* I/O Conf. space is 1MB region */ 215 216 217 218 /* 219 * Peripheral and I/O Configuration Region of Memory 220 * 221 * These are relocatable; we run using the reset value defaults, 222 * and we expect to inherit those intact from the boot firmware. 223 * 224 * Many of these overlap between XLR and XLS, exceptions are ifdef'ed. 225 * 226 * Device region offsets are relative to RMIXL_IO_DEV_PBASE. 227 */ 228 #define RMIXL_IO_DEV_BRIDGE 0x00000 /* System Bridge Controller (SBC) */ 229 #define RMIXL_IO_DEV_DDR_CHNA 0x01000 /* DDR1/DDR2 DRAM_A Channel, Port MA */ 230 #define RMIXL_IO_DEV_DDR_CHNB 0x02000 /* DDR1/DDR2 DRAM_B Channel, Port MB */ 231 #define RMIXL_IO_DEV_DDR_CHNC 0x03000 /* DDR1/DDR2 DRAM_C Channel, Port MC */ 232 #define RMIXL_IO_DEV_DDR_CHND 0x04000 /* DDR1/DDR2 DRAM_D Channel, Port MD */ 233 #if defined(MIPS64_XLR) 234 #define RMIXL_IO_DEV_SRAM 0x07000 /* SRAM Controller, Port SA */ 235 #endif /* MIPS64_XLR */ 236 #define RMIXL_IO_DEV_PIC 0x08000 /* Programmable Interrupt Controller */ 237 #if defined(MIPS64_XLR) 238 #define RMIXL_IO_DEV_PCIX 0x09000 /* PCI-X */ 239 #define RMIXL_IO_DEV_PCIX_EL \ 240 RMIXL_IO_DEV_PCIX /* PXI-X little endian */ 241 #define RMIXL_IO_DEV_PCIX_EB \ 242 (RMIXL_IO_DEV_PCIX | __BIT(11)) /* PXI-X big endian */ 243 #define RMIXL_IO_DEV_HT 0x0a000 /* HyperTransport */ 244 #endif /* MIPS64_XLR */ 245 #define RMIXL_IO_DEV_SAE 0x0b000 /* Security Acceleration Engine */ 246 #if defined(MIPS64_XLS) 247 #define XAUI_INTERFACE_0 0x0c000 /* XAUI Interface_0 */ 248 /* when SGMII Interface_[0-3] are not used */ 249 #define RMIXL_IO_DEV_GMAC_0 0x0c000 /* SGMII-Interface_0, Port SGMII0 */ 250 #define RMIXL_IO_DEV_GMAC_1 0x0d000 /* SGMII-Interface_1, Port SGMII1 */ 251 #define RMIXL_IO_DEV_GMAC_2 0x0e000 /* SGMII-Interface_2, Port SGMII2 */ 252 #define RMIXL_IO_DEV_GMAC_3 0x0f000 /* SGMII-Interface_3, Port SGMII3 */ 253 #endif /* MIPS64_XLS */ 254 #if defined(MIPS64_XLR) 255 #define RMIXL_IO_DEV_GMAC_A 0x0c000 /* RGMII-Interface_0, Port RA */ 256 #define RMIXL_IO_DEV_GMAC_B 0x0d000 /* RGMII-Interface_1, Port RB */ 257 #define RMIXL_IO_DEV_GMAC_C 0x0e000 /* RGMII-Interface_2, Port RC */ 258 #define RMIXL_IO_DEV_GMAC_D 0x0f000 /* RGMII-Interface_3, Port RD */ 259 #define RMIXL_IO_DEV_SPI4_A 0x10000 /* SPI-4.2-Interface_A, Port XA */ 260 #define RMIXL_IO_DEV_XGMAC_A 0x11000 /* XGMII-Interface_A, Port XA */ 261 #define RMIXL_IO_DEV_SPI4_B 0x12000 /* SPI-4.2-Interface_B, Port XB */ 262 #define RMIXL_IO_DEV_XGMAC_B 0x13000 /* XGMII-Interface_B, Port XB */ 263 #endif /* MIPS64_XLR */ 264 #define RMIXL_IO_DEV_UART_1 0x14000 /* UART_1 (16550 w/ ax4 addrs) */ 265 #define RMIXL_IO_DEV_UART_2 0x15000 /* UART_2 (16550 w/ ax4 addrs) */ 266 #define RMIXL_IO_DEV_I2C_1 0x16000 /* I2C_1 */ 267 #define RMIXL_IO_DEV_I2C_2 0x17000 /* I2C_2 */ 268 #define RMIXL_IO_DEV_GPIO 0x18000 /* GPIO */ 269 #define RMIXL_IO_DEV_FLASH 0x19000 /* Peripherals IO Bus, to Flash memory &etc. */ 270 #define RMIXL_IO_DEV_DMA 0x1a000 /* DMA */ 271 #define RMIXL_IO_DEV_L2 0x1b000 /* L2 Cache */ 272 #define RMIXL_IO_DEV_TB 0x1c000 /* Trace Buffer */ 273 #if defined(MIPS64_XLS) 274 #define RMIXL_IO_DEV_CDE 0x1d000 /* Compression/Decompression Engine */ 275 #define RMIXL_IO_DEV_PCIE_BE 0x1e000 /* PCI-Express_BE */ 276 #define RMIXL_IO_DEV_PCIE_LE 0x1f000 /* PCI-Express_LE */ 277 #define RMIXL_IO_DEV_SRIO_BE 0x1e000 /* SRIO_BE */ 278 #define RMIXL_IO_DEV_SRIO_LE 0x1f000 /* SRIO_LE */ 279 #define RMIXL_IO_DEV_XAUI_1 0x20000 /* XAUI Interface_1 */ 280 /* when SGMII Interface_[4-7] are not used */ 281 #define RMIXL_IO_DEV_GMAC_4 0x20000 /* SGMII-Interface_4, Port SGMII4 */ 282 #define RMIXL_IO_DEV_GMAC_5 0x21000 /* SGMII-Interface_5, Port SGMII5 */ 283 #define RMIXL_IO_DEV_GMAC_6 0x22000 /* SGMII-Interface_6, Port SGMII6 */ 284 #define RMIXL_IO_DEV_GMAC_7 0x23000 /* SGMII-Interface_7, Port SGMII7 */ 285 #define RMIXL_IO_DEV_USB_A 0x24000 /* USB Interface Low Address Space */ 286 #define RMIXL_IO_DEV_USB_B 0x25000 /* USB Interface High Address Space */ 287 #endif /* MIPS64_XLS */ 288 289 290 /* 291 * the Programming Reference Manual 292 * lists "Reg ID" values not offsets; 293 * offset = id * 4 294 */ 295 #define _RMIXL_OFFSET(id) ((id) * 4) 296 297 298 /* 299 * System Bridge Controller registers 300 * offsets are relative to RMIXL_IO_DEV_BRIDGE 301 */ 302 #define RMIXL_SBC_DRAM_NBARS 8 303 #define RMIXL_SBC_DRAM_BAR(n) _RMIXL_OFFSET(0x000 + (n)) 304 /* DRAM Region Base Address Regs[0-7] */ 305 #define RMIXL_SBC_DRAM_CHNAC_DTR(n) _RMIXL_OFFSET(0x008 + (n)) 306 /* DRAM Region Channels A,C Address Translation Regs[0-7] */ 307 #define RMIXL_SBC_DRAM_CHNBD_DTR(n) _RMIXL_OFFSET(0x010 + (n)) 308 /* DRAM Region Channels B,D Address Translation Regs[0-7] */ 309 #define RMIXL_SBC_DRAM_BRIDGE_CFG _RMIXL_OFFSET(0x18) /* SBC DRAM config reg */ 310 311 #define RMIXL_SBC_IO_BAR _RMIXL_OFFSET(0x19) /* I/O Config Base Addr reg */ 312 #define RMIXL_SBC_FLASH_BAR _RMIXL_OFFSET(0x1a) /* Flash Memory Base Addr reg */ 313 314 #if defined(MIPS64_XLR) 315 #define RMIXLR_SBC_SRAM_BAR _RMIXL_OFFSET(0x1b) /* SRAM Base Addr reg */ 316 #define RMIXLR_SBC_HTMEM_BAR _RMIXL_OFFSET(0x1c) /* HyperTransport Mem Base Addr reg */ 317 #define RMIXLR_SBC_HTINT_BAR _RMIXL_OFFSET(0x1d) /* HyperTransport Interrupt Base Addr reg */ 318 #define RMIXLR_SBC_HTPIC_BAR _RMIXL_OFFSET(0x1e) /* HyperTransport Legacy PIC Base Addr reg */ 319 #define RMIXLR_SBC_HTSM_BAR _RMIXL_OFFSET(0x1f) /* HyperTransport System Management Base Addr reg */ 320 #define RMIXLR_SBC_HTIO_BAR _RMIXL_OFFSET(0x20) /* HyperTransport IO Base Addr reg */ 321 #define RMIXLR_SBC_HTCFG_BAR _RMIXL_OFFSET(0x21) /* HyperTransport Configuration Base Addr reg */ 322 #define RMIXLR_SBC_PCIX_CFG_BAR _RMIXL_OFFSET(0x22) /* PCI-X Configuration Base Addr reg */ 323 #define RMIXLR_SBC_PCIX_MEM_BAR _RMIXL_OFFSET(0x23) /* PCI-X Mem Base Addr reg */ 324 #define RMIXLR_SBC_PCIX_IO_BAR _RMIXL_OFFSET(0x24) /* PCI-X IO Base Addr reg */ 325 #define RMIXLR_SBC_SYS2IO_CREDITS _RMIXL_OFFSET(0x35) /* System Bridge I/O Transaction Credits register */ 326 #endif /* MIPS64_XLR */ 327 #if defined(MIPS64_XLS) 328 #define RMIXLS_SBC_PCIE_CFG_BAR _RMIXL_OFFSET(0x40) /* PCI Configuration BAR */ 329 #define RMIXLS_SBC_PCIE_ECFG_BAR _RMIXL_OFFSET(0x41) /* PCI Extended Configuration BAR */ 330 #define RMIXLS_SBC_PCIE_MEM_BAR _RMIXL_OFFSET(0x42) /* PCI Memory region BAR */ 331 #define RMIXLS_SBC_PCIE_IO_BAR _RMIXL_OFFSET(0x43) /* PCI IO region BAR */ 332 #endif /* MIPS64_XLS */ 333 334 /* 335 * Address Error registers 336 * offsets are relative to RMIXL_IO_DEV_BRIDGE 337 */ 338 #define RMIXL_ADDR_ERR_DEVICE_MASK _RMIXL_OFFSET(0x25) /* Address Error Device Mask */ 339 #define RMIXL_ADDR_ERR_DEVICE_MASK_2 _RMIXL_OFFSET(0x44) /* extension of Device Mask */ 340 #define RMIXL_ADDR_ERR_AERR0_LOG1 _RMIXL_OFFSET(0x26) /* Address Error Set 0 Log 1 */ 341 #define RMIXL_ADDR_ERR_AERR0_LOG2 _RMIXL_OFFSET(0x27) /* Address Error Set 0 Log 2 */ 342 #define RMIXL_ADDR_ERR_AERR0_LOG3 _RMIXL_OFFSET(0x28) /* Address Error Set 0 Log 3 */ 343 #define RMIXL_ADDR_ERR_AERR0_DEVSTAT _RMIXL_OFFSET(0x29) /* Address Error Set 0 irpt status */ 344 #define RMIXL_ADDR_ERR_AERR1_LOG1 _RMIXL_OFFSET(0x2a) /* Address Error Set 1 Log 1 */ 345 #define RMIXL_ADDR_ERR_AERR1_LOG2 _RMIXL_OFFSET(0x2b) /* Address Error Set 1 Log 2 */ 346 #define RMIXL_ADDR_ERR_AERR1_LOG3 _RMIXL_OFFSET(0x2c) /* Address Error Set 1 Log 3 */ 347 #define RMIXL_ADDR_ERR_AERR1_DEVSTAT _RMIXL_OFFSET(0x2d) /* Address Error Set 1 irpt status */ 348 #define RMIXL_ADDR_ERR_AERR0_EN _RMIXL_OFFSET(0x2e) /* Address Error Set 0 irpt enable */ 349 #define RMIXL_ADDR_ERR_AERR0_UPG _RMIXL_OFFSET(0x2f) /* Address Error Set 0 Upgrade */ 350 #define RMIXL_ADDR_ERR_AERR0_CLEAR _RMIXL_OFFSET(0x30) /* Address Error Set 0 irpt clear */ 351 #define RMIXL_ADDR_ERR_AERR1_CLEAR _RMIXL_OFFSET(0x31) /* Address Error Set 1 irpt clear */ 352 #define RMIXL_ADDR_ERR_SBE_COUNTS _RMIXL_OFFSET(0x32) /* Single Bit Error Counts */ 353 #define RMIXL_ADDR_ERR_DBE_COUNTS _RMIXL_OFFSET(0x33) /* Double Bit Error Counts */ 354 #define RMIXL_ADDR_ERR_BITERR_INT_EN _RMIXL_OFFSET(0x33) /* Bit Error intr enable */ 355 356 /* 357 * RMIXL_SBC_FLASH_BAR bit defines 358 */ 359 #define RMIXL_FLASH_BAR_BASE __BITS(31,16) /* phys address bits 39:24 */ 360 #define RMIXL_FLASH_BAR_TO_BA(r) \ 361 (((r) & RMIXL_FLASH_BAR_BASE) << (24 - 16)) 362 #define RMIXL_FLASH_BAR_MASK __BITS(15,5) /* phys address mask bits 34:24 */ 363 #define RMIXL_FLASH_BAR_TO_MASK(r) \ 364 (((((r) & RMIXL_FLASH_BAR_MASK)) << (24 - 5)) | __BITS(23, 0)) 365 #define RMIXL_FLASH_BAR_RESV __BITS(4,1) /* (reserved) */ 366 #define RMIXL_FLASH_BAR_ENB __BIT(0) /* 1=Enable */ 367 #define RMIXL_FLASH_BAR_MASK_MAX RMIXL_FLASH_BAR_TO_MASK(RMIXL_FLASH_BAR_MASK) 368 369 /* 370 * RMIXL_SBC_DRAM_BAR bit defines 371 */ 372 #define RMIXL_DRAM_BAR_BASE_ADDR __BITS(31,16) /* bits 39:24 of Base Address */ 373 #define DRAM_BAR_TO_BASE(r) \ 374 (((r) & RMIXL_DRAM_BAR_BASE_ADDR) << (24 - 16)) 375 #define RMIXL_DRAM_BAR_ADDR_MASK __BITS(15,4) /* bits 35:24 of Address Mask */ 376 #define DRAM_BAR_TO_SIZE(r) \ 377 ((((r) & RMIXL_DRAM_BAR_ADDR_MASK) + __BIT(4)) << (24 - 4)) 378 #define RMIXL_DRAM_BAR_INTERLEAVE __BITS(3,1) /* Interleave Mode */ 379 #define RMIXL_DRAM_BAR_STATUS __BIT(0) /* 1='region enabled' */ 380 381 /* 382 * RMIXL_SBC_DRAM_CHNAC_DTR and 383 * RMIXL_SBC_DRAM_CHNBD_DTR bit defines 384 * insert 'divisions' (0, 1 or 2) bits 385 * of value 'partition' 386 * at 'position' bit location. 387 */ 388 #define RMIXL_DRAM_DTR_RESa __BITS(31,14) 389 #define RMIXL_DRAM_DTR_PARTITION __BITS(13,12) 390 #define RMIXL_DRAM_DTR_RESb __BITS(11,10) 391 #define RMIXL_DRAM_DTR_DIVISIONS __BITS(9,8) 392 #define RMIXL_DRAM_DTR_RESc __BITS(7,6) 393 #define RMIXL_DRAM_DTR_POSITION __BITS(5,0) 394 #define RMIXL_DRAM_DTR_RESV \ 395 (RMIXL_DRAM_DTR_RESa|RMIXL_DRAM_DTR_RESb|RMIXL_DRAM_DTR_RESc) 396 397 /* 398 * RMIXL_SBC_DRAM_BRIDGE_CFG bit defines 399 */ 400 #define RMIXL_DRAM_CFG_RESa __BITS(31,13) 401 #define RMIXL_DRAM_CFG_CHANNEL_MODE __BIT(12) 402 #define RMIXL_DRAM_CFG_RESb __BIT(11) 403 #define RMIXL_DRAM_CFG_INTERLEAVE_MODE __BITS(10,8) 404 #define RMIXL_DRAM_CFG_RESc __BITS(7,5) 405 #define RMIXL_DRAM_CFG_BUS_MODE __BIT(4) 406 #define RMIXL_DRAM_CFG_RESd __BITS(3,2) 407 #define RMIXL_DRAM_CFG_DRAM_MODE __BITS(1,0) /* 1=DDR2 */ 408 409 /* 410 * RMIXL_SBC_XLR_PCIX_CFG_BAR bit defines 411 */ 412 #define RMIXL_PCIX_CFG_BAR_BASE __BITS(31,17) /* phys address bits 39:25 */ 413 #define RMIXL_PCIX_CFG_BAR_BA_SHIFT (25 - 17) 414 #define RMIXL_PCIX_CFG_BAR_TO_BA(r) \ 415 (((r) & RMIXL_PCIX_CFG_BAR_BASE) << RMIXL_PCIX_CFG_BAR_BA_SHIFT) 416 #define RMIXL_PCIX_CFG_BAR_RESV __BITS(16,1) /* (reserved) */ 417 #define RMIXL_PCIX_CFG_BAR_ENB __BIT(0) /* 1=Enable */ 418 #define RMIXL_PCIX_CFG_SIZE __BIT(25) 419 #define RMIXL_PCIX_CFG_BAR(ba, en) \ 420 ((uint32_t)(((ba) >> (25 - 17)) | ((en) ? RMIXL_PCIX_CFG_BAR_ENB : 0))) 421 422 /* 423 * RMIXLR_SBC_PCIX_MEM_BAR bit defines 424 */ 425 #define RMIXL_PCIX_MEM_BAR_BASE __BITS(31,16) /* phys address bits 39:24 */ 426 #define RMIXL_PCIX_MEM_BAR_TO_BA(r) \ 427 (((r) & RMIXL_PCIX_MEM_BAR_BASE) << (24 - 16)) 428 #define RMIXL_PCIX_MEM_BAR_MASK __BITS(15,1) /* phys address mask bits 38:24 */ 429 #define RMIXL_PCIX_MEM_BAR_TO_SIZE(r) \ 430 ((((r) & RMIXL_PCIX_MEM_BAR_MASK) + 2) << (24 - 1)) 431 #define RMIXL_PCIX_MEM_BAR_ENB __BIT(0) /* 1=Enable */ 432 #define RMIXL_PCIX_MEM_BAR(ba, en) \ 433 ((uint32_t)(((ba) >> (24 - 16)) | ((en) ? RMIXL_PCIX_MEM_BAR_ENB : 0))) 434 435 /* 436 * RMIXLR_SBC_PCIX_IO_BAR bit defines 437 */ 438 #define RMIXL_PCIX_IO_BAR_BASE __BITS(31,18) /* phys address bits 39:26 */ 439 #define RMIXL_PCIX_IO_BAR_TO_BA(r) \ 440 (((r) & RMIXL_PCIX_IO_BAR_BASE) << (26 - 18)) 441 #define RMIXL_PCIX_IO_BAR_RESV __BITS(17,7) /* (reserve) */ 442 #define RMIXL_PCIX_IO_BAR_MASK __BITS(6,1) /* phys address mask bits 31:26 */ 443 #define RMIXL_PCIX_IO_BAR_TO_SIZE(r) \ 444 ((((r) & RMIXL_PCIX_IO_BAR_MASK) + 2) << (26 - 1)) 445 #define RMIXL_PCIX_IO_BAR_ENB __BIT(0) /* 1=Enable */ 446 #define RMIXL_PCIX_IO_BAR(ba, en) \ 447 ((uint32_t)(((ba) >> (26 - 18)) | ((en) ? RMIXL_PCIX_IO_BAR_ENB : 0))) 448 449 /* 450 * RMIXLS_SBC_PCIE_CFG_BAR bit defines 451 */ 452 #define RMIXL_PCIE_CFG_BAR_BASE __BITS(31,17) /* phys address bits 39:25 */ 453 #define RMIXL_PCIE_CFG_BAR_BA_SHIFT (25 - 17) 454 #define RMIXL_PCIE_CFG_BAR_TO_BA(r) \ 455 (((r) & RMIXL_PCIE_CFG_BAR_BASE) << RMIXL_PCIE_CFG_BAR_BA_SHIFT) 456 #define RMIXL_PCIE_CFG_BAR_RESV __BITS(16,1) /* (reserved) */ 457 #define RMIXL_PCIE_CFG_BAR_ENB __BIT(0) /* 1=Enable */ 458 #define RMIXL_PCIE_CFG_SIZE __BIT(25) 459 #define RMIXL_PCIE_CFG_BAR(ba, en) \ 460 ((uint32_t)(((ba) >> (25 - 17)) | ((en) ? RMIXL_PCIE_CFG_BAR_ENB : 0))) 461 462 /* 463 * RMIXLS_SBC_PCIE_ECFG_BAR bit defines 464 * (PCIe extended config space) 465 */ 466 #define RMIXL_PCIE_ECFG_BAR_BASE __BITS(31,21) /* phys address bits 39:29 */ 467 #define RMIXL_PCIE_ECFG_BAR_BA_SHIFT (29 - 21) 468 #define RMIXL_PCIE_ECFG_BAR_TO_BA(r) \ 469 (((r) & RMIXL_PCIE_ECFG_BAR_BASE) << RMIXL_PCIE_ECFG_BAR_BA_SHIFT) 470 #define RMIXL_PCIE_ECFG_BAR_RESV __BITS(20,1) /* (reserved) */ 471 #define RMIXL_PCIE_ECFG_BAR_ENB __BIT(0) /* 1=Enable */ 472 #define RMIXL_PCIE_ECFG_SIZE __BIT(29) 473 #define RMIXL_PCIE_ECFG_BAR(ba, en) \ 474 ((uint32_t)(((ba) >> (29 - 21)) | ((en) ? RMIXL_PCIE_ECFG_BAR_ENB : 0))) 475 476 /* 477 * RMIXLS_SBC_PCIE_MEM_BAR bit defines 478 */ 479 #define RMIXL_PCIE_MEM_BAR_BASE __BITS(31,16) /* phys address bits 39:24 */ 480 #define RMIXL_PCIE_MEM_BAR_TO_BA(r) \ 481 (((r) & RMIXL_PCIE_MEM_BAR_BASE) << (24 - 16)) 482 #define RMIXL_PCIE_MEM_BAR_MASK __BITS(15,1) /* phys address mask bits 38:24 */ 483 #define RMIXL_PCIE_MEM_BAR_TO_SIZE(r) \ 484 ((((r) & RMIXL_PCIE_MEM_BAR_MASK) + 2) << (24 - 1)) 485 #define RMIXL_PCIE_MEM_BAR_ENB __BIT(0) /* 1=Enable */ 486 #define RMIXL_PCIE_MEM_BAR(ba, en) \ 487 ((uint32_t)(((ba) >> (24 - 16)) | ((en) ? RMIXL_PCIE_MEM_BAR_ENB : 0))) 488 489 /* 490 * RMIXLS_SBC_PCIE_IO_BAR bit defines 491 */ 492 #define RMIXL_PCIE_IO_BAR_BASE __BITS(31,18) /* phys address bits 39:26 */ 493 #define RMIXL_PCIE_IO_BAR_TO_BA(r) \ 494 (((r) & RMIXL_PCIE_IO_BAR_BASE) << (26 - 18)) 495 #define RMIXL_PCIE_IO_BAR_RESV __BITS(17,7) /* (reserve) */ 496 #define RMIXL_PCIE_IO_BAR_MASK __BITS(6,1) /* phys address mask bits 31:26 */ 497 #define RMIXL_PCIE_IO_BAR_TO_SIZE(r) \ 498 ((((r) & RMIXL_PCIE_IO_BAR_MASK) + 2) << (26 - 1)) 499 #define RMIXL_PCIE_IO_BAR_ENB __BIT(0) /* 1=Enable */ 500 #define RMIXL_PCIE_IO_BAR(ba, en) \ 501 ((uint32_t)(((ba) >> (26 - 18)) | ((en) ? RMIXL_PCIE_IO_BAR_ENB : 0))) 502 503 504 /* 505 * Programmable Interrupt Controller registers 506 * the Programming Reference Manual table 10.4 507 * lists "Reg ID" values not offsets 508 * Offsets are relative to RMIXL_IO_DEV_BRIDGE 509 */ 510 #define RMIXL_PIC_CONTROL _RMIXL_OFFSET(0x0) 511 #define RMIXL_PIC_IPIBASE _RMIXL_OFFSET(0x4) 512 #define RMIXL_PIC_INTRACK _RMIXL_OFFSET(0x6) 513 #define RMIXL_PIC_WATCHdOGMAXVALUE0 _RMIXL_OFFSET(0x8) 514 #define RMIXL_PIC_WATCHDOGMAXVALUE1 _RMIXL_OFFSET(0x9) 515 #define RMIXL_PIC_WATCHDOGMASK0 _RMIXL_OFFSET(0xa) 516 #define RMIXL_PIC_WATCHDOGMASK1 _RMIXL_OFFSET(0xb) 517 #define RMIXL_PIC_WATCHDOGHEARTBEAT0 _RMIXL_OFFSET(0xc) 518 #define RMIXL_PIC_WATCHDOGHEARTBEAT1 _RMIXL_OFFSET(0xd) 519 #define RMIXL_PIC_IRTENTRYC0(n) _RMIXL_OFFSET(0x40 + (n)) /* 0<=n<=31 */ 520 #define RMIXL_PIC_IRTENTRYC1(n) _RMIXL_OFFSET(0x80 + (n)) /* 0<=n<=31 */ 521 #define RMIXL_PIC_SYSTMRMAXVALC0(n) _RMIXL_OFFSET(0x100 + (n)) /* 0<=n<=7 */ 522 #define RMIXL_PIC_SYSTMRMAXVALC1(n) _RMIXL_OFFSET(0x110 + (n)) /* 0<=n<=7 */ 523 #define RMIXL_PIC_SYSTMRC0(n) _RMIXL_OFFSET(0x120 + (n)) /* 0<=n<=7 */ 524 #define RMIXL_PIC_SYSTMRC1(n) _RMIXL_OFFSET(0x130 + (n)) /* 0<=n<=7 */ 525 526 /* 527 * RMIXL_PIC_CONTROL bits 528 */ 529 #define RMIXL_PIC_CONTROL_WATCHDOG_ENB __BIT(0) 530 #define RMIXL_PIC_CONTROL_GEN_NMI __BITS(2,1) /* do NMI after n WDog irpts */ 531 #define RMIXL_PIC_CONTROL_GEN_NMIn(n) (((n) << 1) & RMIXL_PIC_CONTROL_GEN_NMI) 532 #define RMIXL_PIC_CONTROL_RESa __BITS(7,3) 533 #define RMIXL_PIC_CONTROL_TIMER_ENB __BITS(15,8) /* per-Timer enable bits */ 534 #define RMIXL_PIC_CONTROL_TIMER_ENBn(n) ((1 << (8 + (n))) & RMIXL_PIC_CONTROL_TIMER_ENB) 535 #define RMIXL_PIC_CONTROL_RESb __BITS(31,16) 536 #define RMIXL_PIC_CONTROL_RESV \ 537 (RMIXL_PIC_CONTROL_RESa|RMIXL_PIC_CONTROL_RESb) 538 539 /* 540 * RMIXL_PIC_IPIBASE bits 541 */ 542 #define RMIXL_PIC_IPIBASE_VECTORNUM __BITS(5,0) 543 #define RMIXL_PIC_IPIBASE_RESa __BIT(6) /* undocumented bit */ 544 #define RMIXL_PIC_IPIBASE_BCAST __BIT(7) 545 #define RMIXL_PIC_IPIBASE_NMI __BIT(8) 546 #define RMIXL_PIC_IPIBASE_ID __BITS(31,16) 547 #define RMIXL_PIC_IPIBASE_ID_RESb __BITS(31,23) 548 #define RMIXL_PIC_IPIBASE_ID_CORE __BITS(22,20) /* Physical CPU ID */ 549 #define RMIXL_PIC_IPIBASE_ID_CORE_SHIFT 20 550 #define RMIXL_PIC_IPIBASE_ID_RESc __BITS(19,18) 551 #define RMIXL_PIC_IPIBASE_ID_THREAD __BITS(17,16) /* Thread ID */ 552 #define RMIXL_PIC_IPIBASE_ID_THREAD_SHIFT 16 553 #define RMIXL_PIC_IPIBASE_ID_RESV \ 554 (RMIXL_PIC_IPIBASE_ID_RESa|RMIXL_PIC_IPIBASE_ID_RESb \ 555 |RMIXL_PIC_IPIBASE_ID_RESc) 556 557 /* 558 * RMIXL_PIC_IRTENTRYC0 bits 559 * IRT Entry low word 560 */ 561 #define RMIXL_PIC_IRTENTRYC0_TMASK __BITS(7,0) /* Thread Mask */ 562 #define RMIXL_PIC_IRTENTRYC0_RESa __BITS(3,2) /* write as 0 */ 563 #define RMIXL_PIC_IRTENTRYC0_RESb __BITS(31,8) /* write as 0 */ 564 #define RMIXL_PIC_IRTENTRYC0_RESV \ 565 (RMIXL_PIC_IRTENTRYC0_RESa | RMIXL_PIC_IRTENTRYC0_RESb) 566 567 /* 568 * RMIXL_PIC_IRTENTRYC1 bits 569 * IRT Entry high word 570 */ 571 #define RMIXL_PIC_IRTENTRYC1_INTVEC __BITS(5,0) /* maps to bit# in CPU's EIRR */ 572 #define RMIXL_PIC_IRTENTRYC1_GL __BIT(6) /* 0=Global; 1=Local */ 573 #define RMIXL_PIC_IRTENTRYC1_NMI __BIT(7) /* 0=Maskable; 1=NMI */ 574 #define RMIXL_PIC_IRTENTRYC1_RESV __BITS(28,8) 575 #define RMIXL_PIC_IRTENTRYC1_P __BIT(29) /* 0=Rising/High; 1=Falling/Low */ 576 #define RMIXL_PIC_IRTENTRYC1_TRG __BIT(30) /* 0=Edge; 1=Level */ 577 #define RMIXL_PIC_IRTENTRYC1_VALID __BIT(31) /* 0=Invalid; 1=Valid IRT Entry */ 578 579 580 /* 581 * GPIO Controller registers 582 * bit number is same as GPIO pin number for the GPIO masks below 583 */ 584 585 #define RMIXL_GPIO_NSIGNALS 25 /* 25 GPIO signals supported in HW */ 586 587 /* GPIO Signal Registers */ 588 #define RMIXL_GPIO_INT_ENB _RMIXL_OFFSET(0x0) /* Interrupt Enable register */ 589 #define RMIXL_GPIO_INT_INV _RMIXL_OFFSET(0x1) /* Interrupt Inversion register */ 590 #define RMIXL_GPIO_IO_DIR _RMIXL_OFFSET(0x2) /* I/O Direction register */ 591 #define RMIXL_GPIO_OUTPUT _RMIXL_OFFSET(0x3) /* Output Write register */ 592 #define RMIXL_GPIO_INPUT _RMIXL_OFFSET(0x4) /* Intput Read register *//* ro */ 593 #define RMIXL_GPIO_INT_CLR _RMIXL_OFFSET(0x5) /* Interrupt Clear register */ 594 #define RMIXL_GPIO_INT_STS _RMIXL_OFFSET(0x6) /* Interrupt Status register *//* ro */ 595 #define RMIXL_GPIO_INT_TYP _RMIXL_OFFSET(0x7) /* Interrupt Type register */ 596 #define RMIXL_GPIO_RESET _RMIXL_OFFSET(0x8) /* XLR/XLS Soft Reset register */ 597 598 599 /* 600 * common GPIO bit masks 601 */ 602 #define RMIXL_GPIO_PGM_MASK (__BITS(13,0) | __BITS(22,20) | __BIT(24)) /* programmable pins */ 603 #define RMIXL_GPIO_INTR_MASK (__BITS(13,0) | __BITS(24,20)) /* intr-capable pins */ 604 605 /* 606 * never-programmable fixed-function GPIO signals 607 * bit number is same as GPIO pin 608 */ 609 #define RMIXL_GPIO_FLASH_CPUID __BITS(16,14) /* Flash CPU ID, output only */ 610 #define RMIXL_GPIO_FLASH_CPUID_SHFT 14 611 #define RMIXL_GPIO_FLASH_RDY __BIT(17) /* Flash memory ready, input only */ 612 #define RMIXL_GPIO_FLASH_ADV __BIT(18) /* Flash memory address valid, output only */ 613 #define RMIXL_GPIO_FLASH_RESET_N __BIT(19) /* Flash memory reset, output only */ 614 #define RMIXL_GPIO_THERMAL_INTRPT __BIT(23) /* Thermal interrupt, interrupt only */ 615 616 /* 617 * RMIXL_GPIO_INT_ENB bits 618 */ 619 #define RMIXL_GPIO_INT_ENB_MASK RMIXL_GPIO_INTR_MASK 620 621 /* 622 * RMIXL_GPIO_INT_INV bits 623 * inversion control is possible only on the programmable pins 624 */ 625 #define RMIXL_GPIO_INT_INV_MASK RMIXL_GPIO_PGM_MASK 626 627 /* 628 * RMIXL_GPIO_IO_DIR bits 629 * direction control is possible only on the programmable pins 630 */ 631 #define RMIXL_GPIO_IO_DIR_MASK RMIXL_GPIO_PGM_MASK 632 633 /* 634 * RMIXL_GPIO_OUTPUT bits 635 * output is possible only on the programmable pins and fixed-function outputs 636 */ 637 #define RMIXL_GPIO_OUTPUT_MASK (RMIXL_GPIO_PGM_MASK \ 638 | RMIXL_GPIO_FLASH_ADV \ 639 | RMIXL_GPIO_FLASH_RESET_N) 640 641 /* 642 * RMIXL_GPIO_INPUT bits 643 * input is possible only on the programmable pins and fixed-function inputs & interrupts 644 */ 645 #define RMIXL_GPIO_INPUT_MASK (RMIXL_GPIO_PGM_MASK \ 646 | RMIXL_GPIO_FLASH_RDY \ 647 | RMIXL_GPIO_THERMAL_INTRPT) 648 649 /* 650 * RMIXL_GPIO_INT_CLR bits 651 */ 652 #define RMIXL_GPIO_INT_CLR_MASK RMIXL_GPIO_INTR_MASK 653 654 /* 655 * RMIXL_GPIO_INT_STS bits 656 */ 657 #define RMIXL_GPIO_INT_STS_INT_HI_L __BIT(25) /* INT_HI_L (input) requested */ 658 #define RMIXL_GPIO_INT_STS_INT_LO_L __BIT(26) /* INT_LO_L (input) requested */ 659 #define RMIXL_GPIO_INT_STS_MASK (RMIXL_GPIO_INTR_MASK \ 660 | RMIXL_GPIO_INT_STS_INT_LO_L \ 661 | RMIXL_GPIO_INT_STS_INT_HI_L) 662 663 /* 664 * RMIXL_GPIO_INT_TYP bits 665 * 0=Edge, 1=Level 666 */ 667 #define RMIXL_GPIO_INT_TYP_MASK RMIXL_GPIO_INTR_MASK 668 669 /* 670 * RMIXL_GPIO_RESET bits 671 */ 672 #define RMIXL_GPIO_RESET_RESV __BITS(31,1) 673 #define RMIXL_GPIO_RESET_RESET __BIT(0) 674 675 676 /* GPIO System Control Registers */ 677 #define RMIXL_GPIO_RESET_CFG _RMIXL_OFFSET(0x15) /* Reset Configuration register */ 678 #define RMIXL_GPIO_THERMAL_CSR _RMIXL_OFFSET(0x16) /* Thermal Control/Status register */ 679 #define RMIXL_GPIO_THERMAL_SHFT _RMIXL_OFFSET(0x17) /* Thermal Shift register */ 680 #define RMIXL_GPIO_BIST_ALL_STS _RMIXL_OFFSET(0x18) /* BIST All Status register */ 681 #define RMIXL_GPIO_BIST_EACH_STS _RMIXL_OFFSET(0x19) /* BIST Each Status register */ 682 #define RMIXL_GPIO_SGMII_0_3_PHY_CTL _RMIXL_OFFSET(0x20) /* SGMII #0..3 PHY Control register */ 683 #define RMIXL_GPIO_AUI_0_PHY_CTL _RMIXL_OFFSET(0x20) /* AUI port#0 PHY Control register */ 684 #define RMIXL_GPIO_SGMII_4_7_PLL_CTL _RMIXL_OFFSET(0x21) /* SGMII #4..7 PLL Control register */ 685 #define RMIXL_GPIO_AUI_1_PLL_CTL _RMIXL_OFFSET(0x21) /* AUI port#1 PLL Control register */ 686 #define RMIXL_GPIO_SGMII_4_7_PHY_CTL _RMIXL_OFFSET(0x22) /* SGMII #4..7 PHY Control register */ 687 #define RMIXL_GPIO_AUI_1_PHY_CTL _RMIXL_OFFSET(0x22) /* AUI port#1 PHY Control register */ 688 #define RMIXL_GPIO_INT_MAP _RMIXL_OFFSET(0x25) /* Interrupt Map to PIC, 0=int14, 1=int30 */ 689 #define RMIXL_GPIO_EXT_INT _RMIXL_OFFSET(0x26) /* External Interrupt control register */ 690 #define RMIXL_GPIO_CPU_RST _RMIXL_OFFSET(0x28) /* CPU Reset control register */ 691 #define RMIXL_GPIO_LOW_PWR_DIS _RMIXL_OFFSET(0x29) /* Low Power Dissipation register */ 692 #define RMIXL_GPIO_RANDOM _RMIXL_OFFSET(0x2b) /* Low Power Dissipation register */ 693 #define RMIXL_GPIO_CPU_CLK_DIS _RMIXL_OFFSET(0x2d) /* CPU Clock Disable register */ 694 695 /* 696 * RMIXL_GPIO_RESET_CFG bits 697 */ 698 #define RMIXL_GPIO_RESET_CFG_RESa __BITS(31,28) 699 #define RMIXL_GPIO_RESET_CFG_PCIE_SRIO_SEL __BITS(27,26) /* PCIe or SRIO Select: 700 * 00 = PCIe selected, SRIO not available 701 * 01 = SRIO selected, 1.25 Gbaud (1.0 Gbps) 702 * 10 = SRIO selected, 2.25 Gbaud (2.0 Gbps) 703 * 11 = SRIO selected, 3.125 Gbaud (2.5 Gbps) 704 */ 705 #define RMIXL_GPIO_RESET_CFG_XAUI_PORT1_SEL __BIT(25) /* XAUI Port 1 Select: 706 * 0 = Disabled - Port is SGMII ports 4-7 707 * 1 = Enabled - Port is 4-lane XAUI Port 1 708 */ 709 #define RMIXL_GPIO_RESET_CFG_XAUI_PORT0_SEL __BIT(24) /* XAUI Port 0 Select: 710 * 0 = Disabled - Port is SGMII ports 0-3 711 * 1 = Enabled - Port is 4-lane XAUI Port 0 712 */ 713 #define RMIXL_GPIO_RESET_CFG_RESb __BIT(23) 714 #define RMIXL_GPIO_RESET_CFG_USB_DEV __BIT(22) /* USB Device: 715 * 0 = Device Mode 716 * 1 = Host Mode 717 */ 718 #define RMIXL_GPIO_RESET_CFG_PCIE_CFG __BITS(21,20) /* PCIe or SRIO configuration */ 719 #define RMIXL_GPIO_RESET_CFG_FLASH33_EN __BIT(19) /* Flash 33 MHZ Enable: 720 * 0 = 66.67 MHz 721 * 1 = 33.33 MHz 722 */ 723 #define RMIXL_GPIO_RESET_CFG_BIST_DIAG_EN __BIT(18) /* BIST Diagnostics enable */ 724 #define RMIXL_GPIO_RESET_CFG_BIST_RUN_EN __BIT(18) /* BIST Run enable */ 725 #define RMIXL_GPIO_RESET_CFG_BOOT_NAND __BIT(16) /* Enable boot from NAND Flash */ 726 #define RMIXL_GPIO_RESET_CFG_BOOT_PCMCIA __BIT(15) /* Enable boot from PCMCIA */ 727 #define RMIXL_GPIO_RESET_CFG_FLASH_CFG __BIT(14) /* Flash 32-bit Data Configuration: 728 * 0 = 32-bit address / 16-bit data 729 * 1 = 32-bit address / 32-bit data 730 */ 731 #define RMIXL_GPIO_RESET_CFG_PCMCIA_EN __BIT(13) /* PCMCIA Enable Status */ 732 #define RMIXL_GPIO_RESET_CFG_PARITY_EN __BIT(12) /* Parity Enable Status */ 733 #define RMIXL_GPIO_RESET_CFG_BIGEND __BIT(11) /* Big Endian Mode Enable Status */ 734 #define RMIXL_GPIO_RESET_CFG_PLL1_OUT_DIV __BITS(10,8) /* PLL1 (Core PLL) Output Divider */ 735 #define RMIXL_GPIO_RESET_CFG_PLL1_FB_DIV __BITS(7,0) /* PLL1 Feedback Divider */ 736 737 /* 738 * RMIXL_GPIO_EXT_INT bits 739 */ 740 #define RMIXL_GPIO_EXT_INT_RESV __BITS(31,4) 741 #define RMIXL_GPIO_EXT_INT_HI_MASK __BIT(3) /* mask (input) INT_HI_L */ 742 #define RMIXL_GPIO_EXT_INT_LO_MASK __BIT(2) /* mask (input) INT_HI_L */ 743 #define RMIXL_GPIO_EXT_INT_HI_CTL __BIT(1) /* generate (output) INT_HI_L */ 744 #define RMIXL_GPIO_EXT_INT_LO_CTL __BIT(0) /* generate (output) INT_LO_L */ 745 746 /* 747 * RMIXL_GPIO_LOW_PWR_DIS bits 748 * except as noted, all bits are: 749 * 0 = feature enable (default) 750 * 1 = feature disable 751 */ 752 /* XXX defines are for XLS6xx, XLS4xx-Lite and XLS4xx Devices */ 753 #define RMIXL_GPIO_LOW_PWR_DIS_LP __BIT(0) /* Low Power disable */ 754 #define RMIXL_GPIO_LOW_PWR_DIS_GMAC_QD_0 __BIT(1) /* GMAC Quad 0 (GMAC 0..3) disable */ 755 #define RMIXL_GPIO_LOW_PWR_DIS_GMAC_QD_1 __BIT(2) /* GMAC Quad 1 (GMAC 4..7) disable */ 756 #define RMIXL_GPIO_LOW_PWR_DIS_USB __BIT(3) /* USB disable */ 757 #define RMIXL_GPIO_LOW_PWR_DIS_PCIE __BIT(4) /* PCIE disable */ 758 #define RMIXL_GPIO_LOW_PWR_DIS_CDE __BIT(5) /* Compression/Decompression Engine disable */ 759 #define RMIXL_GPIO_LOW_PWR_DIS_DMA __BIT(6) /* DMA Engine disable */ 760 #define RMIXL_GPIO_LOW_PWR_DIS_SAE __BITS(8,7) /* Security Acceleration Engine disable: 761 * 00 = enable (default) 762 * 01 = reserved 763 * 10 = reserved 764 * 11 = disable 765 */ 766 #define RMIXL_GPIO_LOW_PWR_DIS_RESV __BITS(31,9) 767 768 /* 769 * Peripheral I/O bus (Flash/PCMCIA) controller registers 770 */ 771 #define RMIXL_FLASH_NCS 10 /* number of chip selects */ 772 #define RMIXL_FLASH_CS_BOOT 0 /* CS0 is boot flash */ 773 #define RMIXL_FLASH_CS_PCMCIA_CF 6 /* CS6 is PCMCIA compact flash */ 774 #define RMIXL_FLASH_CSBASE_ADDRn(n) _RMIXL_OFFSET(0x00+(n)) /* CSn Base Address reg */ 775 #define RMIXL_FLASH_CSADDR_MASKn(n) _RMIXL_OFFSET(0x10+(n)) /* CSn Address Mask reg */ 776 #define RMIXL_FLASH_CSDEV_PARMn(n) _RMIXL_OFFSET(0x20+(n)) /* CSn Device Parameter reg */ 777 #define RMIXL_FLASH_CSTIME_PARMAn(n) _RMIXL_OFFSET(0x30+(n)) /* CSn Timing Parameters A reg */ 778 #define RMIXL_FLASH_CSTIME_PARMBn(n) _RMIXL_OFFSET(0x40+(n)) /* CSn Timing Parameters B reg */ 779 #define RMIXL_FLASH_INT_MASK _RMIXL_OFFSET(0x50) /* Flash Interrupt Mask reg */ 780 #define RMIXL_FLASH_INT_STATUS _RMIXL_OFFSET(0x60) /* Flash Interrupt Status reg */ 781 #define RMIXL_FLASH_ERROR_STATUS _RMIXL_OFFSET(0x70) /* Flash Error Status reg */ 782 #define RMIXL_FLASH_ERROR_ADDR _RMIXL_OFFSET(0x80) /* Flash Error Address reg */ 783 784 /* 785 * RMIXL_FLASH_CSDEV_PARMn bits 786 */ 787 #define RMIXL_FLASH_CSDEV_RESV __BITS(31,16) 788 #define RMIXL_FLASH_CSDEV_BFN __BIT(15) /* Boot From Nand 789 * 0=Boot from NOR or 790 * PCCard Type 1 Flash 791 * 1=Boot from NAND 792 */ 793 #define RMIXL_FLASH_CSDEV_NANDEN __BIT(14) /* NAND Flash Enable 794 * 0=NOR 795 * 1=NAND 796 */ 797 #define RMIXL_FLASH_CSDEV_ADVTYPE __BIT(13) /* Add Valid Sensing Type 798 * 0=level 799 * 1=pulse 800 */ 801 #define RMIXL_FLASH_CSDEV_PARITY_TYPE __BIT(12) /* Parity Type 802 * 0=even 803 * 1=odd 804 */ 805 #define RMIXL_FLASH_CSDEV_PARITY_EN __BIT(11) /* Parity Enable */ 806 #define RMIXL_FLASH_CSDEV_GENIF_EN __BIT(10) /* Generic PLD/FPGA interface mode 807 * if this bit is set, then 808 * GPIO[13:10] cannot be used 809 * for interrupts 810 */ 811 #define RMIXL_FLASH_CSDEV_PCMCIA_EN __BIT(9) /* PCMCIA Interface mode */ 812 #define RMIXL_FLASH_CSDEV_DWIDTH __BITS(8,7) /* Data Bus Width: 813 * 00: 8 bit 814 * 01: 16 bit 815 * 10: 32 bit 816 * 11: 8 bit 817 */ 818 #define RMIXL_FLASH_CSDEV_DWIDTH_SHFT 7 819 #define RMIXL_FLASH_CSDEV_MX_ADDR __BIT(6) /* Multiplexed Address 820 * 0: non-muxed 821 * AD[31:24] = Data, 822 * AD[23:0] = Addr 823 * 1: muxed 824 * External latch required 825 */ 826 #define RMIXL_FLASH_CSDEV_WAIT_POL __BIT(5) /* WAIT polarity 827 * 0: Active high 828 * 1: Active low 829 */ 830 #define RMIXL_FLASH_CSDEV_WAIT_EN __BIT(4) /* Enable External WAIT Ack mode */ 831 #define RMIXL_FLASH_CSDEV_BURST __BITS(3,1) /* Burst Length: 832 * 000: 2x 833 * 001: 4x 834 * 010: 8x 835 * 011: 16x 836 * 100: 32x 837 */ 838 #define RMIXL_FLASH_CSDEV_BURST_SHFT 1 839 #define RMIXL_FLASH_CSDEV_BURST_EN __BITS(0) /* Burst Enable */ 840 841 842 /* 843 * NAND Flash Memory Control registers 844 */ 845 #define RMIXL_NAND_CLEn(n) _RMIXL_OFFSET(0x90+(n)) /* CSn 8-bit CLE command value reg */ 846 #define RMIXL_NAND_ALEn(n) _RMIXL_OFFSET(0xa0+(n)) /* CSn 8-bit ALE address phase reg */ 847 848 /* 849 * PCIE Interface Controller registers 850 */ 851 #define RMIXL_PCIE_CTRL1 _RMIXL_OFFSET(0x0) 852 #define RMIXL_PCIE_CTRL2 _RMIXL_OFFSET(0x1) 853 #define RMIXL_PCIE_CTRL3 _RMIXL_OFFSET(0x2) 854 #define RMIXL_PCIE_CTRL4 _RMIXL_OFFSET(0x3) 855 #define RMIXL_PCIE_CTRL _RMIXL_OFFSET(0x4) 856 #define RMIXL_PCIE_IOBM_TIMER _RMIXL_OFFSET(0x5) 857 #define RMIXL_PCIE_MSI_CMD _RMIXL_OFFSET(0x6) 858 #define RMIXL_PCIE_MSI_RESP _RMIXL_OFFSET(0x7) 859 #define RMIXL_PCIE_DWC_CRTL5 _RMIXL_OFFSET(0x8) /* not on XLS408Lite, XLS404Lite */ 860 #define RMIXL_PCIE_DWC_CRTL6 _RMIXL_OFFSET(0x9) /* not on XLS408Lite, XLS404Lite */ 861 #define RMIXL_PCIE_IOBM_SWAP_MEM_BASE _RMIXL_OFFSET(0x10) 862 #define RMIXL_PCIE_IOBM_SWAP_MEM_LIMIT _RMIXL_OFFSET(0x11) 863 #define RMIXL_PCIE_IOBM_SWAP_IO_BASE _RMIXL_OFFSET(0x12) 864 #define RMIXL_PCIE_IOBM_SWAP_IO_LIMIT _RMIXL_OFFSET(0x13) 865 #define RMIXL_PCIE_TRGT_CHRNT_MEM_BASE _RMIXL_OFFSET(0x14) 866 #define RMIXL_PCIE_TRGT_CHRNT_MEM_LIMIT _RMIXL_OFFSET(0x15) 867 #define RMIXL_PCIE_TRGT_L2ALC_MEM_BASE _RMIXL_OFFSET(0x16) 868 #define RMIXL_PCIE_TRGT_L2ALC_MEM_LIMIT _RMIXL_OFFSET(0x17) 869 #define RMIXL_PCIE_TRGT_REX_MEM_BASE _RMIXL_OFFSET(0x18) 870 #define RMIXL_PCIE_TRGT_REX_MEM_LIMIT _RMIXL_OFFSET(0x19) 871 #define RMIXL_PCIE_EP_MEM_BASE _RMIXL_OFFSET(0x1a) 872 #define RMIXL_PCIE_EP_MEM_LIMIT _RMIXL_OFFSET(0x1b) 873 #define RMIXL_PCIE_EP_ADDR_MAP_ENTRY0 _RMIXL_OFFSET(0x1c) 874 #define RMIXL_PCIE_EP_ADDR_MAP_ENTRY1 _RMIXL_OFFSET(0x1d) 875 #define RMIXL_PCIE_EP_ADDR_MAP_ENTRY2 _RMIXL_OFFSET(0x1e) 876 #define RMIXL_PCIE_EP_ADDR_MAP_ENTRY3 _RMIXL_OFFSET(0x1f) 877 #define RMIXL_PCIE_LINK0_STATE _RMIXL_OFFSET(0x20) 878 #define RMIXL_PCIE_LINK1_STATE _RMIXL_OFFSET(0x21) 879 #define RMIXL_PCIE_IOBM_INT_STATUS _RMIXL_OFFSET(0x22) 880 #define RMIXL_PCIE_IOBM_INT_ENABLE _RMIXL_OFFSET(0x23) 881 #define RMIXL_PCIE_LINK0_MSI_STATUS _RMIXL_OFFSET(0x24) 882 #define RMIXL_PCIE_LINK1_MSI_STATUS _RMIXL_OFFSET(0x25) 883 #define RMIXL_PCIE_LINK0_MSI_ENABLE _RMIXL_OFFSET(0x26) 884 #define RMIXL_PCIE_LINK1_MSI_ENABLE _RMIXL_OFFSET(0x27) 885 #define RMIXL_PCIE_LINK0_INT_STATUS0 _RMIXL_OFFSET(0x28) 886 #define RMIXL_PCIE_LINK1_INT_STATUS0 _RMIXL_OFFSET(0x29) 887 #define RMIXL_PCIE_LINK0_INT_STATUS1 _RMIXL_OFFSET(0x2a) 888 #define RMIXL_PCIE_LINK1_INT_STATUS1 _RMIXL_OFFSET(0x2b) 889 #define RMIXL_PCIE_LINK0_INT_ENABLE0 _RMIXL_OFFSET(0x2c) 890 #define RMIXL_PCIE_LINK1_INT_ENABLE0 _RMIXL_OFFSET(0x2d) 891 #define RMIXL_PCIE_LINK0_INT_ENABLE1 _RMIXL_OFFSET(0x2e) 892 #define RMIXL_PCIE_LINK1_INT_ENABLE1 _RMIXL_OFFSET(0x2f) 893 #define RMIXL_PCIE_PHY_CR_CMD _RMIXL_OFFSET(0x30) 894 #define RMIXL_PCIE_PHY_CR_WR_DATA _RMIXL_OFFSET(0x31) 895 #define RMIXL_PCIE_PHY_CR_RESP _RMIXL_OFFSET(0x32) 896 #define RMIXL_PCIE_PHY_CR_RD_DATA _RMIXL_OFFSET(0x33) 897 #define RMIXL_PCIE_IOBM_ERR_CMD _RMIXL_OFFSET(0x34) 898 #define RMIXL_PCIE_IOBM_ERR_LOWER_ADDR _RMIXL_OFFSET(0x35) 899 #define RMIXL_PCIE_IOBM_ERR_UPPER_ADDR _RMIXL_OFFSET(0x36) 900 #define RMIXL_PCIE_IOBM_ERR_BE _RMIXL_OFFSET(0x37) 901 #define RMIXL_PCIE_LINK2_STATE _RMIXL_OFFSET(0x60) /* not on XLS408Lite, XLS404Lite */ 902 #define RMIXL_PCIE_LINK3_STATE _RMIXL_OFFSET(0x61) /* not on XLS408Lite, XLS404Lite */ 903 #define RMIXL_PCIE_LINK2_MSI_STATUS _RMIXL_OFFSET(0x64) /* not on XLS408Lite, XLS404Lite */ 904 #define RMIXL_PCIE_LINK3_MSI_STATUS _RMIXL_OFFSET(0x65) /* not on XLS408Lite, XLS404Lite */ 905 #define RMIXL_PCIE_LINK2_MSI_ENABLE _RMIXL_OFFSET(0x66) /* not on XLS408Lite, XLS404Lite */ 906 #define RMIXL_PCIE_LINK3_MSI_ENABLE _RMIXL_OFFSET(0x67) /* not on XLS408Lite, XLS404Lite */ 907 #define RMIXL_PCIE_LINK2_INT_STATUS0 _RMIXL_OFFSET(0x68) /* not on XLS408Lite, XLS404Lite */ 908 #define RMIXL_PCIE_LINK3_INT_STATUS0 _RMIXL_OFFSET(0x69) /* not on XLS408Lite, XLS404Lite */ 909 #define RMIXL_PCIE_LINK2_INT_STATUS1 _RMIXL_OFFSET(0x6a) /* not on XLS408Lite, XLS404Lite */ 910 #define RMIXL_PCIE_LINK3_INT_STATUS1 _RMIXL_OFFSET(0x6b) /* not on XLS408Lite, XLS404Lite */ 911 #define RMIXL_PCIE_LINK2_INT_ENABLE0 _RMIXL_OFFSET(0x6c) /* not on XLS408Lite, XLS404Lite */ 912 #define RMIXL_PCIE_LINK3_INT_ENABLE0 _RMIXL_OFFSET(0x6d) /* not on XLS408Lite, XLS404Lite */ 913 #define RMIXL_PCIE_LINK2_INT_ENABLE1 _RMIXL_OFFSET(0x6e) /* not on XLS408Lite, XLS404Lite */ 914 #define RMIXL_PCIE_LINK3_INT_ENABLE1 _RMIXL_OFFSET(0x6f) /* not on XLS408Lite, XLS404Lite */ 915 #define RMIXL_VC0_POSTED_RX_QUEUE_CTRL _RMIXL_OFFSET(0x1d2) 916 #define RMIXL_VC0_POSTED_BUFFER_DEPTH _RMIXL_OFFSET(0x1ea) 917 #define RMIXL_PCIE_MSG_TX_THRESHOLD _RMIXL_OFFSET(0x308) 918 #define RMIXL_PCIE_MSG_BUCKET_SIZE_0 _RMIXL_OFFSET(0x320) 919 #define RMIXL_PCIE_MSG_BUCKET_SIZE_1 _RMIXL_OFFSET(0x321) 920 #define RMIXL_PCIE_MSG_BUCKET_SIZE_2 _RMIXL_OFFSET(0x322) 921 #define RMIXL_PCIE_MSG_BUCKET_SIZE_3 _RMIXL_OFFSET(0x323) 922 #define RMIXL_PCIE_MSG_BUCKET_SIZE_4 _RMIXL_OFFSET(0x324) /* not on XLS408Lite, XLS404Lite */ 923 #define RMIXL_PCIE_MSG_BUCKET_SIZE_5 _RMIXL_OFFSET(0x325) /* not on XLS408Lite, XLS404Lite */ 924 #define RMIXL_PCIE_MSG_BUCKET_SIZE_6 _RMIXL_OFFSET(0x326) /* not on XLS408Lite, XLS404Lite */ 925 #define RMIXL_PCIE_MSG_BUCKET_SIZE_7 _RMIXL_OFFSET(0x327) /* not on XLS408Lite, XLS404Lite */ 926 #define RMIXL_PCIE_MSG_CREDIT_FIRST _RMIXL_OFFSET(0x380) 927 #define RMIXL_PCIE_MSG_CREDIT_LAST _RMIXL_OFFSET(0x3ff) 928 929 /* 930 * USB General Interface registers 931 * these are opffset from REGSPACE selected by __BIT(12) == 1 932 * RMIXL_IOREG_VADDR(RMIXL_IO_DEV_USB_B + reg) 933 * see Tables 18-7 and 18-14 in the XLS PRM 934 */ 935 #define RMIXL_USB_GEN_CTRL1 0x00 936 #define RMIXL_USB_GEN_CTRL2 0x04 937 #define RMIXL_USB_GEN_CTRL3 0x08 938 #define RMIXL_USB_IOBM_TIMER 0x0C 939 #define RMIXL_USB_VBUS_TIMER 0x10 940 #define RMIXL_USB_BYTESWAP_EN 0x14 941 #define RMIXL_USB_COHERENT_MEM_BASE 0x40 942 #define RMIXL_USB_COHERENT_MEM_LIMIT 0x44 943 #define RMIXL_USB_L2ALLOC_MEM_BASE 0x48 944 #define RMIXL_USB_L2ALLOC_MEM_LIMIT 0x4C 945 #define RMIXL_USB_READEX_MEM_BASE 0x50 946 #define RMIXL_USB_READEX_MEM_LIMIT 0x54 947 #define RMIXL_USB_PHY_STATUS 0xC0 948 #define RMIXL_USB_INTERRUPT_STATUS 0xC4 949 #define RMIXL_USB_INTERRUPT_ENABLE 0xC8 950 951 /* 952 * RMIXL_USB_GEN_CTRL1 bits 953 */ 954 #define RMIXL_UG_CTRL1_RESV __BITS(31,2) 955 #define RMIXL_UG_CTRL1_HOST_RST __BIT(1) /* Resets the Host Controller 956 * 0: reset 957 * 1: normal operation 958 */ 959 #define RMIXL_UG_CTRL1_DEV_RST __BIT(0) /* Resets the Device Controller 960 * 0: reset 961 * 1: normal operation 962 */ 963 964 /* 965 * RMIXL_USB_GEN_CTRL2 bits 966 */ 967 #define RMIXL_UG_CTRL2_RESa __BITS(31,20) 968 #define RMIXL_UG_CTRL2_TX_TUNE_1 __BITS(19,18) /* Port_1 Transmitter Tuning for High-Speed Operation. 969 * 00: ~-4.5% 970 * 01: Design default 971 * 10: ~+4.5% 972 * 11: ~+9% = Recommended Operating setting 973 */ 974 #define RMIXL_UG_CTRL2_TX_TUNE_0 __BITS(17,16) /* Port_0 Transmitter Tuning for High-Speed Operation 975 * 11: Recommended Operating condition 976 */ 977 #define RMIXL_UG_CTRL2_RESb __BIT(15) 978 #define RMIXL_UG_CTRL2_WEAK_PDEN __BIT(14) /* 500kOhm Pull-Down Resistor on D+ and D- Enable */ 979 #define RMIXL_UG_CTRL2_DP_PULLUP_ESD __BIT(13) /* D+ Pull-Up Resistor Enable */ 980 #define RMIXL_UG_CTRL2_ESD_TEST_MODE __BIT(12) /* D+ Pull-Up Resistor Control Select */ 981 #define RMIXL_UG_CTRL2_TX_BIT_STUFF_EN_H_1 \ 982 __BIT(11) /* Port_1 High-Byte Transmit Bit-Stuffing Enable */ 983 #define RMIXL_UG_CTRL2_TX_BIT_STUFF_EN_H_0 \ 984 __BIT(10) /* Port_0 High-Byte Transmit Bit-Stuffing Enable */ 985 #define RMIXL_UG_CTRL2_TX_BIT_STUFF_EN_L_1 \ 986 __BIT(9) /* Port_1 Low-Byte Transmit Bit-Stuffing Enable */ 987 #define RMIXL_UG_CTRL2_TX_BIT_STUFF_EN_L_0 \ 988 __BIT(8) /* Port_0 Low-Byte Transmit Bit-Stuffing Enable */ 989 #define RMIXL_UG_CTRL2_RESc __BITS(7,6) 990 #define RMIXL_UG_CTRL2_LOOPBACK_ENB_1 __BIT(5) /* Port_1 Loopback Test Enable */ 991 #define RMIXL_UG_CTRL2_LOOPBACK_ENB_0 __BIT(4) /* Port_0 Loopback Test Enable */ 992 #define RMIXL_UG_CTRL2_DEVICE_VBUS __BIT(3) /* VBUS detected (Device mode only) */ 993 #define RMIXL_UG_CTRL2_PHY_PORT_RST_1 __BIT(2) /* Resets Port_1 of the PHY 994 * 1: normal operation 995 * 0: reset 996 */ 997 #define RMIXL_UG_CTRL2_PHY_PORT_RST_0 __BIT(1) /* Resets Port_0 of the PHY 998 * 1: normal operation 999 * 0: reset 1000 */ 1001 #define RMIXL_UG_CTRL2_PHY_RST __BIT(0) /* Resets the PHY 1002 * 1: normal operation 1003 * 0: reset 1004 */ 1005 #define RMIXL_UG_CTRL2_RESV \ 1006 (RMIXL_UG_CTRL2_RESa | RMIXL_UG_CTRL2_RESb | RMIXL_UG_CTRL2_RESc) 1007 1008 1009 /* 1010 * RMIXL_USB_GEN_CTRL3 bits 1011 */ 1012 #define RMIXL_UG_CTRL3_RESa __BITS(31,11) 1013 #define RMIXL_UG_CTRL3_PREFETCH_SIZE __BITS(10,8) /* The pre-fetch size for a memory read transfer 1014 * between USB Interface and DI station. 1015 * Valid value ranges is from 1 to 4. 1016 */ 1017 #define RMIXL_UG_CTRL3_RESb __BIT(7) 1018 #define RMIXL_UG_CTRL3_DEV_UPPERADDR __BITS(6,1) /* Device controller address space selector */ 1019 #define RMIXL_UG_CTRL3_USB_FLUSH __BIT(0) /* Flush the USB interface */ 1020 1021 /* 1022 * RMIXL_USB_PHY_STATUS bits 1023 */ 1024 #define RMIXL_UB_PHY_STATUS_RESV __BITS(31,1) 1025 #define RMIXL_UB_PHY_STATUS_VBUS __BIT(0) /* USB VBUS status */ 1026 1027 /* 1028 * RMIXL_USB_INTERRUPT_STATUS and RMIXL_USB_INTERRUPT_ENABLE bits 1029 */ 1030 #define RMIXL_UB_INTERRUPT_RESV __BITS(31,6) 1031 #define RMIXL_UB_INTERRUPT_FORCE __BIT(5) /* USB force interrupt */ 1032 #define RMIXL_UB_INTERRUPT_PHY __BIT(4) /* USB PHY interrupt */ 1033 #define RMIXL_UB_INTERRUPT_DEV __BIT(3) /* USB Device Controller interrupt */ 1034 #define RMIXL_UB_INTERRUPT_EHCI __BIT(2) /* USB EHCI interrupt */ 1035 #define RMIXL_UB_INTERRUPT_OHCI_1 __BIT(1) /* USB OHCI #1 interrupt */ 1036 #define RMIXL_UB_INTERRUPT_OHCI_0 __BIT(0) /* USB OHCI #0 interrupt */ 1037 #define RMIXL_UB_INTERRUPT_MAX 5 1038 1039 1040 /* 1041 * USB Device Controller registers 1042 * these are opffset from REGSPACE selected by __BIT(12) == 0 1043 * RMIXL_IOREG_VADDR(RMIXL_IO_DEV_USB_A + reg) 1044 * see Table 18-7 in the XLS PRM 1045 */ 1046 #define RMIXL_USB_UDC_GAHBCFG 0x008 /* UDC Configuration A (UDC_GAHBCFG) */ 1047 #define RMIXL_USB_UDC_GUSBCFG 0x00C /* UDC Configuration B (UDC_GUSBCFG) */ 1048 #define RMIXL_USB_UDC_GRSTCTL 0x010 /* UDC Reset */ 1049 #define RMIXL_USB_UDC_GINTSTS 0x014 /* UDC Interrupt Register */ 1050 #define RMIXL_USB_UDC_GINTMSK 0x018 /* UDC Interrupt Mask Register */ 1051 #define RMIXL_USB_UDC_GRXSTSP 0x020 /* UDC Receive Status Read /Pop Register (Read Only) */ 1052 #define RMIXL_USB_UDC_GRXFSIZ 0x024 /* UDC Receive FIFO Size Register */ 1053 #define RMIXL_USB_UDC_GNPTXFSIZ 0x028 /* UDC Non-periodic Transmit FIFO Size Register */ 1054 #define RMIXL_USB_UDC_GUID 0x03C /* UDC User ID Register (UDC_GUID) */ 1055 #define RMIXL_USB_UDC_GSNPSID 0x040 /* UDC ID Register (Read Only) */ 1056 #define RMIXL_USB_UDC_GHWCFG1 0x044 /* UDC User HW Config1 Register (Read Only) */ 1057 #define RMIXL_USB_UDC_GHWCFG2 0x048 /* UDC User HW Config2 Register (Read Only) */ 1058 #define RMIXL_USB_UDC_GHWCFG3 0x04C /* UDC User HW Config3 Register (Read Only) */ 1059 #define RMIXL_USB_UDC_GHWCFG4 0x050 /* UDC User HW Config4 Register (Read Only) */ 1060 #define RMIXL_USB_UDC_DPTXFSIZ0 0x104 1061 #define RMIXL_USB_UDC_DPTXFSIZ1 0x108 1062 #define RMIXL_USB_UDC_DPTXFSIZ2 0x10c 1063 #define RMIXL_USB_UDC_DPTXFSIZn(n) (0x104 + (4 * (n))) 1064 /* UDC Device IN Endpoint Transmit FIFO-n 1065 Size Registers (UDC_DPTXFSIZn) */ 1066 #define RMIXL_USB_UDC_DCFG 0x800 /* UDC Configuration C */ 1067 #define RMIXL_USB_UDC_DCTL 0x804 /* UDC Control Register */ 1068 #define RMIXL_USB_UDC_DSTS 0x808 /* UDC Status Register (Read Only) */ 1069 #define RMIXL_USB_UDC_DIEPMSK 0x810 /* UDC Device IN Endpoint Common 1070 Interrupt Mask Register (UDC_DIEPMSK) */ 1071 #define RMIXL_USB_UDC_DOEPMSK 0x814 /* UDC Device OUT Endpoint Common Interrupt Mask register */ 1072 #define RMIXL_USB_UDC_DAINT 0x818 /* UDC Device All Endpoints Interrupt Register */ 1073 #define RMIXL_USB_UDC_DAINTMSK 0x81C /* UDC Device All Endpoints Interrupt Mask Register */ 1074 #define RMIXL_USB_UDC_DTKNQR3 0x830 /* Device Threshold Control Register */ 1075 #define RMIXL_USB_UDC_DTKNQR4 0x834 /* Device IN Endpoint FIFO Empty Interrupt Mask Register */ 1076 #define RMIXL_USB_UDC_DIEPCTL 0x900 /* Device Control IN Endpoint 0 Control Register */ 1077 #define RMIXL_USB_UDC_DIEPINT 0x908 /* Device IN Endpoint 0 Interrupt Register */ 1078 #define RMIXL_USB_UDC_DIEPTSIZ 0x910 /* Device IN Endpoint 0 Transfer Size Register */ 1079 #define RMIXL_USB_UDC_DIEPDMA 0x914 /* Device IN Endpoint 0 DMA Address Register */ 1080 #define RMIXL_USB_UDC_DTXFSTS 0x918 /* Device IN Endpoint Transmit FIFO Status Register */ 1081 #define RMIXL_USB_DEV_IN_ENDPT(d,n) (0x920 + ((d) * 0x20) + ((n) * 4)) 1082 /* Device IN Endpoint #d Register #n */ 1083 1084 /* 1085 * USB Host Controller register base addrs 1086 * these are offset from REGSPACE selected by __BIT(12) == 0 1087 * RMIXL_IOREG_VADDR(RMIXL_IO_DEV_USB_A + reg) 1088 * see Table 18-14 in the XLS PRM 1089 * specific Host Controller is selected by __BITS(11,10) 1090 */ 1091 #define RMIXL_USB_HOST_EHCI_BASE 0x000 1092 #define RMIXL_USB_HOST_0HCI0_BASE 0x400 1093 #define RMIXL_USB_HOST_0HCI1_BASE 0x800 1094 #define RMIXL_USB_HOST_RESV 0xc00 1095 #define RMIXL_USB_HOST_MASK 0xc00 1096 1097 1098 /* 1099 * FMN non-core station configuration registers 1100 */ 1101 #define RMIXL_FMN_BS_FIRST _RMIXL_OFFSET(0x320) 1102 1103 /* 1104 * SGMII bucket size regs 1105 */ 1106 #define RMIXL_FMN_BS_SGMII_UNUSED0 _RMIXL_OFFSET(0x320) /* initialize as 0 */ 1107 #define RMIXL_FMN_BS_SGMII_FCB _RMIXL_OFFSET(0x321) /* Free Credit Bucket size */ 1108 #define RMIXL_FMN_BS_SGMII_TX0 _RMIXL_OFFSET(0x322) 1109 #define RMIXL_FMN_BS_SGMII_TX1 _RMIXL_OFFSET(0x323) 1110 #define RMIXL_FMN_BS_SGMII_TX2 _RMIXL_OFFSET(0x324) 1111 #define RMIXL_FMN_BS_SGMII_TX3 _RMIXL_OFFSET(0x325) 1112 #define RMIXL_FMN_BS_SGMII_UNUSED1 _RMIXL_OFFSET(0x326) /* initialize as 0 */ 1113 #define RMIXL_FMN_BS_SGMII_FCB1 _RMIXL_OFFSET(0x327) /* Free Credit Bucket1 size */ 1114 1115 /* 1116 * SAE bucket size regs 1117 */ 1118 #define RMIXL_FMN_BS_SAE_PIPE0 _RMIXL_OFFSET(0x320) 1119 #define RMIXL_FMN_BS_SAE_RSA_PIPE _RMIXL_OFFSET(0x321) 1120 1121 /* 1122 * DMA bucket size regs 1123 */ 1124 #define RMIXL_FMN_BS_DMA_CHAN0 _RMIXL_OFFSET(0x320) 1125 #define RMIXL_FMN_BS_DMA_CHAN1 _RMIXL_OFFSET(0x321) 1126 #define RMIXL_FMN_BS_DMA_CHAN2 _RMIXL_OFFSET(0x322) 1127 #define RMIXL_FMN_BS_DMA_CHAN3 _RMIXL_OFFSET(0x323) 1128 1129 /* 1130 * CDE bucket size regs 1131 */ 1132 #define RMIXL_FMN_BS_CDE_FREE_DESC _RMIXL_OFFSET(0x320) 1133 #define RMIXL_FMN_BS_CDE_COMPDECOMP _RMIXL_OFFSET(0x321) 1134 1135 /* 1136 * PCIe bucket size regs 1137 */ 1138 #define RMIXL_FMN_BS_PCIE_TX0 _RMIXL_OFFSET(0x320) 1139 #define RMIXL_FMN_BS_PCIE_RX0 _RMIXL_OFFSET(0x321) 1140 #define RMIXL_FMN_BS_PCIE_TX1 _RMIXL_OFFSET(0x322) 1141 #define RMIXL_FMN_BS_PCIE_RX1 _RMIXL_OFFSET(0x323) 1142 #define RMIXL_FMN_BS_PCIE_TX2 _RMIXL_OFFSET(0x324) 1143 #define RMIXL_FMN_BS_PCIE_RX2 _RMIXL_OFFSET(0x325) 1144 #define RMIXL_FMN_BS_PCIE_TX3 _RMIXL_OFFSET(0x326) 1145 #define RMIXL_FMN_BS_PCIE_RX3 _RMIXL_OFFSET(0x327) 1146 1147 /* 1148 * non-core Credit Counter offsets 1149 */ 1150 #define RMIXL_FMN_CC_FIRST _RMIXL_OFFSET(0x380) 1151 #define RMIXL_FMN_CC_LAST _RMIXL_OFFSET(0x3ff) 1152 1153 /* 1154 * non-core Credit Counter bit defines 1155 */ 1156 #define RMIXL_FMN_CC_RESV __BITS(31,8) 1157 #define RMIXL_FMN_CC_COUNT __BITS(7,0) 1158 1159 #endif /* _MIPS_RMI_RMIRMIXLEGS_H_ */ 1160 1161
Indexes created Tue Sep 30 20:09:53 GMT 2025