rmixlvar.h revision 1.1.2.17
1 /* $NetBSD: rmixlvar.h,v 1.1.2.17 2010/04/07 19:24:13 cliff Exp $ */ 2 3 /* 4 * Copyright 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _MIPS_RMI_RMIXLVAR_H_ 39 #define _MIPS_RMI_RMIXLVAR_H_ 40 41 #include <mips/cpu.h> 42 #include <mips/locore.h> 43 #include <mips/rmi/rmixl_firmware.h> 44 45 #include <machine/bus.h> 46 47 #include <dev/pci/pcivar.h> 48 49 static inline bool 50 cpu_rmixl(const struct pridtab *ct) 51 { 52 if (ct->cpu_cid == MIPS_PRID_CID_RMI) 53 return true; 54 return false; 55 } 56 57 static inline bool 58 cpu_rmixlr(const struct pridtab *ct) 59 { 60 u_int type = ct->cpu_cidflags & MIPS_CIDFL_RMI_TYPE; 61 if (cpu_rmixl(ct) && type == CIDFL_RMI_TYPE_XLR) 62 return true; 63 return false; 64 } 65 66 static inline bool 67 cpu_rmixls(const struct pridtab *ct) 68 { 69 u_int type = ct->cpu_cidflags & MIPS_CIDFL_RMI_TYPE; 70 if (cpu_rmixl(ct) && type == CIDFL_RMI_TYPE_XLS) 71 return true; 72 return false; 73 } 74 75 static inline bool 76 cpu_rmixlp(const struct pridtab *ct) 77 { 78 u_int type = ct->cpu_cidflags & MIPS_CIDFL_RMI_TYPE; 79 if (cpu_rmixl(ct) && type == CIDFL_RMI_TYPE_XLP) 80 return true; 81 return false; 82 } 83 84 static inline int 85 cpu_rmixl_chip_type(const struct pridtab *ct) 86 { 87 return ct->cpu_cidflags & MIPS_CIDFL_RMI_TYPE; 88 } 89 90 typedef enum { 91 PSB_TYPE_UNKNOWN=0, 92 PSB_TYPE_RMI, 93 PSB_TYPE_DELL, 94 } rmixlfw_psb_type_t; 95 96 static inline const char * 97 rmixlfw_psb_type_name(rmixlfw_psb_type_t type) 98 { 99 switch(type) { 100 case PSB_TYPE_UNKNOWN: 101 return "unknown"; 102 case PSB_TYPE_RMI: 103 return "RMI"; 104 case PSB_TYPE_DELL: 105 return "DELL"; 106 default: 107 return "undefined"; 108 } 109 } 110 111 struct rmixl_config { 112 uint64_t rc_io_pbase; 113 bus_addr_t rc_pci_cfg_pbase; 114 bus_size_t rc_pci_cfg_size; 115 bus_addr_t rc_pci_ecfg_pbase; 116 bus_size_t rc_pci_ecfg_size; 117 bus_addr_t rc_pci_mem_pbase; 118 bus_size_t rc_pci_mem_size; 119 bus_addr_t rc_pci_io_pbase; 120 bus_size_t rc_pci_io_size; 121 struct mips_bus_space rc_obio_eb_memt; /* DEVIO -eb */ 122 struct mips_bus_space rc_obio_el_memt; /* DEVIO -el */ 123 struct mips_bus_space rc_pci_cfg_memt; /* PCI CFG */ 124 struct mips_bus_space rc_pci_ecfg_memt; /* PCI ECFG */ 125 struct mips_bus_space rc_pci_memt; /* PCI MEM */ 126 struct mips_bus_space rc_pci_iot; /* PCI IO */ 127 struct mips_bus_dma_tag rc_64bit_dmat; 128 bus_dma_tag_t rc_32bit_dmat; 129 bus_dma_tag_t rc_29bit_dmat; 130 struct extent *rc_phys_ex; /* Note: MB units */ 131 struct extent *rc_obio_eb_ex; 132 struct extent *rc_obio_el_ex; 133 struct extent *rc_pci_cfg_ex; 134 struct extent *rc_pci_ecfg_ex; 135 struct extent *rc_pci_mem_ex; 136 struct extent *rc_pci_io_ex; 137 int rc_mallocsafe; 138 rmixlfw_info_t rc_psb_info; 139 rmixlfw_psb_type_t rc_psb_type; 140 volatile struct rmixlfw_cpu_wakeup_info 141 *rc_cpu_wakeup_info; 142 const void *rc_cpu_wakeup_end; 143 }; 144 145 extern struct rmixl_config rmixl_configuration; 146 147 extern void rmixl_obio_eb_bus_mem_init(bus_space_tag_t, void *); 148 extern void rmixl_obio_el_bus_mem_init(bus_space_tag_t, void *); 149 extern void rmixl_pci_cfg_bus_mem_init(bus_space_tag_t, void *); 150 extern void rmixl_pci_ecfg_bus_mem_init(bus_space_tag_t, void *); 151 extern void rmixl_pci_bus_mem_init(bus_space_tag_t, void *); 152 extern void rmixl_pci_bus_io_init(bus_space_tag_t, void *); 153 154 extern void rmixl_addr_error_init(void); 155 extern int rmixl_addr_error_check(void); 156 157 extern uint64_t rmixl_mfcr(u_int); 158 extern void rmixl_mtcr(uint64_t, u_int); 159 160 161 /* 162 * rmixl_cache_err_dis: 163 * - disable Cache, Data ECC, Snoop Tag Parity, Tag Parity errors 164 * - clear the cache error log 165 * - return previous value from RMIXL_PCR_L1D_CONFIG0 166 */ 167 static inline uint64_t 168 rmixl_cache_err_dis(void) 169 { 170 uint64_t r; 171 172 r = rmixl_mfcr(RMIXL_PCR_L1D_CONFIG0); 173 rmixl_mtcr(RMIXL_PCR_L1D_CONFIG0, r & ~0x2e); 174 rmixl_mtcr(RMIXL_PCR_L1D_CACHE_ERROR_LOG, 0); 175 return r; 176 } 177 178 /* 179 * rmixl_cache_err_restore: 180 * - clear the cache error log, cache error overflow log, 181 * and cache interrupt registers 182 * - restore previous value to RMIXL_PCR_L1D_CONFIG0 183 */ 184 static inline void 185 rmixl_cache_err_restore(uint64_t r) 186 { 187 rmixl_mtcr(RMIXL_PCR_L1D_CACHE_ERROR_LOG, 0); 188 rmixl_mtcr(RMIXL_PCR_L1D_CACHE_ERROR_OVF_LO, 0); 189 rmixl_mtcr(RMIXL_PCR_L1D_CACHE_INTERRUPT, 0); 190 rmixl_mtcr(RMIXL_PCR_L1D_CONFIG0, r); 191 } 192 193 static inline uint64_t 194 rmixl_cache_err_check(void) 195 { 196 return rmixl_mfcr(RMIXL_PCR_L1D_CACHE_ERROR_LOG); 197 } 198 199 static inline int 200 rmixl_probe_4(volatile uint32_t *va) 201 { 202 uint32_t tmp; 203 uint32_t r; 204 int err; 205 int s; 206 207 s = splhigh(); 208 r = rmixl_cache_err_dis(); 209 tmp = *va; /* probe */ 210 err = rmixl_cache_err_check(); 211 rmixl_cache_err_restore(r); 212 splx(s); 213 214 return (err == 0); 215 } 216 217 #endif /* _MIPS_RMI_RMIXLVAR_H_ */ 218
Indexes created Tue Oct 28 09:09:52 GMT 2025