rmixlvar.h revision 1.1.2.23
1 /* $NetBSD: rmixlvar.h,v 1.1.2.23 2011/12/28 05:36:11 matt Exp $ */ 2 3 /* 4 * Copyright 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _MIPS_RMI_RMIXLVAR_H_ 39 #define _MIPS_RMI_RMIXLVAR_H_ 40 41 #include <sys/bus.h> 42 #include <sys/extent.h> 43 44 #include <dev/pci/pcivar.h> 45 46 #include <mips/cpu.h> 47 #include <mips/locore.h> 48 49 #include <mips/rmi/rmixl_firmware.h> 50 #include <mips/rmi/rmixlreg.h> 51 52 void rmixl_pcr_init_core(bool); 53 54 static inline int 55 cpu_rmixl_chip_type(const struct pridtab *ct) 56 { 57 return ct->cpu_cidflags & MIPS_CIDFL_RMI_TYPE; 58 } 59 60 static inline bool 61 cpu_rmixl(const struct pridtab *ct) 62 { 63 return ct->cpu_cid == MIPS_PRID_CID_RMI; 64 } 65 66 static inline bool 67 cpu_rmixlr(const struct pridtab *ct) 68 { 69 return cpu_rmixl(ct) && cpu_rmixl_chip_type(ct) == CIDFL_RMI_TYPE_XLR; 70 } 71 72 static inline bool 73 cpu_rmixls(const struct pridtab *ct) 74 { 75 return cpu_rmixl(ct) && cpu_rmixl_chip_type(ct) == CIDFL_RMI_TYPE_XLS; 76 } 77 78 static inline bool 79 cpu_rmixlp(const struct pridtab *ct) 80 { 81 return cpu_rmixl(ct) && cpu_rmixl_chip_type(ct) == CIDFL_RMI_TYPE_XLP; 82 } 83 84 typedef enum { 85 PSB_TYPE_UNKNOWN=0, 86 PSB_TYPE_RMI, 87 PSB_TYPE_DELL, 88 } rmixlfw_psb_type_t; 89 90 static inline const char * 91 rmixlfw_psb_type_name(rmixlfw_psb_type_t type) 92 { 93 switch(type) { 94 case PSB_TYPE_UNKNOWN: 95 return "unknown"; 96 case PSB_TYPE_RMI: 97 return "RMI"; 98 case PSB_TYPE_DELL: 99 return "DELL"; 100 default: 101 return "undefined"; 102 } 103 } 104 105 typedef enum { 106 RMIXLP_8XX, 107 RMIXLP_4XX, 108 /* These next 4 need to be in this order */ 109 RMIXLP_3XX, 110 RMIXLP_3XXL, 111 RMIXLP_3XXH, 112 RMIXLP_3XXQ, 113 RMIXLP_ANY, /* must be last */ 114 } rmixlp_variant_t; 115 116 struct rmixl_region { 117 bus_addr_t r_pbase; 118 bus_size_t r_size; 119 }; 120 121 struct rmixl_config { 122 struct rmixl_region rc_io; 123 struct rmixl_region rc_flash[RMIXLP_SBC_NFLASH]; /* FLASH_BAR */ 124 struct rmixl_region rc_pci_cfg; 125 struct rmixl_region rc_pci_ecfg; 126 struct rmixl_region rc_pci_mem; 127 struct rmixl_region rc_pci_io; 128 struct rmixl_region rc_pci_link_mem[RMIXLP_SBC_NPCIE_MEM]; 129 struct rmixl_region rc_pci_link_io[RMIXLP_SBC_NPCIE_IO]; 130 struct rmixl_region rc_srio_mem; 131 struct rmixl_region rc_norflash[RMIXLP_NOR_NCS]; /* XLP */ 132 struct mips_bus_space rc_obio_eb_memt; /* DEVIO -eb */ 133 struct mips_bus_space rc_obio_el_memt; /* DEVIO -el */ 134 struct mips_bus_space rc_iobus_memt; /* Peripherals IO Bus */ 135 struct mips_bus_space rc_pci_cfg_memt; /* PCI CFG */ 136 struct mips_bus_space rc_pci_ecfg_eb_memt; /* PCI ECFG */ 137 struct mips_bus_space rc_pci_ecfg_el_memt; /* PCI ECFG */ 138 struct mips_bus_space rc_pci_memt; /* PCI MEM */ 139 struct mips_bus_space rc_pci_iot; /* PCI IO */ 140 struct mips_bus_space rc_srio_memt; /* SRIO MEM */ 141 struct mips_bus_dma_tag rc_dma_tag; 142 struct mips_pci_chipset rc_pci_chipset; /* pci_chipset_t */ 143 bus_space_handle_t rc_pci_cfg_memh; 144 bus_space_handle_t rc_pci_ecfg_eb_memh; 145 bus_space_handle_t rc_pci_ecfg_el_memh; 146 bus_dma_tag_t rc_dmat64; 147 bus_dma_tag_t rc_dmat32; 148 bus_dma_tag_t rc_dmat29; 149 struct extent * rc_phys_ex; /* Note: MB units */ 150 struct extent * rc_obio_eb_ex; 151 struct extent * rc_obio_el_ex; 152 struct extent * rc_iobus_ex; 153 struct extent * rc_pci_mem_ex; 154 struct extent * rc_pci_io_ex; 155 struct extent * rc_srio_mem_ex; 156 int rc_mallocsafe; 157 rmixlfw_info_t rc_psb_info; 158 rmixlfw_psb_type_t rc_psb_type; 159 volatile struct rmixlfw_cpu_wakeup_info * 160 rc_cpu_wakeup_info; 161 const void * rc_cpu_wakeup_end; 162 }; 163 164 extern struct rmixl_config rmixl_configuration; 165 extern const char *rmixl_cpuname; 166 167 extern void rmixl_flash_eb_bus_mem_init(bus_space_tag_t, void *); 168 extern void rmixl_flash_el_bus_mem_init(bus_space_tag_t, void *); 169 extern void rmixl_iobus_bus_mem_init(bus_space_tag_t, void *); 170 extern void rmixl_obio_eb_bus_mem_init(bus_space_tag_t, void *); 171 extern void rmixl_obio_el_bus_mem_init(bus_space_tag_t, void *); 172 extern void rmixl_pci_cfg_el_bus_mem_init(bus_space_tag_t, void *); 173 extern void rmixl_pci_cfg_eb_bus_mem_init(bus_space_tag_t, void *); 174 extern void rmixl_pci_ecfg_el_bus_mem_init(bus_space_tag_t, void *); 175 extern void rmixl_pci_ecfg_eb_bus_mem_init(bus_space_tag_t, void *); 176 extern void rmixl_pci_bus_mem_init(bus_space_tag_t, void *); 177 extern void rmixl_pci_bus_io_init(bus_space_tag_t, void *); 178 179 void rmixlp_pcie_pc_init(void); 180 181 extern void rmixl_addr_error_init(void); 182 extern int rmixl_addr_error_check(void); 183 extern rmixlp_variant_t rmixl_xlp_variant; 184 185 extern uint64_t rmixl_mfcr(u_int); 186 extern void rmixl_mtcr(uint64_t, u_int); 187 188 extern void rmixl_eirr_ack(uint64_t, uint64_t, uint64_t); 189 190 191 /* 192 * rmixl_cache_err_dis: 193 * - disable Cache, Data ECC, Snoop Tag Parity, Tag Parity errors 194 * - clear the cache error log 195 * - return previous value from RMIXL_PCR_L1D_CONFIG0 196 */ 197 static inline uint64_t 198 rmixl_cache_err_dis(void) 199 { 200 uint64_t r; 201 202 r = rmixl_mfcr(RMIXL_PCR_L1D_CONFIG0); 203 rmixl_mtcr(RMIXL_PCR_L1D_CONFIG0, r & ~0x2e); 204 rmixl_mtcr(RMIXL_PCR_L1D_CACHE_ERROR_LOG, 0); 205 return r; 206 } 207 208 /* 209 * rmixl_cache_err_restore: 210 * - clear the cache error log, cache error overflow log, 211 * and cache interrupt registers 212 * - restore previous value to RMIXL_PCR_L1D_CONFIG0 213 */ 214 static inline void 215 rmixl_cache_err_restore(uint64_t r) 216 { 217 rmixl_mtcr(RMIXL_PCR_L1D_CACHE_ERROR_LOG, 0); 218 rmixl_mtcr(RMIXL_PCR_L1D_CACHE_ERROR_OVF_LO, 0); 219 rmixl_mtcr(RMIXL_PCR_L1D_CACHE_INTERRUPT, 0); 220 rmixl_mtcr(RMIXL_PCR_L1D_CONFIG0, r); 221 } 222 223 static inline uint64_t 224 rmixl_cache_err_check(void) 225 { 226 return rmixl_mfcr(RMIXL_PCR_L1D_CACHE_ERROR_LOG); 227 } 228 229 static inline int 230 rmixl_probe_4(volatile uint32_t *va) 231 { 232 uint32_t tmp; 233 uint32_t r; 234 int err; 235 int s; 236 237 s = splhigh(); 238 r = rmixl_cache_err_dis(); 239 tmp = *va; /* probe */ 240 err = rmixl_cache_err_check(); 241 rmixl_cache_err_restore(r); 242 splx(s); 243 244 return (err == 0); 245 } 246 247 static inline uint32_t 248 rmixlp_read_4(uint32_t tag, bus_size_t offset) 249 { 250 #if 0 251 const struct rmixl_config * const rcp = &rmixl_configuration; 252 253 return bus_space_read_4(rcp->rc_pci_ecfg_memt, rcp->rc_pci_ecfg_memh, 254 offset); 255 #else 256 const paddr_t ecfg_addr = rmixl_configuration.rc_pci_ecfg.r_pbase 257 + tag + offset; 258 259 return be32toh(*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(ecfg_addr)); 260 #endif 261 } 262 263 static inline uint64_t 264 rmixlp_read_8(uint32_t tag, bus_size_t offset) 265 { 266 #if 0 267 const struct rmixl_config * const rcp = &rmixl_configuration; 268 269 return bus_space_read_8(rcp->rc_pci_ecfg_memt, rcp->rc_pci_ecfg_memh, 270 offset); 271 #else 272 const paddr_t ecfg_addr = rmixl_configuration.rc_pci_ecfg.r_pbase 273 + tag + offset; 274 275 return be64toh(*(volatile uint64_t *)MIPS_PHYS_TO_KSEG1(ecfg_addr)); 276 #endif 277 } 278 279 static inline void 280 rmixlp_write_4(uint32_t tag, bus_size_t offset, uint32_t v) 281 { 282 const paddr_t ecfg_addr = rmixl_configuration.rc_pci_ecfg.r_pbase 283 + tag + offset; 284 285 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(ecfg_addr) = htobe32(v); 286 __asm __volatile("sync"); 287 } 288 289 static inline void 290 rmixlp_write_8(uint32_t tag, bus_size_t offset, uint64_t v) 291 { 292 const paddr_t ecfg_addr = rmixl_configuration.rc_pci_ecfg.r_pbase 293 + tag + offset; 294 295 *(volatile uint64_t *)MIPS_PHYS_TO_KSEG1(ecfg_addr) = htobe64(v); 296 __asm __volatile("sync"); 297 } 298 299 static inline void 300 rmixl_physaddr_add(struct extent *ext, const char *name, 301 struct rmixl_region *rp, bus_addr_t xpbase, bus_size_t xsize) 302 { 303 rp->r_pbase = xpbase; 304 rp->r_size = xsize; 305 u_long base = xpbase >> 20; 306 u_long size = xsize >> 20; 307 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) { 308 panic("%s: %s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 309 "failed", __func__, name, ext, base, size, EX_NOWAIT); 310 } 311 } 312 313 #endif /* _MIPS_RMI_RMIXLVAR_H_ */ 314
Indexes created Sat Oct 25 16:10:12 GMT 2025