rmixlvar.h revision 1.1.2.24
1 /* $NetBSD: rmixlvar.h,v 1.1.2.24 2011/12/30 06:45:00 matt Exp $ */ 2 3 /* 4 * Copyright 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _MIPS_RMI_RMIXLVAR_H_ 39 #define _MIPS_RMI_RMIXLVAR_H_ 40 41 #include <sys/bus.h> 42 #include <sys/extent.h> 43 44 #include <dev/pci/pcivar.h> 45 46 #include <mips/cpu.h> 47 #include <mips/locore.h> 48 49 #include <mips/rmi/rmixl_firmware.h> 50 #include <mips/rmi/rmixlreg.h> 51 52 void rmixl_pcr_init_core(bool); 53 54 static inline int 55 cpu_rmixl_chip_type(const struct pridtab *ct) 56 { 57 return ct->cpu_cidflags & MIPS_CIDFL_RMI_TYPE; 58 } 59 60 static inline bool 61 cpu_rmixl(const struct pridtab *ct) 62 { 63 return ct->cpu_cid == MIPS_PRID_CID_RMI; 64 } 65 66 static inline bool 67 cpu_rmixlr(const struct pridtab *ct) 68 { 69 return cpu_rmixl(ct) && cpu_rmixl_chip_type(ct) == CIDFL_RMI_TYPE_XLR; 70 } 71 72 static inline bool 73 cpu_rmixls(const struct pridtab *ct) 74 { 75 return cpu_rmixl(ct) && cpu_rmixl_chip_type(ct) == CIDFL_RMI_TYPE_XLS; 76 } 77 78 static inline bool 79 cpu_rmixlp(const struct pridtab *ct) 80 { 81 return cpu_rmixl(ct) && cpu_rmixl_chip_type(ct) == CIDFL_RMI_TYPE_XLP; 82 } 83 84 typedef enum { 85 PSB_TYPE_UNKNOWN=0, 86 PSB_TYPE_RMI, 87 PSB_TYPE_DELL, 88 } rmixlfw_psb_type_t; 89 90 static inline const char * 91 rmixlfw_psb_type_name(rmixlfw_psb_type_t type) 92 { 93 switch(type) { 94 case PSB_TYPE_UNKNOWN: 95 return "unknown"; 96 case PSB_TYPE_RMI: 97 return "RMI"; 98 case PSB_TYPE_DELL: 99 return "DELL"; 100 default: 101 return "undefined"; 102 } 103 } 104 105 typedef enum { 106 RMIXLP_8XX, 107 RMIXLP_4XX, 108 /* These next 4 need to be in this order */ 109 RMIXLP_3XX, 110 RMIXLP_3XXL, 111 RMIXLP_3XXH, 112 RMIXLP_3XXQ, 113 RMIXLP_ANY, /* must be last */ 114 } rmixlp_variant_t; 115 116 struct rmixl_region { 117 bus_addr_t r_pbase; 118 bus_size_t r_size; 119 }; 120 121 struct rmixl_config { 122 struct rmixl_region rc_io; 123 struct rmixl_region rc_flash[RMIXLP_SBC_NFLASH]; /* FLASH_BAR */ 124 struct rmixl_region rc_pci_cfg; 125 struct rmixl_region rc_pci_ecfg; 126 struct rmixl_region rc_pci_mem; 127 struct rmixl_region rc_pci_io; 128 struct rmixl_region rc_pci_link_mem[RMIXLP_SBC_NPCIE_MEM]; 129 struct rmixl_region rc_pci_link_io[RMIXLP_SBC_NPCIE_IO]; 130 struct rmixl_region rc_srio_mem; 131 struct rmixl_region rc_norflash[RMIXLP_NOR_NCS]; /* XLP */ 132 struct mips_bus_space rc_obio_eb_memt; /* DEVIO -eb */ 133 struct mips_bus_space rc_obio_el_memt; /* DEVIO -el */ 134 struct mips_bus_space rc_iobus_memt; /* Peripherals IO Bus */ 135 struct mips_bus_space rc_pci_cfg_memt; /* PCI CFG */ 136 struct mips_bus_space rc_pci_ecfg_eb_memt; /* PCI ECFG */ 137 struct mips_bus_space rc_pci_ecfg_el_memt; /* PCI ECFG */ 138 struct mips_bus_space rc_pci_memt; /* PCI MEM */ 139 struct mips_bus_space rc_pci_iot; /* PCI IO */ 140 struct mips_bus_space rc_srio_memt; /* SRIO MEM */ 141 struct mips_bus_dma_tag rc_dma_tag; 142 struct mips_pci_chipset rc_pci_chipset; /* pci_chipset_t */ 143 bus_space_handle_t rc_pci_cfg_memh; 144 bus_space_handle_t rc_pci_ecfg_eb_memh; 145 bus_space_handle_t rc_pci_ecfg_el_memh; 146 bus_dma_tag_t rc_dmat64; 147 bus_dma_tag_t rc_dmat32; 148 bus_dma_tag_t rc_dmat29; 149 struct extent * rc_phys_ex; /* Note: MB units */ 150 struct extent * rc_obio_eb_ex; 151 struct extent * rc_obio_el_ex; 152 struct extent * rc_iobus_ex; 153 struct extent * rc_pci_mem_ex; 154 struct extent * rc_pci_io_ex; 155 struct extent * rc_srio_mem_ex; 156 int rc_mallocsafe; 157 uint64_t rc_gpio_available; 158 rmixlfw_info_t rc_psb_info; 159 rmixlfw_psb_type_t rc_psb_type; 160 volatile struct rmixlfw_cpu_wakeup_info * 161 rc_cpu_wakeup_info; 162 const void * rc_cpu_wakeup_end; 163 }; 164 165 extern struct rmixl_config rmixl_configuration; 166 extern const char *rmixl_cpuname; 167 168 extern void rmixl_flash_eb_bus_mem_init(bus_space_tag_t, void *); 169 extern void rmixl_flash_el_bus_mem_init(bus_space_tag_t, void *); 170 extern void rmixl_iobus_bus_mem_init(bus_space_tag_t, void *); 171 extern void rmixl_obio_eb_bus_mem_init(bus_space_tag_t, void *); 172 extern void rmixl_obio_el_bus_mem_init(bus_space_tag_t, void *); 173 extern void rmixl_pci_cfg_el_bus_mem_init(bus_space_tag_t, void *); 174 extern void rmixl_pci_cfg_eb_bus_mem_init(bus_space_tag_t, void *); 175 extern void rmixl_pci_ecfg_el_bus_mem_init(bus_space_tag_t, void *); 176 extern void rmixl_pci_ecfg_eb_bus_mem_init(bus_space_tag_t, void *); 177 extern void rmixl_pci_bus_mem_init(bus_space_tag_t, void *); 178 extern void rmixl_pci_bus_io_init(bus_space_tag_t, void *); 179 180 void rmixlp_pcie_pc_init(void); 181 182 extern void rmixl_addr_error_init(void); 183 extern int rmixl_addr_error_check(void); 184 extern rmixlp_variant_t rmixl_xlp_variant; 185 186 extern uint64_t rmixl_mfcr(u_int); 187 extern void rmixl_mtcr(uint64_t, u_int); 188 189 extern void rmixl_eirr_ack(uint64_t, uint64_t, uint64_t); 190 191 192 /* 193 * rmixl_cache_err_dis: 194 * - disable Cache, Data ECC, Snoop Tag Parity, Tag Parity errors 195 * - clear the cache error log 196 * - return previous value from RMIXL_PCR_L1D_CONFIG0 197 */ 198 static inline uint64_t 199 rmixl_cache_err_dis(void) 200 { 201 uint64_t r; 202 203 r = rmixl_mfcr(RMIXL_PCR_L1D_CONFIG0); 204 rmixl_mtcr(RMIXL_PCR_L1D_CONFIG0, r & ~0x2e); 205 rmixl_mtcr(RMIXL_PCR_L1D_CACHE_ERROR_LOG, 0); 206 return r; 207 } 208 209 /* 210 * rmixl_cache_err_restore: 211 * - clear the cache error log, cache error overflow log, 212 * and cache interrupt registers 213 * - restore previous value to RMIXL_PCR_L1D_CONFIG0 214 */ 215 static inline void 216 rmixl_cache_err_restore(uint64_t r) 217 { 218 rmixl_mtcr(RMIXL_PCR_L1D_CACHE_ERROR_LOG, 0); 219 rmixl_mtcr(RMIXL_PCR_L1D_CACHE_ERROR_OVF_LO, 0); 220 rmixl_mtcr(RMIXL_PCR_L1D_CACHE_INTERRUPT, 0); 221 rmixl_mtcr(RMIXL_PCR_L1D_CONFIG0, r); 222 } 223 224 static inline uint64_t 225 rmixl_cache_err_check(void) 226 { 227 return rmixl_mfcr(RMIXL_PCR_L1D_CACHE_ERROR_LOG); 228 } 229 230 static inline int 231 rmixl_probe_4(volatile uint32_t *va) 232 { 233 uint32_t tmp; 234 uint32_t r; 235 int err; 236 int s; 237 238 s = splhigh(); 239 r = rmixl_cache_err_dis(); 240 tmp = *va; /* probe */ 241 err = rmixl_cache_err_check(); 242 rmixl_cache_err_restore(r); 243 splx(s); 244 245 return (err == 0); 246 } 247 248 static inline uint32_t 249 rmixlp_read_4(uint32_t tag, bus_size_t offset) 250 { 251 #if 0 252 const struct rmixl_config * const rcp = &rmixl_configuration; 253 254 return bus_space_read_4(rcp->rc_pci_ecfg_memt, rcp->rc_pci_ecfg_memh, 255 offset); 256 #else 257 const paddr_t ecfg_addr = rmixl_configuration.rc_pci_ecfg.r_pbase 258 + tag + offset; 259 260 return be32toh(*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(ecfg_addr)); 261 #endif 262 } 263 264 static inline uint64_t 265 rmixlp_read_8(uint32_t tag, bus_size_t offset) 266 { 267 #if 0 268 const struct rmixl_config * const rcp = &rmixl_configuration; 269 270 return bus_space_read_8(rcp->rc_pci_ecfg_memt, rcp->rc_pci_ecfg_memh, 271 offset); 272 #else 273 const paddr_t ecfg_addr = rmixl_configuration.rc_pci_ecfg.r_pbase 274 + tag + offset; 275 276 return be64toh(*(volatile uint64_t *)MIPS_PHYS_TO_KSEG1(ecfg_addr)); 277 #endif 278 } 279 280 static inline void 281 rmixlp_write_4(uint32_t tag, bus_size_t offset, uint32_t v) 282 { 283 const paddr_t ecfg_addr = rmixl_configuration.rc_pci_ecfg.r_pbase 284 + tag + offset; 285 286 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(ecfg_addr) = htobe32(v); 287 __asm __volatile("sync"); 288 } 289 290 static inline void 291 rmixlp_write_8(uint32_t tag, bus_size_t offset, uint64_t v) 292 { 293 const paddr_t ecfg_addr = rmixl_configuration.rc_pci_ecfg.r_pbase 294 + tag + offset; 295 296 *(volatile uint64_t *)MIPS_PHYS_TO_KSEG1(ecfg_addr) = htobe64(v); 297 __asm __volatile("sync"); 298 } 299 300 static inline void 301 rmixl_physaddr_add(struct extent *ext, const char *name, 302 struct rmixl_region *rp, bus_addr_t xpbase, bus_size_t xsize) 303 { 304 rp->r_pbase = xpbase; 305 rp->r_size = xsize; 306 u_long base = xpbase >> 20; 307 u_long size = xsize >> 20; 308 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) { 309 panic("%s: %s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 310 "failed", __func__, name, ext, base, size, EX_NOWAIT); 311 } 312 } 313 314 #endif /* _MIPS_RMI_RMIXLVAR_H_ */ 315
Indexes created Sat Oct 25 06:10:15 GMT 2025