rmixlvar.h revision 1.3
1 /* $NetBSD: rmixlvar.h,v 1.3 2011/02/20 07:48:37 matt Exp $ */ 2 3 /* 4 * Copyright 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _MIPS_RMI_RMIXLVAR_H_ 39 #define _MIPS_RMI_RMIXLVAR_H_ 40 41 #include <mips/cpu.h> 42 #include <mips/locore.h> 43 #include <mips/rmi/rmixl_firmware.h> 44 45 #include <machine/bus.h> 46 47 #include <dev/pci/pcivar.h> 48 49 extern void rmixl_pcr_init_core(void); 50 51 static inline bool 52 cpu_rmixl(const struct pridtab *ct) 53 { 54 if (ct->cpu_cid == MIPS_PRID_CID_RMI) 55 return true; 56 return false; 57 } 58 59 static inline bool 60 cpu_rmixlr(const struct pridtab *ct) 61 { 62 u_int type = ct->cpu_cidflags & MIPS_CIDFL_RMI_TYPE; 63 if (cpu_rmixl(ct) && type == CIDFL_RMI_TYPE_XLR) 64 return true; 65 return false; 66 } 67 68 static inline bool 69 cpu_rmixls(const struct pridtab *ct) 70 { 71 u_int type = ct->cpu_cidflags & MIPS_CIDFL_RMI_TYPE; 72 if (cpu_rmixl(ct) && type == CIDFL_RMI_TYPE_XLS) 73 return true; 74 return false; 75 } 76 77 static inline bool 78 cpu_rmixlp(const struct pridtab *ct) 79 { 80 u_int type = ct->cpu_cidflags & MIPS_CIDFL_RMI_TYPE; 81 if (cpu_rmixl(ct) && type == CIDFL_RMI_TYPE_XLP) 82 return true; 83 return false; 84 } 85 86 static inline int 87 cpu_rmixl_chip_type(const struct pridtab *ct) 88 { 89 return ct->cpu_cidflags & MIPS_CIDFL_RMI_TYPE; 90 } 91 92 typedef enum { 93 PSB_TYPE_UNKNOWN=0, 94 PSB_TYPE_RMI, 95 PSB_TYPE_DELL, 96 } rmixlfw_psb_type_t; 97 98 static inline const char * 99 rmixlfw_psb_type_name(rmixlfw_psb_type_t type) 100 { 101 switch(type) { 102 case PSB_TYPE_UNKNOWN: 103 return "unknown"; 104 case PSB_TYPE_RMI: 105 return "RMI"; 106 case PSB_TYPE_DELL: 107 return "DELL"; 108 default: 109 return "undefined"; 110 } 111 } 112 113 struct rmixl_config { 114 uint64_t rc_io_pbase; 115 bus_addr_t rc_pci_cfg_pbase; 116 bus_size_t rc_pci_cfg_size; 117 bus_addr_t rc_pci_ecfg_pbase; 118 bus_size_t rc_pci_ecfg_size; 119 bus_addr_t rc_pci_mem_pbase; 120 bus_size_t rc_pci_mem_size; 121 bus_addr_t rc_pci_io_pbase; 122 bus_size_t rc_pci_io_size; 123 struct mips_bus_space rc_obio_eb_memt; /* DEVIO -eb */ 124 struct mips_bus_space rc_obio_el_memt; /* DEVIO -el */ 125 struct mips_bus_space rc_pci_cfg_memt; /* PCI CFG */ 126 struct mips_bus_space rc_pci_ecfg_memt; /* PCI ECFG */ 127 struct mips_bus_space rc_pci_memt; /* PCI MEM */ 128 struct mips_bus_space rc_pci_iot; /* PCI IO */ 129 struct mips_bus_dma_tag rc_dma_tag; 130 bus_dma_tag_t rc_64bit_dmat; 131 bus_dma_tag_t rc_32bit_dmat; 132 bus_dma_tag_t rc_29bit_dmat; 133 struct extent *rc_phys_ex; /* Note: MB units */ 134 struct extent *rc_obio_eb_ex; 135 struct extent *rc_obio_el_ex; 136 struct extent *rc_pci_cfg_ex; 137 struct extent *rc_pci_ecfg_ex; 138 struct extent *rc_pci_mem_ex; 139 struct extent *rc_pci_io_ex; 140 int rc_mallocsafe; 141 rmixlfw_info_t rc_psb_info; 142 rmixlfw_psb_type_t rc_psb_type; 143 volatile struct rmixlfw_cpu_wakeup_info 144 *rc_cpu_wakeup_info; 145 const void *rc_cpu_wakeup_end; 146 }; 147 148 extern struct rmixl_config rmixl_configuration; 149 150 extern void rmixl_obio_eb_bus_mem_init(bus_space_tag_t, void *); 151 extern void rmixl_obio_el_bus_mem_init(bus_space_tag_t, void *); 152 extern void rmixl_pci_cfg_bus_mem_init(bus_space_tag_t, void *); 153 extern void rmixl_pci_ecfg_bus_mem_init(bus_space_tag_t, void *); 154 extern void rmixl_pci_bus_mem_init(bus_space_tag_t, void *); 155 extern void rmixl_pci_bus_io_init(bus_space_tag_t, void *); 156 157 extern void rmixl_addr_error_init(void); 158 extern int rmixl_addr_error_check(void); 159 160 extern uint64_t rmixl_mfcr(u_int); 161 extern void rmixl_mtcr(uint64_t, u_int); 162 163 164 /* 165 * rmixl_cache_err_dis: 166 * - disable Cache, Data ECC, Snoop Tag Parity, Tag Parity errors 167 * - clear the cache error log 168 * - return previous value from RMIXL_PCR_L1D_CONFIG0 169 */ 170 static inline uint64_t 171 rmixl_cache_err_dis(void) 172 { 173 uint64_t r; 174 175 r = rmixl_mfcr(RMIXL_PCR_L1D_CONFIG0); 176 rmixl_mtcr(RMIXL_PCR_L1D_CONFIG0, r & ~0x2e); 177 rmixl_mtcr(RMIXL_PCR_L1D_CACHE_ERROR_LOG, 0); 178 return r; 179 } 180 181 /* 182 * rmixl_cache_err_restore: 183 * - clear the cache error log, cache error overflow log, 184 * and cache interrupt registers 185 * - restore previous value to RMIXL_PCR_L1D_CONFIG0 186 */ 187 static inline void 188 rmixl_cache_err_restore(uint64_t r) 189 { 190 rmixl_mtcr(RMIXL_PCR_L1D_CACHE_ERROR_LOG, 0); 191 rmixl_mtcr(RMIXL_PCR_L1D_CACHE_ERROR_OVF_LO, 0); 192 rmixl_mtcr(RMIXL_PCR_L1D_CACHE_INTERRUPT, 0); 193 rmixl_mtcr(RMIXL_PCR_L1D_CONFIG0, r); 194 } 195 196 static inline uint64_t 197 rmixl_cache_err_check(void) 198 { 199 return rmixl_mfcr(RMIXL_PCR_L1D_CACHE_ERROR_LOG); 200 } 201 202 static inline int 203 rmixl_probe_4(volatile uint32_t *va) 204 { 205 uint32_t tmp; 206 uint32_t r; 207 int err; 208 int s; 209 210 s = splhigh(); 211 r = rmixl_cache_err_dis(); 212 tmp = *va; /* probe */ 213 err = rmixl_cache_err_check(); 214 rmixl_cache_err_restore(r); 215 splx(s); 216 217 return (err == 0); 218 } 219 220 #endif /* _MIPS_RMI_RMIXLVAR_H_ */ 221
Indexes created Tue Sep 30 11:09:46 GMT 2025