sbmac.c revision 1.1
1 /* $NetBSD: sbmac.c,v 1.1 2002/03/05 23:46:42 simonb Exp $ */ 2 3 /* 4 * Copyright 2000, 2001 5 * Broadcom Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and copied only 8 * in accordance with the following terms and conditions. Subject to these 9 * conditions, you may download, copy, install, use, modify and distribute 10 * modified or unmodified copies of this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce and 14 * retain this copyright notice and list of conditions as they appear in 15 * the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Broadcom Corporation. Neither the "Broadcom Corporation" name nor any 19 * trademark or logo of Broadcom Corporation may be used to endorse or 20 * promote products derived from this software without the prior written 21 * permission of Broadcom Corporation. 22 * 23 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR 26 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE 27 * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE 28 * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include "bpfilter.h" 37 #include "opt_inet.h" 38 #include "opt_ns.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/sockio.h> 43 #include <sys/mbuf.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/queue.h> 48 #include <sys/device.h> 49 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/if_ether.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 56 #if NBPFILTER > 0 57 #include <net/bpf.h> 58 #endif 59 60 #ifdef INET 61 #include <netinet/in.h> 62 #include <netinet/if_inarp.h> 63 #endif 64 65 #ifdef NS 66 #include <netns/ns.h> 67 #include <netns/ns_if.h> 68 #endif 69 70 #include <machine/cpu.h> 71 #include <machine/bus.h> 72 #include <machine/intr.h> 73 #include <machine/locore.h> 74 75 #include "sbobiovar.h" 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 #include <dev/mii/mii_bitbang.h> 80 81 #include <mips/sibyte/include/sb1250_defs.h> 82 #include <mips/sibyte/include/sb1250_regs.h> 83 #include <mips/sibyte/include/sb1250_mac.h> 84 #include <mips/sibyte/include/sb1250_dma.h> 85 86 87 /* ********************************************************************* 88 * Simple types 89 ********************************************************************* */ 90 91 92 typedef u_long sbmac_port_t; 93 typedef uint64_t sbmac_physaddr_t; 94 typedef uint64_t sbmac_enetaddr_t; 95 96 typedef enum { sbmac_speed_auto, sbmac_speed_10, 97 sbmac_speed_100, sbmac_speed_1000 } sbmac_speed_t; 98 99 typedef enum { sbmac_duplex_auto, sbmac_duplex_half, 100 sbmac_duplex_full } sbmac_duplex_t; 101 102 typedef enum { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame, 103 sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t; 104 105 typedef enum { sbmac_state_uninit, sbmac_state_off, sbmac_state_on, 106 sbmac_state_broken } sbmac_state_t; 107 108 109 /* ********************************************************************* 110 * Macros 111 ********************************************************************* */ 112 113 114 #define SBDMA_NEXTBUF(d, f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \ 115 (d)->sbdma_dscrtable : (d)->f+1) 116 117 118 #define CACHELINESIZE 32 119 #define NUMCACHEBLKS(x) (((x)+CACHELINESIZE-1)/CACHELINESIZE) 120 #define KMALLOC(x) malloc((x), M_DEVBUF, M_DONTWAIT) 121 #define KVTOPHYS(x) kvtophys((vaddr_t)(x)) 122 123 #ifdef SBMACDEBUG 124 #define dprintf(x) printf x 125 #else 126 #define dprintf(x) 127 #endif 128 129 #define SBMAC_READCSR(t) mips3_ld((uint64_t *) (t)) 130 #define SBMAC_WRITECSR(t, v) mips3_sd((uint64_t *) (t), (v)) 131 132 #define PKSEG1(x) ((sbmac_port_t) MIPS_PHYS_TO_KSEG1(x)) 133 134 #define SBMAC_MAX_TXDESCR 64 135 #define SBMAC_MAX_RXDESCR 64 136 137 #define ETHER_ALIGN 2 138 139 /* ********************************************************************* 140 * DMA Descriptor structure 141 ********************************************************************* */ 142 143 typedef struct sbdmadscr_s { 144 uint64_t dscr_a; 145 uint64_t dscr_b; 146 } sbdmadscr_t; 147 148 /* ********************************************************************* 149 * DMA Controller structure 150 ********************************************************************* */ 151 152 typedef struct sbmacdma_s { 153 154 /* 155 * This stuff is used to identify the channel and the registers 156 * associated with it. 157 */ 158 159 struct sbmac_softc *sbdma_eth; /* back pointer to associated MAC */ 160 int sbdma_channel; /* channel number */ 161 int sbdma_txdir; /* direction (1=transmit) */ 162 int sbdma_maxdescr; /* total # of descriptors in ring */ 163 sbmac_port_t sbdma_config0; /* DMA config register 0 */ 164 sbmac_port_t sbdma_config1; /* DMA config register 1 */ 165 sbmac_port_t sbdma_dscrbase; /* Descriptor base address */ 166 sbmac_port_t sbdma_dscrcnt; /* Descriptor count register */ 167 sbmac_port_t sbdma_curdscr; /* current descriptor address */ 168 169 /* 170 * This stuff is for maintenance of the ring 171 */ 172 173 sbdmadscr_t *sbdma_dscrtable; /* base of descriptor table */ 174 sbdmadscr_t *sbdma_dscrtable_end; /* end of descriptor table */ 175 176 struct mbuf **sbdma_ctxtable; /* context table, one per descr */ 177 178 paddr_t sbdma_dscrtable_phys; /* and also the phys addr */ 179 sbdmadscr_t *sbdma_addptr; /* next dscr for sw to add */ 180 sbdmadscr_t *sbdma_remptr; /* next dscr for sw to remove */ 181 } sbmacdma_t; 182 183 184 /* ********************************************************************* 185 * Ethernet softc structure 186 ********************************************************************* */ 187 188 struct sbmac_softc { 189 190 /* 191 * NetBSD-specific things 192 */ 193 struct device sc_dev; /* base device (must be first) */ 194 struct ethercom sc_ethercom; /* Ethernet common part */ 195 struct mii_data sc_mii; 196 struct callout sc_tick_ch; 197 198 int sbm_if_flags; 199 void *sbm_intrhand; 200 201 /* 202 * Controller-specific things 203 */ 204 205 sbmac_port_t sbm_base; /* MAC's base address */ 206 sbmac_state_t sbm_state; /* current state */ 207 208 sbmac_port_t sbm_macenable; /* MAC Enable Register */ 209 sbmac_port_t sbm_maccfg; /* MAC Configuration Register */ 210 sbmac_port_t sbm_fifocfg; /* FIFO configuration register */ 211 sbmac_port_t sbm_framecfg; /* Frame configuration register */ 212 sbmac_port_t sbm_rxfilter; /* receive filter register */ 213 sbmac_port_t sbm_isr; /* Interrupt status register */ 214 sbmac_port_t sbm_imr; /* Interrupt mask register */ 215 216 sbmac_speed_t sbm_speed; /* current speed */ 217 sbmac_duplex_t sbm_duplex; /* current duplex */ 218 sbmac_fc_t sbm_fc; /* current flow control setting */ 219 int sbm_rxflags; /* received packet flags */ 220 221 u_char sbm_hwaddr[ETHER_ADDR_LEN]; 222 223 sbmacdma_t sbm_txdma; /* for now, only use channel 0 */ 224 sbmacdma_t sbm_rxdma; 225 }; 226 227 228 /* ********************************************************************* 229 * Externs 230 ********************************************************************* */ 231 232 extern paddr_t kvtophys(vaddr_t); 233 234 /* ********************************************************************* 235 * Prototypes 236 ********************************************************************* */ 237 238 static void sbdma_initctx(sbmacdma_t *d, struct sbmac_softc *s, int chan, 239 int txrx, int maxdescr); 240 static void sbdma_channel_start(sbmacdma_t *d); 241 static int sbdma_add_rcvbuffer(sbmacdma_t *d, struct mbuf *m); 242 static int sbdma_add_txbuffer(sbmacdma_t *d, struct mbuf *m); 243 static void sbdma_emptyring(sbmacdma_t *d); 244 static void sbdma_fillring(sbmacdma_t *d); 245 static void sbdma_rx_process(struct sbmac_softc *sc, sbmacdma_t *d); 246 static void sbdma_tx_process(struct sbmac_softc *sc, sbmacdma_t *d); 247 static void sbmac_initctx(struct sbmac_softc *s); 248 static void sbmac_channel_start(struct sbmac_softc *s); 249 static void sbmac_channel_stop(struct sbmac_softc *s); 250 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *, 251 sbmac_state_t); 252 static void sbmac_promiscuous_mode(struct sbmac_softc *sc, int onoff); 253 static void sbmac_init_and_start(struct sbmac_softc *sc); 254 static uint64_t sbmac_addr2reg(u_char *ptr); 255 static void sbmac_intr(void *xsc, uint32_t status, uint32_t pc); 256 static void sbmac_start(struct ifnet *ifp); 257 static void sbmac_setmulti(struct sbmac_softc *sc); 258 static int sbmac_ether_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 259 static int sbmac_ioctl(struct ifnet *ifp, u_long command, caddr_t data); 260 static int sbmac_mediachange(struct ifnet *ifp); 261 static void sbmac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr); 262 static void sbmac_watchdog(struct ifnet *ifp); 263 static int sbmac_match(struct device *parent, struct cfdata *match, void *aux); 264 static void sbmac_attach(struct device *parent, struct device *self, void *aux); 265 static int sbmac_set_speed(struct sbmac_softc *s, sbmac_speed_t speed); 266 static int sbmac_set_duplex(struct sbmac_softc *s, sbmac_duplex_t duplex, 267 sbmac_fc_t fc); 268 static void sbmac_tick(void *arg); 269 270 271 /* ********************************************************************* 272 * Globals 273 ********************************************************************* */ 274 275 const struct cfattach sbmac_ca = { 276 sizeof(struct sbmac_softc), sbmac_match, sbmac_attach, 277 }; 278 279 280 uint32_t sbmac_mii_bitbang_read(struct device *self); 281 void sbmac_mii_bitbang_write(struct device *self, uint32_t val); 282 283 static const struct mii_bitbang_ops sbmac_mii_bitbang_ops = { 284 sbmac_mii_bitbang_read, 285 sbmac_mii_bitbang_write, 286 { 287 (uint32_t)M_MAC_MDIO_OUT, /* MII_BIT_MDO */ 288 (uint32_t)M_MAC_MDIO_IN, /* MII_BIT_MDI */ 289 (uint32_t)M_MAC_MDC, /* MII_BIT_MDC */ 290 0, /* MII_BIT_DIR_HOST_PHY */ 291 (uint32_t)M_MAC_MDIO_DIR /* MII_BIT_DIR_PHY_HOST */ 292 } 293 }; 294 295 uint32_t 296 sbmac_mii_bitbang_read(struct device *self) 297 { 298 struct sbmac_softc *sc = (void *) self; 299 sbmac_port_t reg; 300 301 reg = PKSEG1(sc->sbm_base + R_MAC_MDIO); 302 return (uint32_t) SBMAC_READCSR(reg); 303 } 304 305 void 306 sbmac_mii_bitbang_write(struct device *self, uint32_t val) 307 { 308 struct sbmac_softc *sc = (void *) self; 309 sbmac_port_t reg; 310 311 reg = PKSEG1(sc->sbm_base + R_MAC_MDIO); 312 313 SBMAC_WRITECSR(reg, (val & 314 (M_MAC_MDC|M_MAC_MDIO_DIR|M_MAC_MDIO_OUT|M_MAC_MDIO_IN))); 315 } 316 317 /* 318 * Read an PHY register through the MII. 319 */ 320 static int 321 sbmac_mii_readreg(struct device *self, int phy, int reg) 322 { 323 324 return (mii_bitbang_readreg(self, &sbmac_mii_bitbang_ops, phy, reg)); 325 } 326 327 /* 328 * Write to a PHY register through the MII. 329 */ 330 static void 331 sbmac_mii_writereg(struct device *self, int phy, int reg, int val) 332 { 333 334 mii_bitbang_writereg(self, &sbmac_mii_bitbang_ops, phy, reg, val); 335 } 336 337 static void 338 sbmac_mii_statchg(struct device *self) 339 { 340 struct sbmac_softc *sc = (struct sbmac_softc *)self; 341 sbmac_state_t oldstate; 342 343 /* Stop the MAC in preparation for changing all of the parameters. */ 344 oldstate = sbmac_set_channel_state(sc, sbmac_state_off); 345 346 switch (sc->sc_ethercom.ec_if.if_baudrate) { 347 default: /* if autonegotiation fails, assume 10Mbit */ 348 case IF_Mbps(10): 349 sbmac_set_speed(sc, sbmac_speed_10); 350 break; 351 352 case IF_Mbps(100): 353 sbmac_set_speed(sc, sbmac_speed_100); 354 break; 355 356 case IF_Mbps(1000): 357 sbmac_set_speed(sc, sbmac_speed_1000); 358 break; 359 } 360 361 if (sc->sc_mii.mii_media_active & IFM_FDX) { 362 /* Configure for full-duplex */ 363 /* XXX: is flow control right for 10, 100? */ 364 sbmac_set_duplex(sc, sbmac_duplex_full, sbmac_fc_frame); 365 } else { 366 /* Configure for half-duplex */ 367 /* XXX: is flow control right? */ 368 sbmac_set_duplex(sc, sbmac_duplex_half, sbmac_fc_disabled); 369 } 370 371 /* And put it back into its former state. */ 372 sbmac_set_channel_state(sc, oldstate); 373 } 374 375 /* ********************************************************************* 376 * SBDMA_INITCTX(d, s, chan, txrx, maxdescr) 377 * 378 * Initialize a DMA channel context. Since there are potentially 379 * eight DMA channels per MAC, it's nice to do this in a standard 380 * way. 381 * 382 * Input parameters: 383 * d - sbmacdma_t structure (DMA channel context) 384 * s - sbmac_softc structure (pointer to a MAC) 385 * chan - channel number (0..1 right now) 386 * txrx - Identifies DMA_TX or DMA_RX for channel direction 387 * maxdescr - number of descriptors 388 * 389 * Return value: 390 * nothing 391 ********************************************************************* */ 392 393 static void 394 sbdma_initctx(sbmacdma_t *d, struct sbmac_softc *s, int chan, int txrx, 395 int maxdescr) 396 { 397 /* 398 * Save away interesting stuff in the structure 399 */ 400 401 d->sbdma_eth = s; 402 d->sbdma_channel = chan; 403 d->sbdma_txdir = txrx; 404 405 /* 406 * initialize register pointers 407 */ 408 409 d->sbdma_config0 = PKSEG1(s->sbm_base + 410 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_CONFIG0)); 411 d->sbdma_config1 = PKSEG1(s->sbm_base + 412 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_CONFIG0)); 413 d->sbdma_dscrbase = PKSEG1(s->sbm_base + 414 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_DSCR_BASE)); 415 d->sbdma_dscrcnt = PKSEG1(s->sbm_base + 416 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_DSCR_CNT)); 417 d->sbdma_curdscr = PKSEG1(s->sbm_base + 418 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_CUR_DSCRADDR)); 419 420 /* 421 * Allocate memory for the ring 422 */ 423 424 d->sbdma_maxdescr = maxdescr; 425 426 d->sbdma_dscrtable = (sbdmadscr_t *) 427 KMALLOC(d->sbdma_maxdescr*sizeof(sbdmadscr_t)); 428 429 bzero(d->sbdma_dscrtable, d->sbdma_maxdescr*sizeof(sbdmadscr_t)); 430 431 d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr; 432 433 d->sbdma_dscrtable_phys = KVTOPHYS(d->sbdma_dscrtable); 434 435 /* 436 * And context table 437 */ 438 439 d->sbdma_ctxtable = (struct mbuf **) 440 KMALLOC(d->sbdma_maxdescr*sizeof(struct mbuf *)); 441 442 bzero(d->sbdma_ctxtable, d->sbdma_maxdescr*sizeof(struct mbuf *)); 443 } 444 445 /* ********************************************************************* 446 * SBDMA_CHANNEL_START(d) 447 * 448 * Initialize the hardware registers for a DMA channel. 449 * 450 * Input parameters: 451 * d - DMA channel to init (context must be previously init'd 452 * 453 * Return value: 454 * nothing 455 ********************************************************************* */ 456 457 static void 458 sbdma_channel_start(sbmacdma_t *d) 459 { 460 /* 461 * Turn on the DMA channel 462 */ 463 464 SBMAC_WRITECSR(d->sbdma_config1, 0); 465 466 SBMAC_WRITECSR(d->sbdma_dscrbase, d->sbdma_dscrtable_phys); 467 468 SBMAC_WRITECSR(d->sbdma_config0, V_DMA_RINGSZ(d->sbdma_maxdescr) | 0); 469 470 /* 471 * Initialize ring pointers 472 */ 473 474 d->sbdma_addptr = d->sbdma_dscrtable; 475 d->sbdma_remptr = d->sbdma_dscrtable; 476 } 477 478 /* ********************************************************************* 479 * SBDMA_ADD_RCVBUFFER(d, m) 480 * 481 * Add a buffer to the specified DMA channel. For receive channels, 482 * this queues a buffer for inbound packets. 483 * 484 * Input parameters: 485 * d - DMA channel descriptor 486 * m - mbuf to add, or NULL if we should allocate one. 487 * 488 * Return value: 489 * 0 if buffer could not be added (ring is full) 490 * 1 if buffer added successfully 491 ********************************************************************* */ 492 493 494 static int 495 sbdma_add_rcvbuffer(sbmacdma_t *d, struct mbuf *m) 496 { 497 sbdmadscr_t *dsc; 498 sbdmadscr_t *nextdsc; 499 struct mbuf *m_new = NULL; 500 501 /* get pointer to our current place in the ring */ 502 503 dsc = d->sbdma_addptr; 504 nextdsc = SBDMA_NEXTBUF(d, sbdma_addptr); 505 506 /* 507 * figure out if the ring is full - if the next descriptor 508 * is the same as the one that we're going to remove from 509 * the ring, the ring is full 510 */ 511 512 if (nextdsc == d->sbdma_remptr) 513 return ENOSPC; 514 515 /* 516 * Allocate an mbuf if we don't already have one. 517 * If we do have an mbuf, reset it so that it's empty. 518 */ 519 520 if (m == NULL) { 521 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 522 if (m_new == NULL) { 523 printf("%s: mbuf allocation failed\n", 524 d->sbdma_eth->sc_dev.dv_xname); 525 return ENOBUFS; 526 } 527 528 MCLGET(m_new, M_DONTWAIT); 529 if (!(m_new->m_flags & M_EXT)) { 530 printf("%s: mbuf cluster allocation failed\n", 531 d->sbdma_eth->sc_dev.dv_xname); 532 m_freem(m_new); 533 return ENOBUFS; 534 } 535 536 m_new->m_len = m_new->m_pkthdr.len= MCLBYTES; 537 m_adj(m_new, ETHER_ALIGN); 538 } else { 539 m_new = m; 540 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 541 m_new->m_data = m_new->m_ext.ext_buf; 542 m_adj(m_new, ETHER_ALIGN); 543 } 544 545 /* 546 * fill in the descriptor 547 */ 548 549 dsc->dscr_a = KVTOPHYS(mtod(m_new, caddr_t)) | 550 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(ETHER_ALIGN + m_new->m_len)) | 551 M_DMA_DSCRA_INTERRUPT; 552 553 /* receiving: no options */ 554 dsc->dscr_b = 0; 555 556 /* 557 * fill in the context 558 */ 559 560 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = m_new; 561 562 /* 563 * point at next packet 564 */ 565 566 d->sbdma_addptr = nextdsc; 567 568 /* 569 * Give the buffer to the DMA engine. 570 */ 571 572 SBMAC_WRITECSR(d->sbdma_dscrcnt, 1); 573 574 return 0; /* we did it */ 575 } 576 577 /* ********************************************************************* 578 * SBDMA_ADD_TXBUFFER(d, m) 579 * 580 * Add a transmit buffer to the specified DMA channel, causing a 581 * transmit to start. 582 * 583 * Input parameters: 584 * d - DMA channel descriptor 585 * m - mbuf to add 586 * 587 * Return value: 588 * 0 transmit queued successfully 589 * otherwise error code 590 ********************************************************************* */ 591 592 593 static int 594 sbdma_add_txbuffer(sbmacdma_t *d, struct mbuf *m) 595 { 596 sbdmadscr_t *dsc; 597 sbdmadscr_t *nextdsc; 598 struct mbuf *m_new = NULL; 599 int length; 600 601 /* get pointer to our current place in the ring */ 602 603 dsc = d->sbdma_addptr; 604 nextdsc = SBDMA_NEXTBUF(d, sbdma_addptr); 605 606 /* 607 * figure out if the ring is full - if the next descriptor 608 * is the same as the one that we're going to remove from 609 * the ring, the ring is full 610 */ 611 612 if (nextdsc == d->sbdma_remptr) 613 return ENOSPC; 614 615 #if 0 616 do { 617 struct mbuf *m0; 618 619 printf("mbuf chain: "); 620 for (m0 = m; m0 != 0; m0 = m0->m_next) { 621 printf("%d%c/%X ", m0->m_len, 622 m0->m_flags & M_EXT ? 'X' : 'N', 623 mtod(m0, u_int)); 624 } 625 printf("\n"); 626 } while (0); 627 #endif 628 629 /* 630 * [BEGIN XXX] 631 * XXX Copy/coalesce the mbufs into a single mbuf cluster (we assume 632 * it will fit). This is a temporary hack to get us going. 633 */ 634 635 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 636 if (m_new == NULL) { 637 printf("%s: mbuf allocation failed\n", 638 d->sbdma_eth->sc_dev.dv_xname); 639 return ENOBUFS; 640 } 641 642 MCLGET(m_new, M_DONTWAIT); 643 if (!(m_new->m_flags & M_EXT)) { 644 printf("%s: mbuf cluster allocation failed\n", 645 d->sbdma_eth->sc_dev.dv_xname); 646 m_freem(m_new); 647 return ENOBUFS; 648 } 649 650 m_new->m_len = m_new->m_pkthdr.len= MCLBYTES; 651 /*m_adj(m_new, ETHER_ALIGN);*/ 652 653 /* 654 * XXX Don't forget to include the offset portion in the 655 * XXX cache block calculation when this code is rewritten! 656 */ 657 658 /* 659 * Copy data 660 */ 661 662 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 663 m_new->m_len = m_new->m_pkthdr.len = m->m_pkthdr.len; 664 665 /* Free old mbuf 'm', actual mbuf is now 'm_new' */ 666 667 // XXX: CALLERS WILL FREE, they might have to bpf_mtap() if this 668 // XXX: function succeeds. 669 // m_freem(m); 670 length = m_new->m_len; 671 672 /* [END XXX] */ 673 674 /* 675 * fill in the descriptor 676 */ 677 678 dsc->dscr_a = KVTOPHYS(mtod(m_new, caddr_t)) | 679 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(m_new->m_len)) | 680 M_DMA_DSCRA_INTERRUPT | 681 M_DMA_ETHTX_SOP; 682 683 /* transmitting: set outbound options and length */ 684 dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) | 685 V_DMA_DSCRB_PKT_SIZE(length); 686 687 /* 688 * fill in the context 689 */ 690 691 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = m_new; 692 693 /* 694 * point at next packet 695 */ 696 697 d->sbdma_addptr = nextdsc; 698 699 /* 700 * Give the buffer to the DMA engine. 701 */ 702 703 SBMAC_WRITECSR(d->sbdma_dscrcnt, 1); 704 705 return 0; /* we did it */ 706 } 707 708 /* ********************************************************************* 709 * SBDMA_EMPTYRING(d) 710 * 711 * Free all allocated mbufs on the specified DMA channel; 712 * 713 * Input parameters: 714 * d - DMA channel 715 * 716 * Return value: 717 * nothing 718 ********************************************************************* */ 719 720 static void 721 sbdma_emptyring(sbmacdma_t *d) 722 { 723 int idx; 724 struct mbuf *m; 725 726 for (idx = 0; idx < d->sbdma_maxdescr; idx++) { 727 m = d->sbdma_ctxtable[idx]; 728 if (m) { 729 m_freem(m); 730 d->sbdma_ctxtable[idx] = NULL; 731 } 732 } 733 } 734 735 /* ********************************************************************* 736 * SBDMA_FILLRING(d) 737 * 738 * Fill the specified DMA channel (must be receive channel) 739 * with mbufs 740 * 741 * Input parameters: 742 * d - DMA channel 743 * 744 * Return value: 745 * nothing 746 ********************************************************************* */ 747 748 static void 749 sbdma_fillring(sbmacdma_t *d) 750 { 751 int idx; 752 753 for (idx = 0; idx < SBMAC_MAX_RXDESCR-1; idx++) 754 if (sbdma_add_rcvbuffer(d, NULL) != 0) 755 break; 756 } 757 758 /* ********************************************************************* 759 * SBDMA_RX_PROCESS(sc, d) 760 * 761 * Process "completed" receive buffers on the specified DMA channel. 762 * Note that this isn't really ideal for priority channels, since 763 * it processes all of the packets on a given channel before 764 * returning. 765 * 766 * Input parameters: 767 * sc - softc structure 768 * d - DMA channel context 769 * 770 * Return value: 771 * nothing 772 ********************************************************************* */ 773 774 static void 775 sbdma_rx_process(struct sbmac_softc *sc, sbmacdma_t *d) 776 { 777 int curidx; 778 int hwidx; 779 sbdmadscr_t *dsc; 780 struct mbuf *m; 781 struct ether_header *eh; 782 int len; 783 784 struct ifnet *ifp = &(sc->sc_ethercom.ec_if); 785 786 for (;;) { 787 /* 788 * figure out where we are (as an index) and where 789 * the hardware is (also as an index) 790 * 791 * This could be done faster if (for example) the 792 * descriptor table was page-aligned and contiguous in 793 * both virtual and physical memory -- you could then 794 * just compare the low-order bits of the virtual address 795 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) 796 */ 797 798 curidx = d->sbdma_remptr - d->sbdma_dscrtable; 799 hwidx = (int) 800 (((SBMAC_READCSR(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - 801 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t)); 802 803 /* 804 * If they're the same, that means we've processed all 805 * of the descriptors up to (but not including) the one that 806 * the hardware is working on right now. 807 */ 808 809 if (curidx == hwidx) 810 break; 811 812 /* 813 * Otherwise, get the packet's mbuf ptr back 814 */ 815 816 dsc = &(d->sbdma_dscrtable[curidx]); 817 m = d->sbdma_ctxtable[curidx]; 818 d->sbdma_ctxtable[curidx] = NULL; 819 820 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4; 821 822 /* 823 * Check packet status. If good, process it. 824 * If not, silently drop it and put it back on the 825 * receive ring. 826 */ 827 828 if (! (dsc->dscr_a & M_DMA_ETHRX_BAD)) { 829 830 /* 831 * Set length into the packet 832 * XXX do we remove the CRC here? 833 */ 834 m->m_pkthdr.len = m->m_len = len; 835 836 ifp->if_ipackets++; 837 eh = mtod(m, struct ether_header *); 838 m->m_pkthdr.rcvif = ifp; 839 840 841 /* 842 * Add a new buffer to replace the old one. 843 */ 844 sbdma_add_rcvbuffer(d, NULL); 845 846 #if (NBPFILTER > 0) 847 /* 848 * Handle BPF listeners. Let the BPF user see the 849 * packet, but don't pass it up to the ether_input() 850 * layer unless it's a broadcast packet, multicast 851 * packet, matches our ethernet address or the 852 * interface is in promiscuous mode. 853 */ 854 855 if (ifp->if_bpf) 856 bpf_mtap(ifp->if_bpf, m); 857 #endif 858 /* 859 * Pass the buffer to the kernel 860 */ 861 (*ifp->if_input)(ifp, m); 862 } else { 863 /* 864 * Packet was mangled somehow. Just drop it and 865 * put it back on the receive ring. 866 */ 867 sbdma_add_rcvbuffer(d, m); 868 } 869 870 /* 871 * .. and advance to the next buffer. 872 */ 873 874 d->sbdma_remptr = SBDMA_NEXTBUF(d, sbdma_remptr); 875 } 876 } 877 878 /* ********************************************************************* 879 * SBDMA_TX_PROCESS(sc, d) 880 * 881 * Process "completed" transmit buffers on the specified DMA channel. 882 * This is normally called within the interrupt service routine. 883 * Note that this isn't really ideal for priority channels, since 884 * it processes all of the packets on a given channel before 885 * returning. 886 * 887 * Input parameters: 888 * sc - softc structure 889 * d - DMA channel context 890 * 891 * Return value: 892 * nothing 893 ********************************************************************* */ 894 895 static void 896 sbdma_tx_process(struct sbmac_softc *sc, sbmacdma_t *d) 897 { 898 int curidx; 899 int hwidx; 900 sbdmadscr_t *dsc; 901 struct mbuf *m; 902 903 struct ifnet *ifp = &(sc->sc_ethercom.ec_if); 904 905 for (;;) { 906 /* 907 * figure out where we are (as an index) and where 908 * the hardware is (also as an index) 909 * 910 * This could be done faster if (for example) the 911 * descriptor table was page-aligned and contiguous in 912 * both virtual and physical memory -- you could then 913 * just compare the low-order bits of the virtual address 914 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) 915 */ 916 917 curidx = d->sbdma_remptr - d->sbdma_dscrtable; 918 hwidx = (int) 919 (((SBMAC_READCSR(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - 920 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t)); 921 922 /* 923 * If they're the same, that means we've processed all 924 * of the descriptors up to (but not including) the one that 925 * the hardware is working on right now. 926 */ 927 928 if (curidx == hwidx) 929 break; 930 931 /* 932 * Otherwise, get the packet's mbuf ptr back 933 */ 934 935 dsc = &(d->sbdma_dscrtable[curidx]); 936 m = d->sbdma_ctxtable[curidx]; 937 d->sbdma_ctxtable[curidx] = NULL; 938 939 /* 940 * for transmits, we just free buffers. 941 */ 942 943 m_freem(m); 944 945 /* 946 * .. and advance to the next buffer. 947 */ 948 949 d->sbdma_remptr = SBDMA_NEXTBUF(d, sbdma_remptr); 950 } 951 952 /* 953 * Decide what to set the IFF_OACTIVE bit in the interface to. 954 * It's supposed to reflect if the interface is actively 955 * transmitting, but that's really hard to do quickly. 956 */ 957 958 ifp->if_flags &= ~IFF_OACTIVE; 959 } 960 961 962 963 /* ********************************************************************* 964 * SBMAC_INITCTX(s) 965 * 966 * Initialize an Ethernet context structure - this is called 967 * once per MAC on the 1250. Memory is allocated here, so don't 968 * call it again from inside the ioctl routines that bring the 969 * interface up/down 970 * 971 * Input parameters: 972 * s - sbmac context structure 973 * 974 * Return value: 975 * 0 976 ********************************************************************* */ 977 978 static void 979 sbmac_initctx(struct sbmac_softc *s) 980 { 981 982 /* 983 * figure out the addresses of some ports 984 */ 985 986 s->sbm_macenable = PKSEG1(s->sbm_base + R_MAC_ENABLE); 987 s->sbm_maccfg = PKSEG1(s->sbm_base + R_MAC_CFG); 988 s->sbm_fifocfg = PKSEG1(s->sbm_base + R_MAC_THRSH_CFG); 989 s->sbm_framecfg = PKSEG1(s->sbm_base + R_MAC_FRAMECFG); 990 s->sbm_rxfilter = PKSEG1(s->sbm_base + R_MAC_ADFILTER_CFG); 991 s->sbm_isr = PKSEG1(s->sbm_base + R_MAC_STATUS); 992 s->sbm_imr = PKSEG1(s->sbm_base + R_MAC_INT_MASK); 993 994 /* 995 * Initialize the DMA channels. Right now, only one per MAC is used 996 * Note: Only do this _once_, as it allocates memory from the kernel! 997 */ 998 999 sbdma_initctx(&(s->sbm_txdma), s, 0, DMA_TX, SBMAC_MAX_TXDESCR); 1000 sbdma_initctx(&(s->sbm_rxdma), s, 0, DMA_RX, SBMAC_MAX_RXDESCR); 1001 1002 /* 1003 * initial state is OFF 1004 */ 1005 1006 s->sbm_state = sbmac_state_off; 1007 1008 /* 1009 * Initial speed is (XXX TEMP) 10MBit/s HDX no FC 1010 */ 1011 1012 s->sbm_speed = sbmac_speed_10; 1013 s->sbm_duplex = sbmac_duplex_half; 1014 s->sbm_fc = sbmac_fc_disabled; 1015 } 1016 1017 1018 /* ********************************************************************* 1019 * SBMAC_CHANNEL_START(s) 1020 * 1021 * Start packet processing on this MAC. 1022 * 1023 * Input parameters: 1024 * s - sbmac structure 1025 * 1026 * Return value: 1027 * nothing 1028 ********************************************************************* */ 1029 1030 static void 1031 sbmac_channel_start(struct sbmac_softc *s) 1032 { 1033 uint64_t reg; 1034 sbmac_port_t port; 1035 uint64_t cfg, fifo, framecfg; 1036 int idx; 1037 1038 /* 1039 * Don't do this if running 1040 */ 1041 1042 if (s->sbm_state == sbmac_state_on) 1043 return; 1044 1045 /* 1046 * Bring the controller out of reset, but leave it off. 1047 */ 1048 1049 SBMAC_WRITECSR(s->sbm_macenable, 0); 1050 1051 /* 1052 * Ignore all received packets 1053 */ 1054 1055 SBMAC_WRITECSR(s->sbm_rxfilter, 0); 1056 1057 /* 1058 * Calculate values for various control registers. 1059 */ 1060 1061 cfg = M_MAC_RETRY_EN | 1062 M_MAC_TX_HOLD_SOP_EN | 1063 V_MAC_TX_PAUSE_CNT_16K | 1064 M_MAC_AP_STAT_EN | 1065 M_MAC_SS_EN | 1066 0; 1067 1068 fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */ 1069 V_MAC_TX_RD_THRSH(4) | 1070 V_MAC_TX_RL_THRSH(4) | 1071 V_MAC_RX_PL_THRSH(4) | 1072 V_MAC_RX_RD_THRSH(4) | /* Must be '4' */ 1073 V_MAC_RX_PL_THRSH(4) | 1074 V_MAC_RX_RL_THRSH(8) | 1075 0; 1076 1077 framecfg = V_MAC_MIN_FRAMESZ_DEFAULT | 1078 V_MAC_MAX_FRAMESZ_DEFAULT | 1079 V_MAC_BACKOFF_SEL(1); 1080 1081 /* 1082 * Clear out the hash address map 1083 */ 1084 1085 port = PKSEG1(s->sbm_base + R_MAC_HASH_BASE); 1086 for (idx = 0; idx < MAC_HASH_COUNT; idx++) { 1087 SBMAC_WRITECSR(port, 0); 1088 port += sizeof(uint64_t); 1089 } 1090 1091 /* 1092 * Clear out the exact-match table 1093 */ 1094 1095 port = PKSEG1(s->sbm_base + R_MAC_ADDR_BASE); 1096 for (idx = 0; idx < MAC_ADDR_COUNT; idx++) { 1097 SBMAC_WRITECSR(port, 0); 1098 port += sizeof(uint64_t); 1099 } 1100 1101 /* 1102 * Clear out the DMA Channel mapping table registers 1103 */ 1104 1105 port = PKSEG1(s->sbm_base + R_MAC_CHUP0_BASE); 1106 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { 1107 SBMAC_WRITECSR(port, 0); 1108 port += sizeof(uint64_t); 1109 } 1110 1111 port = PKSEG1(s->sbm_base + R_MAC_CHLO0_BASE); 1112 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { 1113 SBMAC_WRITECSR(port, 0); 1114 port += sizeof(uint64_t); 1115 } 1116 1117 /* 1118 * Program the hardware address. It goes into the hardware-address 1119 * register as well as the first filter register. 1120 */ 1121 1122 reg = sbmac_addr2reg(s->sbm_hwaddr); 1123 1124 port = PKSEG1(s->sbm_base + R_MAC_ADDR_BASE); 1125 SBMAC_WRITECSR(port, reg); 1126 port = PKSEG1(s->sbm_base + R_MAC_ETHERNET_ADDR); 1127 SBMAC_WRITECSR(port, 0); // pass1 workaround 1128 1129 /* 1130 * Set the receive filter for no packets, and write values 1131 * to the various config registers 1132 */ 1133 1134 SBMAC_WRITECSR(s->sbm_rxfilter, 0); 1135 SBMAC_WRITECSR(s->sbm_imr, 0); 1136 SBMAC_WRITECSR(s->sbm_framecfg, framecfg); 1137 SBMAC_WRITECSR(s->sbm_fifocfg, fifo); 1138 SBMAC_WRITECSR(s->sbm_maccfg, cfg); 1139 1140 /* 1141 * Initialize DMA channels (rings should be ok now) 1142 */ 1143 1144 sbdma_channel_start(&(s->sbm_rxdma)); 1145 sbdma_channel_start(&(s->sbm_txdma)); 1146 1147 /* 1148 * Configure the speed, duplex, and flow control 1149 */ 1150 1151 sbmac_set_speed(s, s->sbm_speed); 1152 sbmac_set_duplex(s, s->sbm_duplex, s->sbm_fc); 1153 1154 /* 1155 * Fill the receive ring 1156 */ 1157 1158 sbdma_fillring(&(s->sbm_rxdma)); 1159 1160 /* 1161 * Turn on the rest of the bits in the enable register 1162 */ 1163 1164 SBMAC_WRITECSR(s->sbm_macenable, M_MAC_RXDMA_EN0 | M_MAC_TXDMA_EN0 | 1165 M_MAC_RX_ENABLE | M_MAC_TX_ENABLE); 1166 1167 1168 /* 1169 * Accept any kind of interrupt on TX and RX DMA channel 0 1170 */ 1171 SBMAC_WRITECSR(s->sbm_imr, 1172 (M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | 1173 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)); 1174 1175 /* 1176 * Enable receiving unicasts and broadcasts 1177 */ 1178 1179 SBMAC_WRITECSR(s->sbm_rxfilter, M_MAC_UCAST_EN | M_MAC_BCAST_EN); 1180 1181 /* 1182 * we're running now. 1183 */ 1184 1185 s->sbm_state = sbmac_state_on; 1186 s->sc_ethercom.ec_if.if_flags |= IFF_RUNNING; 1187 1188 /* 1189 * Program multicast addresses 1190 */ 1191 1192 sbmac_setmulti(s); 1193 1194 /* 1195 * If channel was in promiscuous mode before, turn that on 1196 */ 1197 1198 if (s->sc_ethercom.ec_if.if_flags & IFF_PROMISC) 1199 sbmac_promiscuous_mode(s, 1); 1200 1201 /* 1202 * Turn on the once-per-second timer 1203 */ 1204 1205 callout_reset(&(s->sc_tick_ch), hz, sbmac_tick, s); 1206 } 1207 1208 1209 /* ********************************************************************* 1210 * SBMAC_CHANNEL_STOP(s) 1211 * 1212 * Stop packet processing on this MAC. 1213 * 1214 * Input parameters: 1215 * s - sbmac structure 1216 * 1217 * Return value: 1218 * nothing 1219 ********************************************************************* */ 1220 1221 static void sbmac_channel_stop(struct sbmac_softc *s) 1222 { 1223 uint64_t ctl; 1224 1225 /* don't do this if already stopped */ 1226 1227 if (s->sbm_state == sbmac_state_off) return; 1228 1229 /* don't accept any packets, disable all interrupts */ 1230 1231 SBMAC_WRITECSR(s->sbm_rxfilter, 0); 1232 SBMAC_WRITECSR(s->sbm_imr, 0); 1233 1234 /* Turn off ticker */ 1235 1236 callout_stop(&(s->sc_tick_ch)); 1237 1238 /* turn off receiver and transmitter */ 1239 1240 ctl = SBMAC_READCSR(s->sbm_macenable); 1241 ctl &= ~(M_MAC_RXDMA_EN0 | M_MAC_TXDMA_EN0); 1242 SBMAC_WRITECSR(s->sbm_macenable, ctl); 1243 1244 /* We're stopped now. */ 1245 1246 s->sbm_state = sbmac_state_off; 1247 s->sc_ethercom.ec_if.if_flags &= ~IFF_RUNNING; 1248 1249 /* Empty the receive and transmit rings */ 1250 1251 sbdma_emptyring(&(s->sbm_rxdma)); 1252 sbdma_emptyring(&(s->sbm_txdma)); 1253 1254 } 1255 1256 /* ********************************************************************* 1257 * SBMAC_SET_CHANNEL_STATE(state) 1258 * 1259 * Set the channel's state ON or OFF 1260 * 1261 * Input parameters: 1262 * state - new state 1263 * 1264 * Return value: 1265 * old state 1266 ********************************************************************* */ 1267 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *sc, 1268 sbmac_state_t state) 1269 { 1270 sbmac_state_t oldstate = sc->sbm_state; 1271 1272 /* 1273 * If same as previous state, return 1274 */ 1275 1276 if (state == oldstate) { 1277 return oldstate; 1278 } 1279 1280 /* 1281 * If new state is ON, turn channel on 1282 */ 1283 1284 if (state == sbmac_state_on) { 1285 sbmac_channel_start(sc); 1286 } 1287 else { 1288 sbmac_channel_stop(sc); 1289 } 1290 1291 /* 1292 * Return previous state 1293 */ 1294 1295 return oldstate; 1296 } 1297 1298 1299 /* ********************************************************************* 1300 * SBMAC_PROMISCUOUS_MODE(sc, onoff) 1301 * 1302 * Turn on or off promiscuous mode 1303 * 1304 * Input parameters: 1305 * sc - softc 1306 * onoff - 1 to turn on, 0 to turn off 1307 * 1308 * Return value: 1309 * nothing 1310 ********************************************************************* */ 1311 1312 static void sbmac_promiscuous_mode(struct sbmac_softc *sc, int onoff) 1313 { 1314 uint64_t reg; 1315 1316 if (sc->sbm_state != sbmac_state_on) return; 1317 1318 if (onoff) { 1319 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1320 reg |= M_MAC_ALLPKT_EN; 1321 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1322 } 1323 else { 1324 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1325 reg &= ~M_MAC_ALLPKT_EN; 1326 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1327 } 1328 } 1329 1330 1331 1332 /* ********************************************************************* 1333 * SBMAC_INIT_AND_START(sc) 1334 * 1335 * Stop the channel and restart it. This is generally used 1336 * when we have to do something to the channel that requires 1337 * a swift kick. 1338 * 1339 * Input parameters: 1340 * sc - softc 1341 ********************************************************************* */ 1342 1343 static void sbmac_init_and_start(struct sbmac_softc *sc) 1344 { 1345 int s; 1346 1347 s = splnet(); 1348 1349 mii_pollstat(&sc->sc_mii); /* poll phy for current speed */ 1350 sbmac_mii_statchg((struct device *) sc); /* set state to new speed */ 1351 sbmac_set_channel_state(sc, sbmac_state_on); 1352 1353 splx(s); 1354 } 1355 1356 /* ********************************************************************* 1357 * SBMAC_ADDR2REG(ptr) 1358 * 1359 * Convert six bytes into the 64-bit register value that 1360 * we typically write into the SBMAC's address/mcast registers 1361 * 1362 * Input parameters: 1363 * ptr - pointer to 6 bytes 1364 * 1365 * Return value: 1366 * register value 1367 ********************************************************************* */ 1368 1369 static uint64_t sbmac_addr2reg(u_char *ptr) 1370 { 1371 uint64_t reg = 0; 1372 1373 ptr += 6; 1374 1375 reg |= (uint64_t) *(--ptr); 1376 reg <<= 8; 1377 reg |= (uint64_t) *(--ptr); 1378 reg <<= 8; 1379 reg |= (uint64_t) *(--ptr); 1380 reg <<= 8; 1381 reg |= (uint64_t) *(--ptr); 1382 reg <<= 8; 1383 reg |= (uint64_t) *(--ptr); 1384 reg <<= 8; 1385 reg |= (uint64_t) *(--ptr); 1386 1387 return reg; 1388 } 1389 1390 1391 /* ********************************************************************* 1392 * SBMAC_SET_SPEED(s, speed) 1393 * 1394 * Configure LAN speed for the specified MAC. 1395 * Warning: must be called when MAC is off! 1396 * 1397 * Input parameters: 1398 * s - sbmac structure 1399 * speed - speed to set MAC to (see sbmac_speed_t enum) 1400 * 1401 * Return value: 1402 * 1 if successful 1403 * 0 indicates invalid parameters 1404 ********************************************************************* */ 1405 1406 static int sbmac_set_speed(struct sbmac_softc *s, sbmac_speed_t speed) 1407 { 1408 uint64_t cfg; 1409 uint64_t framecfg; 1410 1411 /* 1412 * Save new current values 1413 */ 1414 1415 s->sbm_speed = speed; 1416 1417 if (s->sbm_state != sbmac_state_off) 1418 panic("sbmac_set_speed while MAC not off"); 1419 1420 /* 1421 * Read current register values 1422 */ 1423 1424 cfg = SBMAC_READCSR(s->sbm_maccfg); 1425 framecfg = SBMAC_READCSR(s->sbm_framecfg); 1426 1427 /* 1428 * Mask out the stuff we want to change 1429 */ 1430 1431 cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL); 1432 framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH | 1433 M_MAC_SLOT_SIZE); 1434 1435 /* 1436 * Now add in the new bits 1437 */ 1438 1439 switch (speed) { 1440 case sbmac_speed_10: 1441 framecfg |= V_MAC_IFG_RX_10 | 1442 V_MAC_IFG_TX_10 | 1443 K_MAC_IFG_THRSH_10 | 1444 V_MAC_SLOT_SIZE_10; 1445 cfg |= V_MAC_SPEED_SEL_10MBPS; 1446 break; 1447 1448 case sbmac_speed_100: 1449 framecfg |= V_MAC_IFG_RX_100 | 1450 V_MAC_IFG_TX_100 | 1451 V_MAC_IFG_THRSH_100 | 1452 V_MAC_SLOT_SIZE_100; 1453 cfg |= V_MAC_SPEED_SEL_100MBPS ; 1454 break; 1455 1456 case sbmac_speed_1000: 1457 framecfg |= V_MAC_IFG_RX_1000 | 1458 V_MAC_IFG_TX_1000 | 1459 V_MAC_IFG_THRSH_1000 | 1460 V_MAC_SLOT_SIZE_1000; 1461 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN; 1462 break; 1463 1464 case sbmac_speed_auto: /* XXX not implemented */ 1465 /* fall through */ 1466 default: 1467 return 0; 1468 } 1469 1470 /* 1471 * Send the bits back to the hardware 1472 */ 1473 1474 SBMAC_WRITECSR(s->sbm_framecfg, framecfg); 1475 SBMAC_WRITECSR(s->sbm_maccfg, cfg); 1476 1477 return 1; 1478 1479 } 1480 1481 /* ********************************************************************* 1482 * SBMAC_SET_DUPLEX(s, duplex, fc) 1483 * 1484 * Set Ethernet duplex and flow control options for this MAC 1485 * Warning: must be called when MAC is off! 1486 * 1487 * Input parameters: 1488 * s - sbmac structure 1489 * duplex - duplex setting (see sbmac_duplex_t) 1490 * fc - flow control setting (see sbmac_fc_t) 1491 * 1492 * Return value: 1493 * 1 if ok 1494 * 0 if an invalid parameter combination was specified 1495 ********************************************************************* */ 1496 1497 static int sbmac_set_duplex(struct sbmac_softc *s, sbmac_duplex_t duplex, sbmac_fc_t fc) 1498 { 1499 uint64_t cfg; 1500 1501 /* 1502 * Save new current values 1503 */ 1504 1505 s->sbm_duplex = duplex; 1506 s->sbm_fc = fc; 1507 1508 if (s->sbm_state != sbmac_state_off) 1509 panic("sbmac_set_duplex while MAC not off"); 1510 1511 /* 1512 * Read current register values 1513 */ 1514 1515 cfg = SBMAC_READCSR(s->sbm_maccfg); 1516 1517 /* 1518 * Mask off the stuff we're about to change 1519 */ 1520 1521 cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN); 1522 1523 1524 switch (duplex) { 1525 case sbmac_duplex_half: 1526 switch (fc) { 1527 case sbmac_fc_disabled: 1528 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED; 1529 break; 1530 1531 case sbmac_fc_collision: 1532 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED; 1533 break; 1534 1535 case sbmac_fc_carrier: 1536 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR; 1537 break; 1538 1539 case sbmac_fc_auto: /* XXX not implemented */ 1540 /* fall through */ 1541 case sbmac_fc_frame: /* not valid in half duplex */ 1542 default: /* invalid selection */ 1543 panic("%s: invalid half duplex fc selection %d\n", 1544 s->sc_dev.dv_xname, fc); 1545 return 0; 1546 } 1547 break; 1548 1549 case sbmac_duplex_full: 1550 switch (fc) { 1551 case sbmac_fc_disabled: 1552 cfg |= V_MAC_FC_CMD_DISABLED; 1553 break; 1554 1555 case sbmac_fc_frame: 1556 cfg |= V_MAC_FC_CMD_ENABLED; 1557 break; 1558 1559 case sbmac_fc_collision: /* not valid in full duplex */ 1560 case sbmac_fc_carrier: /* not valid in full duplex */ 1561 case sbmac_fc_auto: /* XXX not implemented */ 1562 /* fall through */ 1563 default: 1564 panic("%s: invalid full duplex fc selection %d\n", 1565 s->sc_dev.dv_xname, fc); 1566 return 0; 1567 } 1568 break; 1569 1570 default: 1571 /* fall through */ 1572 case sbmac_duplex_auto: 1573 panic("%s: bad duplex %d\n", s->sc_dev.dv_xname, duplex); 1574 /* XXX not implemented */ 1575 break; 1576 } 1577 1578 /* 1579 * Send the bits back to the hardware 1580 */ 1581 1582 SBMAC_WRITECSR(s->sbm_maccfg, cfg); 1583 1584 return 1; 1585 } 1586 1587 1588 1589 1590 /* ********************************************************************* 1591 * SBMAC_INTR() 1592 * 1593 * Interrupt handler for MAC interrupts 1594 * 1595 * Input parameters: 1596 * MAC structure 1597 * 1598 * Return value: 1599 * nothing 1600 ********************************************************************* */ 1601 /* ARGSUSED */ 1602 static void 1603 sbmac_intr(void *xsc, uint32_t status, uint32_t pc) 1604 { 1605 struct sbmac_softc *sc = (struct sbmac_softc *) xsc; 1606 uint64_t isr; 1607 1608 for (;;) { 1609 1610 /* 1611 * Read the ISR (this clears the bits in the real register) 1612 */ 1613 1614 isr = SBMAC_READCSR(sc->sbm_isr); 1615 1616 if (isr == 0) 1617 break; 1618 1619 /* 1620 * Transmits on channel 0 1621 */ 1622 1623 if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) 1624 sbdma_tx_process(sc, &(sc->sbm_txdma)); 1625 1626 /* 1627 * Receives on channel 0 1628 */ 1629 1630 if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) 1631 sbdma_rx_process(sc, &(sc->sbm_rxdma)); 1632 } 1633 } 1634 1635 1636 /* ********************************************************************* 1637 * SBMAC_START(ifp) 1638 * 1639 * Start output on the specified interface. Basically, we 1640 * queue as many buffers as we can until the ring fills up, or 1641 * we run off the end of the queue, whichever comes first. 1642 * 1643 * Input parameters: 1644 * ifp - interface 1645 * 1646 * Return value: 1647 * nothing 1648 ********************************************************************* */ 1649 static void sbmac_start(struct ifnet *ifp) 1650 { 1651 struct sbmac_softc *sc; 1652 struct mbuf *m_head = NULL; 1653 int rv; 1654 1655 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1656 return; 1657 1658 sc = ifp->if_softc; 1659 1660 for (;;) { 1661 1662 IF_DEQUEUE(&ifp->if_snd, m_head); 1663 if (m_head == NULL) break; 1664 1665 /* 1666 * Put the buffer on the transmit ring. If we 1667 * don't have room, set the OACTIVE flag and wait 1668 * for the NIC to drain the ring. 1669 */ 1670 1671 rv = sbdma_add_txbuffer(&(sc->sbm_txdma), m_head); 1672 1673 if (rv == 0) { 1674 /* 1675 * If there's a BPF listener, bounce a copy of this frame 1676 * to it. 1677 */ 1678 #if (NBPFILTER > 0) 1679 if (ifp->if_bpf) { 1680 bpf_mtap(ifp->if_bpf, m_head); 1681 } 1682 #endif 1683 m_freem(m_head); 1684 } else { 1685 IF_PREPEND(&ifp->if_snd, m_head); 1686 ifp->if_flags |= IFF_OACTIVE; 1687 break; 1688 } 1689 } 1690 } 1691 1692 /* ********************************************************************* 1693 * SBMAC_SETMULTI(sc) 1694 * 1695 * Reprogram the multicast table into the hardware, given 1696 * the list of multicasts associated with the interface 1697 * structure. 1698 * 1699 * Input parameters: 1700 * sc - softc 1701 * 1702 * Return value: 1703 * nothing 1704 ********************************************************************* */ 1705 1706 static void sbmac_setmulti(struct sbmac_softc *sc) 1707 { 1708 struct ifnet *ifp; 1709 uint64_t reg; 1710 sbmac_port_t port; 1711 int idx; 1712 struct ether_multi *enm; 1713 struct ether_multistep step; 1714 1715 ifp = &sc->sc_ethercom.ec_if; 1716 1717 /* 1718 * Clear out entire multicast table. We do this by nuking 1719 * the entire hash table and all the direct matches except 1720 * the first one, which is used for our station address 1721 */ 1722 1723 for (idx = 1; idx < MAC_ADDR_COUNT; idx++) { 1724 port = PKSEG1(sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t))); 1725 SBMAC_WRITECSR(port, 0); 1726 } 1727 1728 for (idx = 0; idx < MAC_HASH_COUNT; idx++) { 1729 port = PKSEG1(sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t))); 1730 SBMAC_WRITECSR(port, 0); 1731 } 1732 1733 /* 1734 * Clear the filter to say we don't want any multicasts. 1735 */ 1736 1737 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1738 reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN); 1739 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1740 1741 if (ifp->if_flags & IFF_ALLMULTI) { 1742 /* 1743 * Enable ALL multicasts. Do this by inverting the 1744 * multicast enable bit. 1745 */ 1746 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1747 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN); 1748 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1749 return; 1750 } 1751 1752 /* 1753 * Progam new multicast entries. For now, only use the 1754 * perfect filter. In the future we'll need to use the 1755 * hash filter if the perfect filter overflows 1756 */ 1757 1758 /* XXX only using perfect filter for now, need to use hash 1759 * XXX if the table overflows */ 1760 1761 idx = 1; /* skip station address */ 1762 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1763 while ((enm != NULL) && (idx < MAC_ADDR_COUNT)) { 1764 reg = sbmac_addr2reg(enm->enm_addrlo); 1765 port = PKSEG1(sc->sbm_base + 1766 R_MAC_ADDR_BASE+(idx*sizeof(uint64_t))); 1767 SBMAC_WRITECSR(port, reg); 1768 idx++; 1769 ETHER_NEXT_MULTI(step, enm); 1770 } 1771 1772 /* 1773 * Enable the "accept multicast bits" if we programmed at least one 1774 * multicast. 1775 */ 1776 1777 if (idx > 1) { 1778 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1779 reg |= M_MAC_MCAST_EN; 1780 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1781 } 1782 } 1783 1784 1785 /* ********************************************************************* 1786 * SBMAC_ETHER_IOCTL(ifp, cmd, data) 1787 * 1788 * Generic IOCTL requests for this interface. The basic 1789 * stuff is handled here for bringing the interface up, 1790 * handling multicasts, etc. 1791 * 1792 * Input parameters: 1793 * ifp - interface structure 1794 * cmd - command code 1795 * data - pointer to data 1796 * 1797 * Return value: 1798 * return value (0 is success) 1799 ********************************************************************* */ 1800 1801 static int sbmac_ether_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1802 { 1803 struct ifaddr *ifa = (struct ifaddr *) data; 1804 struct sbmac_softc *sc = ifp->if_softc; 1805 1806 switch (cmd) { 1807 case SIOCSIFADDR: 1808 ifp->if_flags |= IFF_UP; 1809 1810 switch (ifa->ifa_addr->sa_family) { 1811 #ifdef INET 1812 case AF_INET: 1813 sbmac_init_and_start(sc); 1814 arp_ifinit(ifp, ifa); 1815 break; 1816 #endif 1817 #ifdef NS 1818 case AF_NS: 1819 { 1820 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1821 1822 if (ns_nullhost(*ina)) 1823 ina->x_host = *(union ns_host *) 1824 LLADDR(ifp->if_sadl); 1825 else 1826 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1827 ifp->if_addrlen); 1828 /* Set new address. */ 1829 sbmac_init_and_start(sc); 1830 break; 1831 } 1832 #endif 1833 default: 1834 sbmac_init_and_start(sc); 1835 break; 1836 } 1837 break; 1838 1839 default: 1840 return (EINVAL); 1841 } 1842 1843 return (0); 1844 } 1845 1846 1847 /* ********************************************************************* 1848 * SBMAC_IOCTL(ifp, command, data) 1849 * 1850 * Main IOCTL handler - dispatches to other IOCTLs for various 1851 * types of requests. 1852 * 1853 * Input parameters: 1854 * ifp - interface pointer 1855 * command - command code 1856 * data - pointer to argument data 1857 * 1858 * Return value: 1859 * 0 if ok 1860 * else error code 1861 ********************************************************************* */ 1862 1863 static int sbmac_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1864 { 1865 struct sbmac_softc *sc = ifp->if_softc; 1866 struct ifreq *ifr = (struct ifreq *) data; 1867 int s, error = 0; 1868 1869 s = splnet(); 1870 1871 switch(command) { 1872 case SIOCSIFADDR: 1873 case SIOCGIFADDR: 1874 error = sbmac_ether_ioctl(ifp, command, data); 1875 break; 1876 case SIOCSIFMTU: 1877 if (ifr->ifr_mtu > 1518) /* XXX */ 1878 error = EINVAL; 1879 else { 1880 ifp->if_mtu = ifr->ifr_mtu; 1881 /* XXX Program new MTU here */ 1882 } 1883 break; 1884 case SIOCSIFFLAGS: 1885 if (ifp->if_flags & IFF_UP) { 1886 /* 1887 * If only the state of the PROMISC flag changed, 1888 * just tweak the hardware registers. 1889 */ 1890 if ((ifp->if_flags & IFF_RUNNING) && 1891 (ifp->if_flags & IFF_PROMISC)) { 1892 /* turn on promiscuous mode */ 1893 sbmac_promiscuous_mode(sc, 1); 1894 } 1895 else if (ifp->if_flags & IFF_RUNNING && 1896 !(ifp->if_flags & IFF_PROMISC)) { 1897 /* turn off promiscuous mode */ 1898 sbmac_promiscuous_mode(sc, 0); 1899 } 1900 else { 1901 sbmac_set_channel_state(sc, sbmac_state_on); 1902 } 1903 } 1904 else { 1905 if (ifp->if_flags & IFF_RUNNING) { 1906 sbmac_set_channel_state(sc, sbmac_state_off); 1907 } 1908 } 1909 1910 sc->sbm_if_flags = ifp->if_flags; 1911 error = 0; 1912 break; 1913 1914 case SIOCADDMULTI: 1915 case SIOCDELMULTI: 1916 if (ifp->if_flags & IFF_RUNNING) { 1917 sbmac_setmulti(sc); 1918 error = 0; 1919 } 1920 break; 1921 case SIOCSIFMEDIA: 1922 case SIOCGIFMEDIA: 1923 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1924 break; 1925 default: 1926 error = EINVAL; 1927 break; 1928 } 1929 1930 (void)splx(s); 1931 1932 return(error); 1933 } 1934 1935 1936 /* ********************************************************************* 1937 * SBMAC_IFMEDIA_UPD(ifp) 1938 * 1939 * Configure an appropriate media type for this interface, 1940 * given the data in the interface structure 1941 * 1942 * Input parameters: 1943 * ifp - interface 1944 * 1945 * Return value: 1946 * 0 if ok 1947 * else error code 1948 ********************************************************************* */ 1949 1950 static int sbmac_mediachange(struct ifnet *ifp) 1951 { 1952 struct sbmac_softc *sc = ifp->if_softc; 1953 1954 if (ifp->if_flags & IFF_UP) 1955 mii_mediachg(&sc->sc_mii); 1956 return(0); 1957 } 1958 1959 /* ********************************************************************* 1960 * SBMAC_IFMEDIA_STS(ifp, ifmr) 1961 * 1962 * Report current media status (used by ifconfig, for example) 1963 * 1964 * Input parameters: 1965 * ifp - interface structure 1966 * ifmr - media request structure 1967 * 1968 * Return value: 1969 * nothing 1970 ********************************************************************* */ 1971 1972 static void sbmac_mediastatus(struct ifnet *ifp, struct ifmediareq *req) 1973 { 1974 struct sbmac_softc *sc = ifp->if_softc; 1975 1976 mii_pollstat(&sc->sc_mii); 1977 req->ifm_status = sc->sc_mii.mii_media_status; 1978 req->ifm_active = sc->sc_mii.mii_media_active; 1979 } 1980 1981 1982 /* ********************************************************************* 1983 * SBMAC_WATCHDOG(ifp) 1984 * 1985 * Called periodically to make sure we're still happy. 1986 * 1987 * Input parameters: 1988 * ifp - interface structure 1989 * 1990 * Return value: 1991 * nothing 1992 ********************************************************************* */ 1993 1994 static void sbmac_watchdog(struct ifnet *ifp) 1995 { 1996 /* XXX do something */ 1997 } 1998 1999 /* 2000 * One second timer, used to tick MII. 2001 */ 2002 static void sbmac_tick(void *arg) 2003 { 2004 struct sbmac_softc *sc = arg; 2005 int s; 2006 2007 s = splnet(); 2008 mii_tick(&sc->sc_mii); 2009 splx(s); 2010 2011 callout_reset(&sc->sc_tick_ch, hz, sbmac_tick, sc); 2012 } 2013 2014 2015 /* ********************************************************************* 2016 * SBMAC_MATCH(parent, match, aux) 2017 * 2018 * Part of the config process - see if this device matches the 2019 * info about what we expect to find on the bus. 2020 * 2021 * Input parameters: 2022 * parent - parent bus structure 2023 * match - 2024 * aux - bus-specific args 2025 * 2026 * Return value: 2027 * 1 if we match 2028 * 0 if we don't match 2029 ********************************************************************* */ 2030 2031 static int sbmac_match(struct device *parent, struct cfdata *match, void *aux) 2032 { 2033 struct sbobio_attach_args *sap = aux; 2034 2035 /* 2036 * Make sure it's a MAC 2037 */ 2038 2039 if (sap->sa_locs.sa_type != SBOBIO_DEVTYPE_MAC) { 2040 return 0; 2041 } 2042 2043 /* 2044 * Yup, it is. 2045 */ 2046 2047 return 1; 2048 } 2049 2050 2051 /* ********************************************************************* 2052 * SBMAC_PARSE_XDIGIT(str) 2053 * 2054 * Parse a hex digit, returning its value 2055 * 2056 * Input parameters: 2057 * str - character 2058 * 2059 * Return value: 2060 * hex value, or -1 if invalid 2061 ********************************************************************* */ 2062 2063 static int sbmac_parse_xdigit(char str) 2064 { 2065 int digit; 2066 2067 if ((str >= '0') && (str <= '9')) digit = str - '0'; 2068 else if ((str >= 'a') && (str <= 'f')) digit = str - 'a' + 10; 2069 else if ((str >= 'A') && (str <= 'F')) digit = str - 'A' + 10; 2070 else return -1; 2071 2072 return digit; 2073 } 2074 2075 /* ********************************************************************* 2076 * SBMAC_PARSE_HWADDR(str, hwaddr) 2077 * 2078 * Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte 2079 * Ethernet address. 2080 * 2081 * Input parameters: 2082 * str - string 2083 * hwaddr - pointer to hardware address 2084 * 2085 * Return value: 2086 * 0 if ok, else -1 2087 ********************************************************************* */ 2088 2089 static int sbmac_parse_hwaddr(char *str, u_char *hwaddr) 2090 { 2091 int digit1, digit2; 2092 int idx = 6; 2093 2094 while (*str && (idx > 0)) { 2095 digit1 = sbmac_parse_xdigit(*str); 2096 if (digit1 < 0) return -1; 2097 str++; 2098 if (!*str) return -1; 2099 2100 if ((*str == ':') || (*str == '-')) { 2101 digit2 = digit1; 2102 digit1 = 0; 2103 } 2104 else { 2105 digit2 = sbmac_parse_xdigit(*str); 2106 if (digit2 < 0) return -1; 2107 str++; 2108 } 2109 2110 *hwaddr++ = (digit1 << 4) | digit2; 2111 idx--; 2112 2113 if (*str == '-') str++; 2114 if (*str == ':') str++; 2115 } 2116 return 0; 2117 } 2118 2119 /* ********************************************************************* 2120 * SBMAC_ATTACH(parent, self, aux) 2121 * 2122 * Attach routine - init hardware and hook ourselves into NetBSD. 2123 * 2124 * Input parameters: 2125 * parent - parent bus device 2126 * self - our softc 2127 * aux - attach data 2128 * 2129 * Return value: 2130 * nothing 2131 ********************************************************************* */ 2132 2133 static void sbmac_attach(struct device *parent, struct device *self, void *aux) 2134 { 2135 struct ifnet *ifp; 2136 struct sbmac_softc *sc; 2137 struct sbobio_attach_args *sap = aux; 2138 u_char *eaddr; 2139 static int unit = 0; /* XXX */ 2140 uint64_t ea_reg; 2141 int idx; 2142 2143 sc = (struct sbmac_softc *)self; 2144 2145 /* Determine controller base address */ 2146 2147 sc->sbm_base = (sbmac_port_t) sap->sa_base + sap->sa_locs.sa_offset; 2148 2149 eaddr = sc->sbm_hwaddr; 2150 2151 /* 2152 * Initialize context (get pointers to registers and stuff), then 2153 * allocate the memory for the descriptor tables. 2154 */ 2155 2156 sbmac_initctx(sc); 2157 2158 callout_init(&(sc->sc_tick_ch)); 2159 2160 /* 2161 * Read the ethernet address. The firwmare left this programmed 2162 * for us in the ethernet address register for each mac. 2163 */ 2164 2165 ea_reg = SBMAC_READCSR(PKSEG1(sc->sbm_base + R_MAC_ETHERNET_ADDR)); 2166 for (idx = 0; idx < 6; idx++) { 2167 eaddr[idx] = (uint8_t) (ea_reg & 0xFF); 2168 ea_reg >>= 8; 2169 } 2170 2171 #define SBMAC_DEFAULT_HWADDR "40:00:00:00:01:00" 2172 if (eaddr[0] == 0 && eaddr[1] == 0 && eaddr[2] == 0 && 2173 eaddr[3] == 0 && eaddr[4] == 0 && eaddr[5] == 0) { 2174 sbmac_parse_hwaddr(SBMAC_DEFAULT_HWADDR, eaddr); 2175 eaddr[5] = unit; 2176 } 2177 2178 #ifdef SBMAC_ETH0_HWADDR 2179 if (unit == 0) sbmac_parse_hwaddr(SBMAC_ETH0_HWADDR, eaddr); 2180 #endif 2181 #ifdef SBMAC_ETH1_HWADDR 2182 if (unit == 1) sbmac_parse_hwaddr(SBMAC_ETH1_HWADDR, eaddr); 2183 #endif 2184 #ifdef SBMAC_ETH2_HWADDR 2185 if (unit == 2) sbmac_parse_hwaddr(SBMAC_ETH2_HWADDR, eaddr); 2186 #endif 2187 unit++; 2188 2189 /* 2190 * Display Ethernet address (this is called during the config process 2191 * so we need to finish off the config message that was being displayed) 2192 */ 2193 printf(": Ethernet\n%s: Ethernet address: %s\n", self->dv_xname, 2194 ether_sprintf(eaddr)); 2195 2196 2197 /* 2198 * Set up ifnet structure 2199 */ 2200 2201 ifp = &sc->sc_ethercom.ec_if; 2202 ifp->if_softc = sc; 2203 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 2204 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | IFF_NOTRAILERS; 2205 ifp->if_ioctl = sbmac_ioctl; 2206 ifp->if_start = sbmac_start; 2207 ifp->if_watchdog = sbmac_watchdog; 2208 ifp->if_snd.ifq_maxlen = SBMAC_MAX_TXDESCR - 1; 2209 2210 /* 2211 * Set up ifmedia support. 2212 */ 2213 2214 /* 2215 * Initialize MII/media info. 2216 */ 2217 sc->sc_mii.mii_ifp = ifp; 2218 sc->sc_mii.mii_readreg = sbmac_mii_readreg; 2219 sc->sc_mii.mii_writereg = sbmac_mii_writereg; 2220 sc->sc_mii.mii_statchg = sbmac_mii_statchg; 2221 ifmedia_init(&sc->sc_mii.mii_media, 0, sbmac_mediachange, 2222 sbmac_mediastatus); 2223 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 2224 MII_OFFSET_ANY, 0); 2225 2226 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 2227 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 2228 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 2229 } 2230 else { 2231 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2232 } 2233 2234 2235 /* 2236 * map/route interrupt 2237 */ 2238 2239 sc->sbm_intrhand = cpu_intr_establish(sap->sa_locs.sa_intr[0], 2240 IPL_NET, sbmac_intr, sc); 2241 2242 /* 2243 * Call MI attach routines. 2244 */ 2245 if_attach(ifp); 2246 ether_ifattach(ifp, eaddr); 2247 } 2248
Indexes created Sat Sep 27 14:09:57 GMT 2025