sbmac.c revision 1.11
1 /* $NetBSD: sbmac.c,v 1.11 2003/09/26 13:34:56 simonb Exp $ */ 2 3 /* 4 * Copyright 2000, 2001 5 * Broadcom Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and copied only 8 * in accordance with the following terms and conditions. Subject to these 9 * conditions, you may download, copy, install, use, modify and distribute 10 * modified or unmodified copies of this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce and 14 * retain this copyright notice and list of conditions as they appear in 15 * the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Broadcom Corporation. The "Broadcom Corporation" name may not be 19 * used to endorse or promote products derived from this software 20 * without the prior written permission of Broadcom Corporation. 21 * 22 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR 25 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE 26 * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE 27 * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 32 * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: sbmac.c,v 1.11 2003/09/26 13:34:56 simonb Exp $"); 37 38 #include "bpfilter.h" 39 #include "opt_inet.h" 40 #include "opt_ns.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/queue.h> 50 #include <sys/device.h> 51 52 #include <net/if.h> 53 #include <net/if_arp.h> 54 #include <net/if_ether.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 58 #if NBPFILTER > 0 59 #include <net/bpf.h> 60 #endif 61 62 #ifdef INET 63 #include <netinet/in.h> 64 #include <netinet/if_inarp.h> 65 #endif 66 67 #ifdef NS 68 #include <netns/ns.h> 69 #include <netns/ns_if.h> 70 #endif 71 72 #include <machine/locore.h> 73 74 #include "sbobiovar.h" 75 76 #include <dev/mii/mii.h> 77 #include <dev/mii/miivar.h> 78 #include <dev/mii/mii_bitbang.h> 79 80 #include <mips/sibyte/include/sb1250_defs.h> 81 #include <mips/sibyte/include/sb1250_regs.h> 82 #include <mips/sibyte/include/sb1250_mac.h> 83 #include <mips/sibyte/include/sb1250_dma.h> 84 #include <mips/sibyte/include/sb1250_scd.h> 85 86 87 /* Simple types */ 88 89 typedef u_long sbmac_port_t; 90 typedef uint64_t sbmac_physaddr_t; 91 typedef uint64_t sbmac_enetaddr_t; 92 93 typedef enum { sbmac_speed_auto, sbmac_speed_10, 94 sbmac_speed_100, sbmac_speed_1000 } sbmac_speed_t; 95 96 typedef enum { sbmac_duplex_auto, sbmac_duplex_half, 97 sbmac_duplex_full } sbmac_duplex_t; 98 99 typedef enum { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame, 100 sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t; 101 102 typedef enum { sbmac_state_uninit, sbmac_state_off, sbmac_state_on, 103 sbmac_state_broken } sbmac_state_t; 104 105 106 /* Macros */ 107 108 #define SBDMA_NEXTBUF(d, f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \ 109 (d)->sbdma_dscrtable : (d)->f+1) 110 111 112 #define CACHELINESIZE 32 113 #define NUMCACHEBLKS(x) (((x)+CACHELINESIZE-1)/CACHELINESIZE) 114 #define KMALLOC(x) malloc((x), M_DEVBUF, M_DONTWAIT) 115 #define KVTOPHYS(x) kvtophys((vaddr_t)(x)) 116 117 #ifdef SBMACDEBUG 118 #define dprintf(x) printf x 119 #else 120 #define dprintf(x) 121 #endif 122 123 #define SBMAC_READCSR(t) mips3_ld((uint64_t *) (t)) 124 #define SBMAC_WRITECSR(t, v) mips3_sd((uint64_t *) (t), (v)) 125 126 #define PKSEG1(x) ((sbmac_port_t) MIPS_PHYS_TO_KSEG1(x)) 127 128 #define SBMAC_MAX_TXDESCR 64 129 #define SBMAC_MAX_RXDESCR 64 130 131 #define ETHER_ALIGN 2 132 133 /* DMA Descriptor structure */ 134 135 typedef struct sbdmadscr_s { 136 uint64_t dscr_a; 137 uint64_t dscr_b; 138 } sbdmadscr_t; 139 140 141 /* DMA Controller structure */ 142 143 typedef struct sbmacdma_s { 144 145 /* 146 * This stuff is used to identify the channel and the registers 147 * associated with it. 148 */ 149 150 struct sbmac_softc *sbdma_eth; /* back pointer to associated MAC */ 151 int sbdma_channel; /* channel number */ 152 int sbdma_txdir; /* direction (1=transmit) */ 153 int sbdma_maxdescr; /* total # of descriptors in ring */ 154 sbmac_port_t sbdma_config0; /* DMA config register 0 */ 155 sbmac_port_t sbdma_config1; /* DMA config register 1 */ 156 sbmac_port_t sbdma_dscrbase; /* Descriptor base address */ 157 sbmac_port_t sbdma_dscrcnt; /* Descriptor count register */ 158 sbmac_port_t sbdma_curdscr; /* current descriptor address */ 159 160 /* 161 * This stuff is for maintenance of the ring 162 */ 163 164 sbdmadscr_t *sbdma_dscrtable; /* base of descriptor table */ 165 sbdmadscr_t *sbdma_dscrtable_end; /* end of descriptor table */ 166 167 struct mbuf **sbdma_ctxtable; /* context table, one per descr */ 168 169 paddr_t sbdma_dscrtable_phys; /* and also the phys addr */ 170 sbdmadscr_t *sbdma_addptr; /* next dscr for sw to add */ 171 sbdmadscr_t *sbdma_remptr; /* next dscr for sw to remove */ 172 } sbmacdma_t; 173 174 175 /* Ethernet softc structure */ 176 177 struct sbmac_softc { 178 179 /* 180 * NetBSD-specific things 181 */ 182 struct device sc_dev; /* base device (must be first) */ 183 struct ethercom sc_ethercom; /* Ethernet common part */ 184 struct mii_data sc_mii; 185 struct callout sc_tick_ch; 186 187 int sbm_if_flags; 188 void *sbm_intrhand; 189 190 /* 191 * Controller-specific things 192 */ 193 194 sbmac_port_t sbm_base; /* MAC's base address */ 195 sbmac_state_t sbm_state; /* current state */ 196 197 sbmac_port_t sbm_macenable; /* MAC Enable Register */ 198 sbmac_port_t sbm_maccfg; /* MAC Configuration Register */ 199 sbmac_port_t sbm_fifocfg; /* FIFO configuration register */ 200 sbmac_port_t sbm_framecfg; /* Frame configuration register */ 201 sbmac_port_t sbm_rxfilter; /* receive filter register */ 202 sbmac_port_t sbm_isr; /* Interrupt status register */ 203 sbmac_port_t sbm_imr; /* Interrupt mask register */ 204 205 sbmac_speed_t sbm_speed; /* current speed */ 206 sbmac_duplex_t sbm_duplex; /* current duplex */ 207 sbmac_fc_t sbm_fc; /* current flow control setting */ 208 int sbm_rxflags; /* received packet flags */ 209 210 u_char sbm_hwaddr[ETHER_ADDR_LEN]; 211 212 sbmacdma_t sbm_txdma; /* for now, only use channel 0 */ 213 sbmacdma_t sbm_rxdma; 214 215 int sbm_pass3_dma; /* chip has pass3 SOC DMA features */ 216 }; 217 218 219 /* Externs */ 220 221 extern paddr_t kvtophys(vaddr_t); 222 223 /* Prototypes */ 224 225 static void sbdma_initctx(sbmacdma_t *d, struct sbmac_softc *s, int chan, 226 int txrx, int maxdescr); 227 static void sbdma_channel_start(sbmacdma_t *d); 228 static int sbdma_add_rcvbuffer(sbmacdma_t *d, struct mbuf *m); 229 static int sbdma_add_txbuffer(sbmacdma_t *d, struct mbuf *m); 230 static void sbdma_emptyring(sbmacdma_t *d); 231 static void sbdma_fillring(sbmacdma_t *d); 232 static void sbdma_rx_process(struct sbmac_softc *sc, sbmacdma_t *d); 233 static void sbdma_tx_process(struct sbmac_softc *sc, sbmacdma_t *d); 234 static void sbmac_initctx(struct sbmac_softc *s); 235 static void sbmac_channel_start(struct sbmac_softc *s); 236 static void sbmac_channel_stop(struct sbmac_softc *s); 237 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *, 238 sbmac_state_t); 239 static void sbmac_promiscuous_mode(struct sbmac_softc *sc, int onoff); 240 static void sbmac_init_and_start(struct sbmac_softc *sc); 241 static uint64_t sbmac_addr2reg(u_char *ptr); 242 static void sbmac_intr(void *xsc, uint32_t status, uint32_t pc); 243 static void sbmac_start(struct ifnet *ifp); 244 static void sbmac_setmulti(struct sbmac_softc *sc); 245 static int sbmac_ether_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 246 static int sbmac_ioctl(struct ifnet *ifp, u_long command, caddr_t data); 247 static int sbmac_mediachange(struct ifnet *ifp); 248 static void sbmac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr); 249 static void sbmac_watchdog(struct ifnet *ifp); 250 static int sbmac_match(struct device *parent, struct cfdata *match, void *aux); 251 static void sbmac_attach(struct device *parent, struct device *self, void *aux); 252 static int sbmac_set_speed(struct sbmac_softc *s, sbmac_speed_t speed); 253 static int sbmac_set_duplex(struct sbmac_softc *s, sbmac_duplex_t duplex, 254 sbmac_fc_t fc); 255 static void sbmac_tick(void *arg); 256 257 258 /* Globals */ 259 260 CFATTACH_DECL(sbmac, sizeof(struct sbmac_softc), 261 sbmac_match, sbmac_attach, NULL, NULL); 262 263 static uint32_t sbmac_mii_bitbang_read(struct device *self); 264 static void sbmac_mii_bitbang_write(struct device *self, uint32_t val); 265 266 static const struct mii_bitbang_ops sbmac_mii_bitbang_ops = { 267 sbmac_mii_bitbang_read, 268 sbmac_mii_bitbang_write, 269 { 270 (uint32_t)M_MAC_MDIO_OUT, /* MII_BIT_MDO */ 271 (uint32_t)M_MAC_MDIO_IN, /* MII_BIT_MDI */ 272 (uint32_t)M_MAC_MDC, /* MII_BIT_MDC */ 273 0, /* MII_BIT_DIR_HOST_PHY */ 274 (uint32_t)M_MAC_MDIO_DIR /* MII_BIT_DIR_PHY_HOST */ 275 } 276 }; 277 278 static uint32_t 279 sbmac_mii_bitbang_read(struct device *self) 280 { 281 struct sbmac_softc *sc = (void *) self; 282 sbmac_port_t reg; 283 284 reg = PKSEG1(sc->sbm_base + R_MAC_MDIO); 285 return (uint32_t) SBMAC_READCSR(reg); 286 } 287 288 static void 289 sbmac_mii_bitbang_write(struct device *self, uint32_t val) 290 { 291 struct sbmac_softc *sc = (void *) self; 292 sbmac_port_t reg; 293 294 reg = PKSEG1(sc->sbm_base + R_MAC_MDIO); 295 296 SBMAC_WRITECSR(reg, (val & 297 (M_MAC_MDC|M_MAC_MDIO_DIR|M_MAC_MDIO_OUT|M_MAC_MDIO_IN))); 298 } 299 300 /* 301 * Read an PHY register through the MII. 302 */ 303 static int 304 sbmac_mii_readreg(struct device *self, int phy, int reg) 305 { 306 307 return (mii_bitbang_readreg(self, &sbmac_mii_bitbang_ops, phy, reg)); 308 } 309 310 /* 311 * Write to a PHY register through the MII. 312 */ 313 static void 314 sbmac_mii_writereg(struct device *self, int phy, int reg, int val) 315 { 316 317 mii_bitbang_writereg(self, &sbmac_mii_bitbang_ops, phy, reg, val); 318 } 319 320 static void 321 sbmac_mii_statchg(struct device *self) 322 { 323 struct sbmac_softc *sc = (struct sbmac_softc *)self; 324 sbmac_state_t oldstate; 325 326 /* Stop the MAC in preparation for changing all of the parameters. */ 327 oldstate = sbmac_set_channel_state(sc, sbmac_state_off); 328 329 switch (sc->sc_ethercom.ec_if.if_baudrate) { 330 default: /* if autonegotiation fails, assume 10Mbit */ 331 case IF_Mbps(10): 332 sbmac_set_speed(sc, sbmac_speed_10); 333 break; 334 335 case IF_Mbps(100): 336 sbmac_set_speed(sc, sbmac_speed_100); 337 break; 338 339 case IF_Mbps(1000): 340 sbmac_set_speed(sc, sbmac_speed_1000); 341 break; 342 } 343 344 if (sc->sc_mii.mii_media_active & IFM_FDX) { 345 /* Configure for full-duplex */ 346 /* XXX: is flow control right for 10, 100? */ 347 sbmac_set_duplex(sc, sbmac_duplex_full, sbmac_fc_frame); 348 } else { 349 /* Configure for half-duplex */ 350 /* XXX: is flow control right? */ 351 sbmac_set_duplex(sc, sbmac_duplex_half, sbmac_fc_disabled); 352 } 353 354 /* And put it back into its former state. */ 355 sbmac_set_channel_state(sc, oldstate); 356 } 357 358 /* 359 * SBDMA_INITCTX(d, s, chan, txrx, maxdescr) 360 * 361 * Initialize a DMA channel context. Since there are potentially 362 * eight DMA channels per MAC, it's nice to do this in a standard 363 * way. 364 * 365 * Input parameters: 366 * d - sbmacdma_t structure (DMA channel context) 367 * s - sbmac_softc structure (pointer to a MAC) 368 * chan - channel number (0..1 right now) 369 * txrx - Identifies DMA_TX or DMA_RX for channel direction 370 * maxdescr - number of descriptors 371 * 372 * Return value: 373 * nothing 374 */ 375 376 static void 377 sbdma_initctx(sbmacdma_t *d, struct sbmac_softc *s, int chan, int txrx, 378 int maxdescr) 379 { 380 /* 381 * Save away interesting stuff in the structure 382 */ 383 384 d->sbdma_eth = s; 385 d->sbdma_channel = chan; 386 d->sbdma_txdir = txrx; 387 388 /* 389 * initialize register pointers 390 */ 391 392 d->sbdma_config0 = PKSEG1(s->sbm_base + 393 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_CONFIG0)); 394 d->sbdma_config1 = PKSEG1(s->sbm_base + 395 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_CONFIG1)); 396 d->sbdma_dscrbase = PKSEG1(s->sbm_base + 397 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_DSCR_BASE)); 398 d->sbdma_dscrcnt = PKSEG1(s->sbm_base + 399 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_DSCR_CNT)); 400 d->sbdma_curdscr = PKSEG1(s->sbm_base + 401 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_CUR_DSCRADDR)); 402 403 /* 404 * Allocate memory for the ring 405 */ 406 407 d->sbdma_maxdescr = maxdescr; 408 409 d->sbdma_dscrtable = (sbdmadscr_t *) 410 KMALLOC(d->sbdma_maxdescr*sizeof(sbdmadscr_t)); 411 412 bzero(d->sbdma_dscrtable, d->sbdma_maxdescr*sizeof(sbdmadscr_t)); 413 414 d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr; 415 416 d->sbdma_dscrtable_phys = KVTOPHYS(d->sbdma_dscrtable); 417 418 /* 419 * And context table 420 */ 421 422 d->sbdma_ctxtable = (struct mbuf **) 423 KMALLOC(d->sbdma_maxdescr*sizeof(struct mbuf *)); 424 425 bzero(d->sbdma_ctxtable, d->sbdma_maxdescr*sizeof(struct mbuf *)); 426 } 427 428 /* 429 * SBDMA_CHANNEL_START(d) 430 * 431 * Initialize the hardware registers for a DMA channel. 432 * 433 * Input parameters: 434 * d - DMA channel to init (context must be previously init'd 435 * 436 * Return value: 437 * nothing 438 */ 439 440 static void 441 sbdma_channel_start(sbmacdma_t *d) 442 { 443 /* 444 * Turn on the DMA channel 445 */ 446 447 SBMAC_WRITECSR(d->sbdma_config1, 0); 448 449 SBMAC_WRITECSR(d->sbdma_dscrbase, d->sbdma_dscrtable_phys); 450 451 SBMAC_WRITECSR(d->sbdma_config0, V_DMA_RINGSZ(d->sbdma_maxdescr) | 0); 452 453 /* 454 * Initialize ring pointers 455 */ 456 457 d->sbdma_addptr = d->sbdma_dscrtable; 458 d->sbdma_remptr = d->sbdma_dscrtable; 459 } 460 461 /* 462 * SBDMA_ADD_RCVBUFFER(d, m) 463 * 464 * Add a buffer to the specified DMA channel. For receive channels, 465 * this queues a buffer for inbound packets. 466 * 467 * Input parameters: 468 * d - DMA channel descriptor 469 * m - mbuf to add, or NULL if we should allocate one. 470 * 471 * Return value: 472 * 0 if buffer could not be added (ring is full) 473 * 1 if buffer added successfully 474 */ 475 476 static int 477 sbdma_add_rcvbuffer(sbmacdma_t *d, struct mbuf *m) 478 { 479 sbdmadscr_t *dsc; 480 sbdmadscr_t *nextdsc; 481 struct mbuf *m_new = NULL; 482 483 /* get pointer to our current place in the ring */ 484 485 dsc = d->sbdma_addptr; 486 nextdsc = SBDMA_NEXTBUF(d, sbdma_addptr); 487 488 /* 489 * figure out if the ring is full - if the next descriptor 490 * is the same as the one that we're going to remove from 491 * the ring, the ring is full 492 */ 493 494 if (nextdsc == d->sbdma_remptr) 495 return ENOSPC; 496 497 /* 498 * Allocate an mbuf if we don't already have one. 499 * If we do have an mbuf, reset it so that it's empty. 500 */ 501 502 if (m == NULL) { 503 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 504 if (m_new == NULL) { 505 printf("%s: mbuf allocation failed\n", 506 d->sbdma_eth->sc_dev.dv_xname); 507 return ENOBUFS; 508 } 509 510 MCLGET(m_new, M_DONTWAIT); 511 if (!(m_new->m_flags & M_EXT)) { 512 printf("%s: mbuf cluster allocation failed\n", 513 d->sbdma_eth->sc_dev.dv_xname); 514 m_freem(m_new); 515 return ENOBUFS; 516 } 517 518 m_new->m_len = m_new->m_pkthdr.len= MCLBYTES; 519 m_adj(m_new, ETHER_ALIGN); 520 } else { 521 m_new = m; 522 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 523 m_new->m_data = m_new->m_ext.ext_buf; 524 m_adj(m_new, ETHER_ALIGN); 525 } 526 527 /* 528 * fill in the descriptor 529 */ 530 531 dsc->dscr_a = KVTOPHYS(mtod(m_new, caddr_t)) | 532 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(ETHER_ALIGN + m_new->m_len)) | 533 M_DMA_DSCRA_INTERRUPT; 534 535 /* receiving: no options */ 536 dsc->dscr_b = 0; 537 538 /* 539 * fill in the context 540 */ 541 542 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = m_new; 543 544 /* 545 * point at next packet 546 */ 547 548 d->sbdma_addptr = nextdsc; 549 550 /* 551 * Give the buffer to the DMA engine. 552 */ 553 554 SBMAC_WRITECSR(d->sbdma_dscrcnt, 1); 555 556 return 0; /* we did it */ 557 } 558 559 /* 560 * SBDMA_ADD_TXBUFFER(d, m) 561 * 562 * Add a transmit buffer to the specified DMA channel, causing a 563 * transmit to start. 564 * 565 * Input parameters: 566 * d - DMA channel descriptor 567 * m - mbuf to add 568 * 569 * Return value: 570 * 0 transmit queued successfully 571 * otherwise error code 572 */ 573 574 static int 575 sbdma_add_txbuffer(sbmacdma_t *d, struct mbuf *m) 576 { 577 sbdmadscr_t *dsc; 578 sbdmadscr_t *nextdsc; 579 sbdmadscr_t *prevdsc; 580 sbdmadscr_t *origdesc; 581 int length; 582 int num_mbufs = 0; 583 struct sbmac_softc *sc = d->sbdma_eth; 584 585 /* get pointer to our current place in the ring */ 586 587 dsc = d->sbdma_addptr; 588 nextdsc = SBDMA_NEXTBUF(d, sbdma_addptr); 589 590 /* 591 * figure out if the ring is full - if the next descriptor 592 * is the same as the one that we're going to remove from 593 * the ring, the ring is full 594 */ 595 596 if (nextdsc == d->sbdma_remptr) 597 return ENOSPC; 598 599 #if 0 600 do { 601 struct mbuf *m0; 602 603 printf("mbuf chain: "); 604 for (m0 = m; m0 != 0; m0 = m0->m_next) { 605 printf("%d%c/%X ", m0->m_len, 606 m0->m_flags & M_EXT ? 'X' : 'N', 607 mtod(m0, u_int)); 608 } 609 printf("\n"); 610 } while (0); 611 #endif 612 613 /* 614 * PASS3 parts do not have buffer alignment restriction. 615 * No need to copy/coalesce to new mbuf. Also has different 616 * descriptor format 617 */ 618 if (sc->sbm_pass3_dma) { 619 struct mbuf *m_temp = NULL; 620 621 /* 622 * Loop thru this mbuf record. 623 * The head mbuf will have SOP set. 624 */ 625 dsc->dscr_a = KVTOPHYS(mtod(m,caddr_t)) | 626 M_DMA_DSCRA_INTERRUPT | 627 M_DMA_ETHTX_SOP; 628 629 /* 630 * transmitting: set outbound options,buffer A size(+ low 5 631 * bits of start addr),and packet length. 632 */ 633 dsc->dscr_b = 634 V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) | 635 V_DMA_DSCRB_A_SIZE((m->m_len + (mtod(m,unsigned int) & 0x0000001F))) | 636 V_DMA_DSCRB_PKT_SIZE_MSB( (m->m_pkthdr.len & 0xB000) ) | 637 V_DMA_DSCRB_PKT_SIZE(m->m_pkthdr.len); 638 639 d->sbdma_addptr = nextdsc; 640 origdesc = prevdsc = dsc; 641 dsc = d->sbdma_addptr; 642 num_mbufs++; 643 644 /* Start with first non-head mbuf */ 645 for(m_temp = m->m_next; m_temp != 0; m_temp = m_temp->m_next) { 646 647 if (m_temp->m_len == 0) 648 continue; /* Skip 0-length mbufs */ 649 650 /* 651 * fill in the descriptor 652 */ 653 654 dsc->dscr_a = KVTOPHYS(mtod(m_temp,caddr_t)) | 655 M_DMA_DSCRA_INTERRUPT; 656 657 /* transmitting: set outbound options,buffer A size(+ low 5 bits of start addr) */ 658 dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_NOTSOP) | 659 V_DMA_DSCRB_A_SIZE( (m_temp->m_len + (mtod(m_temp,unsigned int) & 0x0000001F)) ); 660 661 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = NULL; 662 663 /* 664 * point at next descriptor 665 */ 666 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr); 667 if (nextdsc == d->sbdma_remptr) { 668 d->sbdma_addptr = origdesc; 669 return ENOSPC; 670 } 671 d->sbdma_addptr = nextdsc; 672 673 prevdsc = dsc; 674 dsc = d->sbdma_addptr; 675 num_mbufs++; 676 } 677 678 /*Set head mbuf to last context index*/ 679 d->sbdma_ctxtable[prevdsc-d->sbdma_dscrtable] = m; 680 } else { 681 struct mbuf *m_new = NULL; 682 /* 683 * [BEGIN XXX] 684 * XXX Copy/coalesce the mbufs into a single mbuf cluster (we assume 685 * it will fit). This is a temporary hack to get us going. 686 */ 687 688 MGETHDR(m_new,M_DONTWAIT,MT_DATA); 689 if (m_new == NULL) { 690 printf("%s: mbuf allocation failed\n", 691 d->sbdma_eth->sc_dev.dv_xname); 692 return ENOBUFS; 693 } 694 695 MCLGET(m_new,M_DONTWAIT); 696 if (!(m_new->m_flags & M_EXT)) { 697 printf("%s: mbuf cluster allocation failed\n", 698 d->sbdma_eth->sc_dev.dv_xname); 699 m_freem(m_new); 700 return ENOBUFS; 701 } 702 703 m_new->m_len = m_new->m_pkthdr.len= MCLBYTES; 704 /*m_adj(m_new,ETHER_ALIGN);*/ 705 706 /* 707 * XXX Don't forget to include the offset portion in the 708 * XXX cache block calculation when this code is rewritten! 709 */ 710 711 /* 712 * Copy data 713 */ 714 715 m_copydata(m,0,m->m_pkthdr.len,mtod(m_new,caddr_t)); 716 m_new->m_len = m_new->m_pkthdr.len = m->m_pkthdr.len; 717 718 /* Free old mbuf 'm', actual mbuf is now 'm_new' */ 719 720 // XXX: CALLERS WILL FREE, they might have to bpf_mtap() if this 721 // XXX: function succeeds. 722 // m_freem(m); 723 length = m_new->m_len; 724 725 /* [END XXX] */ 726 /* 727 * fill in the descriptor 728 */ 729 730 dsc->dscr_a = KVTOPHYS(mtod(m_new,caddr_t)) | 731 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(m_new->m_len)) | 732 M_DMA_DSCRA_INTERRUPT | 733 M_DMA_ETHTX_SOP; 734 735 /* transmitting: set outbound options and length */ 736 dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) | 737 V_DMA_DSCRB_PKT_SIZE(length); 738 739 num_mbufs++; 740 741 /* 742 * fill in the context 743 */ 744 745 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = m_new; 746 747 /* 748 * point at next packet 749 */ 750 d->sbdma_addptr = nextdsc; 751 } 752 753 /* 754 * Give the buffer to the DMA engine. 755 */ 756 757 SBMAC_WRITECSR(d->sbdma_dscrcnt, num_mbufs); 758 759 return 0; /* we did it */ 760 } 761 762 /* 763 * SBDMA_EMPTYRING(d) 764 * 765 * Free all allocated mbufs on the specified DMA channel; 766 * 767 * Input parameters: 768 * d - DMA channel 769 * 770 * Return value: 771 * nothing 772 */ 773 774 static void 775 sbdma_emptyring(sbmacdma_t *d) 776 { 777 int idx; 778 struct mbuf *m; 779 780 for (idx = 0; idx < d->sbdma_maxdescr; idx++) { 781 m = d->sbdma_ctxtable[idx]; 782 if (m) { 783 m_freem(m); 784 d->sbdma_ctxtable[idx] = NULL; 785 } 786 } 787 } 788 789 /* 790 * SBDMA_FILLRING(d) 791 * 792 * Fill the specified DMA channel (must be receive channel) 793 * with mbufs 794 * 795 * Input parameters: 796 * d - DMA channel 797 * 798 * Return value: 799 * nothing 800 */ 801 802 static void 803 sbdma_fillring(sbmacdma_t *d) 804 { 805 int idx; 806 807 for (idx = 0; idx < SBMAC_MAX_RXDESCR-1; idx++) 808 if (sbdma_add_rcvbuffer(d, NULL) != 0) 809 break; 810 } 811 812 /* 813 * SBDMA_RX_PROCESS(sc, d) 814 * 815 * Process "completed" receive buffers on the specified DMA channel. 816 * Note that this isn't really ideal for priority channels, since 817 * it processes all of the packets on a given channel before 818 * returning. 819 * 820 * Input parameters: 821 * sc - softc structure 822 * d - DMA channel context 823 * 824 * Return value: 825 * nothing 826 */ 827 828 static void 829 sbdma_rx_process(struct sbmac_softc *sc, sbmacdma_t *d) 830 { 831 int curidx; 832 int hwidx; 833 sbdmadscr_t *dsc; 834 struct mbuf *m; 835 struct ether_header *eh; 836 int len; 837 838 struct ifnet *ifp = &(sc->sc_ethercom.ec_if); 839 840 for (;;) { 841 /* 842 * figure out where we are (as an index) and where 843 * the hardware is (also as an index) 844 * 845 * This could be done faster if (for example) the 846 * descriptor table was page-aligned and contiguous in 847 * both virtual and physical memory -- you could then 848 * just compare the low-order bits of the virtual address 849 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) 850 */ 851 852 curidx = d->sbdma_remptr - d->sbdma_dscrtable; 853 hwidx = (int) 854 (((SBMAC_READCSR(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - 855 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t)); 856 857 /* 858 * If they're the same, that means we've processed all 859 * of the descriptors up to (but not including) the one that 860 * the hardware is working on right now. 861 */ 862 863 if (curidx == hwidx) 864 break; 865 866 /* 867 * Otherwise, get the packet's mbuf ptr back 868 */ 869 870 dsc = &(d->sbdma_dscrtable[curidx]); 871 m = d->sbdma_ctxtable[curidx]; 872 d->sbdma_ctxtable[curidx] = NULL; 873 874 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4; 875 876 /* 877 * Check packet status. If good, process it. 878 * If not, silently drop it and put it back on the 879 * receive ring. 880 */ 881 882 if (! (dsc->dscr_a & M_DMA_ETHRX_BAD)) { 883 884 /* 885 * Set length into the packet 886 * XXX do we remove the CRC here? 887 */ 888 m->m_pkthdr.len = m->m_len = len; 889 890 ifp->if_ipackets++; 891 eh = mtod(m, struct ether_header *); 892 m->m_pkthdr.rcvif = ifp; 893 894 895 /* 896 * Add a new buffer to replace the old one. 897 */ 898 sbdma_add_rcvbuffer(d, NULL); 899 900 #if (NBPFILTER > 0) 901 /* 902 * Handle BPF listeners. Let the BPF user see the 903 * packet, but don't pass it up to the ether_input() 904 * layer unless it's a broadcast packet, multicast 905 * packet, matches our ethernet address or the 906 * interface is in promiscuous mode. 907 */ 908 909 if (ifp->if_bpf) 910 bpf_mtap(ifp->if_bpf, m); 911 #endif 912 /* 913 * Pass the buffer to the kernel 914 */ 915 (*ifp->if_input)(ifp, m); 916 } else { 917 /* 918 * Packet was mangled somehow. Just drop it and 919 * put it back on the receive ring. 920 */ 921 sbdma_add_rcvbuffer(d, m); 922 } 923 924 /* 925 * .. and advance to the next buffer. 926 */ 927 928 d->sbdma_remptr = SBDMA_NEXTBUF(d, sbdma_remptr); 929 } 930 } 931 932 /* 933 * SBDMA_TX_PROCESS(sc, d) 934 * 935 * Process "completed" transmit buffers on the specified DMA channel. 936 * This is normally called within the interrupt service routine. 937 * Note that this isn't really ideal for priority channels, since 938 * it processes all of the packets on a given channel before 939 * returning. 940 * 941 * Input parameters: 942 * sc - softc structure 943 * d - DMA channel context 944 * 945 * Return value: 946 * nothing 947 */ 948 949 static void 950 sbdma_tx_process(struct sbmac_softc *sc, sbmacdma_t *d) 951 { 952 int curidx; 953 int hwidx; 954 sbdmadscr_t *dsc; 955 struct mbuf *m; 956 957 struct ifnet *ifp = &(sc->sc_ethercom.ec_if); 958 959 for (;;) { 960 /* 961 * figure out where we are (as an index) and where 962 * the hardware is (also as an index) 963 * 964 * This could be done faster if (for example) the 965 * descriptor table was page-aligned and contiguous in 966 * both virtual and physical memory -- you could then 967 * just compare the low-order bits of the virtual address 968 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) 969 */ 970 971 curidx = d->sbdma_remptr - d->sbdma_dscrtable; 972 hwidx = (int) 973 (((SBMAC_READCSR(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - 974 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t)); 975 976 /* 977 * If they're the same, that means we've processed all 978 * of the descriptors up to (but not including) the one that 979 * the hardware is working on right now. 980 */ 981 982 if (curidx == hwidx) 983 break; 984 985 /* 986 * Otherwise, get the packet's mbuf ptr back 987 */ 988 989 dsc = &(d->sbdma_dscrtable[curidx]); 990 m = d->sbdma_ctxtable[curidx]; 991 d->sbdma_ctxtable[curidx] = NULL; 992 993 /* 994 * for transmits, we just free buffers. 995 */ 996 997 m_freem(m); 998 999 /* 1000 * .. and advance to the next buffer. 1001 */ 1002 1003 d->sbdma_remptr = SBDMA_NEXTBUF(d, sbdma_remptr); 1004 } 1005 1006 /* 1007 * Decide what to set the IFF_OACTIVE bit in the interface to. 1008 * It's supposed to reflect if the interface is actively 1009 * transmitting, but that's really hard to do quickly. 1010 */ 1011 1012 ifp->if_flags &= ~IFF_OACTIVE; 1013 } 1014 1015 /* 1016 * SBMAC_INITCTX(s) 1017 * 1018 * Initialize an Ethernet context structure - this is called 1019 * once per MAC on the 1250. Memory is allocated here, so don't 1020 * call it again from inside the ioctl routines that bring the 1021 * interface up/down 1022 * 1023 * Input parameters: 1024 * s - sbmac context structure 1025 * 1026 * Return value: 1027 * 0 1028 */ 1029 1030 static void 1031 sbmac_initctx(struct sbmac_softc *s) 1032 { 1033 uint64_t sysrev; 1034 1035 /* 1036 * figure out the addresses of some ports 1037 */ 1038 1039 s->sbm_macenable = PKSEG1(s->sbm_base + R_MAC_ENABLE); 1040 s->sbm_maccfg = PKSEG1(s->sbm_base + R_MAC_CFG); 1041 s->sbm_fifocfg = PKSEG1(s->sbm_base + R_MAC_THRSH_CFG); 1042 s->sbm_framecfg = PKSEG1(s->sbm_base + R_MAC_FRAMECFG); 1043 s->sbm_rxfilter = PKSEG1(s->sbm_base + R_MAC_ADFILTER_CFG); 1044 s->sbm_isr = PKSEG1(s->sbm_base + R_MAC_STATUS); 1045 s->sbm_imr = PKSEG1(s->sbm_base + R_MAC_INT_MASK); 1046 1047 /* 1048 * Initialize the DMA channels. Right now, only one per MAC is used 1049 * Note: Only do this _once_, as it allocates memory from the kernel! 1050 */ 1051 1052 sbdma_initctx(&(s->sbm_txdma), s, 0, DMA_TX, SBMAC_MAX_TXDESCR); 1053 sbdma_initctx(&(s->sbm_rxdma), s, 0, DMA_RX, SBMAC_MAX_RXDESCR); 1054 1055 /* 1056 * initial state is OFF 1057 */ 1058 1059 s->sbm_state = sbmac_state_off; 1060 1061 /* 1062 * Initial speed is (XXX TEMP) 10MBit/s HDX no FC 1063 */ 1064 1065 s->sbm_speed = sbmac_speed_10; 1066 s->sbm_duplex = sbmac_duplex_half; 1067 s->sbm_fc = sbmac_fc_disabled; 1068 1069 /* 1070 * Determine SOC type. 112x has Pass3 SOC features. 1071 */ 1072 sysrev = SBMAC_READCSR( PKSEG1(A_SCD_SYSTEM_REVISION) ); 1073 s->sbm_pass3_dma = (SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1120 || 1074 SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1125 || 1075 SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1125H || 1076 (SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250 && 1077 0)); 1078 if (s->sbm_pass3_dma) { 1079 printf("\n"); 1080 printf("%s: disabling unaligned tx DMA\n", s->sc_dev.dv_xname); 1081 printf("%s", s->sc_dev.dv_xname); 1082 s->sbm_pass3_dma = 0; 1083 } 1084 } 1085 1086 /* 1087 * SBMAC_CHANNEL_START(s) 1088 * 1089 * Start packet processing on this MAC. 1090 * 1091 * Input parameters: 1092 * s - sbmac structure 1093 * 1094 * Return value: 1095 * nothing 1096 */ 1097 1098 static void 1099 sbmac_channel_start(struct sbmac_softc *s) 1100 { 1101 uint64_t reg; 1102 sbmac_port_t port; 1103 uint64_t cfg, fifo, framecfg; 1104 int idx; 1105 uint64_t dma_cfg0, fifo_cfg; 1106 sbmacdma_t *txdma; 1107 1108 /* 1109 * Don't do this if running 1110 */ 1111 1112 if (s->sbm_state == sbmac_state_on) 1113 return; 1114 1115 /* 1116 * Bring the controller out of reset, but leave it off. 1117 */ 1118 1119 SBMAC_WRITECSR(s->sbm_macenable, 0); 1120 1121 /* 1122 * Ignore all received packets 1123 */ 1124 1125 SBMAC_WRITECSR(s->sbm_rxfilter, 0); 1126 1127 /* 1128 * Calculate values for various control registers. 1129 */ 1130 1131 cfg = M_MAC_RETRY_EN | 1132 M_MAC_TX_HOLD_SOP_EN | 1133 V_MAC_TX_PAUSE_CNT_16K | 1134 M_MAC_AP_STAT_EN | 1135 M_MAC_SS_EN | 1136 0; 1137 1138 fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */ 1139 V_MAC_TX_RD_THRSH(4) | 1140 V_MAC_TX_RL_THRSH(4) | 1141 V_MAC_RX_PL_THRSH(4) | 1142 V_MAC_RX_RD_THRSH(4) | /* Must be '4' */ 1143 V_MAC_RX_PL_THRSH(4) | 1144 V_MAC_RX_RL_THRSH(8) | 1145 0; 1146 1147 framecfg = V_MAC_MIN_FRAMESZ_DEFAULT | 1148 V_MAC_MAX_FRAMESZ_DEFAULT | 1149 V_MAC_BACKOFF_SEL(1); 1150 1151 /* 1152 * Clear out the hash address map 1153 */ 1154 1155 port = PKSEG1(s->sbm_base + R_MAC_HASH_BASE); 1156 for (idx = 0; idx < MAC_HASH_COUNT; idx++) { 1157 SBMAC_WRITECSR(port, 0); 1158 port += sizeof(uint64_t); 1159 } 1160 1161 /* 1162 * Clear out the exact-match table 1163 */ 1164 1165 port = PKSEG1(s->sbm_base + R_MAC_ADDR_BASE); 1166 for (idx = 0; idx < MAC_ADDR_COUNT; idx++) { 1167 SBMAC_WRITECSR(port, 0); 1168 port += sizeof(uint64_t); 1169 } 1170 1171 /* 1172 * Clear out the DMA Channel mapping table registers 1173 */ 1174 1175 port = PKSEG1(s->sbm_base + R_MAC_CHUP0_BASE); 1176 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { 1177 SBMAC_WRITECSR(port, 0); 1178 port += sizeof(uint64_t); 1179 } 1180 1181 port = PKSEG1(s->sbm_base + R_MAC_CHLO0_BASE); 1182 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { 1183 SBMAC_WRITECSR(port, 0); 1184 port += sizeof(uint64_t); 1185 } 1186 1187 /* 1188 * Program the hardware address. It goes into the hardware-address 1189 * register as well as the first filter register. 1190 */ 1191 1192 reg = sbmac_addr2reg(s->sbm_hwaddr); 1193 1194 port = PKSEG1(s->sbm_base + R_MAC_ADDR_BASE); 1195 SBMAC_WRITECSR(port, reg); 1196 port = PKSEG1(s->sbm_base + R_MAC_ETHERNET_ADDR); 1197 SBMAC_WRITECSR(port, 0); // pass1 workaround 1198 1199 /* 1200 * Set the receive filter for no packets, and write values 1201 * to the various config registers 1202 */ 1203 1204 SBMAC_WRITECSR(s->sbm_rxfilter, 0); 1205 SBMAC_WRITECSR(s->sbm_imr, 0); 1206 SBMAC_WRITECSR(s->sbm_framecfg, framecfg); 1207 SBMAC_WRITECSR(s->sbm_fifocfg, fifo); 1208 SBMAC_WRITECSR(s->sbm_maccfg, cfg); 1209 1210 /* 1211 * Initialize DMA channels (rings should be ok now) 1212 */ 1213 1214 sbdma_channel_start(&(s->sbm_rxdma)); 1215 sbdma_channel_start(&(s->sbm_txdma)); 1216 1217 /* 1218 * Configure the speed, duplex, and flow control 1219 */ 1220 1221 sbmac_set_speed(s, s->sbm_speed); 1222 sbmac_set_duplex(s, s->sbm_duplex, s->sbm_fc); 1223 1224 /* 1225 * Fill the receive ring 1226 */ 1227 1228 sbdma_fillring(&(s->sbm_rxdma)); 1229 1230 /* 1231 * Turn on the rest of the bits in the enable register 1232 */ 1233 1234 SBMAC_WRITECSR(s->sbm_macenable, M_MAC_RXDMA_EN0 | M_MAC_TXDMA_EN0 | 1235 M_MAC_RX_ENABLE | M_MAC_TX_ENABLE); 1236 1237 1238 /* 1239 * Accept any kind of interrupt on TX and RX DMA channel 0 1240 */ 1241 SBMAC_WRITECSR(s->sbm_imr, 1242 (M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | 1243 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)); 1244 1245 /* 1246 * Enable receiving unicasts and broadcasts 1247 */ 1248 1249 SBMAC_WRITECSR(s->sbm_rxfilter, M_MAC_UCAST_EN | M_MAC_BCAST_EN); 1250 1251 /* 1252 * On chips which support unaligned DMA features, set the descriptor 1253 * ring for transmit channels to use the unaligned buffer format. 1254 */ 1255 txdma = &(s->sbm_txdma); 1256 1257 if (s->sbm_pass3_dma) { 1258 1259 dma_cfg0 = SBMAC_READCSR(txdma->sbdma_config0); 1260 dma_cfg0 |= V_DMA_DESC_TYPE(K_DMA_DESC_TYPE_RING_UAL_RMW) | 1261 M_DMA_TBX_EN | M_DMA_TDX_EN; 1262 SBMAC_WRITECSR(txdma->sbdma_config0,dma_cfg0); 1263 1264 fifo_cfg = SBMAC_READCSR(s->sbm_fifocfg); 1265 fifo_cfg |= V_MAC_TX_WR_THRSH(8) | 1266 V_MAC_TX_RD_THRSH(8) | V_MAC_TX_RL_THRSH(8); 1267 SBMAC_WRITECSR(s->sbm_fifocfg,fifo_cfg); 1268 } 1269 1270 /* 1271 * we're running now. 1272 */ 1273 1274 s->sbm_state = sbmac_state_on; 1275 s->sc_ethercom.ec_if.if_flags |= IFF_RUNNING; 1276 1277 /* 1278 * Program multicast addresses 1279 */ 1280 1281 sbmac_setmulti(s); 1282 1283 /* 1284 * If channel was in promiscuous mode before, turn that on 1285 */ 1286 1287 if (s->sc_ethercom.ec_if.if_flags & IFF_PROMISC) 1288 sbmac_promiscuous_mode(s, 1); 1289 1290 /* 1291 * Turn on the once-per-second timer 1292 */ 1293 1294 callout_reset(&(s->sc_tick_ch), hz, sbmac_tick, s); 1295 } 1296 1297 /* 1298 * SBMAC_CHANNEL_STOP(s) 1299 * 1300 * Stop packet processing on this MAC. 1301 * 1302 * Input parameters: 1303 * s - sbmac structure 1304 * 1305 * Return value: 1306 * nothing 1307 */ 1308 1309 static void 1310 sbmac_channel_stop(struct sbmac_softc *s) 1311 { 1312 uint64_t ctl; 1313 1314 /* don't do this if already stopped */ 1315 1316 if (s->sbm_state == sbmac_state_off) 1317 return; 1318 1319 /* don't accept any packets, disable all interrupts */ 1320 1321 SBMAC_WRITECSR(s->sbm_rxfilter, 0); 1322 SBMAC_WRITECSR(s->sbm_imr, 0); 1323 1324 /* Turn off ticker */ 1325 1326 callout_stop(&(s->sc_tick_ch)); 1327 1328 /* turn off receiver and transmitter */ 1329 1330 ctl = SBMAC_READCSR(s->sbm_macenable); 1331 ctl &= ~(M_MAC_RXDMA_EN0 | M_MAC_TXDMA_EN0); 1332 SBMAC_WRITECSR(s->sbm_macenable, ctl); 1333 1334 /* We're stopped now. */ 1335 1336 s->sbm_state = sbmac_state_off; 1337 s->sc_ethercom.ec_if.if_flags &= ~IFF_RUNNING; 1338 1339 /* Empty the receive and transmit rings */ 1340 1341 sbdma_emptyring(&(s->sbm_rxdma)); 1342 sbdma_emptyring(&(s->sbm_txdma)); 1343 } 1344 1345 /* 1346 * SBMAC_SET_CHANNEL_STATE(state) 1347 * 1348 * Set the channel's state ON or OFF 1349 * 1350 * Input parameters: 1351 * state - new state 1352 * 1353 * Return value: 1354 * old state 1355 */ 1356 1357 static sbmac_state_t 1358 sbmac_set_channel_state(struct sbmac_softc *sc, sbmac_state_t state) 1359 { 1360 sbmac_state_t oldstate = sc->sbm_state; 1361 1362 /* 1363 * If same as previous state, return 1364 */ 1365 1366 if (state == oldstate) 1367 return oldstate; 1368 1369 /* 1370 * If new state is ON, turn channel on 1371 */ 1372 1373 if (state == sbmac_state_on) 1374 sbmac_channel_start(sc); 1375 else 1376 sbmac_channel_stop(sc); 1377 1378 /* 1379 * Return previous state 1380 */ 1381 1382 return oldstate; 1383 } 1384 1385 /* 1386 * SBMAC_PROMISCUOUS_MODE(sc, onoff) 1387 * 1388 * Turn on or off promiscuous mode 1389 * 1390 * Input parameters: 1391 * sc - softc 1392 * onoff - 1 to turn on, 0 to turn off 1393 * 1394 * Return value: 1395 * nothing 1396 */ 1397 1398 static void 1399 sbmac_promiscuous_mode(struct sbmac_softc *sc, int onoff) 1400 { 1401 uint64_t reg; 1402 1403 if (sc->sbm_state != sbmac_state_on) 1404 return; 1405 1406 if (onoff) { 1407 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1408 reg |= M_MAC_ALLPKT_EN; 1409 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1410 } else { 1411 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1412 reg &= ~M_MAC_ALLPKT_EN; 1413 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1414 } 1415 } 1416 1417 /* 1418 * SBMAC_INIT_AND_START(sc) 1419 * 1420 * Stop the channel and restart it. This is generally used 1421 * when we have to do something to the channel that requires 1422 * a swift kick. 1423 * 1424 * Input parameters: 1425 * sc - softc 1426 */ 1427 1428 static void 1429 sbmac_init_and_start(struct sbmac_softc *sc) 1430 { 1431 int s; 1432 1433 s = splnet(); 1434 1435 mii_pollstat(&sc->sc_mii); /* poll phy for current speed */ 1436 sbmac_mii_statchg((struct device *) sc); /* set state to new speed */ 1437 sbmac_set_channel_state(sc, sbmac_state_on); 1438 1439 splx(s); 1440 } 1441 1442 /* 1443 * SBMAC_ADDR2REG(ptr) 1444 * 1445 * Convert six bytes into the 64-bit register value that 1446 * we typically write into the SBMAC's address/mcast registers 1447 * 1448 * Input parameters: 1449 * ptr - pointer to 6 bytes 1450 * 1451 * Return value: 1452 * register value 1453 */ 1454 1455 static uint64_t 1456 sbmac_addr2reg(u_char *ptr) 1457 { 1458 uint64_t reg = 0; 1459 1460 ptr += 6; 1461 1462 reg |= (uint64_t) *(--ptr); 1463 reg <<= 8; 1464 reg |= (uint64_t) *(--ptr); 1465 reg <<= 8; 1466 reg |= (uint64_t) *(--ptr); 1467 reg <<= 8; 1468 reg |= (uint64_t) *(--ptr); 1469 reg <<= 8; 1470 reg |= (uint64_t) *(--ptr); 1471 reg <<= 8; 1472 reg |= (uint64_t) *(--ptr); 1473 1474 return reg; 1475 } 1476 1477 /* 1478 * SBMAC_SET_SPEED(s, speed) 1479 * 1480 * Configure LAN speed for the specified MAC. 1481 * Warning: must be called when MAC is off! 1482 * 1483 * Input parameters: 1484 * s - sbmac structure 1485 * speed - speed to set MAC to (see sbmac_speed_t enum) 1486 * 1487 * Return value: 1488 * 1 if successful 1489 * 0 indicates invalid parameters 1490 */ 1491 1492 static int 1493 sbmac_set_speed(struct sbmac_softc *s, sbmac_speed_t speed) 1494 { 1495 uint64_t cfg; 1496 uint64_t framecfg; 1497 1498 /* 1499 * Save new current values 1500 */ 1501 1502 s->sbm_speed = speed; 1503 1504 if (s->sbm_state != sbmac_state_off) 1505 panic("sbmac_set_speed while MAC not off"); 1506 1507 /* 1508 * Read current register values 1509 */ 1510 1511 cfg = SBMAC_READCSR(s->sbm_maccfg); 1512 framecfg = SBMAC_READCSR(s->sbm_framecfg); 1513 1514 /* 1515 * Mask out the stuff we want to change 1516 */ 1517 1518 cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL); 1519 framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH | 1520 M_MAC_SLOT_SIZE); 1521 1522 /* 1523 * Now add in the new bits 1524 */ 1525 1526 switch (speed) { 1527 case sbmac_speed_10: 1528 framecfg |= V_MAC_IFG_RX_10 | 1529 V_MAC_IFG_TX_10 | 1530 K_MAC_IFG_THRSH_10 | 1531 V_MAC_SLOT_SIZE_10; 1532 cfg |= V_MAC_SPEED_SEL_10MBPS; 1533 break; 1534 1535 case sbmac_speed_100: 1536 framecfg |= V_MAC_IFG_RX_100 | 1537 V_MAC_IFG_TX_100 | 1538 V_MAC_IFG_THRSH_100 | 1539 V_MAC_SLOT_SIZE_100; 1540 cfg |= V_MAC_SPEED_SEL_100MBPS ; 1541 break; 1542 1543 case sbmac_speed_1000: 1544 framecfg |= V_MAC_IFG_RX_1000 | 1545 V_MAC_IFG_TX_1000 | 1546 V_MAC_IFG_THRSH_1000 | 1547 V_MAC_SLOT_SIZE_1000; 1548 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN; 1549 break; 1550 1551 case sbmac_speed_auto: /* XXX not implemented */ 1552 /* fall through */ 1553 default: 1554 return 0; 1555 } 1556 1557 /* 1558 * Send the bits back to the hardware 1559 */ 1560 1561 SBMAC_WRITECSR(s->sbm_framecfg, framecfg); 1562 SBMAC_WRITECSR(s->sbm_maccfg, cfg); 1563 1564 return 1; 1565 } 1566 1567 /* 1568 * SBMAC_SET_DUPLEX(s, duplex, fc) 1569 * 1570 * Set Ethernet duplex and flow control options for this MAC 1571 * Warning: must be called when MAC is off! 1572 * 1573 * Input parameters: 1574 * s - sbmac structure 1575 * duplex - duplex setting (see sbmac_duplex_t) 1576 * fc - flow control setting (see sbmac_fc_t) 1577 * 1578 * Return value: 1579 * 1 if ok 1580 * 0 if an invalid parameter combination was specified 1581 */ 1582 1583 static int 1584 sbmac_set_duplex(struct sbmac_softc *s, sbmac_duplex_t duplex, sbmac_fc_t fc) 1585 { 1586 uint64_t cfg; 1587 1588 /* 1589 * Save new current values 1590 */ 1591 1592 s->sbm_duplex = duplex; 1593 s->sbm_fc = fc; 1594 1595 if (s->sbm_state != sbmac_state_off) 1596 panic("sbmac_set_duplex while MAC not off"); 1597 1598 /* 1599 * Read current register values 1600 */ 1601 1602 cfg = SBMAC_READCSR(s->sbm_maccfg); 1603 1604 /* 1605 * Mask off the stuff we're about to change 1606 */ 1607 1608 cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN); 1609 1610 switch (duplex) { 1611 case sbmac_duplex_half: 1612 switch (fc) { 1613 case sbmac_fc_disabled: 1614 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED; 1615 break; 1616 1617 case sbmac_fc_collision: 1618 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED; 1619 break; 1620 1621 case sbmac_fc_carrier: 1622 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR; 1623 break; 1624 1625 case sbmac_fc_auto: /* XXX not implemented */ 1626 /* fall through */ 1627 case sbmac_fc_frame: /* not valid in half duplex */ 1628 default: /* invalid selection */ 1629 panic("%s: invalid half duplex fc selection %d", 1630 s->sc_dev.dv_xname, fc); 1631 return 0; 1632 } 1633 break; 1634 1635 case sbmac_duplex_full: 1636 switch (fc) { 1637 case sbmac_fc_disabled: 1638 cfg |= V_MAC_FC_CMD_DISABLED; 1639 break; 1640 1641 case sbmac_fc_frame: 1642 cfg |= V_MAC_FC_CMD_ENABLED; 1643 break; 1644 1645 case sbmac_fc_collision: /* not valid in full duplex */ 1646 case sbmac_fc_carrier: /* not valid in full duplex */ 1647 case sbmac_fc_auto: /* XXX not implemented */ 1648 /* fall through */ 1649 default: 1650 panic("%s: invalid full duplex fc selection %d", 1651 s->sc_dev.dv_xname, fc); 1652 return 0; 1653 } 1654 break; 1655 1656 default: 1657 /* fall through */ 1658 case sbmac_duplex_auto: 1659 panic("%s: bad duplex %d", s->sc_dev.dv_xname, duplex); 1660 /* XXX not implemented */ 1661 break; 1662 } 1663 1664 /* 1665 * Send the bits back to the hardware 1666 */ 1667 1668 SBMAC_WRITECSR(s->sbm_maccfg, cfg); 1669 1670 return 1; 1671 } 1672 1673 /* 1674 * SBMAC_INTR() 1675 * 1676 * Interrupt handler for MAC interrupts 1677 * 1678 * Input parameters: 1679 * MAC structure 1680 * 1681 * Return value: 1682 * nothing 1683 */ 1684 1685 /* ARGSUSED */ 1686 static void 1687 sbmac_intr(void *xsc, uint32_t status, uint32_t pc) 1688 { 1689 struct sbmac_softc *sc = (struct sbmac_softc *) xsc; 1690 uint64_t isr; 1691 1692 for (;;) { 1693 1694 /* 1695 * Read the ISR (this clears the bits in the real register) 1696 */ 1697 1698 isr = SBMAC_READCSR(sc->sbm_isr); 1699 1700 if (isr == 0) 1701 break; 1702 1703 /* 1704 * Transmits on channel 0 1705 */ 1706 1707 if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) 1708 sbdma_tx_process(sc, &(sc->sbm_txdma)); 1709 1710 /* 1711 * Receives on channel 0 1712 */ 1713 1714 if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) 1715 sbdma_rx_process(sc, &(sc->sbm_rxdma)); 1716 } 1717 } 1718 1719 1720 /* 1721 * SBMAC_START(ifp) 1722 * 1723 * Start output on the specified interface. Basically, we 1724 * queue as many buffers as we can until the ring fills up, or 1725 * we run off the end of the queue, whichever comes first. 1726 * 1727 * Input parameters: 1728 * ifp - interface 1729 * 1730 * Return value: 1731 * nothing 1732 */ 1733 1734 static void 1735 sbmac_start(struct ifnet *ifp) 1736 { 1737 struct sbmac_softc *sc; 1738 struct mbuf *m_head = NULL; 1739 int rv; 1740 1741 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1742 return; 1743 1744 sc = ifp->if_softc; 1745 1746 for (;;) { 1747 1748 IF_DEQUEUE(&ifp->if_snd, m_head); 1749 if (m_head == NULL) 1750 break; 1751 1752 /* 1753 * Put the buffer on the transmit ring. If we 1754 * don't have room, set the OACTIVE flag and wait 1755 * for the NIC to drain the ring. 1756 */ 1757 1758 rv = sbdma_add_txbuffer(&(sc->sbm_txdma), m_head); 1759 1760 if (rv == 0) { 1761 /* 1762 * If there's a BPF listener, bounce a copy of this frame 1763 * to it. 1764 */ 1765 #if (NBPFILTER > 0) 1766 if (ifp->if_bpf) 1767 bpf_mtap(ifp->if_bpf, m_head); 1768 #endif 1769 if (!sc->sbm_pass3_dma) { 1770 /* 1771 * Don't free mbuf if we're not copying to new mbuf in sbdma_add_txbuffer. 1772 * It will be freed in sbdma_tx_process. 1773 */ 1774 m_freem(m_head); 1775 } 1776 } else { 1777 IF_PREPEND(&ifp->if_snd, m_head); 1778 ifp->if_flags |= IFF_OACTIVE; 1779 break; 1780 } 1781 } 1782 } 1783 1784 /* 1785 * SBMAC_SETMULTI(sc) 1786 * 1787 * Reprogram the multicast table into the hardware, given 1788 * the list of multicasts associated with the interface 1789 * structure. 1790 * 1791 * Input parameters: 1792 * sc - softc 1793 * 1794 * Return value: 1795 * nothing 1796 */ 1797 1798 static void 1799 sbmac_setmulti(struct sbmac_softc *sc) 1800 { 1801 struct ifnet *ifp; 1802 uint64_t reg; 1803 sbmac_port_t port; 1804 int idx; 1805 struct ether_multi *enm; 1806 struct ether_multistep step; 1807 1808 ifp = &sc->sc_ethercom.ec_if; 1809 1810 /* 1811 * Clear out entire multicast table. We do this by nuking 1812 * the entire hash table and all the direct matches except 1813 * the first one, which is used for our station address 1814 */ 1815 1816 for (idx = 1; idx < MAC_ADDR_COUNT; idx++) { 1817 port = PKSEG1(sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t))); 1818 SBMAC_WRITECSR(port, 0); 1819 } 1820 1821 for (idx = 0; idx < MAC_HASH_COUNT; idx++) { 1822 port = PKSEG1(sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t))); 1823 SBMAC_WRITECSR(port, 0); 1824 } 1825 1826 /* 1827 * Clear the filter to say we don't want any multicasts. 1828 */ 1829 1830 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1831 reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN); 1832 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1833 1834 if (ifp->if_flags & IFF_ALLMULTI) { 1835 /* 1836 * Enable ALL multicasts. Do this by inverting the 1837 * multicast enable bit. 1838 */ 1839 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1840 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN); 1841 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1842 return; 1843 } 1844 1845 /* 1846 * Progam new multicast entries. For now, only use the 1847 * perfect filter. In the future we'll need to use the 1848 * hash filter if the perfect filter overflows 1849 */ 1850 1851 /* 1852 * XXX only using perfect filter for now, need to use hash 1853 * XXX if the table overflows 1854 */ 1855 1856 idx = 1; /* skip station address */ 1857 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1858 while ((enm != NULL) && (idx < MAC_ADDR_COUNT)) { 1859 reg = sbmac_addr2reg(enm->enm_addrlo); 1860 port = PKSEG1(sc->sbm_base + 1861 R_MAC_ADDR_BASE+(idx*sizeof(uint64_t))); 1862 SBMAC_WRITECSR(port, reg); 1863 idx++; 1864 ETHER_NEXT_MULTI(step, enm); 1865 } 1866 1867 /* 1868 * Enable the "accept multicast bits" if we programmed at least one 1869 * multicast. 1870 */ 1871 1872 if (idx > 1) { 1873 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1874 reg |= M_MAC_MCAST_EN; 1875 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1876 } 1877 } 1878 1879 /* 1880 * SBMAC_ETHER_IOCTL(ifp, cmd, data) 1881 * 1882 * Generic IOCTL requests for this interface. The basic 1883 * stuff is handled here for bringing the interface up, 1884 * handling multicasts, etc. 1885 * 1886 * Input parameters: 1887 * ifp - interface structure 1888 * cmd - command code 1889 * data - pointer to data 1890 * 1891 * Return value: 1892 * return value (0 is success) 1893 */ 1894 1895 static int 1896 sbmac_ether_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1897 { 1898 struct ifaddr *ifa = (struct ifaddr *) data; 1899 struct sbmac_softc *sc = ifp->if_softc; 1900 1901 switch (cmd) { 1902 case SIOCSIFADDR: 1903 ifp->if_flags |= IFF_UP; 1904 1905 switch (ifa->ifa_addr->sa_family) { 1906 #ifdef INET 1907 case AF_INET: 1908 sbmac_init_and_start(sc); 1909 arp_ifinit(ifp, ifa); 1910 break; 1911 #endif 1912 #ifdef NS 1913 case AF_NS: 1914 { 1915 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1916 1917 if (ns_nullhost(*ina)) 1918 ina->x_host = *(union ns_host *)LLADDR(ifp->if_sadl); 1919 else 1920 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1921 ifp->if_addrlen); 1922 /* Set new address. */ 1923 sbmac_init_and_start(sc); 1924 break; 1925 } 1926 #endif 1927 default: 1928 sbmac_init_and_start(sc); 1929 break; 1930 } 1931 break; 1932 1933 default: 1934 return (EINVAL); 1935 } 1936 1937 return (0); 1938 } 1939 1940 /* 1941 * SBMAC_IOCTL(ifp, command, data) 1942 * 1943 * Main IOCTL handler - dispatches to other IOCTLs for various 1944 * types of requests. 1945 * 1946 * Input parameters: 1947 * ifp - interface pointer 1948 * command - command code 1949 * data - pointer to argument data 1950 * 1951 * Return value: 1952 * 0 if ok 1953 * else error code 1954 */ 1955 1956 static int 1957 sbmac_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1958 { 1959 struct sbmac_softc *sc = ifp->if_softc; 1960 struct ifreq *ifr = (struct ifreq *) data; 1961 int s, error = 0; 1962 1963 s = splnet(); 1964 1965 switch(command) { 1966 case SIOCSIFADDR: 1967 case SIOCGIFADDR: 1968 error = sbmac_ether_ioctl(ifp, command, data); 1969 break; 1970 case SIOCSIFMTU: 1971 if (ifr->ifr_mtu > ETHER_MAX_LEN) 1972 error = EINVAL; 1973 else { 1974 ifp->if_mtu = ifr->ifr_mtu; 1975 /* XXX Program new MTU here */ 1976 } 1977 break; 1978 case SIOCSIFFLAGS: 1979 if (ifp->if_flags & IFF_UP) { 1980 /* 1981 * If only the state of the PROMISC flag changed, 1982 * just tweak the hardware registers. 1983 */ 1984 if ((ifp->if_flags & IFF_RUNNING) && 1985 (ifp->if_flags & IFF_PROMISC)) { 1986 /* turn on promiscuous mode */ 1987 sbmac_promiscuous_mode(sc, 1); 1988 } else if (ifp->if_flags & IFF_RUNNING && 1989 !(ifp->if_flags & IFF_PROMISC)) { 1990 /* turn off promiscuous mode */ 1991 sbmac_promiscuous_mode(sc, 0); 1992 } else 1993 sbmac_set_channel_state(sc, sbmac_state_on); 1994 } else { 1995 if (ifp->if_flags & IFF_RUNNING) 1996 sbmac_set_channel_state(sc, sbmac_state_off); 1997 } 1998 1999 sc->sbm_if_flags = ifp->if_flags; 2000 error = 0; 2001 break; 2002 2003 case SIOCADDMULTI: 2004 case SIOCDELMULTI: 2005 if (ifp->if_flags & IFF_RUNNING) { 2006 sbmac_setmulti(sc); 2007 error = 0; 2008 } 2009 break; 2010 case SIOCSIFMEDIA: 2011 case SIOCGIFMEDIA: 2012 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 2013 break; 2014 default: 2015 error = EINVAL; 2016 break; 2017 } 2018 2019 (void)splx(s); 2020 2021 return(error); 2022 } 2023 2024 /* 2025 * SBMAC_IFMEDIA_UPD(ifp) 2026 * 2027 * Configure an appropriate media type for this interface, 2028 * given the data in the interface structure 2029 * 2030 * Input parameters: 2031 * ifp - interface 2032 * 2033 * Return value: 2034 * 0 if ok 2035 * else error code 2036 */ 2037 2038 static int 2039 sbmac_mediachange(struct ifnet *ifp) 2040 { 2041 struct sbmac_softc *sc = ifp->if_softc; 2042 2043 if (ifp->if_flags & IFF_UP) 2044 mii_mediachg(&sc->sc_mii); 2045 return(0); 2046 } 2047 2048 /* 2049 * SBMAC_IFMEDIA_STS(ifp, ifmr) 2050 * 2051 * Report current media status (used by ifconfig, for example) 2052 * 2053 * Input parameters: 2054 * ifp - interface structure 2055 * ifmr - media request structure 2056 * 2057 * Return value: 2058 * nothing 2059 */ 2060 2061 static void 2062 sbmac_mediastatus(struct ifnet *ifp, struct ifmediareq *req) 2063 { 2064 struct sbmac_softc *sc = ifp->if_softc; 2065 2066 mii_pollstat(&sc->sc_mii); 2067 req->ifm_status = sc->sc_mii.mii_media_status; 2068 req->ifm_active = sc->sc_mii.mii_media_active; 2069 } 2070 2071 /* 2072 * SBMAC_WATCHDOG(ifp) 2073 * 2074 * Called periodically to make sure we're still happy. 2075 * 2076 * Input parameters: 2077 * ifp - interface structure 2078 * 2079 * Return value: 2080 * nothing 2081 */ 2082 2083 static void 2084 sbmac_watchdog(struct ifnet *ifp) 2085 { 2086 2087 /* XXX do something */ 2088 } 2089 2090 /* 2091 * One second timer, used to tick MII. 2092 */ 2093 static void 2094 sbmac_tick(void *arg) 2095 { 2096 struct sbmac_softc *sc = arg; 2097 int s; 2098 2099 s = splnet(); 2100 mii_tick(&sc->sc_mii); 2101 splx(s); 2102 2103 callout_reset(&sc->sc_tick_ch, hz, sbmac_tick, sc); 2104 } 2105 2106 2107 /* 2108 * SBMAC_MATCH(parent, match, aux) 2109 * 2110 * Part of the config process - see if this device matches the 2111 * info about what we expect to find on the bus. 2112 * 2113 * Input parameters: 2114 * parent - parent bus structure 2115 * match - 2116 * aux - bus-specific args 2117 * 2118 * Return value: 2119 * 1 if we match 2120 * 0 if we don't match 2121 */ 2122 2123 static int 2124 sbmac_match(struct device *parent, struct cfdata *match, void *aux) 2125 { 2126 struct sbobio_attach_args *sap = aux; 2127 2128 /* 2129 * Make sure it's a MAC 2130 */ 2131 2132 if (sap->sa_locs.sa_type != SBOBIO_DEVTYPE_MAC) 2133 return 0; 2134 2135 /* 2136 * Yup, it is. 2137 */ 2138 2139 return 1; 2140 } 2141 2142 /* 2143 * SBMAC_PARSE_XDIGIT(str) 2144 * 2145 * Parse a hex digit, returning its value 2146 * 2147 * Input parameters: 2148 * str - character 2149 * 2150 * Return value: 2151 * hex value, or -1 if invalid 2152 */ 2153 2154 static int 2155 sbmac_parse_xdigit(char str) 2156 { 2157 int digit; 2158 2159 if ((str >= '0') && (str <= '9')) 2160 digit = str - '0'; 2161 else if ((str >= 'a') && (str <= 'f')) 2162 digit = str - 'a' + 10; 2163 else if ((str >= 'A') && (str <= 'F')) 2164 digit = str - 'A' + 10; 2165 else 2166 digit = -1; 2167 2168 return digit; 2169 } 2170 2171 /* 2172 * SBMAC_PARSE_HWADDR(str, hwaddr) 2173 * 2174 * Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte 2175 * Ethernet address. 2176 * 2177 * Input parameters: 2178 * str - string 2179 * hwaddr - pointer to hardware address 2180 * 2181 * Return value: 2182 * 0 if ok, else -1 2183 */ 2184 2185 static int 2186 sbmac_parse_hwaddr(char *str, u_char *hwaddr) 2187 { 2188 int digit1, digit2; 2189 int idx = 6; 2190 2191 while (*str && (idx > 0)) { 2192 digit1 = sbmac_parse_xdigit(*str); 2193 if (digit1 < 0) 2194 return -1; 2195 str++; 2196 if (!*str) 2197 return -1; 2198 2199 if ((*str == ':') || (*str == '-')) { 2200 digit2 = digit1; 2201 digit1 = 0; 2202 } else { 2203 digit2 = sbmac_parse_xdigit(*str); 2204 if (digit2 < 0) 2205 return -1; 2206 str++; 2207 } 2208 2209 *hwaddr++ = (digit1 << 4) | digit2; 2210 idx--; 2211 2212 if (*str == '-') 2213 str++; 2214 if (*str == ':') 2215 str++; 2216 } 2217 return 0; 2218 } 2219 2220 /* 2221 * SBMAC_ATTACH(parent, self, aux) 2222 * 2223 * Attach routine - init hardware and hook ourselves into NetBSD. 2224 * 2225 * Input parameters: 2226 * parent - parent bus device 2227 * self - our softc 2228 * aux - attach data 2229 * 2230 * Return value: 2231 * nothing 2232 */ 2233 2234 static void 2235 sbmac_attach(struct device *parent, struct device *self, void *aux) 2236 { 2237 struct ifnet *ifp; 2238 struct sbmac_softc *sc; 2239 struct sbobio_attach_args *sap = aux; 2240 u_char *eaddr; 2241 static int unit = 0; /* XXX */ 2242 uint64_t ea_reg; 2243 int idx; 2244 2245 sc = (struct sbmac_softc *)self; 2246 2247 /* Determine controller base address */ 2248 2249 sc->sbm_base = (sbmac_port_t) sap->sa_base + sap->sa_locs.sa_offset; 2250 2251 eaddr = sc->sbm_hwaddr; 2252 2253 /* 2254 * Initialize context (get pointers to registers and stuff), then 2255 * allocate the memory for the descriptor tables. 2256 */ 2257 2258 sbmac_initctx(sc); 2259 2260 callout_init(&(sc->sc_tick_ch)); 2261 2262 /* 2263 * Read the ethernet address. The firwmare left this programmed 2264 * for us in the ethernet address register for each mac. 2265 */ 2266 2267 ea_reg = SBMAC_READCSR(PKSEG1(sc->sbm_base + R_MAC_ETHERNET_ADDR)); 2268 for (idx = 0; idx < 6; idx++) { 2269 eaddr[idx] = (uint8_t) (ea_reg & 0xFF); 2270 ea_reg >>= 8; 2271 } 2272 2273 #define SBMAC_DEFAULT_HWADDR "40:00:00:00:01:00" 2274 if (eaddr[0] == 0 && eaddr[1] == 0 && eaddr[2] == 0 && 2275 eaddr[3] == 0 && eaddr[4] == 0 && eaddr[5] == 0) { 2276 sbmac_parse_hwaddr(SBMAC_DEFAULT_HWADDR, eaddr); 2277 eaddr[5] = unit; 2278 } 2279 2280 #ifdef SBMAC_ETH0_HWADDR 2281 if (unit == 0) 2282 sbmac_parse_hwaddr(SBMAC_ETH0_HWADDR, eaddr); 2283 #endif 2284 #ifdef SBMAC_ETH1_HWADDR 2285 if (unit == 1) 2286 sbmac_parse_hwaddr(SBMAC_ETH1_HWADDR, eaddr); 2287 #endif 2288 #ifdef SBMAC_ETH2_HWADDR 2289 if (unit == 2) 2290 sbmac_parse_hwaddr(SBMAC_ETH2_HWADDR, eaddr); 2291 #endif 2292 unit++; 2293 2294 /* 2295 * Display Ethernet address (this is called during the config process 2296 * so we need to finish off the config message that was being displayed) 2297 */ 2298 printf(": Ethernet%s\n", 2299 sc->sbm_pass3_dma ? ", using unaligned tx DMA" : ""); 2300 printf("%s: Ethernet address: %s\n", self->dv_xname, 2301 ether_sprintf(eaddr)); 2302 2303 2304 /* 2305 * Set up ifnet structure 2306 */ 2307 2308 ifp = &sc->sc_ethercom.ec_if; 2309 ifp->if_softc = sc; 2310 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 2311 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | IFF_NOTRAILERS; 2312 ifp->if_ioctl = sbmac_ioctl; 2313 ifp->if_start = sbmac_start; 2314 ifp->if_watchdog = sbmac_watchdog; 2315 ifp->if_snd.ifq_maxlen = SBMAC_MAX_TXDESCR - 1; 2316 2317 /* 2318 * Set up ifmedia support. 2319 */ 2320 2321 /* 2322 * Initialize MII/media info. 2323 */ 2324 sc->sc_mii.mii_ifp = ifp; 2325 sc->sc_mii.mii_readreg = sbmac_mii_readreg; 2326 sc->sc_mii.mii_writereg = sbmac_mii_writereg; 2327 sc->sc_mii.mii_statchg = sbmac_mii_statchg; 2328 ifmedia_init(&sc->sc_mii.mii_media, 0, sbmac_mediachange, 2329 sbmac_mediastatus); 2330 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 2331 MII_OFFSET_ANY, 0); 2332 2333 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 2334 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 2335 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 2336 } else { 2337 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2338 } 2339 2340 2341 /* 2342 * map/route interrupt 2343 */ 2344 2345 sc->sbm_intrhand = cpu_intr_establish(sap->sa_locs.sa_intr[0], IPL_NET, 2346 sbmac_intr, sc); 2347 2348 /* 2349 * Call MI attach routines. 2350 */ 2351 if_attach(ifp); 2352 ether_ifattach(ifp, eaddr); 2353 } 2354
Indexes created Mon Sep 29 21:09:56 GMT 2025