sbmac.c revision 1.13
1 /* $NetBSD: sbmac.c,v 1.13 2004/03/08 11:28:48 simonb Exp $ */ 2 3 /* 4 * Copyright 2000, 2001 5 * Broadcom Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and copied only 8 * in accordance with the following terms and conditions. Subject to these 9 * conditions, you may download, copy, install, use, modify and distribute 10 * modified or unmodified copies of this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce and 14 * retain this copyright notice and list of conditions as they appear in 15 * the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Broadcom Corporation. The "Broadcom Corporation" name may not be 19 * used to endorse or promote products derived from this software 20 * without the prior written permission of Broadcom Corporation. 21 * 22 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR 25 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE 26 * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE 27 * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 32 * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: sbmac.c,v 1.13 2004/03/08 11:28:48 simonb Exp $"); 37 38 #include "bpfilter.h" 39 #include "opt_inet.h" 40 #include "opt_ns.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/queue.h> 50 #include <sys/device.h> 51 52 #include <net/if.h> 53 #include <net/if_arp.h> 54 #include <net/if_ether.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 58 #if NBPFILTER > 0 59 #include <net/bpf.h> 60 #endif 61 62 #ifdef INET 63 #include <netinet/in.h> 64 #include <netinet/if_inarp.h> 65 #endif 66 67 #ifdef NS 68 #include <netns/ns.h> 69 #include <netns/ns_if.h> 70 #endif 71 72 #include <machine/locore.h> 73 74 #include "sbobiovar.h" 75 76 #include <dev/mii/mii.h> 77 #include <dev/mii/miivar.h> 78 #include <dev/mii/mii_bitbang.h> 79 80 #include <mips/sibyte/include/sb1250_defs.h> 81 #include <mips/sibyte/include/sb1250_regs.h> 82 #include <mips/sibyte/include/sb1250_mac.h> 83 #include <mips/sibyte/include/sb1250_dma.h> 84 #include <mips/sibyte/include/sb1250_scd.h> 85 86 87 /* Simple types */ 88 89 typedef u_long sbmac_port_t; 90 typedef uint64_t sbmac_physaddr_t; 91 typedef uint64_t sbmac_enetaddr_t; 92 93 typedef enum { sbmac_speed_auto, sbmac_speed_10, 94 sbmac_speed_100, sbmac_speed_1000 } sbmac_speed_t; 95 96 typedef enum { sbmac_duplex_auto, sbmac_duplex_half, 97 sbmac_duplex_full } sbmac_duplex_t; 98 99 typedef enum { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame, 100 sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t; 101 102 typedef enum { sbmac_state_uninit, sbmac_state_off, sbmac_state_on, 103 sbmac_state_broken } sbmac_state_t; 104 105 106 /* Macros */ 107 108 #define SBDMA_NEXTBUF(d, f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \ 109 (d)->sbdma_dscrtable : (d)->f+1) 110 111 112 #define CACHELINESIZE 32 113 #define NUMCACHEBLKS(x) (((x)+CACHELINESIZE-1)/CACHELINESIZE) 114 #define KMALLOC(x) malloc((x), M_DEVBUF, M_DONTWAIT) 115 #define KVTOPHYS(x) kvtophys((vaddr_t)(x)) 116 117 #ifdef SBMACDEBUG 118 #define dprintf(x) printf x 119 #else 120 #define dprintf(x) 121 #endif 122 123 #define SBMAC_READCSR(t) mips3_ld((uint64_t *) (t)) 124 #define SBMAC_WRITECSR(t, v) mips3_sd((uint64_t *) (t), (v)) 125 126 #define PKSEG1(x) ((sbmac_port_t) MIPS_PHYS_TO_KSEG1(x)) 127 128 #define SBMAC_MAX_TXDESCR 64 129 #define SBMAC_MAX_RXDESCR 64 130 131 #define ETHER_ALIGN 2 132 133 /* DMA Descriptor structure */ 134 135 typedef struct sbdmadscr_s { 136 uint64_t dscr_a; 137 uint64_t dscr_b; 138 } sbdmadscr_t; 139 140 141 /* DMA Controller structure */ 142 143 typedef struct sbmacdma_s { 144 145 /* 146 * This stuff is used to identify the channel and the registers 147 * associated with it. 148 */ 149 150 struct sbmac_softc *sbdma_eth; /* back pointer to associated MAC */ 151 int sbdma_channel; /* channel number */ 152 int sbdma_txdir; /* direction (1=transmit) */ 153 int sbdma_maxdescr; /* total # of descriptors in ring */ 154 sbmac_port_t sbdma_config0; /* DMA config register 0 */ 155 sbmac_port_t sbdma_config1; /* DMA config register 1 */ 156 sbmac_port_t sbdma_dscrbase; /* Descriptor base address */ 157 sbmac_port_t sbdma_dscrcnt; /* Descriptor count register */ 158 sbmac_port_t sbdma_curdscr; /* current descriptor address */ 159 160 /* 161 * This stuff is for maintenance of the ring 162 */ 163 164 sbdmadscr_t *sbdma_dscrtable; /* base of descriptor table */ 165 sbdmadscr_t *sbdma_dscrtable_end; /* end of descriptor table */ 166 167 struct mbuf **sbdma_ctxtable; /* context table, one per descr */ 168 169 paddr_t sbdma_dscrtable_phys; /* and also the phys addr */ 170 sbdmadscr_t *sbdma_addptr; /* next dscr for sw to add */ 171 sbdmadscr_t *sbdma_remptr; /* next dscr for sw to remove */ 172 } sbmacdma_t; 173 174 175 /* Ethernet softc structure */ 176 177 struct sbmac_softc { 178 179 /* 180 * NetBSD-specific things 181 */ 182 struct device sc_dev; /* base device (must be first) */ 183 struct ethercom sc_ethercom; /* Ethernet common part */ 184 struct mii_data sc_mii; 185 struct callout sc_tick_ch; 186 187 int sbm_if_flags; 188 void *sbm_intrhand; 189 190 /* 191 * Controller-specific things 192 */ 193 194 sbmac_port_t sbm_base; /* MAC's base address */ 195 sbmac_state_t sbm_state; /* current state */ 196 197 sbmac_port_t sbm_macenable; /* MAC Enable Register */ 198 sbmac_port_t sbm_maccfg; /* MAC Configuration Register */ 199 sbmac_port_t sbm_fifocfg; /* FIFO configuration register */ 200 sbmac_port_t sbm_framecfg; /* Frame configuration register */ 201 sbmac_port_t sbm_rxfilter; /* receive filter register */ 202 sbmac_port_t sbm_isr; /* Interrupt status register */ 203 sbmac_port_t sbm_imr; /* Interrupt mask register */ 204 205 sbmac_speed_t sbm_speed; /* current speed */ 206 sbmac_duplex_t sbm_duplex; /* current duplex */ 207 sbmac_fc_t sbm_fc; /* current flow control setting */ 208 int sbm_rxflags; /* received packet flags */ 209 210 u_char sbm_hwaddr[ETHER_ADDR_LEN]; 211 212 sbmacdma_t sbm_txdma; /* for now, only use channel 0 */ 213 sbmacdma_t sbm_rxdma; 214 215 int sbm_pass3_dma; /* chip has pass3 SOC DMA features */ 216 }; 217 218 219 /* Externs */ 220 221 extern paddr_t kvtophys(vaddr_t); 222 223 /* Prototypes */ 224 225 static void sbdma_initctx(sbmacdma_t *d, struct sbmac_softc *s, int chan, 226 int txrx, int maxdescr); 227 static void sbdma_channel_start(sbmacdma_t *d); 228 static int sbdma_add_rcvbuffer(sbmacdma_t *d, struct mbuf *m); 229 static int sbdma_add_txbuffer(sbmacdma_t *d, struct mbuf *m); 230 static void sbdma_emptyring(sbmacdma_t *d); 231 static void sbdma_fillring(sbmacdma_t *d); 232 static void sbdma_rx_process(struct sbmac_softc *sc, sbmacdma_t *d); 233 static void sbdma_tx_process(struct sbmac_softc *sc, sbmacdma_t *d); 234 static void sbmac_initctx(struct sbmac_softc *s); 235 static void sbmac_channel_start(struct sbmac_softc *s); 236 static void sbmac_channel_stop(struct sbmac_softc *s); 237 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *, 238 sbmac_state_t); 239 static void sbmac_promiscuous_mode(struct sbmac_softc *sc, int onoff); 240 static void sbmac_init_and_start(struct sbmac_softc *sc); 241 static uint64_t sbmac_addr2reg(u_char *ptr); 242 static void sbmac_intr(void *xsc, uint32_t status, uint32_t pc); 243 static void sbmac_start(struct ifnet *ifp); 244 static void sbmac_setmulti(struct sbmac_softc *sc); 245 static int sbmac_ether_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 246 static int sbmac_ioctl(struct ifnet *ifp, u_long command, caddr_t data); 247 static int sbmac_mediachange(struct ifnet *ifp); 248 static void sbmac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr); 249 static void sbmac_watchdog(struct ifnet *ifp); 250 static int sbmac_match(struct device *parent, struct cfdata *match, void *aux); 251 static void sbmac_attach(struct device *parent, struct device *self, void *aux); 252 static int sbmac_set_speed(struct sbmac_softc *s, sbmac_speed_t speed); 253 static int sbmac_set_duplex(struct sbmac_softc *s, sbmac_duplex_t duplex, 254 sbmac_fc_t fc); 255 static void sbmac_tick(void *arg); 256 257 258 /* Globals */ 259 260 CFATTACH_DECL(sbmac, sizeof(struct sbmac_softc), 261 sbmac_match, sbmac_attach, NULL, NULL); 262 263 static uint32_t sbmac_mii_bitbang_read(struct device *self); 264 static void sbmac_mii_bitbang_write(struct device *self, uint32_t val); 265 266 static const struct mii_bitbang_ops sbmac_mii_bitbang_ops = { 267 sbmac_mii_bitbang_read, 268 sbmac_mii_bitbang_write, 269 { 270 (uint32_t)M_MAC_MDIO_OUT, /* MII_BIT_MDO */ 271 (uint32_t)M_MAC_MDIO_IN, /* MII_BIT_MDI */ 272 (uint32_t)M_MAC_MDC, /* MII_BIT_MDC */ 273 0, /* MII_BIT_DIR_HOST_PHY */ 274 (uint32_t)M_MAC_MDIO_DIR /* MII_BIT_DIR_PHY_HOST */ 275 } 276 }; 277 278 static uint32_t 279 sbmac_mii_bitbang_read(struct device *self) 280 { 281 struct sbmac_softc *sc = (void *) self; 282 sbmac_port_t reg; 283 284 reg = PKSEG1(sc->sbm_base + R_MAC_MDIO); 285 return (uint32_t) SBMAC_READCSR(reg); 286 } 287 288 static void 289 sbmac_mii_bitbang_write(struct device *self, uint32_t val) 290 { 291 struct sbmac_softc *sc = (void *) self; 292 sbmac_port_t reg; 293 294 reg = PKSEG1(sc->sbm_base + R_MAC_MDIO); 295 296 SBMAC_WRITECSR(reg, (val & 297 (M_MAC_MDC|M_MAC_MDIO_DIR|M_MAC_MDIO_OUT|M_MAC_MDIO_IN))); 298 } 299 300 /* 301 * Read an PHY register through the MII. 302 */ 303 static int 304 sbmac_mii_readreg(struct device *self, int phy, int reg) 305 { 306 307 return (mii_bitbang_readreg(self, &sbmac_mii_bitbang_ops, phy, reg)); 308 } 309 310 /* 311 * Write to a PHY register through the MII. 312 */ 313 static void 314 sbmac_mii_writereg(struct device *self, int phy, int reg, int val) 315 { 316 317 mii_bitbang_writereg(self, &sbmac_mii_bitbang_ops, phy, reg, val); 318 } 319 320 static void 321 sbmac_mii_statchg(struct device *self) 322 { 323 struct sbmac_softc *sc = (struct sbmac_softc *)self; 324 sbmac_state_t oldstate; 325 326 /* Stop the MAC in preparation for changing all of the parameters. */ 327 oldstate = sbmac_set_channel_state(sc, sbmac_state_off); 328 329 switch (sc->sc_ethercom.ec_if.if_baudrate) { 330 default: /* if autonegotiation fails, assume 10Mbit */ 331 case IF_Mbps(10): 332 sbmac_set_speed(sc, sbmac_speed_10); 333 break; 334 335 case IF_Mbps(100): 336 sbmac_set_speed(sc, sbmac_speed_100); 337 break; 338 339 case IF_Mbps(1000): 340 sbmac_set_speed(sc, sbmac_speed_1000); 341 break; 342 } 343 344 if (sc->sc_mii.mii_media_active & IFM_FDX) { 345 /* Configure for full-duplex */ 346 /* XXX: is flow control right for 10, 100? */ 347 sbmac_set_duplex(sc, sbmac_duplex_full, sbmac_fc_frame); 348 } else { 349 /* Configure for half-duplex */ 350 /* XXX: is flow control right? */ 351 sbmac_set_duplex(sc, sbmac_duplex_half, sbmac_fc_disabled); 352 } 353 354 /* And put it back into its former state. */ 355 sbmac_set_channel_state(sc, oldstate); 356 } 357 358 /* 359 * SBDMA_INITCTX(d, s, chan, txrx, maxdescr) 360 * 361 * Initialize a DMA channel context. Since there are potentially 362 * eight DMA channels per MAC, it's nice to do this in a standard 363 * way. 364 * 365 * Input parameters: 366 * d - sbmacdma_t structure (DMA channel context) 367 * s - sbmac_softc structure (pointer to a MAC) 368 * chan - channel number (0..1 right now) 369 * txrx - Identifies DMA_TX or DMA_RX for channel direction 370 * maxdescr - number of descriptors 371 * 372 * Return value: 373 * nothing 374 */ 375 376 static void 377 sbdma_initctx(sbmacdma_t *d, struct sbmac_softc *s, int chan, int txrx, 378 int maxdescr) 379 { 380 /* 381 * Save away interesting stuff in the structure 382 */ 383 384 d->sbdma_eth = s; 385 d->sbdma_channel = chan; 386 d->sbdma_txdir = txrx; 387 388 /* 389 * initialize register pointers 390 */ 391 392 d->sbdma_config0 = PKSEG1(s->sbm_base + 393 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_CONFIG0)); 394 d->sbdma_config1 = PKSEG1(s->sbm_base + 395 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_CONFIG1)); 396 d->sbdma_dscrbase = PKSEG1(s->sbm_base + 397 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_DSCR_BASE)); 398 d->sbdma_dscrcnt = PKSEG1(s->sbm_base + 399 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_DSCR_CNT)); 400 d->sbdma_curdscr = PKSEG1(s->sbm_base + 401 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_CUR_DSCRADDR)); 402 403 /* 404 * Allocate memory for the ring 405 */ 406 407 d->sbdma_maxdescr = maxdescr; 408 409 d->sbdma_dscrtable = (sbdmadscr_t *) 410 KMALLOC(d->sbdma_maxdescr*sizeof(sbdmadscr_t)); 411 412 bzero(d->sbdma_dscrtable, d->sbdma_maxdescr*sizeof(sbdmadscr_t)); 413 414 d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr; 415 416 d->sbdma_dscrtable_phys = KVTOPHYS(d->sbdma_dscrtable); 417 418 /* 419 * And context table 420 */ 421 422 d->sbdma_ctxtable = (struct mbuf **) 423 KMALLOC(d->sbdma_maxdescr*sizeof(struct mbuf *)); 424 425 bzero(d->sbdma_ctxtable, d->sbdma_maxdescr*sizeof(struct mbuf *)); 426 } 427 428 /* 429 * SBDMA_CHANNEL_START(d) 430 * 431 * Initialize the hardware registers for a DMA channel. 432 * 433 * Input parameters: 434 * d - DMA channel to init (context must be previously init'd 435 * 436 * Return value: 437 * nothing 438 */ 439 440 static void 441 sbdma_channel_start(sbmacdma_t *d) 442 { 443 /* 444 * Turn on the DMA channel 445 */ 446 447 SBMAC_WRITECSR(d->sbdma_config1, 0); 448 449 SBMAC_WRITECSR(d->sbdma_dscrbase, d->sbdma_dscrtable_phys); 450 451 SBMAC_WRITECSR(d->sbdma_config0, V_DMA_RINGSZ(d->sbdma_maxdescr) | 0); 452 453 /* 454 * Initialize ring pointers 455 */ 456 457 d->sbdma_addptr = d->sbdma_dscrtable; 458 d->sbdma_remptr = d->sbdma_dscrtable; 459 } 460 461 /* 462 * SBDMA_ADD_RCVBUFFER(d, m) 463 * 464 * Add a buffer to the specified DMA channel. For receive channels, 465 * this queues a buffer for inbound packets. 466 * 467 * Input parameters: 468 * d - DMA channel descriptor 469 * m - mbuf to add, or NULL if we should allocate one. 470 * 471 * Return value: 472 * 0 if buffer could not be added (ring is full) 473 * 1 if buffer added successfully 474 */ 475 476 static int 477 sbdma_add_rcvbuffer(sbmacdma_t *d, struct mbuf *m) 478 { 479 sbdmadscr_t *dsc; 480 sbdmadscr_t *nextdsc; 481 struct mbuf *m_new = NULL; 482 483 /* get pointer to our current place in the ring */ 484 485 dsc = d->sbdma_addptr; 486 nextdsc = SBDMA_NEXTBUF(d, sbdma_addptr); 487 488 /* 489 * figure out if the ring is full - if the next descriptor 490 * is the same as the one that we're going to remove from 491 * the ring, the ring is full 492 */ 493 494 if (nextdsc == d->sbdma_remptr) 495 return ENOSPC; 496 497 /* 498 * Allocate an mbuf if we don't already have one. 499 * If we do have an mbuf, reset it so that it's empty. 500 */ 501 502 if (m == NULL) { 503 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 504 if (m_new == NULL) { 505 printf("%s: mbuf allocation failed\n", 506 d->sbdma_eth->sc_dev.dv_xname); 507 return ENOBUFS; 508 } 509 510 MCLGET(m_new, M_DONTWAIT); 511 if (!(m_new->m_flags & M_EXT)) { 512 printf("%s: mbuf cluster allocation failed\n", 513 d->sbdma_eth->sc_dev.dv_xname); 514 m_freem(m_new); 515 return ENOBUFS; 516 } 517 518 m_new->m_len = m_new->m_pkthdr.len= MCLBYTES; 519 m_adj(m_new, ETHER_ALIGN); 520 } else { 521 m_new = m; 522 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 523 m_new->m_data = m_new->m_ext.ext_buf; 524 m_adj(m_new, ETHER_ALIGN); 525 } 526 527 /* 528 * fill in the descriptor 529 */ 530 531 dsc->dscr_a = KVTOPHYS(mtod(m_new, caddr_t)) | 532 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(ETHER_ALIGN + m_new->m_len)) | 533 M_DMA_DSCRA_INTERRUPT; 534 535 /* receiving: no options */ 536 dsc->dscr_b = 0; 537 538 /* 539 * fill in the context 540 */ 541 542 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = m_new; 543 544 /* 545 * point at next packet 546 */ 547 548 d->sbdma_addptr = nextdsc; 549 550 /* 551 * Give the buffer to the DMA engine. 552 */ 553 554 SBMAC_WRITECSR(d->sbdma_dscrcnt, 1); 555 556 return 0; /* we did it */ 557 } 558 559 /* 560 * SBDMA_ADD_TXBUFFER(d, m) 561 * 562 * Add a transmit buffer to the specified DMA channel, causing a 563 * transmit to start. 564 * 565 * Input parameters: 566 * d - DMA channel descriptor 567 * m - mbuf to add 568 * 569 * Return value: 570 * 0 transmit queued successfully 571 * otherwise error code 572 */ 573 574 static int 575 sbdma_add_txbuffer(sbmacdma_t *d, struct mbuf *m) 576 { 577 sbdmadscr_t *dsc; 578 sbdmadscr_t *nextdsc; 579 sbdmadscr_t *prevdsc; 580 sbdmadscr_t *origdesc; 581 int length; 582 int num_mbufs = 0; 583 struct sbmac_softc *sc = d->sbdma_eth; 584 585 /* get pointer to our current place in the ring */ 586 587 dsc = d->sbdma_addptr; 588 nextdsc = SBDMA_NEXTBUF(d, sbdma_addptr); 589 590 /* 591 * figure out if the ring is full - if the next descriptor 592 * is the same as the one that we're going to remove from 593 * the ring, the ring is full 594 */ 595 596 if (nextdsc == d->sbdma_remptr) 597 return ENOSPC; 598 599 #if 0 600 do { 601 struct mbuf *m0; 602 603 printf("mbuf chain: "); 604 for (m0 = m; m0 != 0; m0 = m0->m_next) { 605 printf("%d%c/%X ", m0->m_len, 606 m0->m_flags & M_EXT ? 'X' : 'N', 607 mtod(m0, u_int)); 608 } 609 printf("\n"); 610 } while (0); 611 #endif 612 613 /* 614 * PASS3 parts do not have buffer alignment restriction. 615 * No need to copy/coalesce to new mbuf. Also has different 616 * descriptor format 617 */ 618 if (sc->sbm_pass3_dma) { 619 struct mbuf *m_temp = NULL; 620 621 /* 622 * Loop thru this mbuf record. 623 * The head mbuf will have SOP set. 624 */ 625 dsc->dscr_a = KVTOPHYS(mtod(m,caddr_t)) | 626 M_DMA_DSCRA_INTERRUPT | 627 M_DMA_ETHTX_SOP; 628 629 /* 630 * transmitting: set outbound options,buffer A size(+ low 5 631 * bits of start addr),and packet length. 632 */ 633 dsc->dscr_b = 634 V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) | 635 V_DMA_DSCRB_A_SIZE((m->m_len + (mtod(m,unsigned int) & 0x0000001F))) | 636 V_DMA_DSCRB_PKT_SIZE_MSB( (m->m_pkthdr.len & 0xB000) ) | 637 V_DMA_DSCRB_PKT_SIZE(m->m_pkthdr.len); 638 639 d->sbdma_addptr = nextdsc; 640 origdesc = prevdsc = dsc; 641 dsc = d->sbdma_addptr; 642 num_mbufs++; 643 644 /* Start with first non-head mbuf */ 645 for(m_temp = m->m_next; m_temp != 0; m_temp = m_temp->m_next) { 646 647 if (m_temp->m_len == 0) 648 continue; /* Skip 0-length mbufs */ 649 650 /* 651 * fill in the descriptor 652 */ 653 654 dsc->dscr_a = KVTOPHYS(mtod(m_temp,caddr_t)) | 655 M_DMA_DSCRA_INTERRUPT; 656 657 /* 658 * transmitting: set outbound options,buffer A 659 * size(+ low 5 bits of start addr) 660 */ 661 dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_NOTSOP) | 662 V_DMA_DSCRB_A_SIZE( (m_temp->m_len + 663 (mtod(m_temp,unsigned int) & 0x0000001F)) ); 664 665 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = NULL; 666 667 /* 668 * point at next descriptor 669 */ 670 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr); 671 if (nextdsc == d->sbdma_remptr) { 672 d->sbdma_addptr = origdesc; 673 return ENOSPC; 674 } 675 d->sbdma_addptr = nextdsc; 676 677 prevdsc = dsc; 678 dsc = d->sbdma_addptr; 679 num_mbufs++; 680 } 681 682 /*Set head mbuf to last context index*/ 683 d->sbdma_ctxtable[prevdsc-d->sbdma_dscrtable] = m; 684 } else { 685 struct mbuf *m_new = NULL; 686 /* 687 * [BEGIN XXX] 688 * XXX Copy/coalesce the mbufs into a single mbuf cluster (we 689 * assume it will fit). This is a temporary hack to get us 690 * going. 691 */ 692 693 MGETHDR(m_new,M_DONTWAIT,MT_DATA); 694 if (m_new == NULL) { 695 printf("%s: mbuf allocation failed\n", 696 d->sbdma_eth->sc_dev.dv_xname); 697 return ENOBUFS; 698 } 699 700 MCLGET(m_new,M_DONTWAIT); 701 if (!(m_new->m_flags & M_EXT)) { 702 printf("%s: mbuf cluster allocation failed\n", 703 d->sbdma_eth->sc_dev.dv_xname); 704 m_freem(m_new); 705 return ENOBUFS; 706 } 707 708 m_new->m_len = m_new->m_pkthdr.len= MCLBYTES; 709 /*m_adj(m_new,ETHER_ALIGN);*/ 710 711 /* 712 * XXX Don't forget to include the offset portion in the 713 * XXX cache block calculation when this code is rewritten! 714 */ 715 716 /* 717 * Copy data 718 */ 719 720 m_copydata(m,0,m->m_pkthdr.len,mtod(m_new,caddr_t)); 721 m_new->m_len = m_new->m_pkthdr.len = m->m_pkthdr.len; 722 723 /* Free old mbuf 'm', actual mbuf is now 'm_new' */ 724 725 // XXX: CALLERS WILL FREE, they might have to bpf_mtap() if this 726 // XXX: function succeeds. 727 // m_freem(m); 728 length = m_new->m_len; 729 730 /* [END XXX] */ 731 /* 732 * fill in the descriptor 733 */ 734 735 dsc->dscr_a = KVTOPHYS(mtod(m_new,caddr_t)) | 736 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(m_new->m_len)) | 737 M_DMA_DSCRA_INTERRUPT | 738 M_DMA_ETHTX_SOP; 739 740 /* transmitting: set outbound options and length */ 741 dsc->dscr_b = 742 V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) | 743 V_DMA_DSCRB_PKT_SIZE(length); 744 745 num_mbufs++; 746 747 /* 748 * fill in the context 749 */ 750 751 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = m_new; 752 753 /* 754 * point at next packet 755 */ 756 d->sbdma_addptr = nextdsc; 757 } 758 759 /* 760 * Give the buffer to the DMA engine. 761 */ 762 763 SBMAC_WRITECSR(d->sbdma_dscrcnt, num_mbufs); 764 765 return 0; /* we did it */ 766 } 767 768 /* 769 * SBDMA_EMPTYRING(d) 770 * 771 * Free all allocated mbufs on the specified DMA channel; 772 * 773 * Input parameters: 774 * d - DMA channel 775 * 776 * Return value: 777 * nothing 778 */ 779 780 static void 781 sbdma_emptyring(sbmacdma_t *d) 782 { 783 int idx; 784 struct mbuf *m; 785 786 for (idx = 0; idx < d->sbdma_maxdescr; idx++) { 787 m = d->sbdma_ctxtable[idx]; 788 if (m) { 789 m_freem(m); 790 d->sbdma_ctxtable[idx] = NULL; 791 } 792 } 793 } 794 795 /* 796 * SBDMA_FILLRING(d) 797 * 798 * Fill the specified DMA channel (must be receive channel) 799 * with mbufs 800 * 801 * Input parameters: 802 * d - DMA channel 803 * 804 * Return value: 805 * nothing 806 */ 807 808 static void 809 sbdma_fillring(sbmacdma_t *d) 810 { 811 int idx; 812 813 for (idx = 0; idx < SBMAC_MAX_RXDESCR-1; idx++) 814 if (sbdma_add_rcvbuffer(d, NULL) != 0) 815 break; 816 } 817 818 /* 819 * SBDMA_RX_PROCESS(sc, d) 820 * 821 * Process "completed" receive buffers on the specified DMA channel. 822 * Note that this isn't really ideal for priority channels, since 823 * it processes all of the packets on a given channel before 824 * returning. 825 * 826 * Input parameters: 827 * sc - softc structure 828 * d - DMA channel context 829 * 830 * Return value: 831 * nothing 832 */ 833 834 static void 835 sbdma_rx_process(struct sbmac_softc *sc, sbmacdma_t *d) 836 { 837 int curidx; 838 int hwidx; 839 sbdmadscr_t *dsc; 840 struct mbuf *m; 841 int len; 842 843 struct ifnet *ifp = &(sc->sc_ethercom.ec_if); 844 845 for (;;) { 846 /* 847 * figure out where we are (as an index) and where 848 * the hardware is (also as an index) 849 * 850 * This could be done faster if (for example) the 851 * descriptor table was page-aligned and contiguous in 852 * both virtual and physical memory -- you could then 853 * just compare the low-order bits of the virtual address 854 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) 855 */ 856 857 curidx = d->sbdma_remptr - d->sbdma_dscrtable; 858 hwidx = (int) 859 (((SBMAC_READCSR(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - 860 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t)); 861 862 /* 863 * If they're the same, that means we've processed all 864 * of the descriptors up to (but not including) the one that 865 * the hardware is working on right now. 866 */ 867 868 if (curidx == hwidx) 869 break; 870 871 /* 872 * Otherwise, get the packet's mbuf ptr back 873 */ 874 875 dsc = &(d->sbdma_dscrtable[curidx]); 876 m = d->sbdma_ctxtable[curidx]; 877 d->sbdma_ctxtable[curidx] = NULL; 878 879 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4; 880 881 /* 882 * Check packet status. If good, process it. 883 * If not, silently drop it and put it back on the 884 * receive ring. 885 */ 886 887 if (! (dsc->dscr_a & M_DMA_ETHRX_BAD)) { 888 889 /* 890 * Set length into the packet 891 * XXX do we remove the CRC here? 892 */ 893 m->m_pkthdr.len = m->m_len = len; 894 895 ifp->if_ipackets++; 896 m->m_pkthdr.rcvif = ifp; 897 898 899 /* 900 * Add a new buffer to replace the old one. 901 */ 902 sbdma_add_rcvbuffer(d, NULL); 903 904 #if (NBPFILTER > 0) 905 /* 906 * Handle BPF listeners. Let the BPF user see the 907 * packet, but don't pass it up to the ether_input() 908 * layer unless it's a broadcast packet, multicast 909 * packet, matches our ethernet address or the 910 * interface is in promiscuous mode. 911 */ 912 913 if (ifp->if_bpf) 914 bpf_mtap(ifp->if_bpf, m); 915 #endif 916 /* 917 * Pass the buffer to the kernel 918 */ 919 (*ifp->if_input)(ifp, m); 920 } else { 921 /* 922 * Packet was mangled somehow. Just drop it and 923 * put it back on the receive ring. 924 */ 925 sbdma_add_rcvbuffer(d, m); 926 } 927 928 /* 929 * .. and advance to the next buffer. 930 */ 931 932 d->sbdma_remptr = SBDMA_NEXTBUF(d, sbdma_remptr); 933 } 934 } 935 936 /* 937 * SBDMA_TX_PROCESS(sc, d) 938 * 939 * Process "completed" transmit buffers on the specified DMA channel. 940 * This is normally called within the interrupt service routine. 941 * Note that this isn't really ideal for priority channels, since 942 * it processes all of the packets on a given channel before 943 * returning. 944 * 945 * Input parameters: 946 * sc - softc structure 947 * d - DMA channel context 948 * 949 * Return value: 950 * nothing 951 */ 952 953 static void 954 sbdma_tx_process(struct sbmac_softc *sc, sbmacdma_t *d) 955 { 956 int curidx; 957 int hwidx; 958 struct mbuf *m; 959 960 struct ifnet *ifp = &(sc->sc_ethercom.ec_if); 961 962 for (;;) { 963 /* 964 * figure out where we are (as an index) and where 965 * the hardware is (also as an index) 966 * 967 * This could be done faster if (for example) the 968 * descriptor table was page-aligned and contiguous in 969 * both virtual and physical memory -- you could then 970 * just compare the low-order bits of the virtual address 971 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) 972 */ 973 974 curidx = d->sbdma_remptr - d->sbdma_dscrtable; 975 hwidx = (int) 976 (((SBMAC_READCSR(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - 977 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t)); 978 979 /* 980 * If they're the same, that means we've processed all 981 * of the descriptors up to (but not including) the one that 982 * the hardware is working on right now. 983 */ 984 985 if (curidx == hwidx) 986 break; 987 988 /* 989 * Otherwise, get the packet's mbuf ptr back 990 */ 991 992 m = d->sbdma_ctxtable[curidx]; 993 d->sbdma_ctxtable[curidx] = NULL; 994 995 /* 996 * for transmits, we just free buffers. 997 */ 998 999 m_freem(m); 1000 1001 /* 1002 * .. and advance to the next buffer. 1003 */ 1004 1005 d->sbdma_remptr = SBDMA_NEXTBUF(d, sbdma_remptr); 1006 } 1007 1008 /* 1009 * Decide what to set the IFF_OACTIVE bit in the interface to. 1010 * It's supposed to reflect if the interface is actively 1011 * transmitting, but that's really hard to do quickly. 1012 */ 1013 1014 ifp->if_flags &= ~IFF_OACTIVE; 1015 } 1016 1017 /* 1018 * SBMAC_INITCTX(s) 1019 * 1020 * Initialize an Ethernet context structure - this is called 1021 * once per MAC on the 1250. Memory is allocated here, so don't 1022 * call it again from inside the ioctl routines that bring the 1023 * interface up/down 1024 * 1025 * Input parameters: 1026 * s - sbmac context structure 1027 * 1028 * Return value: 1029 * 0 1030 */ 1031 1032 static void 1033 sbmac_initctx(struct sbmac_softc *s) 1034 { 1035 uint64_t sysrev; 1036 1037 /* 1038 * figure out the addresses of some ports 1039 */ 1040 1041 s->sbm_macenable = PKSEG1(s->sbm_base + R_MAC_ENABLE); 1042 s->sbm_maccfg = PKSEG1(s->sbm_base + R_MAC_CFG); 1043 s->sbm_fifocfg = PKSEG1(s->sbm_base + R_MAC_THRSH_CFG); 1044 s->sbm_framecfg = PKSEG1(s->sbm_base + R_MAC_FRAMECFG); 1045 s->sbm_rxfilter = PKSEG1(s->sbm_base + R_MAC_ADFILTER_CFG); 1046 s->sbm_isr = PKSEG1(s->sbm_base + R_MAC_STATUS); 1047 s->sbm_imr = PKSEG1(s->sbm_base + R_MAC_INT_MASK); 1048 1049 /* 1050 * Initialize the DMA channels. Right now, only one per MAC is used 1051 * Note: Only do this _once_, as it allocates memory from the kernel! 1052 */ 1053 1054 sbdma_initctx(&(s->sbm_txdma), s, 0, DMA_TX, SBMAC_MAX_TXDESCR); 1055 sbdma_initctx(&(s->sbm_rxdma), s, 0, DMA_RX, SBMAC_MAX_RXDESCR); 1056 1057 /* 1058 * initial state is OFF 1059 */ 1060 1061 s->sbm_state = sbmac_state_off; 1062 1063 /* 1064 * Initial speed is (XXX TEMP) 10MBit/s HDX no FC 1065 */ 1066 1067 s->sbm_speed = sbmac_speed_10; 1068 s->sbm_duplex = sbmac_duplex_half; 1069 s->sbm_fc = sbmac_fc_disabled; 1070 1071 /* 1072 * Determine SOC type. 112x has Pass3 SOC features. 1073 */ 1074 sysrev = SBMAC_READCSR( PKSEG1(A_SCD_SYSTEM_REVISION) ); 1075 s->sbm_pass3_dma = (SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1120 || 1076 SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1125 || 1077 SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1125H || 1078 (SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250 && 1079 0)); 1080 if (s->sbm_pass3_dma) { 1081 printf("\n"); 1082 printf("%s: disabling unaligned tx DMA\n", s->sc_dev.dv_xname); 1083 printf("%s", s->sc_dev.dv_xname); 1084 s->sbm_pass3_dma = 0; 1085 } 1086 } 1087 1088 /* 1089 * SBMAC_CHANNEL_START(s) 1090 * 1091 * Start packet processing on this MAC. 1092 * 1093 * Input parameters: 1094 * s - sbmac structure 1095 * 1096 * Return value: 1097 * nothing 1098 */ 1099 1100 static void 1101 sbmac_channel_start(struct sbmac_softc *s) 1102 { 1103 uint64_t reg; 1104 sbmac_port_t port; 1105 uint64_t cfg, fifo, framecfg; 1106 int idx; 1107 uint64_t dma_cfg0, fifo_cfg; 1108 sbmacdma_t *txdma; 1109 1110 /* 1111 * Don't do this if running 1112 */ 1113 1114 if (s->sbm_state == sbmac_state_on) 1115 return; 1116 1117 /* 1118 * Bring the controller out of reset, but leave it off. 1119 */ 1120 1121 SBMAC_WRITECSR(s->sbm_macenable, 0); 1122 1123 /* 1124 * Ignore all received packets 1125 */ 1126 1127 SBMAC_WRITECSR(s->sbm_rxfilter, 0); 1128 1129 /* 1130 * Calculate values for various control registers. 1131 */ 1132 1133 cfg = M_MAC_RETRY_EN | 1134 M_MAC_TX_HOLD_SOP_EN | 1135 V_MAC_TX_PAUSE_CNT_16K | 1136 M_MAC_AP_STAT_EN | 1137 M_MAC_SS_EN | 1138 0; 1139 1140 fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */ 1141 V_MAC_TX_RD_THRSH(4) | 1142 V_MAC_TX_RL_THRSH(4) | 1143 V_MAC_RX_PL_THRSH(4) | 1144 V_MAC_RX_RD_THRSH(4) | /* Must be '4' */ 1145 V_MAC_RX_PL_THRSH(4) | 1146 V_MAC_RX_RL_THRSH(8) | 1147 0; 1148 1149 framecfg = V_MAC_MIN_FRAMESZ_DEFAULT | 1150 V_MAC_MAX_FRAMESZ_DEFAULT | 1151 V_MAC_BACKOFF_SEL(1); 1152 1153 /* 1154 * Clear out the hash address map 1155 */ 1156 1157 port = PKSEG1(s->sbm_base + R_MAC_HASH_BASE); 1158 for (idx = 0; idx < MAC_HASH_COUNT; idx++) { 1159 SBMAC_WRITECSR(port, 0); 1160 port += sizeof(uint64_t); 1161 } 1162 1163 /* 1164 * Clear out the exact-match table 1165 */ 1166 1167 port = PKSEG1(s->sbm_base + R_MAC_ADDR_BASE); 1168 for (idx = 0; idx < MAC_ADDR_COUNT; idx++) { 1169 SBMAC_WRITECSR(port, 0); 1170 port += sizeof(uint64_t); 1171 } 1172 1173 /* 1174 * Clear out the DMA Channel mapping table registers 1175 */ 1176 1177 port = PKSEG1(s->sbm_base + R_MAC_CHUP0_BASE); 1178 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { 1179 SBMAC_WRITECSR(port, 0); 1180 port += sizeof(uint64_t); 1181 } 1182 1183 port = PKSEG1(s->sbm_base + R_MAC_CHLO0_BASE); 1184 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { 1185 SBMAC_WRITECSR(port, 0); 1186 port += sizeof(uint64_t); 1187 } 1188 1189 /* 1190 * Program the hardware address. It goes into the hardware-address 1191 * register as well as the first filter register. 1192 */ 1193 1194 reg = sbmac_addr2reg(s->sbm_hwaddr); 1195 1196 port = PKSEG1(s->sbm_base + R_MAC_ADDR_BASE); 1197 SBMAC_WRITECSR(port, reg); 1198 port = PKSEG1(s->sbm_base + R_MAC_ETHERNET_ADDR); 1199 SBMAC_WRITECSR(port, 0); // pass1 workaround 1200 1201 /* 1202 * Set the receive filter for no packets, and write values 1203 * to the various config registers 1204 */ 1205 1206 SBMAC_WRITECSR(s->sbm_rxfilter, 0); 1207 SBMAC_WRITECSR(s->sbm_imr, 0); 1208 SBMAC_WRITECSR(s->sbm_framecfg, framecfg); 1209 SBMAC_WRITECSR(s->sbm_fifocfg, fifo); 1210 SBMAC_WRITECSR(s->sbm_maccfg, cfg); 1211 1212 /* 1213 * Initialize DMA channels (rings should be ok now) 1214 */ 1215 1216 sbdma_channel_start(&(s->sbm_rxdma)); 1217 sbdma_channel_start(&(s->sbm_txdma)); 1218 1219 /* 1220 * Configure the speed, duplex, and flow control 1221 */ 1222 1223 sbmac_set_speed(s, s->sbm_speed); 1224 sbmac_set_duplex(s, s->sbm_duplex, s->sbm_fc); 1225 1226 /* 1227 * Fill the receive ring 1228 */ 1229 1230 sbdma_fillring(&(s->sbm_rxdma)); 1231 1232 /* 1233 * Turn on the rest of the bits in the enable register 1234 */ 1235 1236 SBMAC_WRITECSR(s->sbm_macenable, M_MAC_RXDMA_EN0 | M_MAC_TXDMA_EN0 | 1237 M_MAC_RX_ENABLE | M_MAC_TX_ENABLE); 1238 1239 1240 /* 1241 * Accept any kind of interrupt on TX and RX DMA channel 0 1242 */ 1243 SBMAC_WRITECSR(s->sbm_imr, 1244 (M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | 1245 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)); 1246 1247 /* 1248 * Enable receiving unicasts and broadcasts 1249 */ 1250 1251 SBMAC_WRITECSR(s->sbm_rxfilter, M_MAC_UCAST_EN | M_MAC_BCAST_EN); 1252 1253 /* 1254 * On chips which support unaligned DMA features, set the descriptor 1255 * ring for transmit channels to use the unaligned buffer format. 1256 */ 1257 txdma = &(s->sbm_txdma); 1258 1259 if (s->sbm_pass3_dma) { 1260 dma_cfg0 = SBMAC_READCSR(txdma->sbdma_config0); 1261 dma_cfg0 |= V_DMA_DESC_TYPE(K_DMA_DESC_TYPE_RING_UAL_RMW) | 1262 M_DMA_TBX_EN | M_DMA_TDX_EN; 1263 SBMAC_WRITECSR(txdma->sbdma_config0,dma_cfg0); 1264 1265 fifo_cfg = SBMAC_READCSR(s->sbm_fifocfg); 1266 fifo_cfg |= V_MAC_TX_WR_THRSH(8) | 1267 V_MAC_TX_RD_THRSH(8) | V_MAC_TX_RL_THRSH(8); 1268 SBMAC_WRITECSR(s->sbm_fifocfg,fifo_cfg); 1269 } 1270 1271 /* 1272 * we're running now. 1273 */ 1274 1275 s->sbm_state = sbmac_state_on; 1276 s->sc_ethercom.ec_if.if_flags |= IFF_RUNNING; 1277 1278 /* 1279 * Program multicast addresses 1280 */ 1281 1282 sbmac_setmulti(s); 1283 1284 /* 1285 * If channel was in promiscuous mode before, turn that on 1286 */ 1287 1288 if (s->sc_ethercom.ec_if.if_flags & IFF_PROMISC) 1289 sbmac_promiscuous_mode(s, 1); 1290 1291 /* 1292 * Turn on the once-per-second timer 1293 */ 1294 1295 callout_reset(&(s->sc_tick_ch), hz, sbmac_tick, s); 1296 } 1297 1298 /* 1299 * SBMAC_CHANNEL_STOP(s) 1300 * 1301 * Stop packet processing on this MAC. 1302 * 1303 * Input parameters: 1304 * s - sbmac structure 1305 * 1306 * Return value: 1307 * nothing 1308 */ 1309 1310 static void 1311 sbmac_channel_stop(struct sbmac_softc *s) 1312 { 1313 uint64_t ctl; 1314 1315 /* don't do this if already stopped */ 1316 1317 if (s->sbm_state == sbmac_state_off) 1318 return; 1319 1320 /* don't accept any packets, disable all interrupts */ 1321 1322 SBMAC_WRITECSR(s->sbm_rxfilter, 0); 1323 SBMAC_WRITECSR(s->sbm_imr, 0); 1324 1325 /* Turn off ticker */ 1326 1327 callout_stop(&(s->sc_tick_ch)); 1328 1329 /* turn off receiver and transmitter */ 1330 1331 ctl = SBMAC_READCSR(s->sbm_macenable); 1332 ctl &= ~(M_MAC_RXDMA_EN0 | M_MAC_TXDMA_EN0); 1333 SBMAC_WRITECSR(s->sbm_macenable, ctl); 1334 1335 /* We're stopped now. */ 1336 1337 s->sbm_state = sbmac_state_off; 1338 s->sc_ethercom.ec_if.if_flags &= ~IFF_RUNNING; 1339 1340 /* Empty the receive and transmit rings */ 1341 1342 sbdma_emptyring(&(s->sbm_rxdma)); 1343 sbdma_emptyring(&(s->sbm_txdma)); 1344 } 1345 1346 /* 1347 * SBMAC_SET_CHANNEL_STATE(state) 1348 * 1349 * Set the channel's state ON or OFF 1350 * 1351 * Input parameters: 1352 * state - new state 1353 * 1354 * Return value: 1355 * old state 1356 */ 1357 1358 static sbmac_state_t 1359 sbmac_set_channel_state(struct sbmac_softc *sc, sbmac_state_t state) 1360 { 1361 sbmac_state_t oldstate = sc->sbm_state; 1362 1363 /* 1364 * If same as previous state, return 1365 */ 1366 1367 if (state == oldstate) 1368 return oldstate; 1369 1370 /* 1371 * If new state is ON, turn channel on 1372 */ 1373 1374 if (state == sbmac_state_on) 1375 sbmac_channel_start(sc); 1376 else 1377 sbmac_channel_stop(sc); 1378 1379 /* 1380 * Return previous state 1381 */ 1382 1383 return oldstate; 1384 } 1385 1386 /* 1387 * SBMAC_PROMISCUOUS_MODE(sc, onoff) 1388 * 1389 * Turn on or off promiscuous mode 1390 * 1391 * Input parameters: 1392 * sc - softc 1393 * onoff - 1 to turn on, 0 to turn off 1394 * 1395 * Return value: 1396 * nothing 1397 */ 1398 1399 static void 1400 sbmac_promiscuous_mode(struct sbmac_softc *sc, int onoff) 1401 { 1402 uint64_t reg; 1403 1404 if (sc->sbm_state != sbmac_state_on) 1405 return; 1406 1407 if (onoff) { 1408 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1409 reg |= M_MAC_ALLPKT_EN; 1410 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1411 } else { 1412 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1413 reg &= ~M_MAC_ALLPKT_EN; 1414 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1415 } 1416 } 1417 1418 /* 1419 * SBMAC_INIT_AND_START(sc) 1420 * 1421 * Stop the channel and restart it. This is generally used 1422 * when we have to do something to the channel that requires 1423 * a swift kick. 1424 * 1425 * Input parameters: 1426 * sc - softc 1427 */ 1428 1429 static void 1430 sbmac_init_and_start(struct sbmac_softc *sc) 1431 { 1432 int s; 1433 1434 s = splnet(); 1435 1436 mii_pollstat(&sc->sc_mii); /* poll phy for current speed */ 1437 sbmac_mii_statchg((struct device *) sc); /* set state to new speed */ 1438 sbmac_set_channel_state(sc, sbmac_state_on); 1439 1440 splx(s); 1441 } 1442 1443 /* 1444 * SBMAC_ADDR2REG(ptr) 1445 * 1446 * Convert six bytes into the 64-bit register value that 1447 * we typically write into the SBMAC's address/mcast registers 1448 * 1449 * Input parameters: 1450 * ptr - pointer to 6 bytes 1451 * 1452 * Return value: 1453 * register value 1454 */ 1455 1456 static uint64_t 1457 sbmac_addr2reg(u_char *ptr) 1458 { 1459 uint64_t reg = 0; 1460 1461 ptr += 6; 1462 1463 reg |= (uint64_t) *(--ptr); 1464 reg <<= 8; 1465 reg |= (uint64_t) *(--ptr); 1466 reg <<= 8; 1467 reg |= (uint64_t) *(--ptr); 1468 reg <<= 8; 1469 reg |= (uint64_t) *(--ptr); 1470 reg <<= 8; 1471 reg |= (uint64_t) *(--ptr); 1472 reg <<= 8; 1473 reg |= (uint64_t) *(--ptr); 1474 1475 return reg; 1476 } 1477 1478 /* 1479 * SBMAC_SET_SPEED(s, speed) 1480 * 1481 * Configure LAN speed for the specified MAC. 1482 * Warning: must be called when MAC is off! 1483 * 1484 * Input parameters: 1485 * s - sbmac structure 1486 * speed - speed to set MAC to (see sbmac_speed_t enum) 1487 * 1488 * Return value: 1489 * 1 if successful 1490 * 0 indicates invalid parameters 1491 */ 1492 1493 static int 1494 sbmac_set_speed(struct sbmac_softc *s, sbmac_speed_t speed) 1495 { 1496 uint64_t cfg; 1497 uint64_t framecfg; 1498 1499 /* 1500 * Save new current values 1501 */ 1502 1503 s->sbm_speed = speed; 1504 1505 if (s->sbm_state != sbmac_state_off) 1506 panic("sbmac_set_speed while MAC not off"); 1507 1508 /* 1509 * Read current register values 1510 */ 1511 1512 cfg = SBMAC_READCSR(s->sbm_maccfg); 1513 framecfg = SBMAC_READCSR(s->sbm_framecfg); 1514 1515 /* 1516 * Mask out the stuff we want to change 1517 */ 1518 1519 cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL); 1520 framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH | 1521 M_MAC_SLOT_SIZE); 1522 1523 /* 1524 * Now add in the new bits 1525 */ 1526 1527 switch (speed) { 1528 case sbmac_speed_10: 1529 framecfg |= V_MAC_IFG_RX_10 | 1530 V_MAC_IFG_TX_10 | 1531 K_MAC_IFG_THRSH_10 | 1532 V_MAC_SLOT_SIZE_10; 1533 cfg |= V_MAC_SPEED_SEL_10MBPS; 1534 break; 1535 1536 case sbmac_speed_100: 1537 framecfg |= V_MAC_IFG_RX_100 | 1538 V_MAC_IFG_TX_100 | 1539 V_MAC_IFG_THRSH_100 | 1540 V_MAC_SLOT_SIZE_100; 1541 cfg |= V_MAC_SPEED_SEL_100MBPS ; 1542 break; 1543 1544 case sbmac_speed_1000: 1545 framecfg |= V_MAC_IFG_RX_1000 | 1546 V_MAC_IFG_TX_1000 | 1547 V_MAC_IFG_THRSH_1000 | 1548 V_MAC_SLOT_SIZE_1000; 1549 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN; 1550 break; 1551 1552 case sbmac_speed_auto: /* XXX not implemented */ 1553 /* fall through */ 1554 default: 1555 return 0; 1556 } 1557 1558 /* 1559 * Send the bits back to the hardware 1560 */ 1561 1562 SBMAC_WRITECSR(s->sbm_framecfg, framecfg); 1563 SBMAC_WRITECSR(s->sbm_maccfg, cfg); 1564 1565 return 1; 1566 } 1567 1568 /* 1569 * SBMAC_SET_DUPLEX(s, duplex, fc) 1570 * 1571 * Set Ethernet duplex and flow control options for this MAC 1572 * Warning: must be called when MAC is off! 1573 * 1574 * Input parameters: 1575 * s - sbmac structure 1576 * duplex - duplex setting (see sbmac_duplex_t) 1577 * fc - flow control setting (see sbmac_fc_t) 1578 * 1579 * Return value: 1580 * 1 if ok 1581 * 0 if an invalid parameter combination was specified 1582 */ 1583 1584 static int 1585 sbmac_set_duplex(struct sbmac_softc *s, sbmac_duplex_t duplex, sbmac_fc_t fc) 1586 { 1587 uint64_t cfg; 1588 1589 /* 1590 * Save new current values 1591 */ 1592 1593 s->sbm_duplex = duplex; 1594 s->sbm_fc = fc; 1595 1596 if (s->sbm_state != sbmac_state_off) 1597 panic("sbmac_set_duplex while MAC not off"); 1598 1599 /* 1600 * Read current register values 1601 */ 1602 1603 cfg = SBMAC_READCSR(s->sbm_maccfg); 1604 1605 /* 1606 * Mask off the stuff we're about to change 1607 */ 1608 1609 cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN); 1610 1611 switch (duplex) { 1612 case sbmac_duplex_half: 1613 switch (fc) { 1614 case sbmac_fc_disabled: 1615 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED; 1616 break; 1617 1618 case sbmac_fc_collision: 1619 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED; 1620 break; 1621 1622 case sbmac_fc_carrier: 1623 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR; 1624 break; 1625 1626 case sbmac_fc_auto: /* XXX not implemented */ 1627 /* fall through */ 1628 case sbmac_fc_frame: /* not valid in half duplex */ 1629 default: /* invalid selection */ 1630 panic("%s: invalid half duplex fc selection %d", 1631 s->sc_dev.dv_xname, fc); 1632 return 0; 1633 } 1634 break; 1635 1636 case sbmac_duplex_full: 1637 switch (fc) { 1638 case sbmac_fc_disabled: 1639 cfg |= V_MAC_FC_CMD_DISABLED; 1640 break; 1641 1642 case sbmac_fc_frame: 1643 cfg |= V_MAC_FC_CMD_ENABLED; 1644 break; 1645 1646 case sbmac_fc_collision: /* not valid in full duplex */ 1647 case sbmac_fc_carrier: /* not valid in full duplex */ 1648 case sbmac_fc_auto: /* XXX not implemented */ 1649 /* fall through */ 1650 default: 1651 panic("%s: invalid full duplex fc selection %d", 1652 s->sc_dev.dv_xname, fc); 1653 return 0; 1654 } 1655 break; 1656 1657 default: 1658 /* fall through */ 1659 case sbmac_duplex_auto: 1660 panic("%s: bad duplex %d", s->sc_dev.dv_xname, duplex); 1661 /* XXX not implemented */ 1662 break; 1663 } 1664 1665 /* 1666 * Send the bits back to the hardware 1667 */ 1668 1669 SBMAC_WRITECSR(s->sbm_maccfg, cfg); 1670 1671 return 1; 1672 } 1673 1674 /* 1675 * SBMAC_INTR() 1676 * 1677 * Interrupt handler for MAC interrupts 1678 * 1679 * Input parameters: 1680 * MAC structure 1681 * 1682 * Return value: 1683 * nothing 1684 */ 1685 1686 /* ARGSUSED */ 1687 static void 1688 sbmac_intr(void *xsc, uint32_t status, uint32_t pc) 1689 { 1690 struct sbmac_softc *sc = (struct sbmac_softc *) xsc; 1691 uint64_t isr; 1692 1693 for (;;) { 1694 1695 /* 1696 * Read the ISR (this clears the bits in the real register) 1697 */ 1698 1699 isr = SBMAC_READCSR(sc->sbm_isr); 1700 1701 if (isr == 0) 1702 break; 1703 1704 /* 1705 * Transmits on channel 0 1706 */ 1707 1708 if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) 1709 sbdma_tx_process(sc, &(sc->sbm_txdma)); 1710 1711 /* 1712 * Receives on channel 0 1713 */ 1714 1715 if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) 1716 sbdma_rx_process(sc, &(sc->sbm_rxdma)); 1717 } 1718 } 1719 1720 1721 /* 1722 * SBMAC_START(ifp) 1723 * 1724 * Start output on the specified interface. Basically, we 1725 * queue as many buffers as we can until the ring fills up, or 1726 * we run off the end of the queue, whichever comes first. 1727 * 1728 * Input parameters: 1729 * ifp - interface 1730 * 1731 * Return value: 1732 * nothing 1733 */ 1734 1735 static void 1736 sbmac_start(struct ifnet *ifp) 1737 { 1738 struct sbmac_softc *sc; 1739 struct mbuf *m_head = NULL; 1740 int rv; 1741 1742 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1743 return; 1744 1745 sc = ifp->if_softc; 1746 1747 for (;;) { 1748 1749 IF_DEQUEUE(&ifp->if_snd, m_head); 1750 if (m_head == NULL) 1751 break; 1752 1753 /* 1754 * Put the buffer on the transmit ring. If we 1755 * don't have room, set the OACTIVE flag and wait 1756 * for the NIC to drain the ring. 1757 */ 1758 1759 rv = sbdma_add_txbuffer(&(sc->sbm_txdma), m_head); 1760 1761 if (rv == 0) { 1762 /* 1763 * If there's a BPF listener, bounce a copy of this 1764 * frame to it. 1765 */ 1766 #if (NBPFILTER > 0) 1767 if (ifp->if_bpf) 1768 bpf_mtap(ifp->if_bpf, m_head); 1769 #endif 1770 if (!sc->sbm_pass3_dma) { 1771 /* 1772 * Don't free mbuf if we're not copying to new 1773 * mbuf in sbdma_add_txbuffer. It will be 1774 * freed in sbdma_tx_process. 1775 */ 1776 m_freem(m_head); 1777 } 1778 } else { 1779 IF_PREPEND(&ifp->if_snd, m_head); 1780 ifp->if_flags |= IFF_OACTIVE; 1781 break; 1782 } 1783 } 1784 } 1785 1786 /* 1787 * SBMAC_SETMULTI(sc) 1788 * 1789 * Reprogram the multicast table into the hardware, given 1790 * the list of multicasts associated with the interface 1791 * structure. 1792 * 1793 * Input parameters: 1794 * sc - softc 1795 * 1796 * Return value: 1797 * nothing 1798 */ 1799 1800 static void 1801 sbmac_setmulti(struct sbmac_softc *sc) 1802 { 1803 struct ifnet *ifp; 1804 uint64_t reg; 1805 sbmac_port_t port; 1806 int idx; 1807 struct ether_multi *enm; 1808 struct ether_multistep step; 1809 1810 ifp = &sc->sc_ethercom.ec_if; 1811 1812 /* 1813 * Clear out entire multicast table. We do this by nuking 1814 * the entire hash table and all the direct matches except 1815 * the first one, which is used for our station address 1816 */ 1817 1818 for (idx = 1; idx < MAC_ADDR_COUNT; idx++) { 1819 port = PKSEG1(sc->sbm_base + 1820 R_MAC_ADDR_BASE+(idx*sizeof(uint64_t))); 1821 SBMAC_WRITECSR(port, 0); 1822 } 1823 1824 for (idx = 0; idx < MAC_HASH_COUNT; idx++) { 1825 port = PKSEG1(sc->sbm_base + 1826 R_MAC_HASH_BASE+(idx*sizeof(uint64_t))); 1827 SBMAC_WRITECSR(port, 0); 1828 } 1829 1830 /* 1831 * Clear the filter to say we don't want any multicasts. 1832 */ 1833 1834 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1835 reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN); 1836 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1837 1838 if (ifp->if_flags & IFF_ALLMULTI) { 1839 /* 1840 * Enable ALL multicasts. Do this by inverting the 1841 * multicast enable bit. 1842 */ 1843 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1844 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN); 1845 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1846 return; 1847 } 1848 1849 /* 1850 * Progam new multicast entries. For now, only use the 1851 * perfect filter. In the future we'll need to use the 1852 * hash filter if the perfect filter overflows 1853 */ 1854 1855 /* 1856 * XXX only using perfect filter for now, need to use hash 1857 * XXX if the table overflows 1858 */ 1859 1860 idx = 1; /* skip station address */ 1861 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1862 while ((enm != NULL) && (idx < MAC_ADDR_COUNT)) { 1863 reg = sbmac_addr2reg(enm->enm_addrlo); 1864 port = PKSEG1(sc->sbm_base + 1865 R_MAC_ADDR_BASE+(idx*sizeof(uint64_t))); 1866 SBMAC_WRITECSR(port, reg); 1867 idx++; 1868 ETHER_NEXT_MULTI(step, enm); 1869 } 1870 1871 /* 1872 * Enable the "accept multicast bits" if we programmed at least one 1873 * multicast. 1874 */ 1875 1876 if (idx > 1) { 1877 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1878 reg |= M_MAC_MCAST_EN; 1879 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1880 } 1881 } 1882 1883 /* 1884 * SBMAC_ETHER_IOCTL(ifp, cmd, data) 1885 * 1886 * Generic IOCTL requests for this interface. The basic 1887 * stuff is handled here for bringing the interface up, 1888 * handling multicasts, etc. 1889 * 1890 * Input parameters: 1891 * ifp - interface structure 1892 * cmd - command code 1893 * data - pointer to data 1894 * 1895 * Return value: 1896 * return value (0 is success) 1897 */ 1898 1899 static int 1900 sbmac_ether_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1901 { 1902 struct ifaddr *ifa = (struct ifaddr *) data; 1903 struct sbmac_softc *sc = ifp->if_softc; 1904 1905 switch (cmd) { 1906 case SIOCSIFADDR: 1907 ifp->if_flags |= IFF_UP; 1908 1909 switch (ifa->ifa_addr->sa_family) { 1910 #ifdef INET 1911 case AF_INET: 1912 sbmac_init_and_start(sc); 1913 arp_ifinit(ifp, ifa); 1914 break; 1915 #endif 1916 #ifdef NS 1917 case AF_NS: 1918 { 1919 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1920 1921 if (ns_nullhost(*ina)) 1922 ina->x_host = 1923 *(union ns_host *)LLADDR(ifp->if_sadl); 1924 else 1925 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1926 ifp->if_addrlen); 1927 /* Set new address. */ 1928 sbmac_init_and_start(sc); 1929 break; 1930 } 1931 #endif 1932 default: 1933 sbmac_init_and_start(sc); 1934 break; 1935 } 1936 break; 1937 1938 default: 1939 return (EINVAL); 1940 } 1941 1942 return (0); 1943 } 1944 1945 /* 1946 * SBMAC_IOCTL(ifp, command, data) 1947 * 1948 * Main IOCTL handler - dispatches to other IOCTLs for various 1949 * types of requests. 1950 * 1951 * Input parameters: 1952 * ifp - interface pointer 1953 * command - command code 1954 * data - pointer to argument data 1955 * 1956 * Return value: 1957 * 0 if ok 1958 * else error code 1959 */ 1960 1961 static int 1962 sbmac_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1963 { 1964 struct sbmac_softc *sc = ifp->if_softc; 1965 struct ifreq *ifr = (struct ifreq *) data; 1966 int s, error = 0; 1967 1968 s = splnet(); 1969 1970 switch(command) { 1971 case SIOCSIFADDR: 1972 case SIOCGIFADDR: 1973 error = sbmac_ether_ioctl(ifp, command, data); 1974 break; 1975 case SIOCSIFMTU: 1976 if (ifr->ifr_mtu > ETHER_MAX_LEN) 1977 error = EINVAL; 1978 else { 1979 ifp->if_mtu = ifr->ifr_mtu; 1980 /* XXX Program new MTU here */ 1981 } 1982 break; 1983 case SIOCSIFFLAGS: 1984 if (ifp->if_flags & IFF_UP) { 1985 /* 1986 * If only the state of the PROMISC flag changed, 1987 * just tweak the hardware registers. 1988 */ 1989 if ((ifp->if_flags & IFF_RUNNING) && 1990 (ifp->if_flags & IFF_PROMISC)) { 1991 /* turn on promiscuous mode */ 1992 sbmac_promiscuous_mode(sc, 1); 1993 } else if (ifp->if_flags & IFF_RUNNING && 1994 !(ifp->if_flags & IFF_PROMISC)) { 1995 /* turn off promiscuous mode */ 1996 sbmac_promiscuous_mode(sc, 0); 1997 } else 1998 sbmac_set_channel_state(sc, sbmac_state_on); 1999 } else { 2000 if (ifp->if_flags & IFF_RUNNING) 2001 sbmac_set_channel_state(sc, sbmac_state_off); 2002 } 2003 2004 sc->sbm_if_flags = ifp->if_flags; 2005 error = 0; 2006 break; 2007 2008 case SIOCADDMULTI: 2009 case SIOCDELMULTI: 2010 if (ifp->if_flags & IFF_RUNNING) { 2011 sbmac_setmulti(sc); 2012 error = 0; 2013 } 2014 break; 2015 case SIOCSIFMEDIA: 2016 case SIOCGIFMEDIA: 2017 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 2018 break; 2019 default: 2020 error = EINVAL; 2021 break; 2022 } 2023 2024 (void)splx(s); 2025 2026 return(error); 2027 } 2028 2029 /* 2030 * SBMAC_IFMEDIA_UPD(ifp) 2031 * 2032 * Configure an appropriate media type for this interface, 2033 * given the data in the interface structure 2034 * 2035 * Input parameters: 2036 * ifp - interface 2037 * 2038 * Return value: 2039 * 0 if ok 2040 * else error code 2041 */ 2042 2043 static int 2044 sbmac_mediachange(struct ifnet *ifp) 2045 { 2046 struct sbmac_softc *sc = ifp->if_softc; 2047 2048 if (ifp->if_flags & IFF_UP) 2049 mii_mediachg(&sc->sc_mii); 2050 return(0); 2051 } 2052 2053 /* 2054 * SBMAC_IFMEDIA_STS(ifp, ifmr) 2055 * 2056 * Report current media status (used by ifconfig, for example) 2057 * 2058 * Input parameters: 2059 * ifp - interface structure 2060 * ifmr - media request structure 2061 * 2062 * Return value: 2063 * nothing 2064 */ 2065 2066 static void 2067 sbmac_mediastatus(struct ifnet *ifp, struct ifmediareq *req) 2068 { 2069 struct sbmac_softc *sc = ifp->if_softc; 2070 2071 mii_pollstat(&sc->sc_mii); 2072 req->ifm_status = sc->sc_mii.mii_media_status; 2073 req->ifm_active = sc->sc_mii.mii_media_active; 2074 } 2075 2076 /* 2077 * SBMAC_WATCHDOG(ifp) 2078 * 2079 * Called periodically to make sure we're still happy. 2080 * 2081 * Input parameters: 2082 * ifp - interface structure 2083 * 2084 * Return value: 2085 * nothing 2086 */ 2087 2088 static void 2089 sbmac_watchdog(struct ifnet *ifp) 2090 { 2091 2092 /* XXX do something */ 2093 } 2094 2095 /* 2096 * One second timer, used to tick MII. 2097 */ 2098 static void 2099 sbmac_tick(void *arg) 2100 { 2101 struct sbmac_softc *sc = arg; 2102 int s; 2103 2104 s = splnet(); 2105 mii_tick(&sc->sc_mii); 2106 splx(s); 2107 2108 callout_reset(&sc->sc_tick_ch, hz, sbmac_tick, sc); 2109 } 2110 2111 2112 /* 2113 * SBMAC_MATCH(parent, match, aux) 2114 * 2115 * Part of the config process - see if this device matches the 2116 * info about what we expect to find on the bus. 2117 * 2118 * Input parameters: 2119 * parent - parent bus structure 2120 * match - 2121 * aux - bus-specific args 2122 * 2123 * Return value: 2124 * 1 if we match 2125 * 0 if we don't match 2126 */ 2127 2128 static int 2129 sbmac_match(struct device *parent, struct cfdata *match, void *aux) 2130 { 2131 struct sbobio_attach_args *sap = aux; 2132 2133 /* 2134 * Make sure it's a MAC 2135 */ 2136 2137 if (sap->sa_locs.sa_type != SBOBIO_DEVTYPE_MAC) 2138 return 0; 2139 2140 /* 2141 * Yup, it is. 2142 */ 2143 2144 return 1; 2145 } 2146 2147 /* 2148 * SBMAC_PARSE_XDIGIT(str) 2149 * 2150 * Parse a hex digit, returning its value 2151 * 2152 * Input parameters: 2153 * str - character 2154 * 2155 * Return value: 2156 * hex value, or -1 if invalid 2157 */ 2158 2159 static int 2160 sbmac_parse_xdigit(char str) 2161 { 2162 int digit; 2163 2164 if ((str >= '0') && (str <= '9')) 2165 digit = str - '0'; 2166 else if ((str >= 'a') && (str <= 'f')) 2167 digit = str - 'a' + 10; 2168 else if ((str >= 'A') && (str <= 'F')) 2169 digit = str - 'A' + 10; 2170 else 2171 digit = -1; 2172 2173 return digit; 2174 } 2175 2176 /* 2177 * SBMAC_PARSE_HWADDR(str, hwaddr) 2178 * 2179 * Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte 2180 * Ethernet address. 2181 * 2182 * Input parameters: 2183 * str - string 2184 * hwaddr - pointer to hardware address 2185 * 2186 * Return value: 2187 * 0 if ok, else -1 2188 */ 2189 2190 static int 2191 sbmac_parse_hwaddr(char *str, u_char *hwaddr) 2192 { 2193 int digit1, digit2; 2194 int idx = 6; 2195 2196 while (*str && (idx > 0)) { 2197 digit1 = sbmac_parse_xdigit(*str); 2198 if (digit1 < 0) 2199 return -1; 2200 str++; 2201 if (!*str) 2202 return -1; 2203 2204 if ((*str == ':') || (*str == '-')) { 2205 digit2 = digit1; 2206 digit1 = 0; 2207 } else { 2208 digit2 = sbmac_parse_xdigit(*str); 2209 if (digit2 < 0) 2210 return -1; 2211 str++; 2212 } 2213 2214 *hwaddr++ = (digit1 << 4) | digit2; 2215 idx--; 2216 2217 if (*str == '-') 2218 str++; 2219 if (*str == ':') 2220 str++; 2221 } 2222 return 0; 2223 } 2224 2225 /* 2226 * SBMAC_ATTACH(parent, self, aux) 2227 * 2228 * Attach routine - init hardware and hook ourselves into NetBSD. 2229 * 2230 * Input parameters: 2231 * parent - parent bus device 2232 * self - our softc 2233 * aux - attach data 2234 * 2235 * Return value: 2236 * nothing 2237 */ 2238 2239 static void 2240 sbmac_attach(struct device *parent, struct device *self, void *aux) 2241 { 2242 struct ifnet *ifp; 2243 struct sbmac_softc *sc; 2244 struct sbobio_attach_args *sap = aux; 2245 u_char *eaddr; 2246 static int unit = 0; /* XXX */ 2247 uint64_t ea_reg; 2248 int idx; 2249 2250 sc = (struct sbmac_softc *)self; 2251 2252 /* Determine controller base address */ 2253 2254 sc->sbm_base = (sbmac_port_t) sap->sa_base + sap->sa_locs.sa_offset; 2255 2256 eaddr = sc->sbm_hwaddr; 2257 2258 /* 2259 * Initialize context (get pointers to registers and stuff), then 2260 * allocate the memory for the descriptor tables. 2261 */ 2262 2263 sbmac_initctx(sc); 2264 2265 callout_init(&(sc->sc_tick_ch)); 2266 2267 /* 2268 * Read the ethernet address. The firwmare left this programmed 2269 * for us in the ethernet address register for each mac. 2270 */ 2271 2272 ea_reg = SBMAC_READCSR(PKSEG1(sc->sbm_base + R_MAC_ETHERNET_ADDR)); 2273 for (idx = 0; idx < 6; idx++) { 2274 eaddr[idx] = (uint8_t) (ea_reg & 0xFF); 2275 ea_reg >>= 8; 2276 } 2277 2278 #define SBMAC_DEFAULT_HWADDR "40:00:00:00:01:00" 2279 if (eaddr[0] == 0 && eaddr[1] == 0 && eaddr[2] == 0 && 2280 eaddr[3] == 0 && eaddr[4] == 0 && eaddr[5] == 0) { 2281 sbmac_parse_hwaddr(SBMAC_DEFAULT_HWADDR, eaddr); 2282 eaddr[5] = unit; 2283 } 2284 2285 #ifdef SBMAC_ETH0_HWADDR 2286 if (unit == 0) 2287 sbmac_parse_hwaddr(SBMAC_ETH0_HWADDR, eaddr); 2288 #endif 2289 #ifdef SBMAC_ETH1_HWADDR 2290 if (unit == 1) 2291 sbmac_parse_hwaddr(SBMAC_ETH1_HWADDR, eaddr); 2292 #endif 2293 #ifdef SBMAC_ETH2_HWADDR 2294 if (unit == 2) 2295 sbmac_parse_hwaddr(SBMAC_ETH2_HWADDR, eaddr); 2296 #endif 2297 unit++; 2298 2299 /* 2300 * Display Ethernet address (this is called during the config process 2301 * so we need to finish off the config message that was being displayed) 2302 */ 2303 printf(": Ethernet%s\n", 2304 sc->sbm_pass3_dma ? ", using unaligned tx DMA" : ""); 2305 printf("%s: Ethernet address: %s\n", self->dv_xname, 2306 ether_sprintf(eaddr)); 2307 2308 2309 /* 2310 * Set up ifnet structure 2311 */ 2312 2313 ifp = &sc->sc_ethercom.ec_if; 2314 ifp->if_softc = sc; 2315 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 2316 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 2317 IFF_NOTRAILERS; 2318 ifp->if_ioctl = sbmac_ioctl; 2319 ifp->if_start = sbmac_start; 2320 ifp->if_watchdog = sbmac_watchdog; 2321 ifp->if_snd.ifq_maxlen = SBMAC_MAX_TXDESCR - 1; 2322 2323 /* 2324 * Set up ifmedia support. 2325 */ 2326 2327 /* 2328 * Initialize MII/media info. 2329 */ 2330 sc->sc_mii.mii_ifp = ifp; 2331 sc->sc_mii.mii_readreg = sbmac_mii_readreg; 2332 sc->sc_mii.mii_writereg = sbmac_mii_writereg; 2333 sc->sc_mii.mii_statchg = sbmac_mii_statchg; 2334 ifmedia_init(&sc->sc_mii.mii_media, 0, sbmac_mediachange, 2335 sbmac_mediastatus); 2336 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 2337 MII_OFFSET_ANY, 0); 2338 2339 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 2340 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 2341 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 2342 } else { 2343 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2344 } 2345 2346 2347 /* 2348 * map/route interrupt 2349 */ 2350 2351 sc->sbm_intrhand = cpu_intr_establish(sap->sa_locs.sa_intr[0], IPL_NET, 2352 sbmac_intr, sc); 2353 2354 /* 2355 * Call MI attach routines. 2356 */ 2357 if_attach(ifp); 2358 ether_ifattach(ifp, eaddr); 2359 } 2360
Indexes created Fri Sep 26 20:09:58 GMT 2025