sbmac.c revision 1.15
1 /* $NetBSD: sbmac.c,v 1.15 2004/03/18 05:57:58 simonb Exp $ */ 2 3 /* 4 * Copyright 2000, 2001 5 * Broadcom Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and copied only 8 * in accordance with the following terms and conditions. Subject to these 9 * conditions, you may download, copy, install, use, modify and distribute 10 * modified or unmodified copies of this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce and 14 * retain this copyright notice and list of conditions as they appear in 15 * the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Broadcom Corporation. The "Broadcom Corporation" name may not be 19 * used to endorse or promote products derived from this software 20 * without the prior written permission of Broadcom Corporation. 21 * 22 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR 25 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE 26 * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE 27 * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 32 * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: sbmac.c,v 1.15 2004/03/18 05:57:58 simonb Exp $"); 37 38 #include "bpfilter.h" 39 #include "opt_inet.h" 40 #include "opt_ns.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/queue.h> 50 #include <sys/device.h> 51 52 #include <net/if.h> 53 #include <net/if_arp.h> 54 #include <net/if_ether.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 58 #if NBPFILTER > 0 59 #include <net/bpf.h> 60 #endif 61 62 #ifdef INET 63 #include <netinet/in.h> 64 #include <netinet/if_inarp.h> 65 #endif 66 67 #ifdef NS 68 #include <netns/ns.h> 69 #include <netns/ns_if.h> 70 #endif 71 72 #include <machine/locore.h> 73 74 #include "sbobiovar.h" 75 76 #include <dev/mii/mii.h> 77 #include <dev/mii/miivar.h> 78 #include <dev/mii/mii_bitbang.h> 79 80 #include <mips/sibyte/include/sb1250_defs.h> 81 #include <mips/sibyte/include/sb1250_regs.h> 82 #include <mips/sibyte/include/sb1250_mac.h> 83 #include <mips/sibyte/include/sb1250_dma.h> 84 #include <mips/sibyte/include/sb1250_scd.h> 85 86 /* Simple types */ 87 88 typedef u_long sbmac_port_t; 89 typedef uint64_t sbmac_physaddr_t; 90 typedef uint64_t sbmac_enetaddr_t; 91 92 typedef enum { sbmac_speed_auto, sbmac_speed_10, 93 sbmac_speed_100, sbmac_speed_1000 } sbmac_speed_t; 94 95 typedef enum { sbmac_duplex_auto, sbmac_duplex_half, 96 sbmac_duplex_full } sbmac_duplex_t; 97 98 typedef enum { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame, 99 sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t; 100 101 typedef enum { sbmac_state_uninit, sbmac_state_off, sbmac_state_on, 102 sbmac_state_broken } sbmac_state_t; 103 104 105 /* Macros */ 106 107 #define SBMAC_EVENT_COUNTERS /* Include counters for various events */ 108 109 #define SBDMA_NEXTBUF(d, f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \ 110 (d)->sbdma_dscrtable : (d)->f+1) 111 112 113 #define CACHELINESIZE 32 114 #define NUMCACHEBLKS(x) (((x)+CACHELINESIZE-1)/CACHELINESIZE) 115 #define KMALLOC(x) malloc((x), M_DEVBUF, M_DONTWAIT) 116 #define KVTOPHYS(x) kvtophys((vaddr_t)(x)) 117 118 #ifdef SBMACDEBUG 119 #define dprintf(x) printf x 120 #else 121 #define dprintf(x) 122 #endif 123 124 #define SBMAC_READCSR(t) mips3_ld((uint64_t *) (t)) 125 #define SBMAC_WRITECSR(t, v) mips3_sd((uint64_t *) (t), (v)) 126 127 #define PKSEG1(x) ((sbmac_port_t) MIPS_PHYS_TO_KSEG1(x)) 128 129 #define SBMAC_MAX_TXDESCR 64 130 #define SBMAC_MAX_RXDESCR 64 131 132 #define ETHER_ALIGN 2 133 134 /* DMA Descriptor structure */ 135 136 typedef struct sbdmadscr_s { 137 uint64_t dscr_a; 138 uint64_t dscr_b; 139 } sbdmadscr_t; 140 141 142 /* DMA Controller structure */ 143 144 typedef struct sbmacdma_s { 145 146 /* 147 * This stuff is used to identify the channel and the registers 148 * associated with it. 149 */ 150 151 struct sbmac_softc *sbdma_eth; /* back pointer to associated MAC */ 152 int sbdma_channel; /* channel number */ 153 int sbdma_txdir; /* direction (1=transmit) */ 154 int sbdma_maxdescr; /* total # of descriptors in ring */ 155 sbmac_port_t sbdma_config0; /* DMA config register 0 */ 156 sbmac_port_t sbdma_config1; /* DMA config register 1 */ 157 sbmac_port_t sbdma_dscrbase; /* Descriptor base address */ 158 sbmac_port_t sbdma_dscrcnt; /* Descriptor count register */ 159 sbmac_port_t sbdma_curdscr; /* current descriptor address */ 160 161 /* 162 * This stuff is for maintenance of the ring 163 */ 164 165 sbdmadscr_t *sbdma_dscrtable; /* base of descriptor table */ 166 sbdmadscr_t *sbdma_dscrtable_end; /* end of descriptor table */ 167 168 struct mbuf **sbdma_ctxtable; /* context table, one per descr */ 169 170 paddr_t sbdma_dscrtable_phys; /* and also the phys addr */ 171 sbdmadscr_t *sbdma_addptr; /* next dscr for sw to add */ 172 sbdmadscr_t *sbdma_remptr; /* next dscr for sw to remove */ 173 } sbmacdma_t; 174 175 176 /* Ethernet softc structure */ 177 178 struct sbmac_softc { 179 180 /* 181 * NetBSD-specific things 182 */ 183 struct device sc_dev; /* base device (must be first) */ 184 struct ethercom sc_ethercom; /* Ethernet common part */ 185 struct mii_data sc_mii; 186 struct callout sc_tick_ch; 187 188 int sbm_if_flags; 189 void *sbm_intrhand; 190 191 /* 192 * Controller-specific things 193 */ 194 195 sbmac_port_t sbm_base; /* MAC's base address */ 196 sbmac_state_t sbm_state; /* current state */ 197 198 sbmac_port_t sbm_macenable; /* MAC Enable Register */ 199 sbmac_port_t sbm_maccfg; /* MAC Configuration Register */ 200 sbmac_port_t sbm_fifocfg; /* FIFO configuration register */ 201 sbmac_port_t sbm_framecfg; /* Frame configuration register */ 202 sbmac_port_t sbm_rxfilter; /* receive filter register */ 203 sbmac_port_t sbm_isr; /* Interrupt status register */ 204 sbmac_port_t sbm_imr; /* Interrupt mask register */ 205 206 sbmac_speed_t sbm_speed; /* current speed */ 207 sbmac_duplex_t sbm_duplex; /* current duplex */ 208 sbmac_fc_t sbm_fc; /* current flow control setting */ 209 int sbm_rxflags; /* received packet flags */ 210 211 u_char sbm_hwaddr[ETHER_ADDR_LEN]; 212 213 sbmacdma_t sbm_txdma; /* for now, only use channel 0 */ 214 sbmacdma_t sbm_rxdma; 215 216 int sbm_pass3_dma; /* chip has pass3 SOC DMA features */ 217 218 #ifdef SBMAC_EVENT_COUNTERS 219 struct evcnt sbm_ev_rxintr; /* Rx interrupts */ 220 struct evcnt sbm_ev_txintr; /* Tx interrupts */ 221 struct evcnt sbm_ev_txdrop; /* Tx dropped due to no mbuf alloc failed */ 222 struct evcnt sbm_ev_txstall; /* Tx stalled due to no descriptors free */ 223 224 struct evcnt sbm_ev_txsplit; /* pass3 Tx split mbuf */ 225 struct evcnt sbm_ev_txkeep; /* pass3 Tx didn't split mbuf */ 226 #endif 227 }; 228 229 230 #ifdef SBMAC_EVENT_COUNTERS 231 #define SBMAC_EVCNT_INCR(ev) (ev).ev_count++ 232 #else 233 #define SBMAC_EVCNT_INCR(ev) do { /* nothing */ } while (0) 234 #endif 235 236 /* Externs */ 237 238 extern paddr_t kvtophys(vaddr_t); 239 240 /* Prototypes */ 241 242 static void sbdma_initctx(sbmacdma_t *d, struct sbmac_softc *s, int chan, 243 int txrx, int maxdescr); 244 static void sbdma_channel_start(sbmacdma_t *d); 245 static int sbdma_add_rcvbuffer(sbmacdma_t *d, struct mbuf *m); 246 static int sbdma_add_txbuffer(sbmacdma_t *d, struct mbuf *m); 247 static void sbdma_emptyring(sbmacdma_t *d); 248 static void sbdma_fillring(sbmacdma_t *d); 249 static void sbdma_rx_process(struct sbmac_softc *sc, sbmacdma_t *d); 250 static void sbdma_tx_process(struct sbmac_softc *sc, sbmacdma_t *d); 251 static void sbmac_initctx(struct sbmac_softc *s); 252 static void sbmac_channel_start(struct sbmac_softc *s); 253 static void sbmac_channel_stop(struct sbmac_softc *s); 254 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *, 255 sbmac_state_t); 256 static void sbmac_promiscuous_mode(struct sbmac_softc *sc, int onoff); 257 static void sbmac_init_and_start(struct sbmac_softc *sc); 258 static uint64_t sbmac_addr2reg(u_char *ptr); 259 static void sbmac_intr(void *xsc, uint32_t status, uint32_t pc); 260 static void sbmac_start(struct ifnet *ifp); 261 static void sbmac_setmulti(struct sbmac_softc *sc); 262 static int sbmac_ether_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 263 static int sbmac_ioctl(struct ifnet *ifp, u_long command, caddr_t data); 264 static int sbmac_mediachange(struct ifnet *ifp); 265 static void sbmac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr); 266 static void sbmac_watchdog(struct ifnet *ifp); 267 static int sbmac_match(struct device *parent, struct cfdata *match, void *aux); 268 static void sbmac_attach(struct device *parent, struct device *self, void *aux); 269 static int sbmac_set_speed(struct sbmac_softc *s, sbmac_speed_t speed); 270 static int sbmac_set_duplex(struct sbmac_softc *s, sbmac_duplex_t duplex, 271 sbmac_fc_t fc); 272 static void sbmac_tick(void *arg); 273 274 275 /* Globals */ 276 277 CFATTACH_DECL(sbmac, sizeof(struct sbmac_softc), 278 sbmac_match, sbmac_attach, NULL, NULL); 279 280 static uint32_t sbmac_mii_bitbang_read(struct device *self); 281 static void sbmac_mii_bitbang_write(struct device *self, uint32_t val); 282 283 static const struct mii_bitbang_ops sbmac_mii_bitbang_ops = { 284 sbmac_mii_bitbang_read, 285 sbmac_mii_bitbang_write, 286 { 287 (uint32_t)M_MAC_MDIO_OUT, /* MII_BIT_MDO */ 288 (uint32_t)M_MAC_MDIO_IN, /* MII_BIT_MDI */ 289 (uint32_t)M_MAC_MDC, /* MII_BIT_MDC */ 290 0, /* MII_BIT_DIR_HOST_PHY */ 291 (uint32_t)M_MAC_MDIO_DIR /* MII_BIT_DIR_PHY_HOST */ 292 } 293 }; 294 295 static uint32_t 296 sbmac_mii_bitbang_read(struct device *self) 297 { 298 struct sbmac_softc *sc = (void *) self; 299 sbmac_port_t reg; 300 301 reg = PKSEG1(sc->sbm_base + R_MAC_MDIO); 302 return (uint32_t) SBMAC_READCSR(reg); 303 } 304 305 static void 306 sbmac_mii_bitbang_write(struct device *self, uint32_t val) 307 { 308 struct sbmac_softc *sc = (void *) self; 309 sbmac_port_t reg; 310 311 reg = PKSEG1(sc->sbm_base + R_MAC_MDIO); 312 313 SBMAC_WRITECSR(reg, (val & 314 (M_MAC_MDC|M_MAC_MDIO_DIR|M_MAC_MDIO_OUT|M_MAC_MDIO_IN))); 315 } 316 317 /* 318 * Read an PHY register through the MII. 319 */ 320 static int 321 sbmac_mii_readreg(struct device *self, int phy, int reg) 322 { 323 324 return (mii_bitbang_readreg(self, &sbmac_mii_bitbang_ops, phy, reg)); 325 } 326 327 /* 328 * Write to a PHY register through the MII. 329 */ 330 static void 331 sbmac_mii_writereg(struct device *self, int phy, int reg, int val) 332 { 333 334 mii_bitbang_writereg(self, &sbmac_mii_bitbang_ops, phy, reg, val); 335 } 336 337 static void 338 sbmac_mii_statchg(struct device *self) 339 { 340 struct sbmac_softc *sc = (struct sbmac_softc *)self; 341 sbmac_state_t oldstate; 342 343 /* Stop the MAC in preparation for changing all of the parameters. */ 344 oldstate = sbmac_set_channel_state(sc, sbmac_state_off); 345 346 switch (sc->sc_ethercom.ec_if.if_baudrate) { 347 default: /* if autonegotiation fails, assume 10Mbit */ 348 case IF_Mbps(10): 349 sbmac_set_speed(sc, sbmac_speed_10); 350 break; 351 352 case IF_Mbps(100): 353 sbmac_set_speed(sc, sbmac_speed_100); 354 break; 355 356 case IF_Mbps(1000): 357 sbmac_set_speed(sc, sbmac_speed_1000); 358 break; 359 } 360 361 if (sc->sc_mii.mii_media_active & IFM_FDX) { 362 /* Configure for full-duplex */ 363 /* XXX: is flow control right for 10, 100? */ 364 sbmac_set_duplex(sc, sbmac_duplex_full, sbmac_fc_frame); 365 } else { 366 /* Configure for half-duplex */ 367 /* XXX: is flow control right? */ 368 sbmac_set_duplex(sc, sbmac_duplex_half, sbmac_fc_disabled); 369 } 370 371 /* And put it back into its former state. */ 372 sbmac_set_channel_state(sc, oldstate); 373 } 374 375 /* 376 * SBDMA_INITCTX(d, s, chan, txrx, maxdescr) 377 * 378 * Initialize a DMA channel context. Since there are potentially 379 * eight DMA channels per MAC, it's nice to do this in a standard 380 * way. 381 * 382 * Input parameters: 383 * d - sbmacdma_t structure (DMA channel context) 384 * s - sbmac_softc structure (pointer to a MAC) 385 * chan - channel number (0..1 right now) 386 * txrx - Identifies DMA_TX or DMA_RX for channel direction 387 * maxdescr - number of descriptors 388 * 389 * Return value: 390 * nothing 391 */ 392 393 static void 394 sbdma_initctx(sbmacdma_t *d, struct sbmac_softc *s, int chan, int txrx, 395 int maxdescr) 396 { 397 /* 398 * Save away interesting stuff in the structure 399 */ 400 401 d->sbdma_eth = s; 402 d->sbdma_channel = chan; 403 d->sbdma_txdir = txrx; 404 405 /* 406 * initialize register pointers 407 */ 408 409 d->sbdma_config0 = PKSEG1(s->sbm_base + 410 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_CONFIG0)); 411 d->sbdma_config1 = PKSEG1(s->sbm_base + 412 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_CONFIG1)); 413 d->sbdma_dscrbase = PKSEG1(s->sbm_base + 414 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_DSCR_BASE)); 415 d->sbdma_dscrcnt = PKSEG1(s->sbm_base + 416 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_DSCR_CNT)); 417 d->sbdma_curdscr = PKSEG1(s->sbm_base + 418 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_CUR_DSCRADDR)); 419 420 /* 421 * Allocate memory for the ring 422 */ 423 424 d->sbdma_maxdescr = maxdescr; 425 426 d->sbdma_dscrtable = (sbdmadscr_t *) 427 KMALLOC(d->sbdma_maxdescr*sizeof(sbdmadscr_t)); 428 429 bzero(d->sbdma_dscrtable, d->sbdma_maxdescr*sizeof(sbdmadscr_t)); 430 431 d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr; 432 433 d->sbdma_dscrtable_phys = KVTOPHYS(d->sbdma_dscrtable); 434 435 /* 436 * And context table 437 */ 438 439 d->sbdma_ctxtable = (struct mbuf **) 440 KMALLOC(d->sbdma_maxdescr*sizeof(struct mbuf *)); 441 442 bzero(d->sbdma_ctxtable, d->sbdma_maxdescr*sizeof(struct mbuf *)); 443 } 444 445 /* 446 * SBDMA_CHANNEL_START(d) 447 * 448 * Initialize the hardware registers for a DMA channel. 449 * 450 * Input parameters: 451 * d - DMA channel to init (context must be previously init'd 452 * 453 * Return value: 454 * nothing 455 */ 456 457 static void 458 sbdma_channel_start(sbmacdma_t *d) 459 { 460 /* 461 * Turn on the DMA channel 462 */ 463 464 SBMAC_WRITECSR(d->sbdma_config1, 0); 465 466 SBMAC_WRITECSR(d->sbdma_dscrbase, d->sbdma_dscrtable_phys); 467 468 SBMAC_WRITECSR(d->sbdma_config0, V_DMA_RINGSZ(d->sbdma_maxdescr) | 0); 469 470 /* 471 * Initialize ring pointers 472 */ 473 474 d->sbdma_addptr = d->sbdma_dscrtable; 475 d->sbdma_remptr = d->sbdma_dscrtable; 476 } 477 478 /* 479 * SBDMA_ADD_RCVBUFFER(d, m) 480 * 481 * Add a buffer to the specified DMA channel. For receive channels, 482 * this queues a buffer for inbound packets. 483 * 484 * Input parameters: 485 * d - DMA channel descriptor 486 * m - mbuf to add, or NULL if we should allocate one. 487 * 488 * Return value: 489 * 0 if buffer could not be added (ring is full) 490 * 1 if buffer added successfully 491 */ 492 493 static int 494 sbdma_add_rcvbuffer(sbmacdma_t *d, struct mbuf *m) 495 { 496 sbdmadscr_t *dsc; 497 sbdmadscr_t *nextdsc; 498 struct mbuf *m_new = NULL; 499 500 /* get pointer to our current place in the ring */ 501 502 dsc = d->sbdma_addptr; 503 nextdsc = SBDMA_NEXTBUF(d, sbdma_addptr); 504 505 /* 506 * figure out if the ring is full - if the next descriptor 507 * is the same as the one that we're going to remove from 508 * the ring, the ring is full 509 */ 510 511 if (nextdsc == d->sbdma_remptr) 512 return ENOSPC; 513 514 /* 515 * Allocate an mbuf if we don't already have one. 516 * If we do have an mbuf, reset it so that it's empty. 517 */ 518 519 if (m == NULL) { 520 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 521 if (m_new == NULL) { 522 printf("%s: mbuf allocation failed\n", 523 d->sbdma_eth->sc_dev.dv_xname); 524 return ENOBUFS; 525 } 526 527 MCLGET(m_new, M_DONTWAIT); 528 if (!(m_new->m_flags & M_EXT)) { 529 printf("%s: mbuf cluster allocation failed\n", 530 d->sbdma_eth->sc_dev.dv_xname); 531 m_freem(m_new); 532 return ENOBUFS; 533 } 534 535 m_new->m_len = m_new->m_pkthdr.len= MCLBYTES; 536 m_adj(m_new, ETHER_ALIGN); 537 } else { 538 m_new = m; 539 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 540 m_new->m_data = m_new->m_ext.ext_buf; 541 m_adj(m_new, ETHER_ALIGN); 542 } 543 544 /* 545 * fill in the descriptor 546 */ 547 548 dsc->dscr_a = KVTOPHYS(mtod(m_new, caddr_t)) | 549 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(ETHER_ALIGN + m_new->m_len)) | 550 M_DMA_DSCRA_INTERRUPT; 551 552 /* receiving: no options */ 553 dsc->dscr_b = 0; 554 555 /* 556 * fill in the context 557 */ 558 559 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = m_new; 560 561 /* 562 * point at next packet 563 */ 564 565 d->sbdma_addptr = nextdsc; 566 567 /* 568 * Give the buffer to the DMA engine. 569 */ 570 571 SBMAC_WRITECSR(d->sbdma_dscrcnt, 1); 572 573 return 0; /* we did it */ 574 } 575 576 /* 577 * SBDMA_ADD_TXBUFFER(d, m) 578 * 579 * Add a transmit buffer to the specified DMA channel, causing a 580 * transmit to start. 581 * 582 * Input parameters: 583 * d - DMA channel descriptor 584 * m - mbuf to add 585 * 586 * Return value: 587 * 0 transmit queued successfully 588 * otherwise error code 589 */ 590 591 static int 592 sbdma_add_txbuffer(sbmacdma_t *d, struct mbuf *m) 593 { 594 sbdmadscr_t *dsc; 595 sbdmadscr_t *nextdsc; 596 sbdmadscr_t *prevdsc; 597 sbdmadscr_t *origdesc; 598 int length; 599 int num_mbufs = 0; 600 struct sbmac_softc *sc = d->sbdma_eth; 601 602 /* get pointer to our current place in the ring */ 603 604 dsc = d->sbdma_addptr; 605 nextdsc = SBDMA_NEXTBUF(d, sbdma_addptr); 606 607 /* 608 * figure out if the ring is full - if the next descriptor 609 * is the same as the one that we're going to remove from 610 * the ring, the ring is full 611 */ 612 613 if (nextdsc == d->sbdma_remptr) { 614 SBMAC_EVCNT_INCR(sc->sbm_ev_txstall); 615 return ENOSPC; 616 } 617 618 /* 619 * PASS3 parts do not have buffer alignment restriction. 620 * No need to copy/coalesce to new mbuf. Also has different 621 * descriptor format 622 */ 623 if (sc->sbm_pass3_dma) { 624 struct mbuf *m_temp = NULL; 625 626 /* 627 * Loop thru this mbuf record. 628 * The head mbuf will have SOP set. 629 */ 630 dsc->dscr_a = KVTOPHYS(mtod(m,caddr_t)) | 631 M_DMA_DSCRA_INTERRUPT | 632 M_DMA_ETHTX_SOP; 633 634 /* 635 * transmitting: set outbound options,buffer A size(+ low 5 636 * bits of start addr),and packet length. 637 */ 638 dsc->dscr_b = 639 V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) | 640 V_DMA_DSCRB_A_SIZE((m->m_len + 641 (mtod(m,unsigned int) & 0x0000001F))) | 642 V_DMA_DSCRB_PKT_SIZE_MSB( (m->m_pkthdr.len & 0xB000) ) | 643 V_DMA_DSCRB_PKT_SIZE(m->m_pkthdr.len); 644 645 d->sbdma_addptr = nextdsc; 646 origdesc = prevdsc = dsc; 647 dsc = d->sbdma_addptr; 648 num_mbufs++; 649 650 /* Start with first non-head mbuf */ 651 for(m_temp = m->m_next; m_temp != 0; m_temp = m_temp->m_next) { 652 int len, next_len; 653 uint64_t addr; 654 655 if (m_temp->m_len == 0) 656 continue; /* Skip 0-length mbufs */ 657 658 len = m_temp->m_len; 659 addr = KVTOPHYS(mtod(m_temp, caddr_t)); 660 661 /* 662 * Check to see if the mbuf spans a page boundary. If 663 * it does, and the physical pages behind the virtual 664 * pages are not contiguous, split it so that each 665 * virtual page uses it's own Tx descriptor. 666 */ 667 if (trunc_page(addr) != trunc_page(addr + len - 1)) { 668 next_len = (addr + len) - trunc_page(addr + len); 669 670 len -= next_len; 671 672 if (addr + len == 673 KVTOPHYS(mtod(m_temp, caddr_t) + len)) { 674 SBMAC_EVCNT_INCR(sc->sbm_ev_txkeep); 675 len += next_len; 676 next_len = 0; 677 } else { 678 SBMAC_EVCNT_INCR(sc->sbm_ev_txsplit); 679 } 680 } else { 681 next_len = 0; 682 } 683 684 again: 685 /* 686 * fill in the descriptor 687 */ 688 dsc->dscr_a = addr | M_DMA_DSCRA_INTERRUPT; 689 690 /* 691 * transmitting: set outbound options,buffer A 692 * size(+ low 5 bits of start addr) 693 */ 694 dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_NOTSOP) | 695 V_DMA_DSCRB_A_SIZE((len + (addr & 0x0000001F))); 696 697 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = NULL; 698 699 /* 700 * point at next descriptor 701 */ 702 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr); 703 if (nextdsc == d->sbdma_remptr) { 704 d->sbdma_addptr = origdesc; 705 SBMAC_EVCNT_INCR(sc->sbm_ev_txstall); 706 return ENOSPC; 707 } 708 d->sbdma_addptr = nextdsc; 709 710 prevdsc = dsc; 711 dsc = d->sbdma_addptr; 712 num_mbufs++; 713 714 if (next_len != 0) { 715 addr = KVTOPHYS(mtod(m_temp, caddr_t) + len); 716 len = next_len; 717 718 next_len = 0; 719 goto again; 720 } 721 722 } 723 /*Set head mbuf to last context index*/ 724 d->sbdma_ctxtable[prevdsc-d->sbdma_dscrtable] = m; 725 } else { 726 struct mbuf *m_new = NULL; 727 /* 728 * [BEGIN XXX] 729 * XXX Copy/coalesce the mbufs into a single mbuf cluster (we 730 * assume it will fit). This is a temporary hack to get us 731 * going. 732 */ 733 734 MGETHDR(m_new,M_DONTWAIT,MT_DATA); 735 if (m_new == NULL) { 736 printf("%s: mbuf allocation failed\n", 737 d->sbdma_eth->sc_dev.dv_xname); 738 SBMAC_EVCNT_INCR(sc->sbm_ev_txdrop); 739 return ENOBUFS; 740 } 741 742 MCLGET(m_new,M_DONTWAIT); 743 if (!(m_new->m_flags & M_EXT)) { 744 printf("%s: mbuf cluster allocation failed\n", 745 d->sbdma_eth->sc_dev.dv_xname); 746 m_freem(m_new); 747 SBMAC_EVCNT_INCR(sc->sbm_ev_txdrop); 748 return ENOBUFS; 749 } 750 751 m_new->m_len = m_new->m_pkthdr.len= MCLBYTES; 752 /*m_adj(m_new,ETHER_ALIGN);*/ 753 754 /* 755 * XXX Don't forget to include the offset portion in the 756 * XXX cache block calculation when this code is rewritten! 757 */ 758 759 /* 760 * Copy data 761 */ 762 763 m_copydata(m,0,m->m_pkthdr.len,mtod(m_new,caddr_t)); 764 m_new->m_len = m_new->m_pkthdr.len = m->m_pkthdr.len; 765 766 /* Free old mbuf 'm', actual mbuf is now 'm_new' */ 767 768 // XXX: CALLERS WILL FREE, they might have to bpf_mtap() if this 769 // XXX: function succeeds. 770 // m_freem(m); 771 length = m_new->m_len; 772 773 /* [END XXX] */ 774 /* 775 * fill in the descriptor 776 */ 777 778 dsc->dscr_a = KVTOPHYS(mtod(m_new,caddr_t)) | 779 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(m_new->m_len)) | 780 M_DMA_DSCRA_INTERRUPT | 781 M_DMA_ETHTX_SOP; 782 783 /* transmitting: set outbound options and length */ 784 dsc->dscr_b = 785 V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) | 786 V_DMA_DSCRB_PKT_SIZE(length); 787 788 num_mbufs++; 789 790 /* 791 * fill in the context 792 */ 793 794 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = m_new; 795 796 /* 797 * point at next packet 798 */ 799 d->sbdma_addptr = nextdsc; 800 } 801 802 /* 803 * Give the buffer to the DMA engine. 804 */ 805 806 SBMAC_WRITECSR(d->sbdma_dscrcnt, num_mbufs); 807 808 return 0; /* we did it */ 809 } 810 811 /* 812 * SBDMA_EMPTYRING(d) 813 * 814 * Free all allocated mbufs on the specified DMA channel; 815 * 816 * Input parameters: 817 * d - DMA channel 818 * 819 * Return value: 820 * nothing 821 */ 822 823 static void 824 sbdma_emptyring(sbmacdma_t *d) 825 { 826 int idx; 827 struct mbuf *m; 828 829 for (idx = 0; idx < d->sbdma_maxdescr; idx++) { 830 m = d->sbdma_ctxtable[idx]; 831 if (m) { 832 m_freem(m); 833 d->sbdma_ctxtable[idx] = NULL; 834 } 835 } 836 } 837 838 /* 839 * SBDMA_FILLRING(d) 840 * 841 * Fill the specified DMA channel (must be receive channel) 842 * with mbufs 843 * 844 * Input parameters: 845 * d - DMA channel 846 * 847 * Return value: 848 * nothing 849 */ 850 851 static void 852 sbdma_fillring(sbmacdma_t *d) 853 { 854 int idx; 855 856 for (idx = 0; idx < SBMAC_MAX_RXDESCR-1; idx++) 857 if (sbdma_add_rcvbuffer(d, NULL) != 0) 858 break; 859 } 860 861 /* 862 * SBDMA_RX_PROCESS(sc, d) 863 * 864 * Process "completed" receive buffers on the specified DMA channel. 865 * Note that this isn't really ideal for priority channels, since 866 * it processes all of the packets on a given channel before 867 * returning. 868 * 869 * Input parameters: 870 * sc - softc structure 871 * d - DMA channel context 872 * 873 * Return value: 874 * nothing 875 */ 876 877 static void 878 sbdma_rx_process(struct sbmac_softc *sc, sbmacdma_t *d) 879 { 880 int curidx; 881 int hwidx; 882 sbdmadscr_t *dsc; 883 struct mbuf *m; 884 int len; 885 886 struct ifnet *ifp = &(sc->sc_ethercom.ec_if); 887 888 for (;;) { 889 /* 890 * figure out where we are (as an index) and where 891 * the hardware is (also as an index) 892 * 893 * This could be done faster if (for example) the 894 * descriptor table was page-aligned and contiguous in 895 * both virtual and physical memory -- you could then 896 * just compare the low-order bits of the virtual address 897 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) 898 */ 899 900 curidx = d->sbdma_remptr - d->sbdma_dscrtable; 901 hwidx = (int) 902 (((SBMAC_READCSR(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - 903 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t)); 904 905 /* 906 * If they're the same, that means we've processed all 907 * of the descriptors up to (but not including) the one that 908 * the hardware is working on right now. 909 */ 910 911 if (curidx == hwidx) 912 break; 913 914 /* 915 * Otherwise, get the packet's mbuf ptr back 916 */ 917 918 dsc = &(d->sbdma_dscrtable[curidx]); 919 m = d->sbdma_ctxtable[curidx]; 920 d->sbdma_ctxtable[curidx] = NULL; 921 922 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4; 923 924 /* 925 * Check packet status. If good, process it. 926 * If not, silently drop it and put it back on the 927 * receive ring. 928 */ 929 930 if (! (dsc->dscr_a & M_DMA_ETHRX_BAD)) { 931 932 /* 933 * Set length into the packet 934 * XXX do we remove the CRC here? 935 */ 936 m->m_pkthdr.len = m->m_len = len; 937 938 ifp->if_ipackets++; 939 m->m_pkthdr.rcvif = ifp; 940 941 942 /* 943 * Add a new buffer to replace the old one. 944 */ 945 sbdma_add_rcvbuffer(d, NULL); 946 947 #if (NBPFILTER > 0) 948 /* 949 * Handle BPF listeners. Let the BPF user see the 950 * packet, but don't pass it up to the ether_input() 951 * layer unless it's a broadcast packet, multicast 952 * packet, matches our ethernet address or the 953 * interface is in promiscuous mode. 954 */ 955 956 if (ifp->if_bpf) 957 bpf_mtap(ifp->if_bpf, m); 958 #endif 959 /* 960 * Pass the buffer to the kernel 961 */ 962 (*ifp->if_input)(ifp, m); 963 } else { 964 /* 965 * Packet was mangled somehow. Just drop it and 966 * put it back on the receive ring. 967 */ 968 sbdma_add_rcvbuffer(d, m); 969 } 970 971 /* 972 * .. and advance to the next buffer. 973 */ 974 975 d->sbdma_remptr = SBDMA_NEXTBUF(d, sbdma_remptr); 976 } 977 } 978 979 /* 980 * SBDMA_TX_PROCESS(sc, d) 981 * 982 * Process "completed" transmit buffers on the specified DMA channel. 983 * This is normally called within the interrupt service routine. 984 * Note that this isn't really ideal for priority channels, since 985 * it processes all of the packets on a given channel before 986 * returning. 987 * 988 * Input parameters: 989 * sc - softc structure 990 * d - DMA channel context 991 * 992 * Return value: 993 * nothing 994 */ 995 996 static void 997 sbdma_tx_process(struct sbmac_softc *sc, sbmacdma_t *d) 998 { 999 int curidx; 1000 int hwidx; 1001 struct mbuf *m; 1002 1003 struct ifnet *ifp = &(sc->sc_ethercom.ec_if); 1004 1005 for (;;) { 1006 /* 1007 * figure out where we are (as an index) and where 1008 * the hardware is (also as an index) 1009 * 1010 * This could be done faster if (for example) the 1011 * descriptor table was page-aligned and contiguous in 1012 * both virtual and physical memory -- you could then 1013 * just compare the low-order bits of the virtual address 1014 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) 1015 */ 1016 1017 curidx = d->sbdma_remptr - d->sbdma_dscrtable; 1018 hwidx = (int) 1019 (((SBMAC_READCSR(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - 1020 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t)); 1021 1022 /* 1023 * If they're the same, that means we've processed all 1024 * of the descriptors up to (but not including) the one that 1025 * the hardware is working on right now. 1026 */ 1027 1028 if (curidx == hwidx) 1029 break; 1030 1031 /* 1032 * Otherwise, get the packet's mbuf ptr back 1033 */ 1034 1035 m = d->sbdma_ctxtable[curidx]; 1036 d->sbdma_ctxtable[curidx] = NULL; 1037 1038 /* 1039 * for transmits, we just free buffers. 1040 */ 1041 1042 m_freem(m); 1043 1044 /* 1045 * .. and advance to the next buffer. 1046 */ 1047 1048 d->sbdma_remptr = SBDMA_NEXTBUF(d, sbdma_remptr); 1049 } 1050 1051 /* 1052 * Decide what to set the IFF_OACTIVE bit in the interface to. 1053 * It's supposed to reflect if the interface is actively 1054 * transmitting, but that's really hard to do quickly. 1055 */ 1056 1057 ifp->if_flags &= ~IFF_OACTIVE; 1058 } 1059 1060 /* 1061 * SBMAC_INITCTX(s) 1062 * 1063 * Initialize an Ethernet context structure - this is called 1064 * once per MAC on the 1250. Memory is allocated here, so don't 1065 * call it again from inside the ioctl routines that bring the 1066 * interface up/down 1067 * 1068 * Input parameters: 1069 * s - sbmac context structure 1070 * 1071 * Return value: 1072 * 0 1073 */ 1074 1075 static void 1076 sbmac_initctx(struct sbmac_softc *s) 1077 { 1078 uint64_t sysrev; 1079 1080 /* 1081 * figure out the addresses of some ports 1082 */ 1083 1084 s->sbm_macenable = PKSEG1(s->sbm_base + R_MAC_ENABLE); 1085 s->sbm_maccfg = PKSEG1(s->sbm_base + R_MAC_CFG); 1086 s->sbm_fifocfg = PKSEG1(s->sbm_base + R_MAC_THRSH_CFG); 1087 s->sbm_framecfg = PKSEG1(s->sbm_base + R_MAC_FRAMECFG); 1088 s->sbm_rxfilter = PKSEG1(s->sbm_base + R_MAC_ADFILTER_CFG); 1089 s->sbm_isr = PKSEG1(s->sbm_base + R_MAC_STATUS); 1090 s->sbm_imr = PKSEG1(s->sbm_base + R_MAC_INT_MASK); 1091 1092 /* 1093 * Initialize the DMA channels. Right now, only one per MAC is used 1094 * Note: Only do this _once_, as it allocates memory from the kernel! 1095 */ 1096 1097 sbdma_initctx(&(s->sbm_txdma), s, 0, DMA_TX, SBMAC_MAX_TXDESCR); 1098 sbdma_initctx(&(s->sbm_rxdma), s, 0, DMA_RX, SBMAC_MAX_RXDESCR); 1099 1100 /* 1101 * initial state is OFF 1102 */ 1103 1104 s->sbm_state = sbmac_state_off; 1105 1106 /* 1107 * Initial speed is (XXX TEMP) 10MBit/s HDX no FC 1108 */ 1109 1110 s->sbm_speed = sbmac_speed_10; 1111 s->sbm_duplex = sbmac_duplex_half; 1112 s->sbm_fc = sbmac_fc_disabled; 1113 1114 /* 1115 * Determine SOC type. 112x has Pass3 SOC features. 1116 */ 1117 sysrev = SBMAC_READCSR( PKSEG1(A_SCD_SYSTEM_REVISION) ); 1118 s->sbm_pass3_dma = (SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1120 || 1119 SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1125 || 1120 SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1125H || 1121 (SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250 && 1122 0)); 1123 #ifdef SBMAC_EVENT_COUNTERS 1124 evcnt_attach_dynamic(&s->sbm_ev_rxintr, EVCNT_TYPE_INTR, 1125 NULL, s->sc_dev.dv_xname, "rxintr"); 1126 evcnt_attach_dynamic(&s->sbm_ev_txintr, EVCNT_TYPE_INTR, 1127 NULL, s->sc_dev.dv_xname, "txintr"); 1128 evcnt_attach_dynamic(&s->sbm_ev_txdrop, EVCNT_TYPE_MISC, 1129 NULL, s->sc_dev.dv_xname, "txdrop"); 1130 evcnt_attach_dynamic(&s->sbm_ev_txstall, EVCNT_TYPE_MISC, 1131 NULL, s->sc_dev.dv_xname, "txstall"); 1132 if (s->sbm_pass3_dma) { 1133 evcnt_attach_dynamic(&s->sbm_ev_txsplit, EVCNT_TYPE_MISC, 1134 NULL, s->sc_dev.dv_xname, "pass3tx-split"); 1135 evcnt_attach_dynamic(&s->sbm_ev_txkeep, EVCNT_TYPE_MISC, 1136 NULL, s->sc_dev.dv_xname, "pass3tx-keep"); 1137 } 1138 #endif 1139 } 1140 1141 /* 1142 * SBMAC_CHANNEL_START(s) 1143 * 1144 * Start packet processing on this MAC. 1145 * 1146 * Input parameters: 1147 * s - sbmac structure 1148 * 1149 * Return value: 1150 * nothing 1151 */ 1152 1153 static void 1154 sbmac_channel_start(struct sbmac_softc *s) 1155 { 1156 uint64_t reg; 1157 sbmac_port_t port; 1158 uint64_t cfg, fifo, framecfg; 1159 int idx; 1160 uint64_t dma_cfg0, fifo_cfg; 1161 sbmacdma_t *txdma; 1162 1163 /* 1164 * Don't do this if running 1165 */ 1166 1167 if (s->sbm_state == sbmac_state_on) 1168 return; 1169 1170 /* 1171 * Bring the controller out of reset, but leave it off. 1172 */ 1173 1174 SBMAC_WRITECSR(s->sbm_macenable, 0); 1175 1176 /* 1177 * Ignore all received packets 1178 */ 1179 1180 SBMAC_WRITECSR(s->sbm_rxfilter, 0); 1181 1182 /* 1183 * Calculate values for various control registers. 1184 */ 1185 1186 cfg = M_MAC_RETRY_EN | 1187 M_MAC_TX_HOLD_SOP_EN | 1188 V_MAC_TX_PAUSE_CNT_16K | 1189 M_MAC_AP_STAT_EN | 1190 M_MAC_SS_EN | 1191 0; 1192 1193 fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */ 1194 V_MAC_TX_RD_THRSH(4) | 1195 V_MAC_TX_RL_THRSH(4) | 1196 V_MAC_RX_PL_THRSH(4) | 1197 V_MAC_RX_RD_THRSH(4) | /* Must be '4' */ 1198 V_MAC_RX_PL_THRSH(4) | 1199 V_MAC_RX_RL_THRSH(8) | 1200 0; 1201 1202 framecfg = V_MAC_MIN_FRAMESZ_DEFAULT | 1203 V_MAC_MAX_FRAMESZ_DEFAULT | 1204 V_MAC_BACKOFF_SEL(1); 1205 1206 /* 1207 * Clear out the hash address map 1208 */ 1209 1210 port = PKSEG1(s->sbm_base + R_MAC_HASH_BASE); 1211 for (idx = 0; idx < MAC_HASH_COUNT; idx++) { 1212 SBMAC_WRITECSR(port, 0); 1213 port += sizeof(uint64_t); 1214 } 1215 1216 /* 1217 * Clear out the exact-match table 1218 */ 1219 1220 port = PKSEG1(s->sbm_base + R_MAC_ADDR_BASE); 1221 for (idx = 0; idx < MAC_ADDR_COUNT; idx++) { 1222 SBMAC_WRITECSR(port, 0); 1223 port += sizeof(uint64_t); 1224 } 1225 1226 /* 1227 * Clear out the DMA Channel mapping table registers 1228 */ 1229 1230 port = PKSEG1(s->sbm_base + R_MAC_CHUP0_BASE); 1231 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { 1232 SBMAC_WRITECSR(port, 0); 1233 port += sizeof(uint64_t); 1234 } 1235 1236 port = PKSEG1(s->sbm_base + R_MAC_CHLO0_BASE); 1237 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { 1238 SBMAC_WRITECSR(port, 0); 1239 port += sizeof(uint64_t); 1240 } 1241 1242 /* 1243 * Program the hardware address. It goes into the hardware-address 1244 * register as well as the first filter register. 1245 */ 1246 1247 reg = sbmac_addr2reg(s->sbm_hwaddr); 1248 1249 port = PKSEG1(s->sbm_base + R_MAC_ADDR_BASE); 1250 SBMAC_WRITECSR(port, reg); 1251 port = PKSEG1(s->sbm_base + R_MAC_ETHERNET_ADDR); 1252 SBMAC_WRITECSR(port, 0); // pass1 workaround 1253 1254 /* 1255 * Set the receive filter for no packets, and write values 1256 * to the various config registers 1257 */ 1258 1259 SBMAC_WRITECSR(s->sbm_rxfilter, 0); 1260 SBMAC_WRITECSR(s->sbm_imr, 0); 1261 SBMAC_WRITECSR(s->sbm_framecfg, framecfg); 1262 SBMAC_WRITECSR(s->sbm_fifocfg, fifo); 1263 SBMAC_WRITECSR(s->sbm_maccfg, cfg); 1264 1265 /* 1266 * Initialize DMA channels (rings should be ok now) 1267 */ 1268 1269 sbdma_channel_start(&(s->sbm_rxdma)); 1270 sbdma_channel_start(&(s->sbm_txdma)); 1271 1272 /* 1273 * Configure the speed, duplex, and flow control 1274 */ 1275 1276 sbmac_set_speed(s, s->sbm_speed); 1277 sbmac_set_duplex(s, s->sbm_duplex, s->sbm_fc); 1278 1279 /* 1280 * Fill the receive ring 1281 */ 1282 1283 sbdma_fillring(&(s->sbm_rxdma)); 1284 1285 /* 1286 * Turn on the rest of the bits in the enable register 1287 */ 1288 1289 SBMAC_WRITECSR(s->sbm_macenable, M_MAC_RXDMA_EN0 | M_MAC_TXDMA_EN0 | 1290 M_MAC_RX_ENABLE | M_MAC_TX_ENABLE); 1291 1292 1293 /* 1294 * Accept any kind of interrupt on TX and RX DMA channel 0 1295 */ 1296 SBMAC_WRITECSR(s->sbm_imr, 1297 (M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | 1298 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)); 1299 1300 /* 1301 * Enable receiving unicasts and broadcasts 1302 */ 1303 1304 SBMAC_WRITECSR(s->sbm_rxfilter, M_MAC_UCAST_EN | M_MAC_BCAST_EN); 1305 1306 /* 1307 * On chips which support unaligned DMA features, set the descriptor 1308 * ring for transmit channels to use the unaligned buffer format. 1309 */ 1310 txdma = &(s->sbm_txdma); 1311 1312 if (s->sbm_pass3_dma) { 1313 dma_cfg0 = SBMAC_READCSR(txdma->sbdma_config0); 1314 dma_cfg0 |= V_DMA_DESC_TYPE(K_DMA_DESC_TYPE_RING_UAL_RMW) | 1315 M_DMA_TBX_EN | M_DMA_TDX_EN; 1316 SBMAC_WRITECSR(txdma->sbdma_config0,dma_cfg0); 1317 1318 fifo_cfg = SBMAC_READCSR(s->sbm_fifocfg); 1319 fifo_cfg |= V_MAC_TX_WR_THRSH(8) | 1320 V_MAC_TX_RD_THRSH(8) | V_MAC_TX_RL_THRSH(8); 1321 SBMAC_WRITECSR(s->sbm_fifocfg,fifo_cfg); 1322 } 1323 1324 /* 1325 * we're running now. 1326 */ 1327 1328 s->sbm_state = sbmac_state_on; 1329 s->sc_ethercom.ec_if.if_flags |= IFF_RUNNING; 1330 1331 /* 1332 * Program multicast addresses 1333 */ 1334 1335 sbmac_setmulti(s); 1336 1337 /* 1338 * If channel was in promiscuous mode before, turn that on 1339 */ 1340 1341 if (s->sc_ethercom.ec_if.if_flags & IFF_PROMISC) 1342 sbmac_promiscuous_mode(s, 1); 1343 1344 /* 1345 * Turn on the once-per-second timer 1346 */ 1347 1348 callout_reset(&(s->sc_tick_ch), hz, sbmac_tick, s); 1349 } 1350 1351 /* 1352 * SBMAC_CHANNEL_STOP(s) 1353 * 1354 * Stop packet processing on this MAC. 1355 * 1356 * Input parameters: 1357 * s - sbmac structure 1358 * 1359 * Return value: 1360 * nothing 1361 */ 1362 1363 static void 1364 sbmac_channel_stop(struct sbmac_softc *s) 1365 { 1366 uint64_t ctl; 1367 1368 /* don't do this if already stopped */ 1369 1370 if (s->sbm_state == sbmac_state_off) 1371 return; 1372 1373 /* don't accept any packets, disable all interrupts */ 1374 1375 SBMAC_WRITECSR(s->sbm_rxfilter, 0); 1376 SBMAC_WRITECSR(s->sbm_imr, 0); 1377 1378 /* Turn off ticker */ 1379 1380 callout_stop(&(s->sc_tick_ch)); 1381 1382 /* turn off receiver and transmitter */ 1383 1384 ctl = SBMAC_READCSR(s->sbm_macenable); 1385 ctl &= ~(M_MAC_RXDMA_EN0 | M_MAC_TXDMA_EN0); 1386 SBMAC_WRITECSR(s->sbm_macenable, ctl); 1387 1388 /* We're stopped now. */ 1389 1390 s->sbm_state = sbmac_state_off; 1391 s->sc_ethercom.ec_if.if_flags &= ~IFF_RUNNING; 1392 1393 /* Empty the receive and transmit rings */ 1394 1395 sbdma_emptyring(&(s->sbm_rxdma)); 1396 sbdma_emptyring(&(s->sbm_txdma)); 1397 } 1398 1399 /* 1400 * SBMAC_SET_CHANNEL_STATE(state) 1401 * 1402 * Set the channel's state ON or OFF 1403 * 1404 * Input parameters: 1405 * state - new state 1406 * 1407 * Return value: 1408 * old state 1409 */ 1410 1411 static sbmac_state_t 1412 sbmac_set_channel_state(struct sbmac_softc *sc, sbmac_state_t state) 1413 { 1414 sbmac_state_t oldstate = sc->sbm_state; 1415 1416 /* 1417 * If same as previous state, return 1418 */ 1419 1420 if (state == oldstate) 1421 return oldstate; 1422 1423 /* 1424 * If new state is ON, turn channel on 1425 */ 1426 1427 if (state == sbmac_state_on) 1428 sbmac_channel_start(sc); 1429 else 1430 sbmac_channel_stop(sc); 1431 1432 /* 1433 * Return previous state 1434 */ 1435 1436 return oldstate; 1437 } 1438 1439 /* 1440 * SBMAC_PROMISCUOUS_MODE(sc, onoff) 1441 * 1442 * Turn on or off promiscuous mode 1443 * 1444 * Input parameters: 1445 * sc - softc 1446 * onoff - 1 to turn on, 0 to turn off 1447 * 1448 * Return value: 1449 * nothing 1450 */ 1451 1452 static void 1453 sbmac_promiscuous_mode(struct sbmac_softc *sc, int onoff) 1454 { 1455 uint64_t reg; 1456 1457 if (sc->sbm_state != sbmac_state_on) 1458 return; 1459 1460 if (onoff) { 1461 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1462 reg |= M_MAC_ALLPKT_EN; 1463 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1464 } else { 1465 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1466 reg &= ~M_MAC_ALLPKT_EN; 1467 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1468 } 1469 } 1470 1471 /* 1472 * SBMAC_INIT_AND_START(sc) 1473 * 1474 * Stop the channel and restart it. This is generally used 1475 * when we have to do something to the channel that requires 1476 * a swift kick. 1477 * 1478 * Input parameters: 1479 * sc - softc 1480 */ 1481 1482 static void 1483 sbmac_init_and_start(struct sbmac_softc *sc) 1484 { 1485 int s; 1486 1487 s = splnet(); 1488 1489 mii_pollstat(&sc->sc_mii); /* poll phy for current speed */ 1490 sbmac_mii_statchg((struct device *) sc); /* set state to new speed */ 1491 sbmac_set_channel_state(sc, sbmac_state_on); 1492 1493 splx(s); 1494 } 1495 1496 /* 1497 * SBMAC_ADDR2REG(ptr) 1498 * 1499 * Convert six bytes into the 64-bit register value that 1500 * we typically write into the SBMAC's address/mcast registers 1501 * 1502 * Input parameters: 1503 * ptr - pointer to 6 bytes 1504 * 1505 * Return value: 1506 * register value 1507 */ 1508 1509 static uint64_t 1510 sbmac_addr2reg(u_char *ptr) 1511 { 1512 uint64_t reg = 0; 1513 1514 ptr += 6; 1515 1516 reg |= (uint64_t) *(--ptr); 1517 reg <<= 8; 1518 reg |= (uint64_t) *(--ptr); 1519 reg <<= 8; 1520 reg |= (uint64_t) *(--ptr); 1521 reg <<= 8; 1522 reg |= (uint64_t) *(--ptr); 1523 reg <<= 8; 1524 reg |= (uint64_t) *(--ptr); 1525 reg <<= 8; 1526 reg |= (uint64_t) *(--ptr); 1527 1528 return reg; 1529 } 1530 1531 /* 1532 * SBMAC_SET_SPEED(s, speed) 1533 * 1534 * Configure LAN speed for the specified MAC. 1535 * Warning: must be called when MAC is off! 1536 * 1537 * Input parameters: 1538 * s - sbmac structure 1539 * speed - speed to set MAC to (see sbmac_speed_t enum) 1540 * 1541 * Return value: 1542 * 1 if successful 1543 * 0 indicates invalid parameters 1544 */ 1545 1546 static int 1547 sbmac_set_speed(struct sbmac_softc *s, sbmac_speed_t speed) 1548 { 1549 uint64_t cfg; 1550 uint64_t framecfg; 1551 1552 /* 1553 * Save new current values 1554 */ 1555 1556 s->sbm_speed = speed; 1557 1558 if (s->sbm_state != sbmac_state_off) 1559 panic("sbmac_set_speed while MAC not off"); 1560 1561 /* 1562 * Read current register values 1563 */ 1564 1565 cfg = SBMAC_READCSR(s->sbm_maccfg); 1566 framecfg = SBMAC_READCSR(s->sbm_framecfg); 1567 1568 /* 1569 * Mask out the stuff we want to change 1570 */ 1571 1572 cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL); 1573 framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH | 1574 M_MAC_SLOT_SIZE); 1575 1576 /* 1577 * Now add in the new bits 1578 */ 1579 1580 switch (speed) { 1581 case sbmac_speed_10: 1582 framecfg |= V_MAC_IFG_RX_10 | 1583 V_MAC_IFG_TX_10 | 1584 K_MAC_IFG_THRSH_10 | 1585 V_MAC_SLOT_SIZE_10; 1586 cfg |= V_MAC_SPEED_SEL_10MBPS; 1587 break; 1588 1589 case sbmac_speed_100: 1590 framecfg |= V_MAC_IFG_RX_100 | 1591 V_MAC_IFG_TX_100 | 1592 V_MAC_IFG_THRSH_100 | 1593 V_MAC_SLOT_SIZE_100; 1594 cfg |= V_MAC_SPEED_SEL_100MBPS ; 1595 break; 1596 1597 case sbmac_speed_1000: 1598 framecfg |= V_MAC_IFG_RX_1000 | 1599 V_MAC_IFG_TX_1000 | 1600 V_MAC_IFG_THRSH_1000 | 1601 V_MAC_SLOT_SIZE_1000; 1602 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN; 1603 break; 1604 1605 case sbmac_speed_auto: /* XXX not implemented */ 1606 /* fall through */ 1607 default: 1608 return 0; 1609 } 1610 1611 /* 1612 * Send the bits back to the hardware 1613 */ 1614 1615 SBMAC_WRITECSR(s->sbm_framecfg, framecfg); 1616 SBMAC_WRITECSR(s->sbm_maccfg, cfg); 1617 1618 return 1; 1619 } 1620 1621 /* 1622 * SBMAC_SET_DUPLEX(s, duplex, fc) 1623 * 1624 * Set Ethernet duplex and flow control options for this MAC 1625 * Warning: must be called when MAC is off! 1626 * 1627 * Input parameters: 1628 * s - sbmac structure 1629 * duplex - duplex setting (see sbmac_duplex_t) 1630 * fc - flow control setting (see sbmac_fc_t) 1631 * 1632 * Return value: 1633 * 1 if ok 1634 * 0 if an invalid parameter combination was specified 1635 */ 1636 1637 static int 1638 sbmac_set_duplex(struct sbmac_softc *s, sbmac_duplex_t duplex, sbmac_fc_t fc) 1639 { 1640 uint64_t cfg; 1641 1642 /* 1643 * Save new current values 1644 */ 1645 1646 s->sbm_duplex = duplex; 1647 s->sbm_fc = fc; 1648 1649 if (s->sbm_state != sbmac_state_off) 1650 panic("sbmac_set_duplex while MAC not off"); 1651 1652 /* 1653 * Read current register values 1654 */ 1655 1656 cfg = SBMAC_READCSR(s->sbm_maccfg); 1657 1658 /* 1659 * Mask off the stuff we're about to change 1660 */ 1661 1662 cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN); 1663 1664 switch (duplex) { 1665 case sbmac_duplex_half: 1666 switch (fc) { 1667 case sbmac_fc_disabled: 1668 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED; 1669 break; 1670 1671 case sbmac_fc_collision: 1672 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED; 1673 break; 1674 1675 case sbmac_fc_carrier: 1676 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR; 1677 break; 1678 1679 case sbmac_fc_auto: /* XXX not implemented */ 1680 /* fall through */ 1681 case sbmac_fc_frame: /* not valid in half duplex */ 1682 default: /* invalid selection */ 1683 panic("%s: invalid half duplex fc selection %d", 1684 s->sc_dev.dv_xname, fc); 1685 return 0; 1686 } 1687 break; 1688 1689 case sbmac_duplex_full: 1690 switch (fc) { 1691 case sbmac_fc_disabled: 1692 cfg |= V_MAC_FC_CMD_DISABLED; 1693 break; 1694 1695 case sbmac_fc_frame: 1696 cfg |= V_MAC_FC_CMD_ENABLED; 1697 break; 1698 1699 case sbmac_fc_collision: /* not valid in full duplex */ 1700 case sbmac_fc_carrier: /* not valid in full duplex */ 1701 case sbmac_fc_auto: /* XXX not implemented */ 1702 /* fall through */ 1703 default: 1704 panic("%s: invalid full duplex fc selection %d", 1705 s->sc_dev.dv_xname, fc); 1706 return 0; 1707 } 1708 break; 1709 1710 default: 1711 /* fall through */ 1712 case sbmac_duplex_auto: 1713 panic("%s: bad duplex %d", s->sc_dev.dv_xname, duplex); 1714 /* XXX not implemented */ 1715 break; 1716 } 1717 1718 /* 1719 * Send the bits back to the hardware 1720 */ 1721 1722 SBMAC_WRITECSR(s->sbm_maccfg, cfg); 1723 1724 return 1; 1725 } 1726 1727 /* 1728 * SBMAC_INTR() 1729 * 1730 * Interrupt handler for MAC interrupts 1731 * 1732 * Input parameters: 1733 * MAC structure 1734 * 1735 * Return value: 1736 * nothing 1737 */ 1738 1739 /* ARGSUSED */ 1740 static void 1741 sbmac_intr(void *xsc, uint32_t status, uint32_t pc) 1742 { 1743 struct sbmac_softc *sc = (struct sbmac_softc *) xsc; 1744 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1745 uint64_t isr; 1746 1747 for (;;) { 1748 1749 /* 1750 * Read the ISR (this clears the bits in the real register) 1751 */ 1752 1753 isr = SBMAC_READCSR(sc->sbm_isr); 1754 1755 if (isr == 0) 1756 break; 1757 1758 /* 1759 * Transmits on channel 0 1760 */ 1761 1762 if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) { 1763 sbdma_tx_process(sc, &(sc->sbm_txdma)); 1764 SBMAC_EVCNT_INCR(sc->sbm_ev_txintr); 1765 } 1766 1767 /* 1768 * Receives on channel 0 1769 */ 1770 1771 if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) { 1772 sbdma_rx_process(sc, &(sc->sbm_rxdma)); 1773 SBMAC_EVCNT_INCR(sc->sbm_ev_rxintr); 1774 } 1775 } 1776 1777 /* try to get more packets going */ 1778 sbmac_start(ifp); 1779 } 1780 1781 1782 /* 1783 * SBMAC_START(ifp) 1784 * 1785 * Start output on the specified interface. Basically, we 1786 * queue as many buffers as we can until the ring fills up, or 1787 * we run off the end of the queue, whichever comes first. 1788 * 1789 * Input parameters: 1790 * ifp - interface 1791 * 1792 * Return value: 1793 * nothing 1794 */ 1795 1796 static void 1797 sbmac_start(struct ifnet *ifp) 1798 { 1799 struct sbmac_softc *sc; 1800 struct mbuf *m_head = NULL; 1801 int rv; 1802 1803 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1804 return; 1805 1806 sc = ifp->if_softc; 1807 1808 for (;;) { 1809 1810 IF_DEQUEUE(&ifp->if_snd, m_head); 1811 if (m_head == NULL) 1812 break; 1813 1814 /* 1815 * Put the buffer on the transmit ring. If we 1816 * don't have room, set the OACTIVE flag and wait 1817 * for the NIC to drain the ring. 1818 */ 1819 1820 rv = sbdma_add_txbuffer(&(sc->sbm_txdma), m_head); 1821 1822 if (rv == 0) { 1823 /* 1824 * If there's a BPF listener, bounce a copy of this 1825 * frame to it. 1826 */ 1827 #if (NBPFILTER > 0) 1828 if (ifp->if_bpf) 1829 bpf_mtap(ifp->if_bpf, m_head); 1830 #endif 1831 if (!sc->sbm_pass3_dma) { 1832 /* 1833 * Don't free mbuf if we're not copying to new 1834 * mbuf in sbdma_add_txbuffer. It will be 1835 * freed in sbdma_tx_process. 1836 */ 1837 m_freem(m_head); 1838 } 1839 } else { 1840 IF_PREPEND(&ifp->if_snd, m_head); 1841 ifp->if_flags |= IFF_OACTIVE; 1842 break; 1843 } 1844 } 1845 } 1846 1847 /* 1848 * SBMAC_SETMULTI(sc) 1849 * 1850 * Reprogram the multicast table into the hardware, given 1851 * the list of multicasts associated with the interface 1852 * structure. 1853 * 1854 * Input parameters: 1855 * sc - softc 1856 * 1857 * Return value: 1858 * nothing 1859 */ 1860 1861 static void 1862 sbmac_setmulti(struct sbmac_softc *sc) 1863 { 1864 struct ifnet *ifp; 1865 uint64_t reg; 1866 sbmac_port_t port; 1867 int idx; 1868 struct ether_multi *enm; 1869 struct ether_multistep step; 1870 1871 ifp = &sc->sc_ethercom.ec_if; 1872 1873 /* 1874 * Clear out entire multicast table. We do this by nuking 1875 * the entire hash table and all the direct matches except 1876 * the first one, which is used for our station address 1877 */ 1878 1879 for (idx = 1; idx < MAC_ADDR_COUNT; idx++) { 1880 port = PKSEG1(sc->sbm_base + 1881 R_MAC_ADDR_BASE+(idx*sizeof(uint64_t))); 1882 SBMAC_WRITECSR(port, 0); 1883 } 1884 1885 for (idx = 0; idx < MAC_HASH_COUNT; idx++) { 1886 port = PKSEG1(sc->sbm_base + 1887 R_MAC_HASH_BASE+(idx*sizeof(uint64_t))); 1888 SBMAC_WRITECSR(port, 0); 1889 } 1890 1891 /* 1892 * Clear the filter to say we don't want any multicasts. 1893 */ 1894 1895 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1896 reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN); 1897 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1898 1899 if (ifp->if_flags & IFF_ALLMULTI) { 1900 /* 1901 * Enable ALL multicasts. Do this by inverting the 1902 * multicast enable bit. 1903 */ 1904 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1905 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN); 1906 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1907 return; 1908 } 1909 1910 /* 1911 * Progam new multicast entries. For now, only use the 1912 * perfect filter. In the future we'll need to use the 1913 * hash filter if the perfect filter overflows 1914 */ 1915 1916 /* 1917 * XXX only using perfect filter for now, need to use hash 1918 * XXX if the table overflows 1919 */ 1920 1921 idx = 1; /* skip station address */ 1922 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1923 while ((enm != NULL) && (idx < MAC_ADDR_COUNT)) { 1924 reg = sbmac_addr2reg(enm->enm_addrlo); 1925 port = PKSEG1(sc->sbm_base + 1926 R_MAC_ADDR_BASE+(idx*sizeof(uint64_t))); 1927 SBMAC_WRITECSR(port, reg); 1928 idx++; 1929 ETHER_NEXT_MULTI(step, enm); 1930 } 1931 1932 /* 1933 * Enable the "accept multicast bits" if we programmed at least one 1934 * multicast. 1935 */ 1936 1937 if (idx > 1) { 1938 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1939 reg |= M_MAC_MCAST_EN; 1940 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1941 } 1942 } 1943 1944 /* 1945 * SBMAC_ETHER_IOCTL(ifp, cmd, data) 1946 * 1947 * Generic IOCTL requests for this interface. The basic 1948 * stuff is handled here for bringing the interface up, 1949 * handling multicasts, etc. 1950 * 1951 * Input parameters: 1952 * ifp - interface structure 1953 * cmd - command code 1954 * data - pointer to data 1955 * 1956 * Return value: 1957 * return value (0 is success) 1958 */ 1959 1960 static int 1961 sbmac_ether_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1962 { 1963 struct ifaddr *ifa = (struct ifaddr *) data; 1964 struct sbmac_softc *sc = ifp->if_softc; 1965 1966 switch (cmd) { 1967 case SIOCSIFADDR: 1968 ifp->if_flags |= IFF_UP; 1969 1970 switch (ifa->ifa_addr->sa_family) { 1971 #ifdef INET 1972 case AF_INET: 1973 sbmac_init_and_start(sc); 1974 arp_ifinit(ifp, ifa); 1975 break; 1976 #endif 1977 #ifdef NS 1978 case AF_NS: 1979 { 1980 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1981 1982 if (ns_nullhost(*ina)) 1983 ina->x_host = 1984 *(union ns_host *)LLADDR(ifp->if_sadl); 1985 else 1986 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1987 ifp->if_addrlen); 1988 /* Set new address. */ 1989 sbmac_init_and_start(sc); 1990 break; 1991 } 1992 #endif 1993 default: 1994 sbmac_init_and_start(sc); 1995 break; 1996 } 1997 break; 1998 1999 default: 2000 return (EINVAL); 2001 } 2002 2003 return (0); 2004 } 2005 2006 /* 2007 * SBMAC_IOCTL(ifp, command, data) 2008 * 2009 * Main IOCTL handler - dispatches to other IOCTLs for various 2010 * types of requests. 2011 * 2012 * Input parameters: 2013 * ifp - interface pointer 2014 * command - command code 2015 * data - pointer to argument data 2016 * 2017 * Return value: 2018 * 0 if ok 2019 * else error code 2020 */ 2021 2022 static int 2023 sbmac_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2024 { 2025 struct sbmac_softc *sc = ifp->if_softc; 2026 struct ifreq *ifr = (struct ifreq *) data; 2027 int s, error = 0; 2028 2029 s = splnet(); 2030 2031 switch(command) { 2032 case SIOCSIFADDR: 2033 case SIOCGIFADDR: 2034 error = sbmac_ether_ioctl(ifp, command, data); 2035 break; 2036 case SIOCSIFMTU: 2037 if (ifr->ifr_mtu > ETHER_MAX_LEN) 2038 error = EINVAL; 2039 else { 2040 ifp->if_mtu = ifr->ifr_mtu; 2041 /* XXX Program new MTU here */ 2042 } 2043 break; 2044 case SIOCSIFFLAGS: 2045 if (ifp->if_flags & IFF_UP) { 2046 /* 2047 * If only the state of the PROMISC flag changed, 2048 * just tweak the hardware registers. 2049 */ 2050 if ((ifp->if_flags & IFF_RUNNING) && 2051 (ifp->if_flags & IFF_PROMISC)) { 2052 /* turn on promiscuous mode */ 2053 sbmac_promiscuous_mode(sc, 1); 2054 } else if (ifp->if_flags & IFF_RUNNING && 2055 !(ifp->if_flags & IFF_PROMISC)) { 2056 /* turn off promiscuous mode */ 2057 sbmac_promiscuous_mode(sc, 0); 2058 } else 2059 sbmac_set_channel_state(sc, sbmac_state_on); 2060 } else { 2061 if (ifp->if_flags & IFF_RUNNING) 2062 sbmac_set_channel_state(sc, sbmac_state_off); 2063 } 2064 2065 sc->sbm_if_flags = ifp->if_flags; 2066 error = 0; 2067 break; 2068 2069 case SIOCADDMULTI: 2070 case SIOCDELMULTI: 2071 if (ifp->if_flags & IFF_RUNNING) { 2072 sbmac_setmulti(sc); 2073 error = 0; 2074 } 2075 break; 2076 case SIOCSIFMEDIA: 2077 case SIOCGIFMEDIA: 2078 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 2079 break; 2080 default: 2081 error = EINVAL; 2082 break; 2083 } 2084 2085 (void)splx(s); 2086 2087 return(error); 2088 } 2089 2090 /* 2091 * SBMAC_IFMEDIA_UPD(ifp) 2092 * 2093 * Configure an appropriate media type for this interface, 2094 * given the data in the interface structure 2095 * 2096 * Input parameters: 2097 * ifp - interface 2098 * 2099 * Return value: 2100 * 0 if ok 2101 * else error code 2102 */ 2103 2104 static int 2105 sbmac_mediachange(struct ifnet *ifp) 2106 { 2107 struct sbmac_softc *sc = ifp->if_softc; 2108 2109 if (ifp->if_flags & IFF_UP) 2110 mii_mediachg(&sc->sc_mii); 2111 return(0); 2112 } 2113 2114 /* 2115 * SBMAC_IFMEDIA_STS(ifp, ifmr) 2116 * 2117 * Report current media status (used by ifconfig, for example) 2118 * 2119 * Input parameters: 2120 * ifp - interface structure 2121 * ifmr - media request structure 2122 * 2123 * Return value: 2124 * nothing 2125 */ 2126 2127 static void 2128 sbmac_mediastatus(struct ifnet *ifp, struct ifmediareq *req) 2129 { 2130 struct sbmac_softc *sc = ifp->if_softc; 2131 2132 mii_pollstat(&sc->sc_mii); 2133 req->ifm_status = sc->sc_mii.mii_media_status; 2134 req->ifm_active = sc->sc_mii.mii_media_active; 2135 } 2136 2137 /* 2138 * SBMAC_WATCHDOG(ifp) 2139 * 2140 * Called periodically to make sure we're still happy. 2141 * 2142 * Input parameters: 2143 * ifp - interface structure 2144 * 2145 * Return value: 2146 * nothing 2147 */ 2148 2149 static void 2150 sbmac_watchdog(struct ifnet *ifp) 2151 { 2152 2153 /* XXX do something */ 2154 } 2155 2156 /* 2157 * One second timer, used to tick MII. 2158 */ 2159 static void 2160 sbmac_tick(void *arg) 2161 { 2162 struct sbmac_softc *sc = arg; 2163 int s; 2164 2165 s = splnet(); 2166 mii_tick(&sc->sc_mii); 2167 splx(s); 2168 2169 callout_reset(&sc->sc_tick_ch, hz, sbmac_tick, sc); 2170 } 2171 2172 2173 /* 2174 * SBMAC_MATCH(parent, match, aux) 2175 * 2176 * Part of the config process - see if this device matches the 2177 * info about what we expect to find on the bus. 2178 * 2179 * Input parameters: 2180 * parent - parent bus structure 2181 * match - 2182 * aux - bus-specific args 2183 * 2184 * Return value: 2185 * 1 if we match 2186 * 0 if we don't match 2187 */ 2188 2189 static int 2190 sbmac_match(struct device *parent, struct cfdata *match, void *aux) 2191 { 2192 struct sbobio_attach_args *sap = aux; 2193 2194 /* 2195 * Make sure it's a MAC 2196 */ 2197 2198 if (sap->sa_locs.sa_type != SBOBIO_DEVTYPE_MAC) 2199 return 0; 2200 2201 /* 2202 * Yup, it is. 2203 */ 2204 2205 return 1; 2206 } 2207 2208 /* 2209 * SBMAC_PARSE_XDIGIT(str) 2210 * 2211 * Parse a hex digit, returning its value 2212 * 2213 * Input parameters: 2214 * str - character 2215 * 2216 * Return value: 2217 * hex value, or -1 if invalid 2218 */ 2219 2220 static int 2221 sbmac_parse_xdigit(char str) 2222 { 2223 int digit; 2224 2225 if ((str >= '0') && (str <= '9')) 2226 digit = str - '0'; 2227 else if ((str >= 'a') && (str <= 'f')) 2228 digit = str - 'a' + 10; 2229 else if ((str >= 'A') && (str <= 'F')) 2230 digit = str - 'A' + 10; 2231 else 2232 digit = -1; 2233 2234 return digit; 2235 } 2236 2237 /* 2238 * SBMAC_PARSE_HWADDR(str, hwaddr) 2239 * 2240 * Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte 2241 * Ethernet address. 2242 * 2243 * Input parameters: 2244 * str - string 2245 * hwaddr - pointer to hardware address 2246 * 2247 * Return value: 2248 * 0 if ok, else -1 2249 */ 2250 2251 static int 2252 sbmac_parse_hwaddr(char *str, u_char *hwaddr) 2253 { 2254 int digit1, digit2; 2255 int idx = 6; 2256 2257 while (*str && (idx > 0)) { 2258 digit1 = sbmac_parse_xdigit(*str); 2259 if (digit1 < 0) 2260 return -1; 2261 str++; 2262 if (!*str) 2263 return -1; 2264 2265 if ((*str == ':') || (*str == '-')) { 2266 digit2 = digit1; 2267 digit1 = 0; 2268 } else { 2269 digit2 = sbmac_parse_xdigit(*str); 2270 if (digit2 < 0) 2271 return -1; 2272 str++; 2273 } 2274 2275 *hwaddr++ = (digit1 << 4) | digit2; 2276 idx--; 2277 2278 if (*str == '-') 2279 str++; 2280 if (*str == ':') 2281 str++; 2282 } 2283 return 0; 2284 } 2285 2286 /* 2287 * SBMAC_ATTACH(parent, self, aux) 2288 * 2289 * Attach routine - init hardware and hook ourselves into NetBSD. 2290 * 2291 * Input parameters: 2292 * parent - parent bus device 2293 * self - our softc 2294 * aux - attach data 2295 * 2296 * Return value: 2297 * nothing 2298 */ 2299 2300 static void 2301 sbmac_attach(struct device *parent, struct device *self, void *aux) 2302 { 2303 struct ifnet *ifp; 2304 struct sbmac_softc *sc; 2305 struct sbobio_attach_args *sap = aux; 2306 u_char *eaddr; 2307 static int unit = 0; /* XXX */ 2308 uint64_t ea_reg; 2309 int idx; 2310 2311 sc = (struct sbmac_softc *)self; 2312 2313 /* Determine controller base address */ 2314 2315 sc->sbm_base = (sbmac_port_t) sap->sa_base + sap->sa_locs.sa_offset; 2316 2317 eaddr = sc->sbm_hwaddr; 2318 2319 /* 2320 * Initialize context (get pointers to registers and stuff), then 2321 * allocate the memory for the descriptor tables. 2322 */ 2323 2324 sbmac_initctx(sc); 2325 2326 callout_init(&(sc->sc_tick_ch)); 2327 2328 /* 2329 * Read the ethernet address. The firwmare left this programmed 2330 * for us in the ethernet address register for each mac. 2331 */ 2332 2333 ea_reg = SBMAC_READCSR(PKSEG1(sc->sbm_base + R_MAC_ETHERNET_ADDR)); 2334 for (idx = 0; idx < 6; idx++) { 2335 eaddr[idx] = (uint8_t) (ea_reg & 0xFF); 2336 ea_reg >>= 8; 2337 } 2338 2339 #define SBMAC_DEFAULT_HWADDR "40:00:00:00:01:00" 2340 if (eaddr[0] == 0 && eaddr[1] == 0 && eaddr[2] == 0 && 2341 eaddr[3] == 0 && eaddr[4] == 0 && eaddr[5] == 0) { 2342 sbmac_parse_hwaddr(SBMAC_DEFAULT_HWADDR, eaddr); 2343 eaddr[5] = unit; 2344 } 2345 2346 #ifdef SBMAC_ETH0_HWADDR 2347 if (unit == 0) 2348 sbmac_parse_hwaddr(SBMAC_ETH0_HWADDR, eaddr); 2349 #endif 2350 #ifdef SBMAC_ETH1_HWADDR 2351 if (unit == 1) 2352 sbmac_parse_hwaddr(SBMAC_ETH1_HWADDR, eaddr); 2353 #endif 2354 #ifdef SBMAC_ETH2_HWADDR 2355 if (unit == 2) 2356 sbmac_parse_hwaddr(SBMAC_ETH2_HWADDR, eaddr); 2357 #endif 2358 unit++; 2359 2360 /* 2361 * Display Ethernet address (this is called during the config process 2362 * so we need to finish off the config message that was being displayed) 2363 */ 2364 printf(": Ethernet%s\n", 2365 sc->sbm_pass3_dma ? ", using unaligned tx DMA" : ""); 2366 printf("%s: Ethernet address: %s\n", self->dv_xname, 2367 ether_sprintf(eaddr)); 2368 2369 2370 /* 2371 * Set up ifnet structure 2372 */ 2373 2374 ifp = &sc->sc_ethercom.ec_if; 2375 ifp->if_softc = sc; 2376 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 2377 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 2378 IFF_NOTRAILERS; 2379 ifp->if_ioctl = sbmac_ioctl; 2380 ifp->if_start = sbmac_start; 2381 ifp->if_watchdog = sbmac_watchdog; 2382 ifp->if_snd.ifq_maxlen = SBMAC_MAX_TXDESCR - 1; 2383 2384 /* 2385 * Set up ifmedia support. 2386 */ 2387 2388 /* 2389 * Initialize MII/media info. 2390 */ 2391 sc->sc_mii.mii_ifp = ifp; 2392 sc->sc_mii.mii_readreg = sbmac_mii_readreg; 2393 sc->sc_mii.mii_writereg = sbmac_mii_writereg; 2394 sc->sc_mii.mii_statchg = sbmac_mii_statchg; 2395 ifmedia_init(&sc->sc_mii.mii_media, 0, sbmac_mediachange, 2396 sbmac_mediastatus); 2397 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 2398 MII_OFFSET_ANY, 0); 2399 2400 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 2401 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 2402 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 2403 } else { 2404 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2405 } 2406 2407 2408 /* 2409 * map/route interrupt 2410 */ 2411 2412 sc->sbm_intrhand = cpu_intr_establish(sap->sa_locs.sa_intr[0], IPL_NET, 2413 sbmac_intr, sc); 2414 2415 /* 2416 * Call MI attach routines. 2417 */ 2418 if_attach(ifp); 2419 ether_ifattach(ifp, eaddr); 2420 } 2421
Indexes created Mon Sep 29 21:09:56 GMT 2025