sbmac.c revision 1.18
1 /* $NetBSD: sbmac.c,v 1.18 2004/03/19 06:01:31 cgd Exp $ */ 2 3 /* 4 * Copyright 2000, 2001 5 * Broadcom Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and copied only 8 * in accordance with the following terms and conditions. Subject to these 9 * conditions, you may download, copy, install, use, modify and distribute 10 * modified or unmodified copies of this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce and 14 * retain this copyright notice and list of conditions as they appear in 15 * the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Broadcom Corporation. The "Broadcom Corporation" name may not be 19 * used to endorse or promote products derived from this software 20 * without the prior written permission of Broadcom Corporation. 21 * 22 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR 25 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE 26 * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE 27 * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 32 * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: sbmac.c,v 1.18 2004/03/19 06:01:31 cgd Exp $"); 37 38 #include "bpfilter.h" 39 #include "opt_inet.h" 40 #include "opt_ns.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/queue.h> 50 #include <sys/device.h> 51 52 #include <net/if.h> 53 #include <net/if_arp.h> 54 #include <net/if_ether.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 58 #if NBPFILTER > 0 59 #include <net/bpf.h> 60 #endif 61 62 #ifdef INET 63 #include <netinet/in.h> 64 #include <netinet/if_inarp.h> 65 #endif 66 67 #ifdef NS 68 #include <netns/ns.h> 69 #include <netns/ns_if.h> 70 #endif 71 72 #include <machine/locore.h> 73 74 #include "sbobiovar.h" 75 76 #include <dev/mii/mii.h> 77 #include <dev/mii/miivar.h> 78 #include <dev/mii/mii_bitbang.h> 79 80 #include <mips/sibyte/include/sb1250_defs.h> 81 #include <mips/sibyte/include/sb1250_regs.h> 82 #include <mips/sibyte/include/sb1250_mac.h> 83 #include <mips/sibyte/include/sb1250_dma.h> 84 #include <mips/sibyte/include/sb1250_scd.h> 85 86 /* Simple types */ 87 88 typedef u_long sbmac_port_t; 89 typedef uint64_t sbmac_physaddr_t; 90 typedef uint64_t sbmac_enetaddr_t; 91 92 typedef enum { sbmac_speed_auto, sbmac_speed_10, 93 sbmac_speed_100, sbmac_speed_1000 } sbmac_speed_t; 94 95 typedef enum { sbmac_duplex_auto, sbmac_duplex_half, 96 sbmac_duplex_full } sbmac_duplex_t; 97 98 typedef enum { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame, 99 sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t; 100 101 typedef enum { sbmac_state_uninit, sbmac_state_off, sbmac_state_on, 102 sbmac_state_broken } sbmac_state_t; 103 104 105 /* Macros */ 106 107 #define SBMAC_EVENT_COUNTERS /* Include counters for various events */ 108 109 #define SBDMA_NEXTBUF(d, f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \ 110 (d)->sbdma_dscrtable : (d)->f+1) 111 112 113 #define CACHELINESIZE 32 114 #define NUMCACHEBLKS(x) (((x)+CACHELINESIZE-1)/CACHELINESIZE) 115 #define KMALLOC(x) malloc((x), M_DEVBUF, M_DONTWAIT) 116 #define KVTOPHYS(x) kvtophys((vaddr_t)(x)) 117 118 #ifdef SBMACDEBUG 119 #define dprintf(x) printf x 120 #else 121 #define dprintf(x) 122 #endif 123 124 #define SBMAC_READCSR(t) mips3_ld((uint64_t *) (t)) 125 #define SBMAC_WRITECSR(t, v) mips3_sd((uint64_t *) (t), (v)) 126 127 #define PKSEG1(x) ((sbmac_port_t) MIPS_PHYS_TO_KSEG1(x)) 128 129 /* These are limited to fit within one virtual page. */ 130 #define SBMAC_MAX_TXDESCR 256 /* should be 1024 */ 131 #define SBMAC_MAX_RXDESCR 256 /* should be 512 */ 132 133 #define ETHER_ALIGN 2 134 135 /* DMA Descriptor structure */ 136 137 typedef struct sbdmadscr_s { 138 uint64_t dscr_a; 139 uint64_t dscr_b; 140 } sbdmadscr_t; 141 142 143 /* DMA Controller structure */ 144 145 typedef struct sbmacdma_s { 146 147 /* 148 * This stuff is used to identify the channel and the registers 149 * associated with it. 150 */ 151 152 struct sbmac_softc *sbdma_eth; /* back pointer to associated MAC */ 153 int sbdma_channel; /* channel number */ 154 int sbdma_txdir; /* direction (1=transmit) */ 155 int sbdma_maxdescr; /* total # of descriptors in ring */ 156 sbmac_port_t sbdma_config0; /* DMA config register 0 */ 157 sbmac_port_t sbdma_config1; /* DMA config register 1 */ 158 sbmac_port_t sbdma_dscrbase; /* Descriptor base address */ 159 sbmac_port_t sbdma_dscrcnt; /* Descriptor count register */ 160 sbmac_port_t sbdma_curdscr; /* current descriptor address */ 161 162 /* 163 * This stuff is for maintenance of the ring 164 */ 165 166 sbdmadscr_t *sbdma_dscrtable; /* base of descriptor table */ 167 sbdmadscr_t *sbdma_dscrtable_end; /* end of descriptor table */ 168 169 struct mbuf **sbdma_ctxtable; /* context table, one per descr */ 170 171 paddr_t sbdma_dscrtable_phys; /* and also the phys addr */ 172 sbdmadscr_t *sbdma_addptr; /* next dscr for sw to add */ 173 sbdmadscr_t *sbdma_remptr; /* next dscr for sw to remove */ 174 } sbmacdma_t; 175 176 177 /* Ethernet softc structure */ 178 179 struct sbmac_softc { 180 181 /* 182 * NetBSD-specific things 183 */ 184 struct device sc_dev; /* base device (must be first) */ 185 struct ethercom sc_ethercom; /* Ethernet common part */ 186 struct mii_data sc_mii; 187 struct callout sc_tick_ch; 188 189 int sbm_if_flags; 190 void *sbm_intrhand; 191 192 /* 193 * Controller-specific things 194 */ 195 196 sbmac_port_t sbm_base; /* MAC's base address */ 197 sbmac_state_t sbm_state; /* current state */ 198 199 sbmac_port_t sbm_macenable; /* MAC Enable Register */ 200 sbmac_port_t sbm_maccfg; /* MAC Configuration Register */ 201 sbmac_port_t sbm_fifocfg; /* FIFO configuration register */ 202 sbmac_port_t sbm_framecfg; /* Frame configuration register */ 203 sbmac_port_t sbm_rxfilter; /* receive filter register */ 204 sbmac_port_t sbm_isr; /* Interrupt status register */ 205 sbmac_port_t sbm_imr; /* Interrupt mask register */ 206 207 sbmac_speed_t sbm_speed; /* current speed */ 208 sbmac_duplex_t sbm_duplex; /* current duplex */ 209 sbmac_fc_t sbm_fc; /* current flow control setting */ 210 int sbm_rxflags; /* received packet flags */ 211 212 u_char sbm_hwaddr[ETHER_ADDR_LEN]; 213 214 sbmacdma_t sbm_txdma; /* for now, only use channel 0 */ 215 sbmacdma_t sbm_rxdma; 216 217 int sbm_pass3_dma; /* chip has pass3 SOC DMA features */ 218 219 #ifdef SBMAC_EVENT_COUNTERS 220 struct evcnt sbm_ev_rxintr; /* Rx interrupts */ 221 struct evcnt sbm_ev_txintr; /* Tx interrupts */ 222 struct evcnt sbm_ev_txdrop; /* Tx dropped due to no mbuf alloc failed */ 223 struct evcnt sbm_ev_txstall; /* Tx stalled due to no descriptors free */ 224 225 struct evcnt sbm_ev_txsplit; /* pass3 Tx split mbuf */ 226 struct evcnt sbm_ev_txkeep; /* pass3 Tx didn't split mbuf */ 227 #endif 228 }; 229 230 231 #ifdef SBMAC_EVENT_COUNTERS 232 #define SBMAC_EVCNT_INCR(ev) (ev).ev_count++ 233 #else 234 #define SBMAC_EVCNT_INCR(ev) do { /* nothing */ } while (0) 235 #endif 236 237 /* Externs */ 238 239 extern paddr_t kvtophys(vaddr_t); 240 241 /* Prototypes */ 242 243 static void sbdma_initctx(sbmacdma_t *d, struct sbmac_softc *s, int chan, 244 int txrx, int maxdescr); 245 static void sbdma_channel_start(sbmacdma_t *d); 246 static int sbdma_add_rcvbuffer(sbmacdma_t *d, struct mbuf *m); 247 static int sbdma_add_txbuffer(sbmacdma_t *d, struct mbuf *m); 248 static void sbdma_emptyring(sbmacdma_t *d); 249 static void sbdma_fillring(sbmacdma_t *d); 250 static void sbdma_rx_process(struct sbmac_softc *sc, sbmacdma_t *d); 251 static void sbdma_tx_process(struct sbmac_softc *sc, sbmacdma_t *d); 252 static void sbmac_initctx(struct sbmac_softc *s); 253 static void sbmac_channel_start(struct sbmac_softc *s); 254 static void sbmac_channel_stop(struct sbmac_softc *s); 255 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *, 256 sbmac_state_t); 257 static void sbmac_promiscuous_mode(struct sbmac_softc *sc, int onoff); 258 static void sbmac_init_and_start(struct sbmac_softc *sc); 259 static uint64_t sbmac_addr2reg(u_char *ptr); 260 static void sbmac_intr(void *xsc, uint32_t status, uint32_t pc); 261 static void sbmac_start(struct ifnet *ifp); 262 static void sbmac_setmulti(struct sbmac_softc *sc); 263 static int sbmac_ether_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 264 static int sbmac_ioctl(struct ifnet *ifp, u_long command, caddr_t data); 265 static int sbmac_mediachange(struct ifnet *ifp); 266 static void sbmac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr); 267 static void sbmac_watchdog(struct ifnet *ifp); 268 static int sbmac_match(struct device *parent, struct cfdata *match, void *aux); 269 static void sbmac_attach(struct device *parent, struct device *self, void *aux); 270 static int sbmac_set_speed(struct sbmac_softc *s, sbmac_speed_t speed); 271 static int sbmac_set_duplex(struct sbmac_softc *s, sbmac_duplex_t duplex, 272 sbmac_fc_t fc); 273 static void sbmac_tick(void *arg); 274 275 276 /* Globals */ 277 278 CFATTACH_DECL(sbmac, sizeof(struct sbmac_softc), 279 sbmac_match, sbmac_attach, NULL, NULL); 280 281 static uint32_t sbmac_mii_bitbang_read(struct device *self); 282 static void sbmac_mii_bitbang_write(struct device *self, uint32_t val); 283 284 static const struct mii_bitbang_ops sbmac_mii_bitbang_ops = { 285 sbmac_mii_bitbang_read, 286 sbmac_mii_bitbang_write, 287 { 288 (uint32_t)M_MAC_MDIO_OUT, /* MII_BIT_MDO */ 289 (uint32_t)M_MAC_MDIO_IN, /* MII_BIT_MDI */ 290 (uint32_t)M_MAC_MDC, /* MII_BIT_MDC */ 291 0, /* MII_BIT_DIR_HOST_PHY */ 292 (uint32_t)M_MAC_MDIO_DIR /* MII_BIT_DIR_PHY_HOST */ 293 } 294 }; 295 296 static uint32_t 297 sbmac_mii_bitbang_read(struct device *self) 298 { 299 struct sbmac_softc *sc = (void *) self; 300 sbmac_port_t reg; 301 302 reg = PKSEG1(sc->sbm_base + R_MAC_MDIO); 303 return (uint32_t) SBMAC_READCSR(reg); 304 } 305 306 static void 307 sbmac_mii_bitbang_write(struct device *self, uint32_t val) 308 { 309 struct sbmac_softc *sc = (void *) self; 310 sbmac_port_t reg; 311 312 reg = PKSEG1(sc->sbm_base + R_MAC_MDIO); 313 314 SBMAC_WRITECSR(reg, (val & 315 (M_MAC_MDC|M_MAC_MDIO_DIR|M_MAC_MDIO_OUT|M_MAC_MDIO_IN))); 316 } 317 318 /* 319 * Read an PHY register through the MII. 320 */ 321 static int 322 sbmac_mii_readreg(struct device *self, int phy, int reg) 323 { 324 325 return (mii_bitbang_readreg(self, &sbmac_mii_bitbang_ops, phy, reg)); 326 } 327 328 /* 329 * Write to a PHY register through the MII. 330 */ 331 static void 332 sbmac_mii_writereg(struct device *self, int phy, int reg, int val) 333 { 334 335 mii_bitbang_writereg(self, &sbmac_mii_bitbang_ops, phy, reg, val); 336 } 337 338 static void 339 sbmac_mii_statchg(struct device *self) 340 { 341 struct sbmac_softc *sc = (struct sbmac_softc *)self; 342 sbmac_state_t oldstate; 343 344 /* Stop the MAC in preparation for changing all of the parameters. */ 345 oldstate = sbmac_set_channel_state(sc, sbmac_state_off); 346 347 switch (sc->sc_ethercom.ec_if.if_baudrate) { 348 default: /* if autonegotiation fails, assume 10Mbit */ 349 case IF_Mbps(10): 350 sbmac_set_speed(sc, sbmac_speed_10); 351 break; 352 353 case IF_Mbps(100): 354 sbmac_set_speed(sc, sbmac_speed_100); 355 break; 356 357 case IF_Mbps(1000): 358 sbmac_set_speed(sc, sbmac_speed_1000); 359 break; 360 } 361 362 if (sc->sc_mii.mii_media_active & IFM_FDX) { 363 /* Configure for full-duplex */ 364 /* XXX: is flow control right for 10, 100? */ 365 sbmac_set_duplex(sc, sbmac_duplex_full, sbmac_fc_frame); 366 } else { 367 /* Configure for half-duplex */ 368 /* XXX: is flow control right? */ 369 sbmac_set_duplex(sc, sbmac_duplex_half, sbmac_fc_disabled); 370 } 371 372 /* And put it back into its former state. */ 373 sbmac_set_channel_state(sc, oldstate); 374 } 375 376 /* 377 * SBDMA_INITCTX(d, s, chan, txrx, maxdescr) 378 * 379 * Initialize a DMA channel context. Since there are potentially 380 * eight DMA channels per MAC, it's nice to do this in a standard 381 * way. 382 * 383 * Input parameters: 384 * d - sbmacdma_t structure (DMA channel context) 385 * s - sbmac_softc structure (pointer to a MAC) 386 * chan - channel number (0..1 right now) 387 * txrx - Identifies DMA_TX or DMA_RX for channel direction 388 * maxdescr - number of descriptors 389 * 390 * Return value: 391 * nothing 392 */ 393 394 static void 395 sbdma_initctx(sbmacdma_t *d, struct sbmac_softc *s, int chan, int txrx, 396 int maxdescr) 397 { 398 /* 399 * Save away interesting stuff in the structure 400 */ 401 402 d->sbdma_eth = s; 403 d->sbdma_channel = chan; 404 d->sbdma_txdir = txrx; 405 406 /* 407 * initialize register pointers 408 */ 409 410 d->sbdma_config0 = PKSEG1(s->sbm_base + 411 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_CONFIG0)); 412 d->sbdma_config1 = PKSEG1(s->sbm_base + 413 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_CONFIG1)); 414 d->sbdma_dscrbase = PKSEG1(s->sbm_base + 415 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_DSCR_BASE)); 416 d->sbdma_dscrcnt = PKSEG1(s->sbm_base + 417 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_DSCR_CNT)); 418 d->sbdma_curdscr = PKSEG1(s->sbm_base + 419 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_CUR_DSCRADDR)); 420 421 /* 422 * Allocate memory for the ring 423 */ 424 425 d->sbdma_maxdescr = maxdescr; 426 427 d->sbdma_dscrtable = (sbdmadscr_t *) 428 KMALLOC(d->sbdma_maxdescr*sizeof(sbdmadscr_t)); 429 430 bzero(d->sbdma_dscrtable, d->sbdma_maxdescr*sizeof(sbdmadscr_t)); 431 432 d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr; 433 434 d->sbdma_dscrtable_phys = KVTOPHYS(d->sbdma_dscrtable); 435 436 /* 437 * And context table 438 */ 439 440 d->sbdma_ctxtable = (struct mbuf **) 441 KMALLOC(d->sbdma_maxdescr*sizeof(struct mbuf *)); 442 443 bzero(d->sbdma_ctxtable, d->sbdma_maxdescr*sizeof(struct mbuf *)); 444 } 445 446 /* 447 * SBDMA_CHANNEL_START(d) 448 * 449 * Initialize the hardware registers for a DMA channel. 450 * 451 * Input parameters: 452 * d - DMA channel to init (context must be previously init'd 453 * 454 * Return value: 455 * nothing 456 */ 457 458 static void 459 sbdma_channel_start(sbmacdma_t *d) 460 { 461 /* 462 * Turn on the DMA channel 463 */ 464 465 SBMAC_WRITECSR(d->sbdma_config1, 0); 466 467 SBMAC_WRITECSR(d->sbdma_dscrbase, d->sbdma_dscrtable_phys); 468 469 SBMAC_WRITECSR(d->sbdma_config0, V_DMA_RINGSZ(d->sbdma_maxdescr) | 0); 470 471 /* 472 * Initialize ring pointers 473 */ 474 475 d->sbdma_addptr = d->sbdma_dscrtable; 476 d->sbdma_remptr = d->sbdma_dscrtable; 477 } 478 479 /* 480 * SBDMA_ADD_RCVBUFFER(d, m) 481 * 482 * Add a buffer to the specified DMA channel. For receive channels, 483 * this queues a buffer for inbound packets. 484 * 485 * Input parameters: 486 * d - DMA channel descriptor 487 * m - mbuf to add, or NULL if we should allocate one. 488 * 489 * Return value: 490 * 0 if buffer could not be added (ring is full) 491 * 1 if buffer added successfully 492 */ 493 494 static int 495 sbdma_add_rcvbuffer(sbmacdma_t *d, struct mbuf *m) 496 { 497 sbdmadscr_t *dsc; 498 sbdmadscr_t *nextdsc; 499 struct mbuf *m_new = NULL; 500 501 /* get pointer to our current place in the ring */ 502 503 dsc = d->sbdma_addptr; 504 nextdsc = SBDMA_NEXTBUF(d, sbdma_addptr); 505 506 /* 507 * figure out if the ring is full - if the next descriptor 508 * is the same as the one that we're going to remove from 509 * the ring, the ring is full 510 */ 511 512 if (nextdsc == d->sbdma_remptr) 513 return ENOSPC; 514 515 /* 516 * Allocate an mbuf if we don't already have one. 517 * If we do have an mbuf, reset it so that it's empty. 518 */ 519 520 if (m == NULL) { 521 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 522 if (m_new == NULL) { 523 printf("%s: mbuf allocation failed\n", 524 d->sbdma_eth->sc_dev.dv_xname); 525 return ENOBUFS; 526 } 527 528 MCLGET(m_new, M_DONTWAIT); 529 if (!(m_new->m_flags & M_EXT)) { 530 printf("%s: mbuf cluster allocation failed\n", 531 d->sbdma_eth->sc_dev.dv_xname); 532 m_freem(m_new); 533 return ENOBUFS; 534 } 535 536 m_new->m_len = m_new->m_pkthdr.len= MCLBYTES; 537 m_adj(m_new, ETHER_ALIGN); 538 } else { 539 m_new = m; 540 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 541 m_new->m_data = m_new->m_ext.ext_buf; 542 m_adj(m_new, ETHER_ALIGN); 543 } 544 545 /* 546 * fill in the descriptor 547 */ 548 549 dsc->dscr_a = KVTOPHYS(mtod(m_new, caddr_t)) | 550 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(ETHER_ALIGN + m_new->m_len)) | 551 M_DMA_DSCRA_INTERRUPT; 552 553 /* receiving: no options */ 554 dsc->dscr_b = 0; 555 556 /* 557 * fill in the context 558 */ 559 560 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = m_new; 561 562 /* 563 * point at next packet 564 */ 565 566 d->sbdma_addptr = nextdsc; 567 568 /* 569 * Give the buffer to the DMA engine. 570 */ 571 572 SBMAC_WRITECSR(d->sbdma_dscrcnt, 1); 573 574 return 0; /* we did it */ 575 } 576 577 /* 578 * SBDMA_ADD_TXBUFFER(d, m) 579 * 580 * Add a transmit buffer to the specified DMA channel, causing a 581 * transmit to start. 582 * 583 * Input parameters: 584 * d - DMA channel descriptor 585 * m - mbuf to add 586 * 587 * Return value: 588 * 0 transmit queued successfully 589 * otherwise error code 590 */ 591 592 static int 593 sbdma_add_txbuffer(sbmacdma_t *d, struct mbuf *m) 594 { 595 sbdmadscr_t *dsc; 596 sbdmadscr_t *nextdsc; 597 sbdmadscr_t *prevdsc; 598 sbdmadscr_t *origdesc; 599 int length; 600 int num_mbufs = 0; 601 struct sbmac_softc *sc = d->sbdma_eth; 602 603 /* get pointer to our current place in the ring */ 604 605 dsc = d->sbdma_addptr; 606 nextdsc = SBDMA_NEXTBUF(d, sbdma_addptr); 607 608 /* 609 * figure out if the ring is full - if the next descriptor 610 * is the same as the one that we're going to remove from 611 * the ring, the ring is full 612 */ 613 614 if (nextdsc == d->sbdma_remptr) { 615 SBMAC_EVCNT_INCR(sc->sbm_ev_txstall); 616 return ENOSPC; 617 } 618 619 /* 620 * PASS3 parts do not have buffer alignment restriction. 621 * No need to copy/coalesce to new mbuf. Also has different 622 * descriptor format 623 */ 624 if (sc->sbm_pass3_dma) { 625 struct mbuf *m_temp = NULL; 626 627 /* 628 * Loop thru this mbuf record. 629 * The head mbuf will have SOP set. 630 */ 631 dsc->dscr_a = KVTOPHYS(mtod(m,caddr_t)) | 632 M_DMA_ETHTX_SOP; 633 634 /* 635 * transmitting: set outbound options,buffer A size(+ low 5 636 * bits of start addr),and packet length. 637 */ 638 dsc->dscr_b = 639 V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) | 640 V_DMA_DSCRB_A_SIZE((m->m_len + 641 (mtod(m,unsigned int) & 0x0000001F))) | 642 V_DMA_DSCRB_PKT_SIZE_MSB((m->m_pkthdr.len & 0xc000) >> 14) | 643 V_DMA_DSCRB_PKT_SIZE(m->m_pkthdr.len & 0x3fff); 644 645 d->sbdma_addptr = nextdsc; 646 origdesc = prevdsc = dsc; 647 dsc = d->sbdma_addptr; 648 num_mbufs++; 649 650 /* Start with first non-head mbuf */ 651 for(m_temp = m->m_next; m_temp != 0; m_temp = m_temp->m_next) { 652 int len, next_len; 653 uint64_t addr; 654 655 if (m_temp->m_len == 0) 656 continue; /* Skip 0-length mbufs */ 657 658 len = m_temp->m_len; 659 addr = KVTOPHYS(mtod(m_temp, caddr_t)); 660 661 /* 662 * Check to see if the mbuf spans a page boundary. If 663 * it does, and the physical pages behind the virtual 664 * pages are not contiguous, split it so that each 665 * virtual page uses it's own Tx descriptor. 666 */ 667 if (trunc_page(addr) != trunc_page(addr + len - 1)) { 668 next_len = (addr + len) - trunc_page(addr + len); 669 670 len -= next_len; 671 672 if (addr + len == 673 KVTOPHYS(mtod(m_temp, caddr_t) + len)) { 674 SBMAC_EVCNT_INCR(sc->sbm_ev_txkeep); 675 len += next_len; 676 next_len = 0; 677 } else { 678 SBMAC_EVCNT_INCR(sc->sbm_ev_txsplit); 679 } 680 } else { 681 next_len = 0; 682 } 683 684 again: 685 /* 686 * fill in the descriptor 687 */ 688 dsc->dscr_a = addr; 689 690 /* 691 * transmitting: set outbound options,buffer A 692 * size(+ low 5 bits of start addr) 693 */ 694 dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_NOTSOP) | 695 V_DMA_DSCRB_A_SIZE((len + (addr & 0x0000001F))); 696 697 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = NULL; 698 699 /* 700 * point at next descriptor 701 */ 702 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr); 703 if (nextdsc == d->sbdma_remptr) { 704 d->sbdma_addptr = origdesc; 705 SBMAC_EVCNT_INCR(sc->sbm_ev_txstall); 706 return ENOSPC; 707 } 708 d->sbdma_addptr = nextdsc; 709 710 prevdsc = dsc; 711 dsc = d->sbdma_addptr; 712 num_mbufs++; 713 714 if (next_len != 0) { 715 addr = KVTOPHYS(mtod(m_temp, caddr_t) + len); 716 len = next_len; 717 718 next_len = 0; 719 goto again; 720 } 721 722 } 723 /* Set head mbuf to last context index */ 724 d->sbdma_ctxtable[prevdsc-d->sbdma_dscrtable] = m; 725 726 /* Interrupt on last dscr of packet. */ 727 prevdsc->dscr_a |= M_DMA_DSCRA_INTERRUPT; 728 } else { 729 struct mbuf *m_new = NULL; 730 /* 731 * [BEGIN XXX] 732 * XXX Copy/coalesce the mbufs into a single mbuf cluster (we 733 * assume it will fit). This is a temporary hack to get us 734 * going. 735 */ 736 737 MGETHDR(m_new,M_DONTWAIT,MT_DATA); 738 if (m_new == NULL) { 739 printf("%s: mbuf allocation failed\n", 740 d->sbdma_eth->sc_dev.dv_xname); 741 SBMAC_EVCNT_INCR(sc->sbm_ev_txdrop); 742 return ENOBUFS; 743 } 744 745 MCLGET(m_new,M_DONTWAIT); 746 if (!(m_new->m_flags & M_EXT)) { 747 printf("%s: mbuf cluster allocation failed\n", 748 d->sbdma_eth->sc_dev.dv_xname); 749 m_freem(m_new); 750 SBMAC_EVCNT_INCR(sc->sbm_ev_txdrop); 751 return ENOBUFS; 752 } 753 754 m_new->m_len = m_new->m_pkthdr.len= MCLBYTES; 755 /*m_adj(m_new,ETHER_ALIGN);*/ 756 757 /* 758 * XXX Don't forget to include the offset portion in the 759 * XXX cache block calculation when this code is rewritten! 760 */ 761 762 /* 763 * Copy data 764 */ 765 766 m_copydata(m,0,m->m_pkthdr.len,mtod(m_new,caddr_t)); 767 m_new->m_len = m_new->m_pkthdr.len = m->m_pkthdr.len; 768 769 /* Free old mbuf 'm', actual mbuf is now 'm_new' */ 770 771 // XXX: CALLERS WILL FREE, they might have to bpf_mtap() if this 772 // XXX: function succeeds. 773 // m_freem(m); 774 length = m_new->m_len; 775 776 /* [END XXX] */ 777 /* 778 * fill in the descriptor 779 */ 780 781 dsc->dscr_a = KVTOPHYS(mtod(m_new,caddr_t)) | 782 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(m_new->m_len)) | 783 M_DMA_DSCRA_INTERRUPT | 784 M_DMA_ETHTX_SOP; 785 786 /* transmitting: set outbound options and length */ 787 dsc->dscr_b = 788 V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) | 789 V_DMA_DSCRB_PKT_SIZE(length); 790 791 num_mbufs++; 792 793 /* 794 * fill in the context 795 */ 796 797 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = m_new; 798 799 /* 800 * point at next packet 801 */ 802 d->sbdma_addptr = nextdsc; 803 } 804 805 /* 806 * Give the buffer to the DMA engine. 807 */ 808 809 SBMAC_WRITECSR(d->sbdma_dscrcnt, num_mbufs); 810 811 return 0; /* we did it */ 812 } 813 814 /* 815 * SBDMA_EMPTYRING(d) 816 * 817 * Free all allocated mbufs on the specified DMA channel; 818 * 819 * Input parameters: 820 * d - DMA channel 821 * 822 * Return value: 823 * nothing 824 */ 825 826 static void 827 sbdma_emptyring(sbmacdma_t *d) 828 { 829 int idx; 830 struct mbuf *m; 831 832 for (idx = 0; idx < d->sbdma_maxdescr; idx++) { 833 m = d->sbdma_ctxtable[idx]; 834 if (m) { 835 m_freem(m); 836 d->sbdma_ctxtable[idx] = NULL; 837 } 838 } 839 } 840 841 /* 842 * SBDMA_FILLRING(d) 843 * 844 * Fill the specified DMA channel (must be receive channel) 845 * with mbufs 846 * 847 * Input parameters: 848 * d - DMA channel 849 * 850 * Return value: 851 * nothing 852 */ 853 854 static void 855 sbdma_fillring(sbmacdma_t *d) 856 { 857 int idx; 858 859 for (idx = 0; idx < SBMAC_MAX_RXDESCR-1; idx++) 860 if (sbdma_add_rcvbuffer(d, NULL) != 0) 861 break; 862 } 863 864 /* 865 * SBDMA_RX_PROCESS(sc, d) 866 * 867 * Process "completed" receive buffers on the specified DMA channel. 868 * Note that this isn't really ideal for priority channels, since 869 * it processes all of the packets on a given channel before 870 * returning. 871 * 872 * Input parameters: 873 * sc - softc structure 874 * d - DMA channel context 875 * 876 * Return value: 877 * nothing 878 */ 879 880 static void 881 sbdma_rx_process(struct sbmac_softc *sc, sbmacdma_t *d) 882 { 883 int curidx; 884 int hwidx; 885 sbdmadscr_t *dsc; 886 struct mbuf *m; 887 int len; 888 889 struct ifnet *ifp = &(sc->sc_ethercom.ec_if); 890 891 for (;;) { 892 /* 893 * figure out where we are (as an index) and where 894 * the hardware is (also as an index) 895 * 896 * This could be done faster if (for example) the 897 * descriptor table was page-aligned and contiguous in 898 * both virtual and physical memory -- you could then 899 * just compare the low-order bits of the virtual address 900 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) 901 */ 902 903 curidx = d->sbdma_remptr - d->sbdma_dscrtable; 904 hwidx = (int) 905 (((SBMAC_READCSR(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - 906 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t)); 907 908 /* 909 * If they're the same, that means we've processed all 910 * of the descriptors up to (but not including) the one that 911 * the hardware is working on right now. 912 */ 913 914 if (curidx == hwidx) 915 break; 916 917 /* 918 * Otherwise, get the packet's mbuf ptr back 919 */ 920 921 dsc = &(d->sbdma_dscrtable[curidx]); 922 m = d->sbdma_ctxtable[curidx]; 923 d->sbdma_ctxtable[curidx] = NULL; 924 925 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4; 926 927 /* 928 * Check packet status. If good, process it. 929 * If not, silently drop it and put it back on the 930 * receive ring. 931 */ 932 933 if (! (dsc->dscr_a & M_DMA_ETHRX_BAD)) { 934 935 /* 936 * Set length into the packet 937 * XXX do we remove the CRC here? 938 */ 939 m->m_pkthdr.len = m->m_len = len; 940 941 ifp->if_ipackets++; 942 m->m_pkthdr.rcvif = ifp; 943 944 945 /* 946 * Add a new buffer to replace the old one. 947 */ 948 sbdma_add_rcvbuffer(d, NULL); 949 950 #if (NBPFILTER > 0) 951 /* 952 * Handle BPF listeners. Let the BPF user see the 953 * packet, but don't pass it up to the ether_input() 954 * layer unless it's a broadcast packet, multicast 955 * packet, matches our ethernet address or the 956 * interface is in promiscuous mode. 957 */ 958 959 if (ifp->if_bpf) 960 bpf_mtap(ifp->if_bpf, m); 961 #endif 962 /* 963 * Pass the buffer to the kernel 964 */ 965 (*ifp->if_input)(ifp, m); 966 } else { 967 /* 968 * Packet was mangled somehow. Just drop it and 969 * put it back on the receive ring. 970 */ 971 sbdma_add_rcvbuffer(d, m); 972 } 973 974 /* 975 * .. and advance to the next buffer. 976 */ 977 978 d->sbdma_remptr = SBDMA_NEXTBUF(d, sbdma_remptr); 979 } 980 } 981 982 /* 983 * SBDMA_TX_PROCESS(sc, d) 984 * 985 * Process "completed" transmit buffers on the specified DMA channel. 986 * This is normally called within the interrupt service routine. 987 * Note that this isn't really ideal for priority channels, since 988 * it processes all of the packets on a given channel before 989 * returning. 990 * 991 * Input parameters: 992 * sc - softc structure 993 * d - DMA channel context 994 * 995 * Return value: 996 * nothing 997 */ 998 999 static void 1000 sbdma_tx_process(struct sbmac_softc *sc, sbmacdma_t *d) 1001 { 1002 int curidx; 1003 int hwidx; 1004 struct mbuf *m; 1005 1006 struct ifnet *ifp = &(sc->sc_ethercom.ec_if); 1007 1008 for (;;) { 1009 /* 1010 * figure out where we are (as an index) and where 1011 * the hardware is (also as an index) 1012 * 1013 * This could be done faster if (for example) the 1014 * descriptor table was page-aligned and contiguous in 1015 * both virtual and physical memory -- you could then 1016 * just compare the low-order bits of the virtual address 1017 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) 1018 */ 1019 1020 curidx = d->sbdma_remptr - d->sbdma_dscrtable; 1021 hwidx = (int) 1022 (((SBMAC_READCSR(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - 1023 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t)); 1024 1025 /* 1026 * If they're the same, that means we've processed all 1027 * of the descriptors up to (but not including) the one that 1028 * the hardware is working on right now. 1029 */ 1030 1031 if (curidx == hwidx) 1032 break; 1033 1034 /* 1035 * Otherwise, get the packet's mbuf ptr back 1036 */ 1037 1038 m = d->sbdma_ctxtable[curidx]; 1039 d->sbdma_ctxtable[curidx] = NULL; 1040 1041 /* 1042 * for transmits, we just free buffers. 1043 */ 1044 1045 m_freem(m); 1046 1047 /* 1048 * .. and advance to the next buffer. 1049 */ 1050 1051 d->sbdma_remptr = SBDMA_NEXTBUF(d, sbdma_remptr); 1052 } 1053 1054 /* 1055 * Decide what to set the IFF_OACTIVE bit in the interface to. 1056 * It's supposed to reflect if the interface is actively 1057 * transmitting, but that's really hard to do quickly. 1058 */ 1059 1060 ifp->if_flags &= ~IFF_OACTIVE; 1061 } 1062 1063 /* 1064 * SBMAC_INITCTX(s) 1065 * 1066 * Initialize an Ethernet context structure - this is called 1067 * once per MAC on the 1250. Memory is allocated here, so don't 1068 * call it again from inside the ioctl routines that bring the 1069 * interface up/down 1070 * 1071 * Input parameters: 1072 * s - sbmac context structure 1073 * 1074 * Return value: 1075 * 0 1076 */ 1077 1078 static void 1079 sbmac_initctx(struct sbmac_softc *s) 1080 { 1081 uint64_t sysrev; 1082 1083 /* 1084 * figure out the addresses of some ports 1085 */ 1086 1087 s->sbm_macenable = PKSEG1(s->sbm_base + R_MAC_ENABLE); 1088 s->sbm_maccfg = PKSEG1(s->sbm_base + R_MAC_CFG); 1089 s->sbm_fifocfg = PKSEG1(s->sbm_base + R_MAC_THRSH_CFG); 1090 s->sbm_framecfg = PKSEG1(s->sbm_base + R_MAC_FRAMECFG); 1091 s->sbm_rxfilter = PKSEG1(s->sbm_base + R_MAC_ADFILTER_CFG); 1092 s->sbm_isr = PKSEG1(s->sbm_base + R_MAC_STATUS); 1093 s->sbm_imr = PKSEG1(s->sbm_base + R_MAC_INT_MASK); 1094 1095 /* 1096 * Initialize the DMA channels. Right now, only one per MAC is used 1097 * Note: Only do this _once_, as it allocates memory from the kernel! 1098 */ 1099 1100 sbdma_initctx(&(s->sbm_txdma), s, 0, DMA_TX, SBMAC_MAX_TXDESCR); 1101 sbdma_initctx(&(s->sbm_rxdma), s, 0, DMA_RX, SBMAC_MAX_RXDESCR); 1102 1103 /* 1104 * initial state is OFF 1105 */ 1106 1107 s->sbm_state = sbmac_state_off; 1108 1109 /* 1110 * Initial speed is (XXX TEMP) 10MBit/s HDX no FC 1111 */ 1112 1113 s->sbm_speed = sbmac_speed_10; 1114 s->sbm_duplex = sbmac_duplex_half; 1115 s->sbm_fc = sbmac_fc_disabled; 1116 1117 /* 1118 * Determine SOC type. 112x has Pass3 SOC features. 1119 */ 1120 sysrev = SBMAC_READCSR( PKSEG1(A_SCD_SYSTEM_REVISION) ); 1121 s->sbm_pass3_dma = (SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1120 || 1122 SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1125 || 1123 SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1125H || 1124 (SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250 && 1125 G_SYS_REVISION(sysrev) >= K_SYS_REVISION_BCM1250_PASS3)); 1126 #ifdef SBMAC_EVENT_COUNTERS 1127 evcnt_attach_dynamic(&s->sbm_ev_rxintr, EVCNT_TYPE_INTR, 1128 NULL, s->sc_dev.dv_xname, "rxintr"); 1129 evcnt_attach_dynamic(&s->sbm_ev_txintr, EVCNT_TYPE_INTR, 1130 NULL, s->sc_dev.dv_xname, "txintr"); 1131 evcnt_attach_dynamic(&s->sbm_ev_txdrop, EVCNT_TYPE_MISC, 1132 NULL, s->sc_dev.dv_xname, "txdrop"); 1133 evcnt_attach_dynamic(&s->sbm_ev_txstall, EVCNT_TYPE_MISC, 1134 NULL, s->sc_dev.dv_xname, "txstall"); 1135 if (s->sbm_pass3_dma) { 1136 evcnt_attach_dynamic(&s->sbm_ev_txsplit, EVCNT_TYPE_MISC, 1137 NULL, s->sc_dev.dv_xname, "pass3tx-split"); 1138 evcnt_attach_dynamic(&s->sbm_ev_txkeep, EVCNT_TYPE_MISC, 1139 NULL, s->sc_dev.dv_xname, "pass3tx-keep"); 1140 } 1141 #endif 1142 } 1143 1144 /* 1145 * SBMAC_CHANNEL_START(s) 1146 * 1147 * Start packet processing on this MAC. 1148 * 1149 * Input parameters: 1150 * s - sbmac structure 1151 * 1152 * Return value: 1153 * nothing 1154 */ 1155 1156 static void 1157 sbmac_channel_start(struct sbmac_softc *s) 1158 { 1159 uint64_t reg; 1160 sbmac_port_t port; 1161 uint64_t cfg, fifo, framecfg; 1162 int idx; 1163 uint64_t dma_cfg0, fifo_cfg; 1164 sbmacdma_t *txdma; 1165 1166 /* 1167 * Don't do this if running 1168 */ 1169 1170 if (s->sbm_state == sbmac_state_on) 1171 return; 1172 1173 /* 1174 * Bring the controller out of reset, but leave it off. 1175 */ 1176 1177 SBMAC_WRITECSR(s->sbm_macenable, 0); 1178 1179 /* 1180 * Ignore all received packets 1181 */ 1182 1183 SBMAC_WRITECSR(s->sbm_rxfilter, 0); 1184 1185 /* 1186 * Calculate values for various control registers. 1187 */ 1188 1189 cfg = M_MAC_RETRY_EN | 1190 M_MAC_TX_HOLD_SOP_EN | 1191 V_MAC_TX_PAUSE_CNT_16K | 1192 M_MAC_AP_STAT_EN | 1193 M_MAC_SS_EN | 1194 0; 1195 1196 fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */ 1197 V_MAC_TX_RD_THRSH(4) | 1198 V_MAC_TX_RL_THRSH(4) | 1199 V_MAC_RX_PL_THRSH(4) | 1200 V_MAC_RX_RD_THRSH(4) | /* Must be '4' */ 1201 V_MAC_RX_PL_THRSH(4) | 1202 V_MAC_RX_RL_THRSH(8) | 1203 0; 1204 1205 framecfg = V_MAC_MIN_FRAMESZ_DEFAULT | 1206 V_MAC_MAX_FRAMESZ_DEFAULT | 1207 V_MAC_BACKOFF_SEL(1); 1208 1209 /* 1210 * Clear out the hash address map 1211 */ 1212 1213 port = PKSEG1(s->sbm_base + R_MAC_HASH_BASE); 1214 for (idx = 0; idx < MAC_HASH_COUNT; idx++) { 1215 SBMAC_WRITECSR(port, 0); 1216 port += sizeof(uint64_t); 1217 } 1218 1219 /* 1220 * Clear out the exact-match table 1221 */ 1222 1223 port = PKSEG1(s->sbm_base + R_MAC_ADDR_BASE); 1224 for (idx = 0; idx < MAC_ADDR_COUNT; idx++) { 1225 SBMAC_WRITECSR(port, 0); 1226 port += sizeof(uint64_t); 1227 } 1228 1229 /* 1230 * Clear out the DMA Channel mapping table registers 1231 */ 1232 1233 port = PKSEG1(s->sbm_base + R_MAC_CHUP0_BASE); 1234 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { 1235 SBMAC_WRITECSR(port, 0); 1236 port += sizeof(uint64_t); 1237 } 1238 1239 port = PKSEG1(s->sbm_base + R_MAC_CHLO0_BASE); 1240 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { 1241 SBMAC_WRITECSR(port, 0); 1242 port += sizeof(uint64_t); 1243 } 1244 1245 /* 1246 * Program the hardware address. It goes into the hardware-address 1247 * register as well as the first filter register. 1248 */ 1249 1250 reg = sbmac_addr2reg(s->sbm_hwaddr); 1251 1252 port = PKSEG1(s->sbm_base + R_MAC_ADDR_BASE); 1253 SBMAC_WRITECSR(port, reg); 1254 port = PKSEG1(s->sbm_base + R_MAC_ETHERNET_ADDR); 1255 SBMAC_WRITECSR(port, 0); // pass1 workaround 1256 1257 /* 1258 * Set the receive filter for no packets, and write values 1259 * to the various config registers 1260 */ 1261 1262 SBMAC_WRITECSR(s->sbm_rxfilter, 0); 1263 SBMAC_WRITECSR(s->sbm_imr, 0); 1264 SBMAC_WRITECSR(s->sbm_framecfg, framecfg); 1265 SBMAC_WRITECSR(s->sbm_fifocfg, fifo); 1266 SBMAC_WRITECSR(s->sbm_maccfg, cfg); 1267 1268 /* 1269 * Initialize DMA channels (rings should be ok now) 1270 */ 1271 1272 sbdma_channel_start(&(s->sbm_rxdma)); 1273 sbdma_channel_start(&(s->sbm_txdma)); 1274 1275 /* 1276 * Configure the speed, duplex, and flow control 1277 */ 1278 1279 sbmac_set_speed(s, s->sbm_speed); 1280 sbmac_set_duplex(s, s->sbm_duplex, s->sbm_fc); 1281 1282 /* 1283 * Fill the receive ring 1284 */ 1285 1286 sbdma_fillring(&(s->sbm_rxdma)); 1287 1288 /* 1289 * Turn on the rest of the bits in the enable register 1290 */ 1291 1292 SBMAC_WRITECSR(s->sbm_macenable, M_MAC_RXDMA_EN0 | M_MAC_TXDMA_EN0 | 1293 M_MAC_RX_ENABLE | M_MAC_TX_ENABLE); 1294 1295 1296 /* 1297 * Accept any kind of interrupt on TX and RX DMA channel 0 1298 */ 1299 SBMAC_WRITECSR(s->sbm_imr, 1300 (M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | 1301 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)); 1302 1303 /* 1304 * Enable receiving unicasts and broadcasts 1305 */ 1306 1307 SBMAC_WRITECSR(s->sbm_rxfilter, M_MAC_UCAST_EN | M_MAC_BCAST_EN); 1308 1309 /* 1310 * On chips which support unaligned DMA features, set the descriptor 1311 * ring for transmit channels to use the unaligned buffer format. 1312 */ 1313 txdma = &(s->sbm_txdma); 1314 1315 if (s->sbm_pass3_dma) { 1316 dma_cfg0 = SBMAC_READCSR(txdma->sbdma_config0); 1317 dma_cfg0 |= V_DMA_DESC_TYPE(K_DMA_DESC_TYPE_RING_UAL_RMW) | 1318 M_DMA_TBX_EN | M_DMA_TDX_EN; 1319 SBMAC_WRITECSR(txdma->sbdma_config0,dma_cfg0); 1320 1321 fifo_cfg = SBMAC_READCSR(s->sbm_fifocfg); 1322 fifo_cfg |= V_MAC_TX_WR_THRSH(8) | 1323 V_MAC_TX_RD_THRSH(8) | V_MAC_TX_RL_THRSH(8); 1324 SBMAC_WRITECSR(s->sbm_fifocfg,fifo_cfg); 1325 } 1326 1327 /* 1328 * we're running now. 1329 */ 1330 1331 s->sbm_state = sbmac_state_on; 1332 s->sc_ethercom.ec_if.if_flags |= IFF_RUNNING; 1333 1334 /* 1335 * Program multicast addresses 1336 */ 1337 1338 sbmac_setmulti(s); 1339 1340 /* 1341 * If channel was in promiscuous mode before, turn that on 1342 */ 1343 1344 if (s->sc_ethercom.ec_if.if_flags & IFF_PROMISC) 1345 sbmac_promiscuous_mode(s, 1); 1346 1347 /* 1348 * Turn on the once-per-second timer 1349 */ 1350 1351 callout_reset(&(s->sc_tick_ch), hz, sbmac_tick, s); 1352 } 1353 1354 /* 1355 * SBMAC_CHANNEL_STOP(s) 1356 * 1357 * Stop packet processing on this MAC. 1358 * 1359 * Input parameters: 1360 * s - sbmac structure 1361 * 1362 * Return value: 1363 * nothing 1364 */ 1365 1366 static void 1367 sbmac_channel_stop(struct sbmac_softc *s) 1368 { 1369 uint64_t ctl; 1370 1371 /* don't do this if already stopped */ 1372 1373 if (s->sbm_state == sbmac_state_off) 1374 return; 1375 1376 /* don't accept any packets, disable all interrupts */ 1377 1378 SBMAC_WRITECSR(s->sbm_rxfilter, 0); 1379 SBMAC_WRITECSR(s->sbm_imr, 0); 1380 1381 /* Turn off ticker */ 1382 1383 callout_stop(&(s->sc_tick_ch)); 1384 1385 /* turn off receiver and transmitter */ 1386 1387 ctl = SBMAC_READCSR(s->sbm_macenable); 1388 ctl &= ~(M_MAC_RXDMA_EN0 | M_MAC_TXDMA_EN0); 1389 SBMAC_WRITECSR(s->sbm_macenable, ctl); 1390 1391 /* We're stopped now. */ 1392 1393 s->sbm_state = sbmac_state_off; 1394 s->sc_ethercom.ec_if.if_flags &= ~IFF_RUNNING; 1395 1396 /* Empty the receive and transmit rings */ 1397 1398 sbdma_emptyring(&(s->sbm_rxdma)); 1399 sbdma_emptyring(&(s->sbm_txdma)); 1400 } 1401 1402 /* 1403 * SBMAC_SET_CHANNEL_STATE(state) 1404 * 1405 * Set the channel's state ON or OFF 1406 * 1407 * Input parameters: 1408 * state - new state 1409 * 1410 * Return value: 1411 * old state 1412 */ 1413 1414 static sbmac_state_t 1415 sbmac_set_channel_state(struct sbmac_softc *sc, sbmac_state_t state) 1416 { 1417 sbmac_state_t oldstate = sc->sbm_state; 1418 1419 /* 1420 * If same as previous state, return 1421 */ 1422 1423 if (state == oldstate) 1424 return oldstate; 1425 1426 /* 1427 * If new state is ON, turn channel on 1428 */ 1429 1430 if (state == sbmac_state_on) 1431 sbmac_channel_start(sc); 1432 else 1433 sbmac_channel_stop(sc); 1434 1435 /* 1436 * Return previous state 1437 */ 1438 1439 return oldstate; 1440 } 1441 1442 /* 1443 * SBMAC_PROMISCUOUS_MODE(sc, onoff) 1444 * 1445 * Turn on or off promiscuous mode 1446 * 1447 * Input parameters: 1448 * sc - softc 1449 * onoff - 1 to turn on, 0 to turn off 1450 * 1451 * Return value: 1452 * nothing 1453 */ 1454 1455 static void 1456 sbmac_promiscuous_mode(struct sbmac_softc *sc, int onoff) 1457 { 1458 uint64_t reg; 1459 1460 if (sc->sbm_state != sbmac_state_on) 1461 return; 1462 1463 if (onoff) { 1464 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1465 reg |= M_MAC_ALLPKT_EN; 1466 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1467 } else { 1468 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1469 reg &= ~M_MAC_ALLPKT_EN; 1470 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1471 } 1472 } 1473 1474 /* 1475 * SBMAC_INIT_AND_START(sc) 1476 * 1477 * Stop the channel and restart it. This is generally used 1478 * when we have to do something to the channel that requires 1479 * a swift kick. 1480 * 1481 * Input parameters: 1482 * sc - softc 1483 */ 1484 1485 static void 1486 sbmac_init_and_start(struct sbmac_softc *sc) 1487 { 1488 int s; 1489 1490 s = splnet(); 1491 1492 mii_pollstat(&sc->sc_mii); /* poll phy for current speed */ 1493 sbmac_mii_statchg((struct device *) sc); /* set state to new speed */ 1494 sbmac_set_channel_state(sc, sbmac_state_on); 1495 1496 splx(s); 1497 } 1498 1499 /* 1500 * SBMAC_ADDR2REG(ptr) 1501 * 1502 * Convert six bytes into the 64-bit register value that 1503 * we typically write into the SBMAC's address/mcast registers 1504 * 1505 * Input parameters: 1506 * ptr - pointer to 6 bytes 1507 * 1508 * Return value: 1509 * register value 1510 */ 1511 1512 static uint64_t 1513 sbmac_addr2reg(u_char *ptr) 1514 { 1515 uint64_t reg = 0; 1516 1517 ptr += 6; 1518 1519 reg |= (uint64_t) *(--ptr); 1520 reg <<= 8; 1521 reg |= (uint64_t) *(--ptr); 1522 reg <<= 8; 1523 reg |= (uint64_t) *(--ptr); 1524 reg <<= 8; 1525 reg |= (uint64_t) *(--ptr); 1526 reg <<= 8; 1527 reg |= (uint64_t) *(--ptr); 1528 reg <<= 8; 1529 reg |= (uint64_t) *(--ptr); 1530 1531 return reg; 1532 } 1533 1534 /* 1535 * SBMAC_SET_SPEED(s, speed) 1536 * 1537 * Configure LAN speed for the specified MAC. 1538 * Warning: must be called when MAC is off! 1539 * 1540 * Input parameters: 1541 * s - sbmac structure 1542 * speed - speed to set MAC to (see sbmac_speed_t enum) 1543 * 1544 * Return value: 1545 * 1 if successful 1546 * 0 indicates invalid parameters 1547 */ 1548 1549 static int 1550 sbmac_set_speed(struct sbmac_softc *s, sbmac_speed_t speed) 1551 { 1552 uint64_t cfg; 1553 uint64_t framecfg; 1554 1555 /* 1556 * Save new current values 1557 */ 1558 1559 s->sbm_speed = speed; 1560 1561 if (s->sbm_state != sbmac_state_off) 1562 panic("sbmac_set_speed while MAC not off"); 1563 1564 /* 1565 * Read current register values 1566 */ 1567 1568 cfg = SBMAC_READCSR(s->sbm_maccfg); 1569 framecfg = SBMAC_READCSR(s->sbm_framecfg); 1570 1571 /* 1572 * Mask out the stuff we want to change 1573 */ 1574 1575 cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL); 1576 framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH | 1577 M_MAC_SLOT_SIZE); 1578 1579 /* 1580 * Now add in the new bits 1581 */ 1582 1583 switch (speed) { 1584 case sbmac_speed_10: 1585 framecfg |= V_MAC_IFG_RX_10 | 1586 V_MAC_IFG_TX_10 | 1587 K_MAC_IFG_THRSH_10 | 1588 V_MAC_SLOT_SIZE_10; 1589 cfg |= V_MAC_SPEED_SEL_10MBPS; 1590 break; 1591 1592 case sbmac_speed_100: 1593 framecfg |= V_MAC_IFG_RX_100 | 1594 V_MAC_IFG_TX_100 | 1595 V_MAC_IFG_THRSH_100 | 1596 V_MAC_SLOT_SIZE_100; 1597 cfg |= V_MAC_SPEED_SEL_100MBPS ; 1598 break; 1599 1600 case sbmac_speed_1000: 1601 framecfg |= V_MAC_IFG_RX_1000 | 1602 V_MAC_IFG_TX_1000 | 1603 V_MAC_IFG_THRSH_1000 | 1604 V_MAC_SLOT_SIZE_1000; 1605 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN; 1606 break; 1607 1608 case sbmac_speed_auto: /* XXX not implemented */ 1609 /* fall through */ 1610 default: 1611 return 0; 1612 } 1613 1614 /* 1615 * Send the bits back to the hardware 1616 */ 1617 1618 SBMAC_WRITECSR(s->sbm_framecfg, framecfg); 1619 SBMAC_WRITECSR(s->sbm_maccfg, cfg); 1620 1621 return 1; 1622 } 1623 1624 /* 1625 * SBMAC_SET_DUPLEX(s, duplex, fc) 1626 * 1627 * Set Ethernet duplex and flow control options for this MAC 1628 * Warning: must be called when MAC is off! 1629 * 1630 * Input parameters: 1631 * s - sbmac structure 1632 * duplex - duplex setting (see sbmac_duplex_t) 1633 * fc - flow control setting (see sbmac_fc_t) 1634 * 1635 * Return value: 1636 * 1 if ok 1637 * 0 if an invalid parameter combination was specified 1638 */ 1639 1640 static int 1641 sbmac_set_duplex(struct sbmac_softc *s, sbmac_duplex_t duplex, sbmac_fc_t fc) 1642 { 1643 uint64_t cfg; 1644 1645 /* 1646 * Save new current values 1647 */ 1648 1649 s->sbm_duplex = duplex; 1650 s->sbm_fc = fc; 1651 1652 if (s->sbm_state != sbmac_state_off) 1653 panic("sbmac_set_duplex while MAC not off"); 1654 1655 /* 1656 * Read current register values 1657 */ 1658 1659 cfg = SBMAC_READCSR(s->sbm_maccfg); 1660 1661 /* 1662 * Mask off the stuff we're about to change 1663 */ 1664 1665 cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN); 1666 1667 switch (duplex) { 1668 case sbmac_duplex_half: 1669 switch (fc) { 1670 case sbmac_fc_disabled: 1671 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED; 1672 break; 1673 1674 case sbmac_fc_collision: 1675 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED; 1676 break; 1677 1678 case sbmac_fc_carrier: 1679 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR; 1680 break; 1681 1682 case sbmac_fc_auto: /* XXX not implemented */ 1683 /* fall through */ 1684 case sbmac_fc_frame: /* not valid in half duplex */ 1685 default: /* invalid selection */ 1686 panic("%s: invalid half duplex fc selection %d", 1687 s->sc_dev.dv_xname, fc); 1688 return 0; 1689 } 1690 break; 1691 1692 case sbmac_duplex_full: 1693 switch (fc) { 1694 case sbmac_fc_disabled: 1695 cfg |= V_MAC_FC_CMD_DISABLED; 1696 break; 1697 1698 case sbmac_fc_frame: 1699 cfg |= V_MAC_FC_CMD_ENABLED; 1700 break; 1701 1702 case sbmac_fc_collision: /* not valid in full duplex */ 1703 case sbmac_fc_carrier: /* not valid in full duplex */ 1704 case sbmac_fc_auto: /* XXX not implemented */ 1705 /* fall through */ 1706 default: 1707 panic("%s: invalid full duplex fc selection %d", 1708 s->sc_dev.dv_xname, fc); 1709 return 0; 1710 } 1711 break; 1712 1713 default: 1714 /* fall through */ 1715 case sbmac_duplex_auto: 1716 panic("%s: bad duplex %d", s->sc_dev.dv_xname, duplex); 1717 /* XXX not implemented */ 1718 break; 1719 } 1720 1721 /* 1722 * Send the bits back to the hardware 1723 */ 1724 1725 SBMAC_WRITECSR(s->sbm_maccfg, cfg); 1726 1727 return 1; 1728 } 1729 1730 /* 1731 * SBMAC_INTR() 1732 * 1733 * Interrupt handler for MAC interrupts 1734 * 1735 * Input parameters: 1736 * MAC structure 1737 * 1738 * Return value: 1739 * nothing 1740 */ 1741 1742 /* ARGSUSED */ 1743 static void 1744 sbmac_intr(void *xsc, uint32_t status, uint32_t pc) 1745 { 1746 struct sbmac_softc *sc = (struct sbmac_softc *) xsc; 1747 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1748 uint64_t isr; 1749 1750 for (;;) { 1751 1752 /* 1753 * Read the ISR (this clears the bits in the real register) 1754 */ 1755 1756 isr = SBMAC_READCSR(sc->sbm_isr); 1757 1758 if (isr == 0) 1759 break; 1760 1761 /* 1762 * Transmits on channel 0 1763 */ 1764 1765 if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) { 1766 sbdma_tx_process(sc, &(sc->sbm_txdma)); 1767 SBMAC_EVCNT_INCR(sc->sbm_ev_txintr); 1768 } 1769 1770 /* 1771 * Receives on channel 0 1772 */ 1773 1774 if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) { 1775 sbdma_rx_process(sc, &(sc->sbm_rxdma)); 1776 SBMAC_EVCNT_INCR(sc->sbm_ev_rxintr); 1777 } 1778 } 1779 1780 /* try to get more packets going */ 1781 sbmac_start(ifp); 1782 } 1783 1784 1785 /* 1786 * SBMAC_START(ifp) 1787 * 1788 * Start output on the specified interface. Basically, we 1789 * queue as many buffers as we can until the ring fills up, or 1790 * we run off the end of the queue, whichever comes first. 1791 * 1792 * Input parameters: 1793 * ifp - interface 1794 * 1795 * Return value: 1796 * nothing 1797 */ 1798 1799 static void 1800 sbmac_start(struct ifnet *ifp) 1801 { 1802 struct sbmac_softc *sc; 1803 struct mbuf *m_head = NULL; 1804 int rv; 1805 1806 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1807 return; 1808 1809 sc = ifp->if_softc; 1810 1811 for (;;) { 1812 1813 IF_DEQUEUE(&ifp->if_snd, m_head); 1814 if (m_head == NULL) 1815 break; 1816 1817 /* 1818 * Put the buffer on the transmit ring. If we 1819 * don't have room, set the OACTIVE flag and wait 1820 * for the NIC to drain the ring. 1821 */ 1822 1823 rv = sbdma_add_txbuffer(&(sc->sbm_txdma), m_head); 1824 1825 if (rv == 0) { 1826 /* 1827 * If there's a BPF listener, bounce a copy of this 1828 * frame to it. 1829 */ 1830 #if (NBPFILTER > 0) 1831 if (ifp->if_bpf) 1832 bpf_mtap(ifp->if_bpf, m_head); 1833 #endif 1834 if (!sc->sbm_pass3_dma) { 1835 /* 1836 * Don't free mbuf if we're not copying to new 1837 * mbuf in sbdma_add_txbuffer. It will be 1838 * freed in sbdma_tx_process. 1839 */ 1840 m_freem(m_head); 1841 } 1842 } else { 1843 IF_PREPEND(&ifp->if_snd, m_head); 1844 ifp->if_flags |= IFF_OACTIVE; 1845 break; 1846 } 1847 } 1848 } 1849 1850 /* 1851 * SBMAC_SETMULTI(sc) 1852 * 1853 * Reprogram the multicast table into the hardware, given 1854 * the list of multicasts associated with the interface 1855 * structure. 1856 * 1857 * Input parameters: 1858 * sc - softc 1859 * 1860 * Return value: 1861 * nothing 1862 */ 1863 1864 static void 1865 sbmac_setmulti(struct sbmac_softc *sc) 1866 { 1867 struct ifnet *ifp; 1868 uint64_t reg; 1869 sbmac_port_t port; 1870 int idx; 1871 struct ether_multi *enm; 1872 struct ether_multistep step; 1873 1874 ifp = &sc->sc_ethercom.ec_if; 1875 1876 /* 1877 * Clear out entire multicast table. We do this by nuking 1878 * the entire hash table and all the direct matches except 1879 * the first one, which is used for our station address 1880 */ 1881 1882 for (idx = 1; idx < MAC_ADDR_COUNT; idx++) { 1883 port = PKSEG1(sc->sbm_base + 1884 R_MAC_ADDR_BASE+(idx*sizeof(uint64_t))); 1885 SBMAC_WRITECSR(port, 0); 1886 } 1887 1888 for (idx = 0; idx < MAC_HASH_COUNT; idx++) { 1889 port = PKSEG1(sc->sbm_base + 1890 R_MAC_HASH_BASE+(idx*sizeof(uint64_t))); 1891 SBMAC_WRITECSR(port, 0); 1892 } 1893 1894 /* 1895 * Clear the filter to say we don't want any multicasts. 1896 */ 1897 1898 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1899 reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN); 1900 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1901 1902 if (ifp->if_flags & IFF_ALLMULTI) { 1903 /* 1904 * Enable ALL multicasts. Do this by inverting the 1905 * multicast enable bit. 1906 */ 1907 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1908 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN); 1909 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1910 return; 1911 } 1912 1913 /* 1914 * Progam new multicast entries. For now, only use the 1915 * perfect filter. In the future we'll need to use the 1916 * hash filter if the perfect filter overflows 1917 */ 1918 1919 /* 1920 * XXX only using perfect filter for now, need to use hash 1921 * XXX if the table overflows 1922 */ 1923 1924 idx = 1; /* skip station address */ 1925 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1926 while ((enm != NULL) && (idx < MAC_ADDR_COUNT)) { 1927 reg = sbmac_addr2reg(enm->enm_addrlo); 1928 port = PKSEG1(sc->sbm_base + 1929 R_MAC_ADDR_BASE+(idx*sizeof(uint64_t))); 1930 SBMAC_WRITECSR(port, reg); 1931 idx++; 1932 ETHER_NEXT_MULTI(step, enm); 1933 } 1934 1935 /* 1936 * Enable the "accept multicast bits" if we programmed at least one 1937 * multicast. 1938 */ 1939 1940 if (idx > 1) { 1941 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1942 reg |= M_MAC_MCAST_EN; 1943 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1944 } 1945 } 1946 1947 /* 1948 * SBMAC_ETHER_IOCTL(ifp, cmd, data) 1949 * 1950 * Generic IOCTL requests for this interface. The basic 1951 * stuff is handled here for bringing the interface up, 1952 * handling multicasts, etc. 1953 * 1954 * Input parameters: 1955 * ifp - interface structure 1956 * cmd - command code 1957 * data - pointer to data 1958 * 1959 * Return value: 1960 * return value (0 is success) 1961 */ 1962 1963 static int 1964 sbmac_ether_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1965 { 1966 struct ifaddr *ifa = (struct ifaddr *) data; 1967 struct sbmac_softc *sc = ifp->if_softc; 1968 1969 switch (cmd) { 1970 case SIOCSIFADDR: 1971 ifp->if_flags |= IFF_UP; 1972 1973 switch (ifa->ifa_addr->sa_family) { 1974 #ifdef INET 1975 case AF_INET: 1976 sbmac_init_and_start(sc); 1977 arp_ifinit(ifp, ifa); 1978 break; 1979 #endif 1980 #ifdef NS 1981 case AF_NS: 1982 { 1983 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1984 1985 if (ns_nullhost(*ina)) 1986 ina->x_host = 1987 *(union ns_host *)LLADDR(ifp->if_sadl); 1988 else 1989 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1990 ifp->if_addrlen); 1991 /* Set new address. */ 1992 sbmac_init_and_start(sc); 1993 break; 1994 } 1995 #endif 1996 default: 1997 sbmac_init_and_start(sc); 1998 break; 1999 } 2000 break; 2001 2002 default: 2003 return (EINVAL); 2004 } 2005 2006 return (0); 2007 } 2008 2009 /* 2010 * SBMAC_IOCTL(ifp, command, data) 2011 * 2012 * Main IOCTL handler - dispatches to other IOCTLs for various 2013 * types of requests. 2014 * 2015 * Input parameters: 2016 * ifp - interface pointer 2017 * command - command code 2018 * data - pointer to argument data 2019 * 2020 * Return value: 2021 * 0 if ok 2022 * else error code 2023 */ 2024 2025 static int 2026 sbmac_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2027 { 2028 struct sbmac_softc *sc = ifp->if_softc; 2029 struct ifreq *ifr = (struct ifreq *) data; 2030 int s, error = 0; 2031 2032 s = splnet(); 2033 2034 switch(command) { 2035 case SIOCSIFADDR: 2036 case SIOCGIFADDR: 2037 error = sbmac_ether_ioctl(ifp, command, data); 2038 break; 2039 case SIOCSIFMTU: 2040 if (ifr->ifr_mtu > ETHER_MAX_LEN) 2041 error = EINVAL; 2042 else { 2043 ifp->if_mtu = ifr->ifr_mtu; 2044 /* XXX Program new MTU here */ 2045 } 2046 break; 2047 case SIOCSIFFLAGS: 2048 if (ifp->if_flags & IFF_UP) { 2049 /* 2050 * If only the state of the PROMISC flag changed, 2051 * just tweak the hardware registers. 2052 */ 2053 if ((ifp->if_flags & IFF_RUNNING) && 2054 (ifp->if_flags & IFF_PROMISC)) { 2055 /* turn on promiscuous mode */ 2056 sbmac_promiscuous_mode(sc, 1); 2057 } else if (ifp->if_flags & IFF_RUNNING && 2058 !(ifp->if_flags & IFF_PROMISC)) { 2059 /* turn off promiscuous mode */ 2060 sbmac_promiscuous_mode(sc, 0); 2061 } else 2062 sbmac_set_channel_state(sc, sbmac_state_on); 2063 } else { 2064 if (ifp->if_flags & IFF_RUNNING) 2065 sbmac_set_channel_state(sc, sbmac_state_off); 2066 } 2067 2068 sc->sbm_if_flags = ifp->if_flags; 2069 error = 0; 2070 break; 2071 2072 case SIOCADDMULTI: 2073 case SIOCDELMULTI: 2074 if (ifp->if_flags & IFF_RUNNING) { 2075 sbmac_setmulti(sc); 2076 error = 0; 2077 } 2078 break; 2079 case SIOCSIFMEDIA: 2080 case SIOCGIFMEDIA: 2081 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 2082 break; 2083 default: 2084 error = EINVAL; 2085 break; 2086 } 2087 2088 (void)splx(s); 2089 2090 return(error); 2091 } 2092 2093 /* 2094 * SBMAC_IFMEDIA_UPD(ifp) 2095 * 2096 * Configure an appropriate media type for this interface, 2097 * given the data in the interface structure 2098 * 2099 * Input parameters: 2100 * ifp - interface 2101 * 2102 * Return value: 2103 * 0 if ok 2104 * else error code 2105 */ 2106 2107 static int 2108 sbmac_mediachange(struct ifnet *ifp) 2109 { 2110 struct sbmac_softc *sc = ifp->if_softc; 2111 2112 if (ifp->if_flags & IFF_UP) 2113 mii_mediachg(&sc->sc_mii); 2114 return(0); 2115 } 2116 2117 /* 2118 * SBMAC_IFMEDIA_STS(ifp, ifmr) 2119 * 2120 * Report current media status (used by ifconfig, for example) 2121 * 2122 * Input parameters: 2123 * ifp - interface structure 2124 * ifmr - media request structure 2125 * 2126 * Return value: 2127 * nothing 2128 */ 2129 2130 static void 2131 sbmac_mediastatus(struct ifnet *ifp, struct ifmediareq *req) 2132 { 2133 struct sbmac_softc *sc = ifp->if_softc; 2134 2135 mii_pollstat(&sc->sc_mii); 2136 req->ifm_status = sc->sc_mii.mii_media_status; 2137 req->ifm_active = sc->sc_mii.mii_media_active; 2138 } 2139 2140 /* 2141 * SBMAC_WATCHDOG(ifp) 2142 * 2143 * Called periodically to make sure we're still happy. 2144 * 2145 * Input parameters: 2146 * ifp - interface structure 2147 * 2148 * Return value: 2149 * nothing 2150 */ 2151 2152 static void 2153 sbmac_watchdog(struct ifnet *ifp) 2154 { 2155 2156 /* XXX do something */ 2157 } 2158 2159 /* 2160 * One second timer, used to tick MII. 2161 */ 2162 static void 2163 sbmac_tick(void *arg) 2164 { 2165 struct sbmac_softc *sc = arg; 2166 int s; 2167 2168 s = splnet(); 2169 mii_tick(&sc->sc_mii); 2170 splx(s); 2171 2172 callout_reset(&sc->sc_tick_ch, hz, sbmac_tick, sc); 2173 } 2174 2175 2176 /* 2177 * SBMAC_MATCH(parent, match, aux) 2178 * 2179 * Part of the config process - see if this device matches the 2180 * info about what we expect to find on the bus. 2181 * 2182 * Input parameters: 2183 * parent - parent bus structure 2184 * match - 2185 * aux - bus-specific args 2186 * 2187 * Return value: 2188 * 1 if we match 2189 * 0 if we don't match 2190 */ 2191 2192 static int 2193 sbmac_match(struct device *parent, struct cfdata *match, void *aux) 2194 { 2195 struct sbobio_attach_args *sap = aux; 2196 2197 /* 2198 * Make sure it's a MAC 2199 */ 2200 2201 if (sap->sa_locs.sa_type != SBOBIO_DEVTYPE_MAC) 2202 return 0; 2203 2204 /* 2205 * Yup, it is. 2206 */ 2207 2208 return 1; 2209 } 2210 2211 /* 2212 * SBMAC_PARSE_XDIGIT(str) 2213 * 2214 * Parse a hex digit, returning its value 2215 * 2216 * Input parameters: 2217 * str - character 2218 * 2219 * Return value: 2220 * hex value, or -1 if invalid 2221 */ 2222 2223 static int 2224 sbmac_parse_xdigit(char str) 2225 { 2226 int digit; 2227 2228 if ((str >= '0') && (str <= '9')) 2229 digit = str - '0'; 2230 else if ((str >= 'a') && (str <= 'f')) 2231 digit = str - 'a' + 10; 2232 else if ((str >= 'A') && (str <= 'F')) 2233 digit = str - 'A' + 10; 2234 else 2235 digit = -1; 2236 2237 return digit; 2238 } 2239 2240 /* 2241 * SBMAC_PARSE_HWADDR(str, hwaddr) 2242 * 2243 * Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte 2244 * Ethernet address. 2245 * 2246 * Input parameters: 2247 * str - string 2248 * hwaddr - pointer to hardware address 2249 * 2250 * Return value: 2251 * 0 if ok, else -1 2252 */ 2253 2254 static int 2255 sbmac_parse_hwaddr(char *str, u_char *hwaddr) 2256 { 2257 int digit1, digit2; 2258 int idx = 6; 2259 2260 while (*str && (idx > 0)) { 2261 digit1 = sbmac_parse_xdigit(*str); 2262 if (digit1 < 0) 2263 return -1; 2264 str++; 2265 if (!*str) 2266 return -1; 2267 2268 if ((*str == ':') || (*str == '-')) { 2269 digit2 = digit1; 2270 digit1 = 0; 2271 } else { 2272 digit2 = sbmac_parse_xdigit(*str); 2273 if (digit2 < 0) 2274 return -1; 2275 str++; 2276 } 2277 2278 *hwaddr++ = (digit1 << 4) | digit2; 2279 idx--; 2280 2281 if (*str == '-') 2282 str++; 2283 if (*str == ':') 2284 str++; 2285 } 2286 return 0; 2287 } 2288 2289 /* 2290 * SBMAC_ATTACH(parent, self, aux) 2291 * 2292 * Attach routine - init hardware and hook ourselves into NetBSD. 2293 * 2294 * Input parameters: 2295 * parent - parent bus device 2296 * self - our softc 2297 * aux - attach data 2298 * 2299 * Return value: 2300 * nothing 2301 */ 2302 2303 static void 2304 sbmac_attach(struct device *parent, struct device *self, void *aux) 2305 { 2306 struct ifnet *ifp; 2307 struct sbmac_softc *sc; 2308 struct sbobio_attach_args *sap = aux; 2309 u_char *eaddr; 2310 static int unit = 0; /* XXX */ 2311 uint64_t ea_reg; 2312 int idx; 2313 2314 sc = (struct sbmac_softc *)self; 2315 2316 /* Determine controller base address */ 2317 2318 sc->sbm_base = (sbmac_port_t) sap->sa_base + sap->sa_locs.sa_offset; 2319 2320 eaddr = sc->sbm_hwaddr; 2321 2322 /* 2323 * Initialize context (get pointers to registers and stuff), then 2324 * allocate the memory for the descriptor tables. 2325 */ 2326 2327 sbmac_initctx(sc); 2328 2329 callout_init(&(sc->sc_tick_ch)); 2330 2331 /* 2332 * Read the ethernet address. The firwmare left this programmed 2333 * for us in the ethernet address register for each mac. 2334 */ 2335 2336 ea_reg = SBMAC_READCSR(PKSEG1(sc->sbm_base + R_MAC_ETHERNET_ADDR)); 2337 for (idx = 0; idx < 6; idx++) { 2338 eaddr[idx] = (uint8_t) (ea_reg & 0xFF); 2339 ea_reg >>= 8; 2340 } 2341 2342 #define SBMAC_DEFAULT_HWADDR "40:00:00:00:01:00" 2343 if (eaddr[0] == 0 && eaddr[1] == 0 && eaddr[2] == 0 && 2344 eaddr[3] == 0 && eaddr[4] == 0 && eaddr[5] == 0) { 2345 sbmac_parse_hwaddr(SBMAC_DEFAULT_HWADDR, eaddr); 2346 eaddr[5] = unit; 2347 } 2348 2349 #ifdef SBMAC_ETH0_HWADDR 2350 if (unit == 0) 2351 sbmac_parse_hwaddr(SBMAC_ETH0_HWADDR, eaddr); 2352 #endif 2353 #ifdef SBMAC_ETH1_HWADDR 2354 if (unit == 1) 2355 sbmac_parse_hwaddr(SBMAC_ETH1_HWADDR, eaddr); 2356 #endif 2357 #ifdef SBMAC_ETH2_HWADDR 2358 if (unit == 2) 2359 sbmac_parse_hwaddr(SBMAC_ETH2_HWADDR, eaddr); 2360 #endif 2361 unit++; 2362 2363 /* 2364 * Display Ethernet address (this is called during the config process 2365 * so we need to finish off the config message that was being displayed) 2366 */ 2367 printf(": Ethernet%s\n", 2368 sc->sbm_pass3_dma ? ", using unaligned tx DMA" : ""); 2369 printf("%s: Ethernet address: %s\n", self->dv_xname, 2370 ether_sprintf(eaddr)); 2371 2372 2373 /* 2374 * Set up ifnet structure 2375 */ 2376 2377 ifp = &sc->sc_ethercom.ec_if; 2378 ifp->if_softc = sc; 2379 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 2380 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 2381 IFF_NOTRAILERS; 2382 ifp->if_ioctl = sbmac_ioctl; 2383 ifp->if_start = sbmac_start; 2384 ifp->if_watchdog = sbmac_watchdog; 2385 ifp->if_snd.ifq_maxlen = SBMAC_MAX_TXDESCR - 1; 2386 2387 /* 2388 * Set up ifmedia support. 2389 */ 2390 2391 /* 2392 * Initialize MII/media info. 2393 */ 2394 sc->sc_mii.mii_ifp = ifp; 2395 sc->sc_mii.mii_readreg = sbmac_mii_readreg; 2396 sc->sc_mii.mii_writereg = sbmac_mii_writereg; 2397 sc->sc_mii.mii_statchg = sbmac_mii_statchg; 2398 ifmedia_init(&sc->sc_mii.mii_media, 0, sbmac_mediachange, 2399 sbmac_mediastatus); 2400 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 2401 MII_OFFSET_ANY, 0); 2402 2403 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 2404 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 2405 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 2406 } else { 2407 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2408 } 2409 2410 2411 /* 2412 * map/route interrupt 2413 */ 2414 2415 sc->sbm_intrhand = cpu_intr_establish(sap->sa_locs.sa_intr[0], IPL_NET, 2416 sbmac_intr, sc); 2417 2418 /* 2419 * Call MI attach routines. 2420 */ 2421 if_attach(ifp); 2422 ether_ifattach(ifp, eaddr); 2423 } 2424
Indexes created Mon Sep 29 21:09:56 GMT 2025