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sb1250_int.h revision 1.3 
      1 /*  *********************************************************************
      2     *  SB1250 Board Support Package
      3     *
      4     *  Interrupt Mapper definitions		File: sb1250_int.h
      5     *
      6     *  This module contains constants for manipulating the SB1250's
      7     *  interrupt mapper and definitions for the interrupt sources.
      8     *
      9     *  SB1250 specification level:  User's manual 1/02/02
     10     *
     11     *  Author:  Mitch Lichtenberg (mpl (at) broadcom.com)
     12     *
     13     *********************************************************************
     14     *
     15     *  Copyright 2000,2001
     16     *  Broadcom Corporation. All rights reserved.
     17     *
     18     *  This software is furnished under license and may be used and
     19     *  copied only in accordance with the following terms and
     20     *  conditions.  Subject to these conditions, you may download,
     21     *  copy, install, use, modify and distribute modified or unmodified
     22     *  copies of this software in source and/or binary form.  No title
     23     *  or ownership is transferred hereby.
     24     *
     25     *  1) Any source code used, modified or distributed must reproduce
     26     *     and retain this copyright notice and list of conditions as
     27     *     they appear in the source file.
     28     *
     29     *  2) No right is granted to use any trade name, trademark, or
     30     *     logo of Broadcom Corporation. Neither the "Broadcom
     31     *     Corporation" name nor any trademark or logo of Broadcom
     32     *     Corporation may be used to endorse or promote products
     33     *     derived from this software without the prior written
     34     *     permission of Broadcom Corporation.
     35     *
     36     *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
     37     *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
     38     *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
     39     *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
     40     *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
     41     *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
     42     *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     43     *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
     44     *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
     45     *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
     46     *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
     47     *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
     48     *     THE POSSIBILITY OF SUCH DAMAGE.
     49     ********************************************************************* */
     50 
     51 
     52 #ifndef _SB1250_INT_H
     53 #define _SB1250_INT_H
     54 
     55 #include "sb1250_defs.h"
     56 
     57 /*  *********************************************************************
     58     *  Interrupt Mapper Constants
     59     ********************************************************************* */
     60 
     61 /*
     62  * Interrupt sources (Table 4-8, UM 0.2)
     63  *
     64  * First, the interrupt numbers.
     65  */
     66 
     67 #define K_INT_WATCHDOG_TIMER_0      0
     68 #define K_INT_WATCHDOG_TIMER_1      1
     69 #define K_INT_TIMER_0               2
     70 #define K_INT_TIMER_1               3
     71 #define K_INT_TIMER_2               4
     72 #define K_INT_TIMER_3               5
     73 #define K_INT_SMB_0                 6
     74 #define K_INT_SMB_1                 7
     75 #define K_INT_UART_0                8
     76 #define K_INT_UART_1                9
     77 #define K_INT_SER_0                 10
     78 #define K_INT_SER_1                 11
     79 #define K_INT_PCMCIA                12
     80 #define K_INT_ADDR_TRAP             13
     81 #define K_INT_PERF_CNT              14
     82 #define K_INT_TRACE_FREEZE          15
     83 #define K_INT_BAD_ECC               16
     84 #define K_INT_COR_ECC               17
     85 #define K_INT_IO_BUS                18
     86 #define K_INT_MAC_0                 19
     87 #define K_INT_MAC_1                 20
     88 #define K_INT_MAC_2                 21
     89 #define K_INT_DM_CH_0               22
     90 #define K_INT_DM_CH_1               23
     91 #define K_INT_DM_CH_2               24
     92 #define K_INT_DM_CH_3               25
     93 #define K_INT_MBOX_0                26
     94 #define K_INT_MBOX_1                27
     95 #define K_INT_MBOX_2                28
     96 #define K_INT_MBOX_3                29
     97 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
     98 #define K_INT_CYCLE_CP0_INT	    30
     99 #define K_INT_CYCLE_CP1_INT	    31
    100 #endif /* 1250 PASS2 || 112x PASS1 */
    101 #define K_INT_GPIO_0                32
    102 #define K_INT_GPIO_1                33
    103 #define K_INT_GPIO_2                34
    104 #define K_INT_GPIO_3                35
    105 #define K_INT_GPIO_4                36
    106 #define K_INT_GPIO_5                37
    107 #define K_INT_GPIO_6                38
    108 #define K_INT_GPIO_7                39
    109 #define K_INT_GPIO_8                40
    110 #define K_INT_GPIO_9                41
    111 #define K_INT_GPIO_10               42
    112 #define K_INT_GPIO_11               43
    113 #define K_INT_GPIO_12               44
    114 #define K_INT_GPIO_13               45
    115 #define K_INT_GPIO_14               46
    116 #define K_INT_GPIO_15               47
    117 #define K_INT_LDT_FATAL             48
    118 #define K_INT_LDT_NONFATAL          49
    119 #define K_INT_LDT_SMI               50
    120 #define K_INT_LDT_NMI               51
    121 #define K_INT_LDT_INIT              52
    122 #define K_INT_LDT_STARTUP           53
    123 #define K_INT_LDT_EXT               54
    124 #define K_INT_PCI_ERROR             55
    125 #define K_INT_PCI_INTA              56
    126 #define K_INT_PCI_INTB              57
    127 #define K_INT_PCI_INTC              58
    128 #define K_INT_PCI_INTD              59
    129 #define K_INT_SPARE_2               60
    130 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
    131 #define K_INT_MAC_0_CH1		    61
    132 #define K_INT_MAC_1_CH1		    62
    133 #define K_INT_MAC_2_CH1		    63
    134 #endif /* 1250 PASS2 || 112x PASS1 */
    135 
    136 /*
    137  * Mask values for each interrupt
    138  */
    139 
    140 #define M_INT_WATCHDOG_TIMER_0      _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0)
    141 #define M_INT_WATCHDOG_TIMER_1      _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1)
    142 #define M_INT_TIMER_0               _SB_MAKEMASK1(K_INT_TIMER_0)
    143 #define M_INT_TIMER_1               _SB_MAKEMASK1(K_INT_TIMER_1)
    144 #define M_INT_TIMER_2               _SB_MAKEMASK1(K_INT_TIMER_2)
    145 #define M_INT_TIMER_3               _SB_MAKEMASK1(K_INT_TIMER_3)
    146 #define M_INT_SMB_0                 _SB_MAKEMASK1(K_INT_SMB_0)
    147 #define M_INT_SMB_1                 _SB_MAKEMASK1(K_INT_SMB_1)
    148 #define M_INT_UART_0                _SB_MAKEMASK1(K_INT_UART_0)
    149 #define M_INT_UART_1                _SB_MAKEMASK1(K_INT_UART_1)
    150 #define M_INT_SER_0                 _SB_MAKEMASK1(K_INT_SER_0)
    151 #define M_INT_SER_1                 _SB_MAKEMASK1(K_INT_SER_1)
    152 #define M_INT_PCMCIA                _SB_MAKEMASK1(K_INT_PCMCIA)
    153 #define M_INT_ADDR_TRAP             _SB_MAKEMASK1(K_INT_ADDR_TRAP)
    154 #define M_INT_PERF_CNT              _SB_MAKEMASK1(K_INT_PERF_CNT)
    155 #define M_INT_TRACE_FREEZE          _SB_MAKEMASK1(K_INT_TRACE_FREEZE)
    156 #define M_INT_BAD_ECC               _SB_MAKEMASK1(K_INT_BAD_ECC)
    157 #define M_INT_COR_ECC               _SB_MAKEMASK1(K_INT_COR_ECC)
    158 #define M_INT_IO_BUS                _SB_MAKEMASK1(K_INT_IO_BUS)
    159 #define M_INT_MAC_0                 _SB_MAKEMASK1(K_INT_MAC_0)
    160 #define M_INT_MAC_1                 _SB_MAKEMASK1(K_INT_MAC_1)
    161 #define M_INT_MAC_2                 _SB_MAKEMASK1(K_INT_MAC_2)
    162 #define M_INT_DM_CH_0               _SB_MAKEMASK1(K_INT_DM_CH_0)
    163 #define M_INT_DM_CH_1               _SB_MAKEMASK1(K_INT_DM_CH_1)
    164 #define M_INT_DM_CH_2               _SB_MAKEMASK1(K_INT_DM_CH_2)
    165 #define M_INT_DM_CH_3               _SB_MAKEMASK1(K_INT_DM_CH_3)
    166 #define M_INT_MBOX_0                _SB_MAKEMASK1(K_INT_MBOX_0)
    167 #define M_INT_MBOX_1                _SB_MAKEMASK1(K_INT_MBOX_1)
    168 #define M_INT_MBOX_2                _SB_MAKEMASK1(K_INT_MBOX_2)
    169 #define M_INT_MBOX_3                _SB_MAKEMASK1(K_INT_MBOX_3)
    170 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
    171 #define M_INT_CYCLE_CP0_INT	    _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT)
    172 #define M_INT_CYCLE_CP1_INT	    _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT)
    173 #endif /* 1250 PASS2 || 112x PASS1 */
    174 #define M_INT_GPIO_0                _SB_MAKEMASK1(K_INT_GPIO_0)
    175 #define M_INT_GPIO_1                _SB_MAKEMASK1(K_INT_GPIO_1)
    176 #define M_INT_GPIO_2                _SB_MAKEMASK1(K_INT_GPIO_2)
    177 #define M_INT_GPIO_3                _SB_MAKEMASK1(K_INT_GPIO_3)
    178 #define M_INT_GPIO_4                _SB_MAKEMASK1(K_INT_GPIO_4)
    179 #define M_INT_GPIO_5                _SB_MAKEMASK1(K_INT_GPIO_5)
    180 #define M_INT_GPIO_6                _SB_MAKEMASK1(K_INT_GPIO_6)
    181 #define M_INT_GPIO_7                _SB_MAKEMASK1(K_INT_GPIO_7)
    182 #define M_INT_GPIO_8                _SB_MAKEMASK1(K_INT_GPIO_8)
    183 #define M_INT_GPIO_9                _SB_MAKEMASK1(K_INT_GPIO_9)
    184 #define M_INT_GPIO_10               _SB_MAKEMASK1(K_INT_GPIO_10)
    185 #define M_INT_GPIO_11               _SB_MAKEMASK1(K_INT_GPIO_11)
    186 #define M_INT_GPIO_12               _SB_MAKEMASK1(K_INT_GPIO_12)
    187 #define M_INT_GPIO_13               _SB_MAKEMASK1(K_INT_GPIO_13)
    188 #define M_INT_GPIO_14               _SB_MAKEMASK1(K_INT_GPIO_14)
    189 #define M_INT_GPIO_15               _SB_MAKEMASK1(K_INT_GPIO_15)
    190 #define M_INT_LDT_FATAL             _SB_MAKEMASK1(K_INT_LDT_FATAL)
    191 #define M_INT_LDT_NONFATAL          _SB_MAKEMASK1(K_INT_LDT_NONFATAL)
    192 #define M_INT_LDT_SMI               _SB_MAKEMASK1(K_INT_LDT_SMI)
    193 #define M_INT_LDT_NMI               _SB_MAKEMASK1(K_INT_LDT_NMI)
    194 #define M_INT_LDT_INIT              _SB_MAKEMASK1(K_INT_LDT_INIT)
    195 #define M_INT_LDT_STARTUP           _SB_MAKEMASK1(K_INT_LDT_STARTUP)
    196 #define M_INT_LDT_EXT               _SB_MAKEMASK1(K_INT_LDT_EXT)
    197 #define M_INT_PCI_ERROR             _SB_MAKEMASK1(K_INT_PCI_ERROR)
    198 #define M_INT_PCI_INTA              _SB_MAKEMASK1(K_INT_PCI_INTA)
    199 #define M_INT_PCI_INTB              _SB_MAKEMASK1(K_INT_PCI_INTB)
    200 #define M_INT_PCI_INTC              _SB_MAKEMASK1(K_INT_PCI_INTC)
    201 #define M_INT_PCI_INTD              _SB_MAKEMASK1(K_INT_PCI_INTD)
    202 #define M_INT_SPARE_2               _SB_MAKEMASK1(K_INT_SPARE_2)
    203 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
    204 #define M_INT_MAC_0_CH1		    _SB_MAKEMASK1(K_INT_MAC_0_CH1)
    205 #define M_INT_MAC_1_CH1		    _SB_MAKEMASK1(K_INT_MAC_1_CH1)
    206 #define M_INT_MAC_2_CH1		    _SB_MAKEMASK1(K_INT_MAC_2_CH1)
    207 #endif /* 1250 PASS2 || 112x PASS1 */
    208 
    209 /*
    210  * Interrupt mappings
    211  */
    212 
    213 #define K_INT_MAP_I0	0		/* interrupt pins on processor */
    214 #define K_INT_MAP_I1	1
    215 #define K_INT_MAP_I2	2
    216 #define K_INT_MAP_I3	3
    217 #define K_INT_MAP_I4	4
    218 #define K_INT_MAP_I5	5
    219 #define K_INT_MAP_NMI	6		/* nonmaskable */
    220 #define K_INT_MAP_DINT	7		/* debug interrupt */
    221 
    222 /*
    223  * LDT Interrupt Set Register (table 4-5)
    224  */
    225 
    226 #define S_INT_LDT_INTMSG	      0
    227 #define M_INT_LDT_INTMSG              _SB_MAKEMASK(3,S_INT_LDT_INTMSG)
    228 #define V_INT_LDT_INTMSG(x)           _SB_MAKEVALUE(x,S_INT_LDT_INTMSG)
    229 #define G_INT_LDT_INTMSG(x)           _SB_GETVALUE(x,S_INT_LDT_INTMSG,M_INT_LDT_INTMSG)
    230 
    231 #define K_INT_LDT_INTMSG_FIXED	      0
    232 #define K_INT_LDT_INTMSG_ARBITRATED   1
    233 #define K_INT_LDT_INTMSG_SMI	      2
    234 #define K_INT_LDT_INTMSG_NMI	      3
    235 #define K_INT_LDT_INTMSG_INIT	      4
    236 #define K_INT_LDT_INTMSG_STARTUP      5
    237 #define K_INT_LDT_INTMSG_EXTINT	      6
    238 #define K_INT_LDT_INTMSG_RESERVED     7
    239 
    240 #define M_INT_LDT_EDGETRIGGER         0
    241 #define M_INT_LDT_LEVELTRIGGER        _SB_MAKEMASK1(3)
    242 
    243 #define M_INT_LDT_PHYSICALDEST        0
    244 #define M_INT_LDT_LOGICALDEST         _SB_MAKEMASK1(4)
    245 
    246 #define S_INT_LDT_INTDEST             5
    247 #define M_INT_LDT_INTDEST             _SB_MAKEMASK(10,S_INT_LDT_INTDEST)
    248 #define V_INT_LDT_INTDEST(x)          _SB_MAKEVALUE(x,S_INT_LDT_INTDEST)
    249 #define G_INT_LDT_INTDEST(x)          _SB_GETVALUE(x,S_INT_LDT_INTDEST,M_INT_LDT_INTDEST)
    250 
    251 #define S_INT_LDT_VECTOR              13
    252 #define M_INT_LDT_VECTOR              _SB_MAKEMASK(8,S_INT_LDT_VECTOR)
    253 #define V_INT_LDT_VECTOR(x)           _SB_MAKEVALUE(x,S_INT_LDT_VECTOR)
    254 #define G_INT_LDT_VECTOR(x)           _SB_GETVALUE(x,S_INT_LDT_VECTOR,M_INT_LDT_VECTOR)
    255 
    256 /*
    257  * Vector format (Table 4-6)
    258  */
    259 
    260 #define M_LDTVECT_RAISEINT		0x00
    261 #define M_LDTVECT_RAISEMBOX             0x40
    262 
    263 
    264 #endif
    265