sb1250_mac.h revision 1.5
1 /* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * MAC constants and macros File: sb1250_mac.h 5 * 6 * This module contains constants and macros for the SB1250's 7 * ethernet controllers. 8 * 9 * SB1250 specification level: User's manual 1/02/02 10 * 11 * Author: Mitch Lichtenberg 12 * 13 ********************************************************************* 14 * 15 * Copyright 2000,2001,2002,2003 16 * Broadcom Corporation. All rights reserved. 17 * 18 * This software is furnished under license and may be used and 19 * copied only in accordance with the following terms and 20 * conditions. Subject to these conditions, you may download, 21 * copy, install, use, modify and distribute modified or unmodified 22 * copies of this software in source and/or binary form. No title 23 * or ownership is transferred hereby. 24 * 25 * 1) Any source code used, modified or distributed must reproduce 26 * and retain this copyright notice and list of conditions 27 * as they appear in the source file. 28 * 29 * 2) No right is granted to use any trade name, trademark, or 30 * logo of Broadcom Corporation. The "Broadcom Corporation" 31 * name may not be used to endorse or promote products derived 32 * from this software without the prior written permission of 33 * Broadcom Corporation. 34 * 35 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 36 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 37 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 38 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 39 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 40 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 41 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 42 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 43 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 44 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 45 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 46 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 47 * THE POSSIBILITY OF SUCH DAMAGE. 48 ********************************************************************* */ 49 50 51 #ifndef _SB1250_MAC_H 52 #define _SB1250_MAC_H 53 54 #include "sb1250_defs.h" 55 56 /* ********************************************************************* 57 * Ethernet MAC Registers 58 ********************************************************************* */ 59 60 /* 61 * MAC Configuration Register (Table 9-13) 62 * Register: MAC_CFG_0 63 * Register: MAC_CFG_1 64 * Register: MAC_CFG_2 65 */ 66 67 68 #define M_MAC_RESERVED0 _SB_MAKEMASK1(0) 69 #define M_MAC_TX_HOLD_SOP_EN _SB_MAKEMASK1(1) 70 #define M_MAC_RETRY_EN _SB_MAKEMASK1(2) 71 #define M_MAC_RET_DRPREQ_EN _SB_MAKEMASK1(3) 72 #define M_MAC_RET_UFL_EN _SB_MAKEMASK1(4) 73 #define M_MAC_BURST_EN _SB_MAKEMASK1(5) 74 75 #define S_MAC_TX_PAUSE _SB_MAKE64(6) 76 #define M_MAC_TX_PAUSE_CNT _SB_MAKEMASK(3,S_MAC_TX_PAUSE) 77 #define V_MAC_TX_PAUSE_CNT(x) _SB_MAKEVALUE(x,S_MAC_TX_PAUSE) 78 79 #define K_MAC_TX_PAUSE_CNT_512 0 80 #define K_MAC_TX_PAUSE_CNT_1K 1 81 #define K_MAC_TX_PAUSE_CNT_2K 2 82 #define K_MAC_TX_PAUSE_CNT_4K 3 83 #define K_MAC_TX_PAUSE_CNT_8K 4 84 #define K_MAC_TX_PAUSE_CNT_16K 5 85 #define K_MAC_TX_PAUSE_CNT_32K 6 86 #define K_MAC_TX_PAUSE_CNT_64K 7 87 88 #define V_MAC_TX_PAUSE_CNT_512 V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_512) 89 #define V_MAC_TX_PAUSE_CNT_1K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_1K) 90 #define V_MAC_TX_PAUSE_CNT_2K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_2K) 91 #define V_MAC_TX_PAUSE_CNT_4K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_4K) 92 #define V_MAC_TX_PAUSE_CNT_8K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_8K) 93 #define V_MAC_TX_PAUSE_CNT_16K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_16K) 94 #define V_MAC_TX_PAUSE_CNT_32K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K) 95 #define V_MAC_TX_PAUSE_CNT_64K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K) 96 97 #define M_MAC_RESERVED1 _SB_MAKEMASK(8,9) 98 99 #define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17) 100 101 #if SIBYTE_HDR_FEATURE_CHIP(1280) 102 #define M_MAC_TIMESTAMP _SB_MAKEMASK1(18) 103 #endif 104 #define M_MAC_DRP_ERRPKT_EN _SB_MAKEMASK1(19) 105 #define M_MAC_DRP_FCSERRPKT_EN _SB_MAKEMASK1(20) 106 #define M_MAC_DRP_CODEERRPKT_EN _SB_MAKEMASK1(21) 107 #define M_MAC_DRP_DRBLERRPKT_EN _SB_MAKEMASK1(22) 108 #define M_MAC_DRP_RNTPKT_EN _SB_MAKEMASK1(23) 109 #define M_MAC_DRP_OSZPKT_EN _SB_MAKEMASK1(24) 110 #define M_MAC_DRP_LENERRPKT_EN _SB_MAKEMASK1(25) 111 112 #define M_MAC_RESERVED3 _SB_MAKEMASK(6,26) 113 114 #define M_MAC_BYPASS_SEL _SB_MAKEMASK1(32) 115 #define M_MAC_HDX_EN _SB_MAKEMASK1(33) 116 117 #define S_MAC_SPEED_SEL _SB_MAKE64(34) 118 #define M_MAC_SPEED_SEL _SB_MAKEMASK(2,S_MAC_SPEED_SEL) 119 #define V_MAC_SPEED_SEL(x) _SB_MAKEVALUE(x,S_MAC_SPEED_SEL) 120 #define G_MAC_SPEED_SEL(x) _SB_GETVALUE(x,S_MAC_SPEED_SEL,M_MAC_SPEED_SEL) 121 122 #define K_MAC_SPEED_SEL_10MBPS 0 123 #define K_MAC_SPEED_SEL_100MBPS 1 124 #define K_MAC_SPEED_SEL_1000MBPS 2 125 #define K_MAC_SPEED_SEL_RESERVED 3 126 127 #define V_MAC_SPEED_SEL_10MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_10MBPS) 128 #define V_MAC_SPEED_SEL_100MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_100MBPS) 129 #define V_MAC_SPEED_SEL_1000MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_1000MBPS) 130 #define V_MAC_SPEED_SEL_RESERVED V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_RESERVED) 131 132 #define M_MAC_TX_CLK_EDGE_SEL _SB_MAKEMASK1(36) 133 #define M_MAC_LOOPBACK_SEL _SB_MAKEMASK1(37) 134 #define M_MAC_FAST_SYNC _SB_MAKEMASK1(38) 135 #define M_MAC_SS_EN _SB_MAKEMASK1(39) 136 137 #define S_MAC_BYPASS_CFG _SB_MAKE64(40) 138 #define M_MAC_BYPASS_CFG _SB_MAKEMASK(2,S_MAC_BYPASS_CFG) 139 #define V_MAC_BYPASS_CFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_CFG) 140 #define G_MAC_BYPASS_CFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_CFG,M_MAC_BYPASS_CFG) 141 142 #define K_MAC_BYPASS_GMII 0 143 #define K_MAC_BYPASS_ENCODED 1 144 #define K_MAC_BYPASS_SOP 2 145 #define K_MAC_BYPASS_EOP 3 146 147 #define M_MAC_BYPASS_16 _SB_MAKEMASK1(42) 148 #define M_MAC_BYPASS_FCS_CHK _SB_MAKEMASK1(43) 149 150 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 151 #define M_MAC_RX_CH_SEL_MSB _SB_MAKEMASK1(44) 152 #endif /* 1250 PASS2 || 112x PASS1 */ 153 154 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1280) 155 #define M_MAC_SPLIT_CH_SEL _SB_MAKEMASK1(45) 156 #endif /* 1250 PASS3 || 112x PASS1 || 1280 */ 157 158 #define S_MAC_BYPASS_IFG _SB_MAKE64(46) 159 #define M_MAC_BYPASS_IFG _SB_MAKEMASK(8,S_MAC_BYPASS_IFG) 160 #define V_MAC_BYPASS_IFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_IFG) 161 #define G_MAC_BYPASS_IFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_IFG,M_MAC_BYPASS_IFG) 162 163 #define K_MAC_FC_CMD_DISABLED 0 164 #define K_MAC_FC_CMD_ENABLED 1 165 #define K_MAC_FC_CMD_ENAB_FALSECARR 2 166 167 #define V_MAC_FC_CMD_DISABLED V_MAC_FC_CMD(K_MAC_FC_CMD_DISABLED) 168 #define V_MAC_FC_CMD_ENABLED V_MAC_FC_CMD(K_MAC_FC_CMD_ENABLED) 169 #define V_MAC_FC_CMD_ENAB_FALSECARR V_MAC_FC_CMD(K_MAC_FC_CMD_ENAB_FALSECARR) 170 171 #define M_MAC_FC_SEL _SB_MAKEMASK1(54) 172 173 #define S_MAC_FC_CMD _SB_MAKE64(55) 174 #define M_MAC_FC_CMD _SB_MAKEMASK(2,S_MAC_FC_CMD) 175 #define V_MAC_FC_CMD(x) _SB_MAKEVALUE(x,S_MAC_FC_CMD) 176 #define G_MAC_FC_CMD(x) _SB_GETVALUE(x,S_MAC_FC_CMD,M_MAC_FC_CMD) 177 178 #define S_MAC_RX_CH_SEL _SB_MAKE64(57) 179 #define M_MAC_RX_CH_SEL _SB_MAKEMASK(7,S_MAC_RX_CH_SEL) 180 #define V_MAC_RX_CH_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_SEL) 181 #define G_MAC_RX_CH_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_SEL,M_MAC_RX_CH_SEL) 182 183 184 /* 185 * MAC Enable Registers 186 * Register: MAC_ENABLE_0 187 * Register: MAC_ENABLE_1 188 * Register: MAC_ENABLE_2 189 */ 190 191 #define M_MAC_RXDMA_EN0 _SB_MAKEMASK1(0) 192 #define M_MAC_RXDMA_EN1 _SB_MAKEMASK1(1) 193 #define M_MAC_TXDMA_EN0 _SB_MAKEMASK1(4) 194 #define M_MAC_TXDMA_EN1 _SB_MAKEMASK1(5) 195 196 #define M_MAC_PORT_RESET _SB_MAKEMASK1(8) 197 198 #if (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x)) 199 #define M_MAC_RX_ENABLE _SB_MAKEMASK1(10) 200 #define M_MAC_TX_ENABLE _SB_MAKEMASK1(11) 201 #define M_MAC_BYP_RX_ENABLE _SB_MAKEMASK1(12) 202 #define M_MAC_BYP_TX_ENABLE _SB_MAKEMASK1(13) 203 #endif 204 205 /* 206 * MAC reset information register (1280/1255) 207 */ 208 #if SIBYTE_HDR_FEATURE_CHIP(1280) 209 #define M_MAC_RX_CH0_PAUSE_ON _SB_MAKEMASK1(8) 210 #define M_MAC_RX_CH1_PAUSE_ON _SB_MAKEMASK1(16) 211 #define M_MAC_TX_CH0_PAUSE_ON _SB_MAKEMASK1(24) 212 #define M_MAC_TX_CH1_PAUSE_ON _SB_MAKEMASK1(32) 213 #endif 214 215 /* 216 * MAC DMA Control Register 217 * Register: MAC_TXD_CTL_0 218 * Register: MAC_TXD_CTL_1 219 * Register: MAC_TXD_CTL_2 220 */ 221 222 #define S_MAC_TXD_WEIGHT0 _SB_MAKE64(0) 223 #define M_MAC_TXD_WEIGHT0 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT0) 224 #define V_MAC_TXD_WEIGHT0(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT0) 225 #define G_MAC_TXD_WEIGHT0(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT0,M_MAC_TXD_WEIGHT0) 226 227 #define S_MAC_TXD_WEIGHT1 _SB_MAKE64(4) 228 #define M_MAC_TXD_WEIGHT1 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT1) 229 #define V_MAC_TXD_WEIGHT1(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT1) 230 #define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT1,M_MAC_TXD_WEIGHT1) 231 232 /* 233 * MAC Fifo Threshhold registers (Table 9-14) 234 * Register: MAC_THRSH_CFG_0 235 * Register: MAC_THRSH_CFG_1 236 * Register: MAC_THRSH_CFG_2 237 */ 238 239 #define S_MAC_TX_WR_THRSH _SB_MAKE64(0) 240 #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) 241 /* XXX: Can't enable, as it has the same name as a pass2+ define below. */ 242 /* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6,S_MAC_TX_WR_THRSH) */ 243 #endif /* up to 1250 PASS1 */ 244 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 245 #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7,S_MAC_TX_WR_THRSH) 246 #endif /* 1250 PASS2 || 112x PASS1 */ 247 #define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_WR_THRSH) 248 #define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_WR_THRSH,M_MAC_TX_WR_THRSH) 249 250 #define S_MAC_TX_RD_THRSH _SB_MAKE64(8) 251 #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) 252 /* XXX: Can't enable, as it has the same name as a pass2+ define below. */ 253 /* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6,S_MAC_TX_RD_THRSH) */ 254 #endif /* up to 1250 PASS1 */ 255 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 256 #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7,S_MAC_TX_RD_THRSH) 257 #endif /* 1250 PASS2 || 112x PASS1 */ 258 #define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RD_THRSH) 259 #define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RD_THRSH,M_MAC_TX_RD_THRSH) 260 261 #define S_MAC_TX_RL_THRSH _SB_MAKE64(16) 262 #define M_MAC_TX_RL_THRSH _SB_MAKEMASK(4,S_MAC_TX_RL_THRSH) 263 #define V_MAC_TX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RL_THRSH) 264 #define G_MAC_TX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RL_THRSH,M_MAC_TX_RL_THRSH) 265 266 #define S_MAC_RX_PL_THRSH _SB_MAKE64(24) 267 #define M_MAC_RX_PL_THRSH _SB_MAKEMASK(6,S_MAC_RX_PL_THRSH) 268 #define V_MAC_RX_PL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_PL_THRSH) 269 #define G_MAC_RX_PL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_PL_THRSH,M_MAC_RX_PL_THRSH) 270 271 #define S_MAC_RX_RD_THRSH _SB_MAKE64(32) 272 #define M_MAC_RX_RD_THRSH _SB_MAKEMASK(6,S_MAC_RX_RD_THRSH) 273 #define V_MAC_RX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RD_THRSH) 274 #define G_MAC_RX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RD_THRSH,M_MAC_RX_RD_THRSH) 275 276 #define S_MAC_RX_RL_THRSH _SB_MAKE64(40) 277 #define M_MAC_RX_RL_THRSH _SB_MAKEMASK(6,S_MAC_RX_RL_THRSH) 278 #define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RL_THRSH) 279 #define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RL_THRSH,M_MAC_RX_RL_THRSH) 280 281 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 282 #define S_MAC_ENC_FC_THRSH _SB_MAKE64(56) 283 #define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6,S_MAC_ENC_FC_THRSH) 284 #define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x,S_MAC_ENC_FC_THRSH) 285 #define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x,S_MAC_ENC_FC_THRSH,M_MAC_ENC_FC_THRSH) 286 #endif /* 1250 PASS2 || 112x PASS1 */ 287 288 /* 289 * MAC Frame Configuration Registers (Table 9-15) 290 * Register: MAC_FRAME_CFG_0 291 * Register: MAC_FRAME_CFG_1 292 * Register: MAC_FRAME_CFG_2 293 */ 294 295 /* XXXCGD: ??? Unused in pass2? */ 296 #define S_MAC_IFG_RX _SB_MAKE64(0) 297 #define M_MAC_IFG_RX _SB_MAKEMASK(6,S_MAC_IFG_RX) 298 #define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x,S_MAC_IFG_RX) 299 #define G_MAC_IFG_RX(x) _SB_GETVALUE(x,S_MAC_IFG_RX,M_MAC_IFG_RX) 300 301 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1280) 302 #define S_MAC_PRE_LEN _SB_MAKE64(0) 303 #define M_MAC_PRE_LEN _SB_MAKEMASK(6,S_MAC_PRE_LEN) 304 #define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x,S_MAC_PRE_LEN) 305 #define G_MAC_PRE_LEN(x) _SB_GETVALUE(x,S_MAC_PRE_LEN,M_MAC_PRE_LEN) 306 #endif /* 1250 PASS3 || 112x PASS1 || 1280 */ 307 308 #define S_MAC_IFG_TX _SB_MAKE64(6) 309 #define M_MAC_IFG_TX _SB_MAKEMASK(6,S_MAC_IFG_TX) 310 #define V_MAC_IFG_TX(x) _SB_MAKEVALUE(x,S_MAC_IFG_TX) 311 #define G_MAC_IFG_TX(x) _SB_GETVALUE(x,S_MAC_IFG_TX,M_MAC_IFG_TX) 312 313 #define S_MAC_IFG_THRSH _SB_MAKE64(12) 314 #define M_MAC_IFG_THRSH _SB_MAKEMASK(6,S_MAC_IFG_THRSH) 315 #define V_MAC_IFG_THRSH(x) _SB_MAKEVALUE(x,S_MAC_IFG_THRSH) 316 #define G_MAC_IFG_THRSH(x) _SB_GETVALUE(x,S_MAC_IFG_THRSH,M_MAC_IFG_THRSH) 317 318 #define S_MAC_BACKOFF_SEL _SB_MAKE64(18) 319 #define M_MAC_BACKOFF_SEL _SB_MAKEMASK(4,S_MAC_BACKOFF_SEL) 320 #define V_MAC_BACKOFF_SEL(x) _SB_MAKEVALUE(x,S_MAC_BACKOFF_SEL) 321 #define G_MAC_BACKOFF_SEL(x) _SB_GETVALUE(x,S_MAC_BACKOFF_SEL,M_MAC_BACKOFF_SEL) 322 323 #define S_MAC_LFSR_SEED _SB_MAKE64(22) 324 #define M_MAC_LFSR_SEED _SB_MAKEMASK(8,S_MAC_LFSR_SEED) 325 #define V_MAC_LFSR_SEED(x) _SB_MAKEVALUE(x,S_MAC_LFSR_SEED) 326 #define G_MAC_LFSR_SEED(x) _SB_GETVALUE(x,S_MAC_LFSR_SEED,M_MAC_LFSR_SEED) 327 328 #define S_MAC_SLOT_SIZE _SB_MAKE64(30) 329 #define M_MAC_SLOT_SIZE _SB_MAKEMASK(10,S_MAC_SLOT_SIZE) 330 #define V_MAC_SLOT_SIZE(x) _SB_MAKEVALUE(x,S_MAC_SLOT_SIZE) 331 #define G_MAC_SLOT_SIZE(x) _SB_GETVALUE(x,S_MAC_SLOT_SIZE,M_MAC_SLOT_SIZE) 332 333 #define S_MAC_MIN_FRAMESZ _SB_MAKE64(40) 334 #define M_MAC_MIN_FRAMESZ _SB_MAKEMASK(8,S_MAC_MIN_FRAMESZ) 335 #define V_MAC_MIN_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MIN_FRAMESZ) 336 #define G_MAC_MIN_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MIN_FRAMESZ,M_MAC_MIN_FRAMESZ) 337 338 #define S_MAC_MAX_FRAMESZ _SB_MAKE64(48) 339 #define M_MAC_MAX_FRAMESZ _SB_MAKEMASK(16,S_MAC_MAX_FRAMESZ) 340 #define V_MAC_MAX_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MAX_FRAMESZ) 341 #define G_MAC_MAX_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MAX_FRAMESZ,M_MAC_MAX_FRAMESZ) 342 343 /* 344 * These constants are used to configure the fields within the Frame 345 * Configuration Register. 346 */ 347 348 #define K_MAC_IFG_RX_10 _SB_MAKE64(0) /* See table 176, not used */ 349 #define K_MAC_IFG_RX_100 _SB_MAKE64(0) 350 #define K_MAC_IFG_RX_1000 _SB_MAKE64(0) 351 352 #define K_MAC_IFG_TX_10 _SB_MAKE64(20) 353 #define K_MAC_IFG_TX_100 _SB_MAKE64(20) 354 #define K_MAC_IFG_TX_1000 _SB_MAKE64(8) 355 356 #define K_MAC_IFG_THRSH_10 _SB_MAKE64(4) 357 #define K_MAC_IFG_THRSH_100 _SB_MAKE64(4) 358 #define K_MAC_IFG_THRSH_1000 _SB_MAKE64(0) 359 360 #define K_MAC_SLOT_SIZE_10 _SB_MAKE64(0) 361 #define K_MAC_SLOT_SIZE_100 _SB_MAKE64(0) 362 #define K_MAC_SLOT_SIZE_1000 _SB_MAKE64(0) 363 364 #define V_MAC_IFG_RX_10 V_MAC_IFG_RX(K_MAC_IFG_RX_10) 365 #define V_MAC_IFG_RX_100 V_MAC_IFG_RX(K_MAC_IFG_RX_100) 366 #define V_MAC_IFG_RX_1000 V_MAC_IFG_RX(K_MAC_IFG_RX_1000) 367 368 #define V_MAC_IFG_TX_10 V_MAC_IFG_TX(K_MAC_IFG_TX_10) 369 #define V_MAC_IFG_TX_100 V_MAC_IFG_TX(K_MAC_IFG_TX_100) 370 #define V_MAC_IFG_TX_1000 V_MAC_IFG_TX(K_MAC_IFG_TX_1000) 371 372 #define V_MAC_IFG_THRSH_10 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_10) 373 #define V_MAC_IFG_THRSH_100 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_100) 374 #define V_MAC_IFG_THRSH_1000 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_1000) 375 376 #define V_MAC_SLOT_SIZE_10 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_10) 377 #define V_MAC_SLOT_SIZE_100 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_100) 378 #define V_MAC_SLOT_SIZE_1000 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_1000) 379 380 #define K_MAC_MIN_FRAMESZ_FIFO _SB_MAKE64(9) 381 #define K_MAC_MIN_FRAMESZ_DEFAULT _SB_MAKE64(64) 382 #define K_MAC_MAX_FRAMESZ_DEFAULT _SB_MAKE64(1518) 383 #define K_MAC_MAX_FRAMESZ_JUMBO _SB_MAKE64(9216) 384 385 #define V_MAC_MIN_FRAMESZ_FIFO V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_FIFO) 386 #define V_MAC_MIN_FRAMESZ_DEFAULT V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_DEFAULT) 387 #define V_MAC_MAX_FRAMESZ_DEFAULT V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_DEFAULT) 388 #define V_MAC_MAX_FRAMESZ_JUMBO V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_JUMBO) 389 390 /* 391 * MAC VLAN Tag Registers (Table 9-16) 392 * Register: MAC_VLANTAG_0 393 * Register: MAC_VLANTAG_1 394 * Register: MAC_VLANTAG_2 395 */ 396 397 #define S_MAC_VLAN_TAG _SB_MAKE64(0) 398 #define M_MAC_VLAN_TAG _SB_MAKEMASK(32,S_MAC_VLAN_TAG) 399 #define V_MAC_VLAN_TAG(x) _SB_MAKEVALUE(x,S_MAC_VLAN_TAG) 400 #define G_MAC_VLAN_TAG(x) _SB_GETVALUE(x,S_MAC_VLAN_TAG,M_MAC_VLAN_TAG) 401 402 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 403 #define S_MAC_TX_PKT_OFFSET _SB_MAKE64(32) 404 #define M_MAC_TX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_TX_PKT_OFFSET) 405 #define V_MAC_TX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_PKT_OFFSET) 406 #define G_MAC_TX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_PKT_OFFSET,M_MAC_TX_PKT_OFFSET) 407 408 #define S_MAC_TX_CRC_OFFSET _SB_MAKE64(40) 409 #define M_MAC_TX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_TX_CRC_OFFSET) 410 #define V_MAC_TX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_CRC_OFFSET) 411 #define G_MAC_TX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_CRC_OFFSET,M_MAC_TX_CRC_OFFSET) 412 413 #define M_MAC_CH_BASE_FC_EN _SB_MAKEMASK1(48) 414 #endif /* 1250 PASS3 || 112x PASS1 */ 415 416 /* 417 * MAC Status Registers (Table 9-17) 418 * Also used for the MAC Interrupt Mask Register (Table 9-18) 419 * Register: MAC_STATUS_0 420 * Register: MAC_STATUS_1 421 * Register: MAC_STATUS_2 422 * Register: MAC_INT_MASK_0 423 * Register: MAC_INT_MASK_1 424 * Register: MAC_INT_MASK_2 425 */ 426 427 /* 428 * Use these constants to shift the appropriate channel 429 * into the CH0 position so the same tests can be used 430 * on each channel. 431 */ 432 433 #define S_MAC_RX_CH0 _SB_MAKE64(0) 434 #define S_MAC_RX_CH1 _SB_MAKE64(8) 435 #define S_MAC_TX_CH0 _SB_MAKE64(16) 436 #define S_MAC_TX_CH1 _SB_MAKE64(24) 437 438 #define S_MAC_TXCHANNELS _SB_MAKE64(16) /* this is 1st TX chan */ 439 #define S_MAC_CHANWIDTH _SB_MAKE64(8) /* bits between channels */ 440 441 /* 442 * These are the same as RX channel 0. The idea here 443 * is that you'll use one of the "S_" things above 444 * and pass just the six bits to a DMA-channel-specific ISR 445 */ 446 #define M_MAC_INT_CHANNEL _SB_MAKEMASK(8,0) 447 #define M_MAC_INT_EOP_COUNT _SB_MAKEMASK1(0) 448 #define M_MAC_INT_EOP_TIMER _SB_MAKEMASK1(1) 449 #define M_MAC_INT_EOP_SEEN _SB_MAKEMASK1(2) 450 #define M_MAC_INT_HWM _SB_MAKEMASK1(3) 451 #define M_MAC_INT_LWM _SB_MAKEMASK1(4) 452 #define M_MAC_INT_DSCR _SB_MAKEMASK1(5) 453 #define M_MAC_INT_ERR _SB_MAKEMASK1(6) 454 #define M_MAC_INT_DZERO _SB_MAKEMASK1(7) /* only for TX channels */ 455 #define M_MAC_INT_DROP _SB_MAKEMASK1(7) /* only for RX channels */ 456 457 /* 458 * In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see 459 * also DMA_TX/DMA_RX in sb_regs.h). 460 */ 461 #define S_MAC_STATUS_CH_OFFSET(ch,txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH) 462 463 #define M_MAC_STATUS_CHANNEL(ch,txrx) _SB_MAKEVALUE(_SB_MAKEMASK(8,0),S_MAC_STATUS_CH_OFFSET(ch,txrx)) 464 #define M_MAC_STATUS_EOP_COUNT(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 465 #define M_MAC_STATUS_EOP_TIMER(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 466 #define M_MAC_STATUS_EOP_SEEN(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 467 #define M_MAC_STATUS_HWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_HWM,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 468 #define M_MAC_STATUS_LWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_LWM,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 469 #define M_MAC_STATUS_DSCR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DSCR,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 470 #define M_MAC_STATUS_ERR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_ERR,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 471 #define M_MAC_STATUS_DZERO(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DZERO,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 472 #define M_MAC_STATUS_DROP(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DROP,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 473 #define M_MAC_STATUS_OTHER_ERR _SB_MAKEVALUE(_SB_MAKEMASK(7,0),40) 474 475 476 #define M_MAC_RX_UNDRFL _SB_MAKEMASK1(40) 477 #define M_MAC_RX_OVRFL _SB_MAKEMASK1(41) 478 #define M_MAC_TX_UNDRFL _SB_MAKEMASK1(42) 479 #define M_MAC_TX_OVRFL _SB_MAKEMASK1(43) 480 #define M_MAC_LTCOL_ERR _SB_MAKEMASK1(44) 481 #define M_MAC_EXCOL_ERR _SB_MAKEMASK1(45) 482 #define M_MAC_CNTR_OVRFL_ERR _SB_MAKEMASK1(46) 483 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 484 #define M_MAC_SPLIT_EN _SB_MAKEMASK1(47) /* interrupt mask only */ 485 #endif /* 1250 PASS2 || 112x PASS1 */ 486 487 #define S_MAC_COUNTER_ADDR _SB_MAKE64(47) 488 #define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5,S_MAC_COUNTER_ADDR) 489 #define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x,S_MAC_COUNTER_ADDR) 490 #define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x,S_MAC_COUNTER_ADDR,M_MAC_COUNTER_ADDR) 491 492 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1280) 493 #define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52) 494 #endif /* 1250 PASS3 || 112x PASS1 || 1280 */ 495 496 /* 497 * MAC Fifo Pointer Registers (Table 9-19) [Debug register] 498 * Register: MAC_FIFO_PTRS_0 499 * Register: MAC_FIFO_PTRS_1 500 * Register: MAC_FIFO_PTRS_2 501 */ 502 503 #define S_MAC_TX_WRPTR _SB_MAKE64(0) 504 #define M_MAC_TX_WRPTR _SB_MAKEMASK(6,S_MAC_TX_WRPTR) 505 #define V_MAC_TX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_WRPTR) 506 #define G_MAC_TX_WRPTR(x) _SB_GETVALUE(x,S_MAC_TX_WRPTR,M_MAC_TX_WRPTR) 507 508 #define S_MAC_TX_RDPTR _SB_MAKE64(8) 509 #define M_MAC_TX_RDPTR _SB_MAKEMASK(6,S_MAC_TX_RDPTR) 510 #define V_MAC_TX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_RDPTR) 511 #define G_MAC_TX_RDPTR(x) _SB_GETVALUE(x,S_MAC_TX_RDPTR,M_MAC_TX_RDPTR) 512 513 #define S_MAC_RX_WRPTR _SB_MAKE64(16) 514 #define M_MAC_RX_WRPTR _SB_MAKEMASK(6,S_MAC_RX_WRPTR) 515 #define V_MAC_RX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_WRPTR) 516 #define G_MAC_RX_WRPTR(x) _SB_GETVALUE(x,S_MAC_RX_WRPTR,M_MAC_TX_WRPTR) 517 518 #define S_MAC_RX_RDPTR _SB_MAKE64(24) 519 #define M_MAC_RX_RDPTR _SB_MAKEMASK(6,S_MAC_RX_RDPTR) 520 #define V_MAC_RX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_RDPTR) 521 #define G_MAC_RX_RDPTR(x) _SB_GETVALUE(x,S_MAC_RX_RDPTR,M_MAC_TX_RDPTR) 522 523 /* 524 * MAC Fifo End Of Packet Count Registers (Table 9-20) [Debug register] 525 * Register: MAC_EOPCNT_0 526 * Register: MAC_EOPCNT_1 527 * Register: MAC_EOPCNT_2 528 */ 529 530 #define S_MAC_TX_EOP_COUNTER _SB_MAKE64(0) 531 #define M_MAC_TX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_TX_EOP_COUNTER) 532 #define V_MAC_TX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_TX_EOP_COUNTER) 533 #define G_MAC_TX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_TX_EOP_COUNTER,M_MAC_TX_EOP_COUNTER) 534 535 #define S_MAC_RX_EOP_COUNTER _SB_MAKE64(8) 536 #define M_MAC_RX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_RX_EOP_COUNTER) 537 #define V_MAC_RX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_RX_EOP_COUNTER) 538 #define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_RX_EOP_COUNTER,M_MAC_RX_EOP_COUNTER) 539 540 /* 541 * MAC Recieve Address Filter Exact Match Registers (Table 9-21) 542 * Registers: MAC_ADDR0_0 through MAC_ADDR7_0 543 * Registers: MAC_ADDR0_1 through MAC_ADDR7_1 544 * Registers: MAC_ADDR0_2 through MAC_ADDR7_2 545 */ 546 547 /* No bitfields */ 548 549 /* 550 * MAC Receive Address Filter Mask Registers 551 * Registers: MAC_ADDRMASK0_0 and MAC_ADDRMASK0_1 552 * Registers: MAC_ADDRMASK1_0 and MAC_ADDRMASK1_1 553 * Registers: MAC_ADDRMASK2_0 and MAC_ADDRMASK2_1 554 */ 555 556 /* No bitfields */ 557 558 /* 559 * MAC Recieve Address Filter Hash Match Registers (Table 9-22) 560 * Registers: MAC_HASH0_0 through MAC_HASH7_0 561 * Registers: MAC_HASH0_1 through MAC_HASH7_1 562 * Registers: MAC_HASH0_2 through MAC_HASH7_2 563 */ 564 565 /* No bitfields */ 566 567 /* 568 * MAC Transmit Source Address Registers (Table 9-23) 569 * Register: MAC_ETHERNET_ADDR_0 570 * Register: MAC_ETHERNET_ADDR_1 571 * Register: MAC_ETHERNET_ADDR_2 572 */ 573 574 /* No bitfields */ 575 576 /* 577 * MAC Packet Type Configuration Register 578 * Register: MAC_TYPE_CFG_0 579 * Register: MAC_TYPE_CFG_1 580 * Register: MAC_TYPE_CFG_2 581 */ 582 583 #define S_TYPECFG_TYPESIZE _SB_MAKE64(16) 584 585 #define S_TYPECFG_TYPE0 _SB_MAKE64(0) 586 #define M_TYPECFG_TYPE0 _SB_MAKEMASK(16,S_TYPECFG_TYPE0) 587 #define V_TYPECFG_TYPE0(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE0) 588 #define G_TYPECFG_TYPE0(x) _SB_GETVALUE(x,S_TYPECFG_TYPE0,M_TYPECFG_TYPE0) 589 590 #define S_TYPECFG_TYPE1 _SB_MAKE64(0) 591 #define M_TYPECFG_TYPE1 _SB_MAKEMASK(16,S_TYPECFG_TYPE1) 592 #define V_TYPECFG_TYPE1(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE1) 593 #define G_TYPECFG_TYPE1(x) _SB_GETVALUE(x,S_TYPECFG_TYPE1,M_TYPECFG_TYPE1) 594 595 #define S_TYPECFG_TYPE2 _SB_MAKE64(0) 596 #define M_TYPECFG_TYPE2 _SB_MAKEMASK(16,S_TYPECFG_TYPE2) 597 #define V_TYPECFG_TYPE2(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE2) 598 #define G_TYPECFG_TYPE2(x) _SB_GETVALUE(x,S_TYPECFG_TYPE2,M_TYPECFG_TYPE2) 599 600 #define S_TYPECFG_TYPE3 _SB_MAKE64(0) 601 #define M_TYPECFG_TYPE3 _SB_MAKEMASK(16,S_TYPECFG_TYPE3) 602 #define V_TYPECFG_TYPE3(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE3) 603 #define G_TYPECFG_TYPE3(x) _SB_GETVALUE(x,S_TYPECFG_TYPE3,M_TYPECFG_TYPE3) 604 605 /* 606 * MAC Receive Address Filter Control Registers (Table 9-24) 607 * Register: MAC_ADFILTER_CFG_0 608 * Register: MAC_ADFILTER_CFG_1 609 * Register: MAC_ADFILTER_CFG_2 610 */ 611 612 #define M_MAC_ALLPKT_EN _SB_MAKEMASK1(0) 613 #define M_MAC_UCAST_EN _SB_MAKEMASK1(1) 614 #define M_MAC_UCAST_INV _SB_MAKEMASK1(2) 615 #define M_MAC_MCAST_EN _SB_MAKEMASK1(3) 616 #define M_MAC_MCAST_INV _SB_MAKEMASK1(4) 617 #define M_MAC_BCAST_EN _SB_MAKEMASK1(5) 618 #define M_MAC_DIRECT_INV _SB_MAKEMASK1(6) 619 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 620 #define M_MAC_ALLMCAST_EN _SB_MAKEMASK1(7) 621 #endif /* 1250 PASS2 || 112x PASS1 */ 622 623 #define S_MAC_IPHDR_OFFSET _SB_MAKE64(8) 624 #define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8,S_MAC_IPHDR_OFFSET) 625 #define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_IPHDR_OFFSET) 626 #define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x,S_MAC_IPHDR_OFFSET,M_MAC_IPHDR_OFFSET) 627 628 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1280) 629 #define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16) 630 #define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_RX_CRC_OFFSET) 631 #define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_CRC_OFFSET) 632 #define G_MAC_RX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_CRC_OFFSET,M_MAC_RX_CRC_OFFSET) 633 634 #define S_MAC_RX_PKT_OFFSET _SB_MAKE64(24) 635 #define M_MAC_RX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_RX_PKT_OFFSET) 636 #define V_MAC_RX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_PKT_OFFSET) 637 #define G_MAC_RX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_PKT_OFFSET,M_MAC_RX_PKT_OFFSET) 638 639 #define M_MAC_FWDPAUSE_EN _SB_MAKEMASK1(32) 640 #define M_MAC_VLAN_DET_EN _SB_MAKEMASK1(33) 641 642 #define S_MAC_RX_CH_MSN_SEL _SB_MAKE64(34) 643 #define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8,S_MAC_RX_CH_MSN_SEL) 644 #define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_MSN_SEL) 645 #define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_MSN_SEL,M_MAC_RX_CH_MSN_SEL) 646 #endif /* 1250 PASS3 || 112x PASS1 || 1280 */ 647 648 /* 649 * MAC Receive Channel Select Registers (Table 9-25) 650 */ 651 652 /* no bitfields */ 653 654 /* 655 * MAC MII Management Interface Registers (Table 9-26) 656 * Register: MAC_MDIO_0 657 * Register: MAC_MDIO_1 658 * Register: MAC_MDIO_2 659 */ 660 661 #define S_MAC_MDC 0 662 #define S_MAC_MDIO_DIR 1 663 #define S_MAC_MDIO_OUT 2 664 #define S_MAC_GENC 3 665 #define S_MAC_MDIO_IN 4 666 667 #define M_MAC_MDC _SB_MAKEMASK1(S_MAC_MDC) 668 #define M_MAC_MDIO_DIR _SB_MAKEMASK1(S_MAC_MDIO_DIR) 669 #define M_MAC_MDIO_DIR_INPUT _SB_MAKEMASK1(S_MAC_MDIO_DIR) 670 #define M_MAC_MDIO_OUT _SB_MAKEMASK1(S_MAC_MDIO_OUT) 671 #define M_MAC_GENC _SB_MAKEMASK1(S_MAC_GENC) 672 #define M_MAC_MDIO_IN _SB_MAKEMASK1(S_MAC_MDIO_IN) 673 674 #endif 675
Indexes created Wed Oct 01 07:09:59 GMT 2025