sb1250_mc.h revision 1.2.2.2
1 1.2.2.2 nathanw /* ********************************************************************* 2 1.2.2.2 nathanw * SB1250 Board Support Package 3 1.2.2.2 nathanw * 4 1.2.2.2 nathanw * Memory Controller constants File: sb1250_mc.h 5 1.2.2.2 nathanw * 6 1.2.2.2 nathanw * This module contains constants and macros useful for 7 1.2.2.2 nathanw * programming the memory controller. 8 1.2.2.2 nathanw * 9 1.2.2.2 nathanw * SB1250 specification level: User's manual 1/02/02 10 1.2.2.2 nathanw * 11 1.2.2.2 nathanw * Author: Mitch Lichtenberg (mpl (at) broadcom.com) 12 1.2.2.2 nathanw * 13 1.2.2.2 nathanw ********************************************************************* 14 1.2.2.2 nathanw * 15 1.2.2.2 nathanw * Copyright 2000,2001 16 1.2.2.2 nathanw * Broadcom Corporation. All rights reserved. 17 1.2.2.2 nathanw * 18 1.2.2.2 nathanw * This software is furnished under license and may be used and 19 1.2.2.2 nathanw * copied only in accordance with the following terms and 20 1.2.2.2 nathanw * conditions. Subject to these conditions, you may download, 21 1.2.2.2 nathanw * copy, install, use, modify and distribute modified or unmodified 22 1.2.2.2 nathanw * copies of this software in source and/or binary form. No title 23 1.2.2.2 nathanw * or ownership is transferred hereby. 24 1.2.2.2 nathanw * 25 1.2.2.2 nathanw * 1) Any source code used, modified or distributed must reproduce 26 1.2.2.2 nathanw * and retain this copyright notice and list of conditions as 27 1.2.2.2 nathanw * they appear in the source file. 28 1.2.2.2 nathanw * 29 1.2.2.2 nathanw * 2) No right is granted to use any trade name, trademark, or 30 1.2.2.2 nathanw * logo of Broadcom Corporation. Neither the "Broadcom 31 1.2.2.2 nathanw * Corporation" name nor any trademark or logo of Broadcom 32 1.2.2.2 nathanw * Corporation may be used to endorse or promote products 33 1.2.2.2 nathanw * derived from this software without the prior written 34 1.2.2.2 nathanw * permission of Broadcom Corporation. 35 1.2.2.2 nathanw * 36 1.2.2.2 nathanw * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 37 1.2.2.2 nathanw * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 38 1.2.2.2 nathanw * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 39 1.2.2.2 nathanw * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 40 1.2.2.2 nathanw * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 41 1.2.2.2 nathanw * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 42 1.2.2.2 nathanw * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 43 1.2.2.2 nathanw * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 44 1.2.2.2 nathanw * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 45 1.2.2.2 nathanw * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 46 1.2.2.2 nathanw * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 47 1.2.2.2 nathanw * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 48 1.2.2.2 nathanw * THE POSSIBILITY OF SUCH DAMAGE. 49 1.2.2.2 nathanw ********************************************************************* */ 50 1.2.2.2 nathanw 51 1.2.2.2 nathanw 52 1.2.2.2 nathanw #ifndef _SB1250_MC_H 53 1.2.2.2 nathanw #define _SB1250_MC_H 54 1.2.2.2 nathanw 55 1.2.2.2 nathanw #include "sb1250_defs.h" 56 1.2.2.2 nathanw 57 1.2.2.2 nathanw /* 58 1.2.2.2 nathanw * Memory Channel Config Register (table 6-14) 59 1.2.2.2 nathanw */ 60 1.2.2.2 nathanw 61 1.2.2.2 nathanw #define S_MC_RESERVED0 0 62 1.2.2.2 nathanw #define M_MC_RESERVED0 _SB_MAKEMASK(8,S_MC_RESERVED0) 63 1.2.2.2 nathanw 64 1.2.2.2 nathanw #define S_MC_CHANNEL_SEL 8 65 1.2.2.2 nathanw #define M_MC_CHANNEL_SEL _SB_MAKEMASK(8,S_MC_CHANNEL_SEL) 66 1.2.2.2 nathanw #define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x,S_MC_CHANNEL_SEL) 67 1.2.2.2 nathanw #define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x,S_MC_CHANNEL_SEL,M_MC_CHANNEL_SEL) 68 1.2.2.2 nathanw 69 1.2.2.2 nathanw #define S_MC_BANK0_MAP 16 70 1.2.2.2 nathanw #define M_MC_BANK0_MAP _SB_MAKEMASK(4,S_MC_BANK0_MAP) 71 1.2.2.2 nathanw #define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK0_MAP) 72 1.2.2.2 nathanw #define G_MC_BANK0_MAP(x) _SB_GETVALUE(x,S_MC_BANK0_MAP,M_MC_BANK0_MAP) 73 1.2.2.2 nathanw 74 1.2.2.2 nathanw #define K_MC_BANK0_MAP_DEFAULT 0x00 75 1.2.2.2 nathanw #define V_MC_BANK0_MAP_DEFAULT V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT) 76 1.2.2.2 nathanw 77 1.2.2.2 nathanw #define S_MC_BANK1_MAP 20 78 1.2.2.2 nathanw #define M_MC_BANK1_MAP _SB_MAKEMASK(4,S_MC_BANK1_MAP) 79 1.2.2.2 nathanw #define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK1_MAP) 80 1.2.2.2 nathanw #define G_MC_BANK1_MAP(x) _SB_GETVALUE(x,S_MC_BANK1_MAP,M_MC_BANK1_MAP) 81 1.2.2.2 nathanw 82 1.2.2.2 nathanw #define K_MC_BANK1_MAP_DEFAULT 0x08 83 1.2.2.2 nathanw #define V_MC_BANK1_MAP_DEFAULT V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT) 84 1.2.2.2 nathanw 85 1.2.2.2 nathanw #define S_MC_BANK2_MAP 24 86 1.2.2.2 nathanw #define M_MC_BANK2_MAP _SB_MAKEMASK(4,S_MC_BANK2_MAP) 87 1.2.2.2 nathanw #define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK2_MAP) 88 1.2.2.2 nathanw #define G_MC_BANK2_MAP(x) _SB_GETVALUE(x,S_MC_BANK2_MAP,M_MC_BANK2_MAP) 89 1.2.2.2 nathanw 90 1.2.2.2 nathanw #define K_MC_BANK2_MAP_DEFAULT 0x09 91 1.2.2.2 nathanw #define V_MC_BANK2_MAP_DEFAULT V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT) 92 1.2.2.2 nathanw 93 1.2.2.2 nathanw #define S_MC_BANK3_MAP 28 94 1.2.2.2 nathanw #define M_MC_BANK3_MAP _SB_MAKEMASK(4,S_MC_BANK3_MAP) 95 1.2.2.2 nathanw #define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK3_MAP) 96 1.2.2.2 nathanw #define G_MC_BANK3_MAP(x) _SB_GETVALUE(x,S_MC_BANK3_MAP,M_MC_BANK3_MAP) 97 1.2.2.2 nathanw 98 1.2.2.2 nathanw #define K_MC_BANK3_MAP_DEFAULT 0x0C 99 1.2.2.2 nathanw #define V_MC_BANK3_MAP_DEFAULT V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT) 100 1.2.2.2 nathanw 101 1.2.2.2 nathanw #define M_MC_RESERVED1 _SB_MAKEMASK(8,32) 102 1.2.2.2 nathanw 103 1.2.2.2 nathanw #define S_MC_QUEUE_SIZE 40 104 1.2.2.2 nathanw #define M_MC_QUEUE_SIZE _SB_MAKEMASK(4,S_MC_QUEUE_SIZE) 105 1.2.2.2 nathanw #define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x,S_MC_QUEUE_SIZE) 106 1.2.2.2 nathanw #define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x,S_MC_QUEUE_SIZE,M_MC_QUEUE_SIZE) 107 1.2.2.2 nathanw #define V_MC_QUEUE_SIZE_DEFAULT V_MC_QUEUE_SIZE(0x0A) 108 1.2.2.2 nathanw 109 1.2.2.2 nathanw #define S_MC_AGE_LIMIT 44 110 1.2.2.2 nathanw #define M_MC_AGE_LIMIT _SB_MAKEMASK(4,S_MC_AGE_LIMIT) 111 1.2.2.2 nathanw #define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x,S_MC_AGE_LIMIT) 112 1.2.2.2 nathanw #define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x,S_MC_AGE_LIMIT,M_MC_AGE_LIMIT) 113 1.2.2.2 nathanw #define V_MC_AGE_LIMIT_DEFAULT V_MC_AGE_LIMIT(8) 114 1.2.2.2 nathanw 115 1.2.2.2 nathanw #define S_MC_WR_LIMIT 48 116 1.2.2.2 nathanw #define M_MC_WR_LIMIT _SB_MAKEMASK(4,S_MC_WR_LIMIT) 117 1.2.2.2 nathanw #define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x,S_MC_WR_LIMIT) 118 1.2.2.2 nathanw #define G_MC_WR_LIMIT(x) _SB_GETVALUE(x,S_MC_WR_LIMIT,M_MC_WR_LIMIT) 119 1.2.2.2 nathanw #define V_MC_WR_LIMIT_DEFAULT V_MC_WR_LIMIT(5) 120 1.2.2.2 nathanw 121 1.2.2.2 nathanw #define M_MC_IOB1HIGHPRIORITY _SB_MAKEMASK1(52) 122 1.2.2.2 nathanw 123 1.2.2.2 nathanw #define M_MC_RESERVED2 _SB_MAKEMASK(3,53) 124 1.2.2.2 nathanw 125 1.2.2.2 nathanw #define S_MC_CS_MODE 56 126 1.2.2.2 nathanw #define M_MC_CS_MODE _SB_MAKEMASK(4,S_MC_CS_MODE) 127 1.2.2.2 nathanw #define V_MC_CS_MODE(x) _SB_MAKEVALUE(x,S_MC_CS_MODE) 128 1.2.2.2 nathanw #define G_MC_CS_MODE(x) _SB_GETVALUE(x,S_MC_CS_MODE,M_MC_CS_MODE) 129 1.2.2.2 nathanw 130 1.2.2.2 nathanw #define K_MC_CS_MODE_MSB_CS 0 131 1.2.2.2 nathanw #define K_MC_CS_MODE_INTLV_CS 15 132 1.2.2.2 nathanw #define K_MC_CS_MODE_MIXED_CS_10 12 133 1.2.2.2 nathanw #define K_MC_CS_MODE_MIXED_CS_30 6 134 1.2.2.2 nathanw #define K_MC_CS_MODE_MIXED_CS_32 3 135 1.2.2.2 nathanw 136 1.2.2.2 nathanw #define V_MC_CS_MODE_MSB_CS V_MC_CS_MODE(K_MC_CS_MODE_MSB_CS) 137 1.2.2.2 nathanw #define V_MC_CS_MODE_INTLV_CS V_MC_CS_MODE(K_MC_CS_MODE_INTLV_CS) 138 1.2.2.2 nathanw #define V_MC_CS_MODE_MIXED_CS_10 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_10) 139 1.2.2.2 nathanw #define V_MC_CS_MODE_MIXED_CS_30 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_30) 140 1.2.2.2 nathanw #define V_MC_CS_MODE_MIXED_CS_32 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_32) 141 1.2.2.2 nathanw 142 1.2.2.2 nathanw #define M_MC_ECC_DISABLE _SB_MAKEMASK1(60) 143 1.2.2.2 nathanw #define M_MC_BERR_DISABLE _SB_MAKEMASK1(61) 144 1.2.2.2 nathanw #define M_MC_FORCE_SEQ _SB_MAKEMASK1(62) 145 1.2.2.2 nathanw #define M_MC_DEBUG _SB_MAKEMASK1(63) 146 1.2.2.2 nathanw 147 1.2.2.2 nathanw #define V_MC_CONFIG_DEFAULT V_MC_WR_LIMIT_DEFAULT | V_MC_AGE_LIMIT_DEFAULT | \ 148 1.2.2.2 nathanw V_MC_BANK0_MAP_DEFAULT | V_MC_BANK1_MAP_DEFAULT | \ 149 1.2.2.2 nathanw V_MC_BANK2_MAP_DEFAULT | V_MC_BANK3_MAP_DEFAULT | V_MC_CHANNEL_SEL(0) | \ 150 1.2.2.2 nathanw M_MC_IOB1HIGHPRIORITY | V_MC_QUEUE_SIZE_DEFAULT 151 1.2.2.2 nathanw 152 1.2.2.2 nathanw 153 1.2.2.2 nathanw /* 154 1.2.2.2 nathanw * Memory clock config register (Table 6-15) 155 1.2.2.2 nathanw * 156 1.2.2.2 nathanw * Note: this field has been updated to be consistent with the errata to 0.2 157 1.2.2.2 nathanw */ 158 1.2.2.2 nathanw 159 1.2.2.2 nathanw #define S_MC_CLK_RATIO 0 160 1.2.2.2 nathanw #define M_MC_CLK_RATIO _SB_MAKEMASK(4,S_MC_CLK_RATIO) 161 1.2.2.2 nathanw #define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x,S_MC_CLK_RATIO) 162 1.2.2.2 nathanw #define G_MC_CLK_RATIO(x) _SB_GETVALUE(x,S_MC_CLK_RATIO,M_MC_CLK_RATIO) 163 1.2.2.2 nathanw 164 1.2.2.2 nathanw #define K_MC_CLK_RATIO_2X 4 165 1.2.2.2 nathanw #define K_MC_CLK_RATIO_25X 5 166 1.2.2.2 nathanw #define K_MC_CLK_RATIO_3X 6 167 1.2.2.2 nathanw #define K_MC_CLK_RATIO_35X 7 168 1.2.2.2 nathanw #define K_MC_CLK_RATIO_4X 8 169 1.2.2.2 nathanw #define K_MC_CLK_RATIO_45X 9 170 1.2.2.2 nathanw 171 1.2.2.2 nathanw #define V_MC_CLK_RATIO_2X V_MC_CLK_RATIO(K_MC_CLK_RATIO_2X) 172 1.2.2.2 nathanw #define V_MC_CLK_RATIO_25X V_MC_CLK_RATIO(K_MC_CLK_RATIO_25X) 173 1.2.2.2 nathanw #define V_MC_CLK_RATIO_3X V_MC_CLK_RATIO(K_MC_CLK_RATIO_3X) 174 1.2.2.2 nathanw #define V_MC_CLK_RATIO_35X V_MC_CLK_RATIO(K_MC_CLK_RATIO_35X) 175 1.2.2.2 nathanw #define V_MC_CLK_RATIO_4X V_MC_CLK_RATIO(K_MC_CLK_RATIO_4X) 176 1.2.2.2 nathanw #define V_MC_CLK_RATIO_45X V_MC_CLK_RATIO(K_MC_CLK_RATIO_45X) 177 1.2.2.2 nathanw #define V_MC_CLK_RATIO_DEFAULT V_MC_CLK_RATIO_25X 178 1.2.2.2 nathanw 179 1.2.2.2 nathanw #define S_MC_REF_RATE 8 180 1.2.2.2 nathanw #define M_MC_REF_RATE _SB_MAKEMASK(8,S_MC_REF_RATE) 181 1.2.2.2 nathanw #define V_MC_REF_RATE(x) _SB_MAKEVALUE(x,S_MC_REF_RATE) 182 1.2.2.2 nathanw #define G_MC_REF_RATE(x) _SB_GETVALUE(x,S_MC_REF_RATE,M_MC_REF_RATE) 183 1.2.2.2 nathanw 184 1.2.2.2 nathanw #define K_MC_REF_RATE_100MHz 0x62 185 1.2.2.2 nathanw #define K_MC_REF_RATE_133MHz 0x81 186 1.2.2.2 nathanw #define K_MC_REF_RATE_200MHz 0xC4 187 1.2.2.2 nathanw 188 1.2.2.2 nathanw #define V_MC_REF_RATE_100MHz V_MC_REF_RATE(K_MC_REF_RATE_100MHz) 189 1.2.2.2 nathanw #define V_MC_REF_RATE_133MHz V_MC_REF_RATE(K_MC_REF_RATE_133MHz) 190 1.2.2.2 nathanw #define V_MC_REF_RATE_200MHz V_MC_REF_RATE(K_MC_REF_RATE_200MHz) 191 1.2.2.2 nathanw #define V_MC_REF_RATE_DEFAULT V_MC_REF_RATE_100MHz 192 1.2.2.2 nathanw 193 1.2.2.2 nathanw #define S_MC_CLOCK_DRIVE 16 194 1.2.2.2 nathanw #define M_MC_CLOCK_DRIVE _SB_MAKEMASK(4,S_MC_CLOCK_DRIVE) 195 1.2.2.2 nathanw #define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x,S_MC_CLOCK_DRIVE) 196 1.2.2.2 nathanw #define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x,S_MC_CLOCK_DRIVE,M_MC_CLOCK_DRIVE) 197 1.2.2.2 nathanw #define V_MC_CLOCK_DRIVE_DEFAULT V_MC_CLOCK_DRIVE(0xF) 198 1.2.2.2 nathanw 199 1.2.2.2 nathanw #define S_MC_DATA_DRIVE 20 200 1.2.2.2 nathanw #define M_MC_DATA_DRIVE _SB_MAKEMASK(4,S_MC_DATA_DRIVE) 201 1.2.2.2 nathanw #define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x,S_MC_DATA_DRIVE) 202 1.2.2.2 nathanw #define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x,S_MC_DATA_DRIVE,M_MC_DATA_DRIVE) 203 1.2.2.2 nathanw #define V_MC_DATA_DRIVE_DEFAULT V_MC_DATA_DRIVE(0x0) 204 1.2.2.2 nathanw 205 1.2.2.2 nathanw #define S_MC_ADDR_DRIVE 24 206 1.2.2.2 nathanw #define M_MC_ADDR_DRIVE _SB_MAKEMASK(4,S_MC_ADDR_DRIVE) 207 1.2.2.2 nathanw #define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x,S_MC_ADDR_DRIVE) 208 1.2.2.2 nathanw #define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x,S_MC_ADDR_DRIVE,M_MC_ADDR_DRIVE) 209 1.2.2.2 nathanw #define V_MC_ADDR_DRIVE_DEFAULT V_MC_ADDR_DRIVE(0x0) 210 1.2.2.2 nathanw 211 1.2.2.2 nathanw #if SIBYTE_HDR_FEATURE(112x, PASS1) 212 1.2.2.2 nathanw #define M_MC_REF_DISABLE _SB_MAKEMASK1(30) 213 1.2.2.2 nathanw #endif /* 112x PASS1 */ 214 1.2.2.2 nathanw 215 1.2.2.2 nathanw #define M_MC_DLL_BYPASS _SB_MAKEMASK1(31) 216 1.2.2.2 nathanw 217 1.2.2.2 nathanw #define S_MC_DQI_SKEW 32 218 1.2.2.2 nathanw #define M_MC_DQI_SKEW _SB_MAKEMASK(8,S_MC_DQI_SKEW) 219 1.2.2.2 nathanw #define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQI_SKEW) 220 1.2.2.2 nathanw #define G_MC_DQI_SKEW(x) _SB_GETVALUE(x,S_MC_DQI_SKEW,M_MC_DQI_SKEW) 221 1.2.2.2 nathanw #define V_MC_DQI_SKEW_DEFAULT V_MC_DQI_SKEW(0) 222 1.2.2.2 nathanw 223 1.2.2.2 nathanw #define S_MC_DQO_SKEW 40 224 1.2.2.2 nathanw #define M_MC_DQO_SKEW _SB_MAKEMASK(8,S_MC_DQO_SKEW) 225 1.2.2.2 nathanw #define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQO_SKEW) 226 1.2.2.2 nathanw #define G_MC_DQO_SKEW(x) _SB_GETVALUE(x,S_MC_DQO_SKEW,M_MC_DQO_SKEW) 227 1.2.2.2 nathanw #define V_MC_DQO_SKEW_DEFAULT V_MC_DQO_SKEW(0) 228 1.2.2.2 nathanw 229 1.2.2.2 nathanw #define S_MC_ADDR_SKEW 48 230 1.2.2.2 nathanw #define M_MC_ADDR_SKEW _SB_MAKEMASK(8,S_MC_ADDR_SKEW) 231 1.2.2.2 nathanw #define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x,S_MC_ADDR_SKEW) 232 1.2.2.2 nathanw #define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x,S_MC_ADDR_SKEW,M_MC_ADDR_SKEW) 233 1.2.2.2 nathanw #define V_MC_ADDR_SKEW_DEFAULT V_MC_ADDR_SKEW(0x0F) 234 1.2.2.2 nathanw 235 1.2.2.2 nathanw #define S_MC_DLL_DEFAULT 56 236 1.2.2.2 nathanw #define M_MC_DLL_DEFAULT _SB_MAKEMASK(8,S_MC_DLL_DEFAULT) 237 1.2.2.2 nathanw #define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_MC_DLL_DEFAULT) 238 1.2.2.2 nathanw #define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_MC_DLL_DEFAULT,M_MC_DLL_DEFAULT) 239 1.2.2.2 nathanw #define V_MC_DLL_DEFAULT_DEFAULT V_MC_DLL_DEFAULT(0x10) 240 1.2.2.2 nathanw 241 1.2.2.2 nathanw #define V_MC_CLKCONFIG_DEFAULT V_MC_DLL_DEFAULT_DEFAULT | \ 242 1.2.2.2 nathanw V_MC_ADDR_SKEW_DEFAULT | \ 243 1.2.2.2 nathanw V_MC_DQO_SKEW_DEFAULT | \ 244 1.2.2.2 nathanw V_MC_DQI_SKEW_DEFAULT | \ 245 1.2.2.2 nathanw V_MC_ADDR_DRIVE_DEFAULT | \ 246 1.2.2.2 nathanw V_MC_DATA_DRIVE_DEFAULT | \ 247 1.2.2.2 nathanw V_MC_CLOCK_DRIVE_DEFAULT | \ 248 1.2.2.2 nathanw V_MC_REF_RATE_DEFAULT 249 1.2.2.2 nathanw 250 1.2.2.2 nathanw 251 1.2.2.2 nathanw 252 1.2.2.2 nathanw /* 253 1.2.2.2 nathanw * DRAM Command Register (Table 6-13) 254 1.2.2.2 nathanw */ 255 1.2.2.2 nathanw 256 1.2.2.2 nathanw #define S_MC_COMMAND 0 257 1.2.2.2 nathanw #define M_MC_COMMAND _SB_MAKEMASK(4,S_MC_COMMAND) 258 1.2.2.2 nathanw #define V_MC_COMMAND(x) _SB_MAKEVALUE(x,S_MC_COMMAND) 259 1.2.2.2 nathanw #define G_MC_COMMAND(x) _SB_GETVALUE(x,S_MC_COMMAND,M_MC_COMMAND) 260 1.2.2.2 nathanw 261 1.2.2.2 nathanw #define K_MC_COMMAND_EMRS 0 262 1.2.2.2 nathanw #define K_MC_COMMAND_MRS 1 263 1.2.2.2 nathanw #define K_MC_COMMAND_PRE 2 264 1.2.2.2 nathanw #define K_MC_COMMAND_AR 3 265 1.2.2.2 nathanw #define K_MC_COMMAND_SETRFSH 4 266 1.2.2.2 nathanw #define K_MC_COMMAND_CLRRFSH 5 267 1.2.2.2 nathanw #define K_MC_COMMAND_SETPWRDN 6 268 1.2.2.2 nathanw #define K_MC_COMMAND_CLRPWRDN 7 269 1.2.2.2 nathanw 270 1.2.2.2 nathanw #define V_MC_COMMAND_EMRS V_MC_COMMAND(K_MC_COMMAND_EMRS) 271 1.2.2.2 nathanw #define V_MC_COMMAND_MRS V_MC_COMMAND(K_MC_COMMAND_MRS) 272 1.2.2.2 nathanw #define V_MC_COMMAND_PRE V_MC_COMMAND(K_MC_COMMAND_PRE) 273 1.2.2.2 nathanw #define V_MC_COMMAND_AR V_MC_COMMAND(K_MC_COMMAND_AR) 274 1.2.2.2 nathanw #define V_MC_COMMAND_SETRFSH V_MC_COMMAND(K_MC_COMMAND_SETRFSH) 275 1.2.2.2 nathanw #define V_MC_COMMAND_CLRRFSH V_MC_COMMAND(K_MC_COMMAND_CLRRFSH) 276 1.2.2.2 nathanw #define V_MC_COMMAND_SETPWRDN V_MC_COMMAND(K_MC_COMMAND_SETPWRDN) 277 1.2.2.2 nathanw #define V_MC_COMMAND_CLRPWRDN V_MC_COMMAND(K_MC_COMMAND_CLRPWRDN) 278 1.2.2.2 nathanw 279 1.2.2.2 nathanw #define M_MC_CS0 _SB_MAKEMASK1(4) 280 1.2.2.2 nathanw #define M_MC_CS1 _SB_MAKEMASK1(5) 281 1.2.2.2 nathanw #define M_MC_CS2 _SB_MAKEMASK1(6) 282 1.2.2.2 nathanw #define M_MC_CS3 _SB_MAKEMASK1(7) 283 1.2.2.2 nathanw 284 1.2.2.2 nathanw /* 285 1.2.2.2 nathanw * DRAM Mode Register (Table 6-14) 286 1.2.2.2 nathanw */ 287 1.2.2.2 nathanw 288 1.2.2.2 nathanw #define S_MC_EMODE 0 289 1.2.2.2 nathanw #define M_MC_EMODE _SB_MAKEMASK(15,S_MC_EMODE) 290 1.2.2.2 nathanw #define V_MC_EMODE(x) _SB_MAKEVALUE(x,S_MC_EMODE) 291 1.2.2.2 nathanw #define G_MC_EMODE(x) _SB_GETVALUE(x,S_MC_EMODE,M_MC_EMODE) 292 1.2.2.2 nathanw #define V_MC_EMODE_DEFAULT V_MC_EMODE(0) 293 1.2.2.2 nathanw 294 1.2.2.2 nathanw #define S_MC_MODE 16 295 1.2.2.2 nathanw #define M_MC_MODE _SB_MAKEMASK(15,S_MC_MODE) 296 1.2.2.2 nathanw #define V_MC_MODE(x) _SB_MAKEVALUE(x,S_MC_MODE) 297 1.2.2.2 nathanw #define G_MC_MODE(x) _SB_GETVALUE(x,S_MC_MODE,M_MC_MODE) 298 1.2.2.2 nathanw #define V_MC_MODE_DEFAULT V_MC_MODE(0x22) 299 1.2.2.2 nathanw 300 1.2.2.2 nathanw #define S_MC_DRAM_TYPE 32 301 1.2.2.2 nathanw #define M_MC_DRAM_TYPE _SB_MAKEMASK(3,S_MC_DRAM_TYPE) 302 1.2.2.2 nathanw #define V_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x,S_MC_DRAM_TYPE) 303 1.2.2.2 nathanw #define G_MC_DRAM_TYPE(x) _SB_GETVALUE(x,S_MC_DRAM_TYPE,M_MC_DRAM_TYPE) 304 1.2.2.2 nathanw 305 1.2.2.2 nathanw #define K_MC_DRAM_TYPE_JEDEC 0 306 1.2.2.2 nathanw #define K_MC_DRAM_TYPE_FCRAM 1 307 1.2.2.2 nathanw #define K_MC_DRAM_TYPE_SGRAM 2 308 1.2.2.2 nathanw 309 1.2.2.2 nathanw #define V_MC_DRAM_TYPE_JEDEC V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_JEDEC) 310 1.2.2.2 nathanw #define V_MC_DRAM_TYPE_FCRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_FCRAM) 311 1.2.2.2 nathanw #define V_MC_DRAM_TYPE_SGRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_SGRAM) 312 1.2.2.2 nathanw 313 1.2.2.2 nathanw #define M_MC_EXTERNALDECODE _SB_MAKEMASK1(35) 314 1.2.2.2 nathanw 315 1.2.2.2 nathanw #if SIBYTE_HDR_FEATURE(112x, PASS1) 316 1.2.2.2 nathanw #define M_MC_PRE_ON_A8 _SB_MAKEMASK1(36) 317 1.2.2.2 nathanw #define M_MC_RAM_WITH_A13 _SB_MAKEMASK1(38) 318 1.2.2.2 nathanw #endif /* 112x PASS1 */ 319 1.2.2.2 nathanw 320 1.2.2.2 nathanw 321 1.2.2.2 nathanw 322 1.2.2.2 nathanw /* 323 1.2.2.2 nathanw * SDRAM Timing Register (Table 6-15) 324 1.2.2.2 nathanw */ 325 1.2.2.2 nathanw 326 1.2.2.2 nathanw #define M_MC_w2rIDLE_TWOCYCLES _SB_MAKEMASK1(60) 327 1.2.2.2 nathanw #define M_MC_r2wIDLE_TWOCYCLES _SB_MAKEMASK1(61) 328 1.2.2.2 nathanw #define M_MC_r2rIDLE_TWOCYCLES _SB_MAKEMASK1(62) 329 1.2.2.2 nathanw 330 1.2.2.2 nathanw #define S_MC_tFIFO 56 331 1.2.2.2 nathanw #define M_MC_tFIFO _SB_MAKEMASK(4,S_MC_tFIFO) 332 1.2.2.2 nathanw #define V_MC_tFIFO(x) _SB_MAKEVALUE(x,S_MC_tFIFO) 333 1.2.2.2 nathanw #define G_MC_tFIFO(x) _SB_GETVALUE(x,S_MC_tFIFO,M_MC_tFIFO) 334 1.2.2.2 nathanw #define K_MC_tFIFO_DEFAULT 1 335 1.2.2.2 nathanw #define V_MC_tFIFO_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) 336 1.2.2.2 nathanw 337 1.2.2.2 nathanw #define S_MC_tRFC 52 338 1.2.2.2 nathanw #define M_MC_tRFC _SB_MAKEMASK(4,S_MC_tRFC) 339 1.2.2.2 nathanw #define V_MC_tRFC(x) _SB_MAKEVALUE(x,S_MC_tRFC) 340 1.2.2.2 nathanw #define G_MC_tRFC(x) _SB_GETVALUE(x,S_MC_tRFC,M_MC_tRFC) 341 1.2.2.2 nathanw #define K_MC_tRFC_DEFAULT 12 342 1.2.2.2 nathanw #define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT) 343 1.2.2.2 nathanw 344 1.2.2.2 nathanw #define S_MC_tCwCr 40 345 1.2.2.2 nathanw #define M_MC_tCwCr _SB_MAKEMASK(4,S_MC_tCwCr) 346 1.2.2.2 nathanw #define V_MC_tCwCr(x) _SB_MAKEVALUE(x,S_MC_tCwCr) 347 1.2.2.2 nathanw #define G_MC_tCwCr(x) _SB_GETVALUE(x,S_MC_tCwCr,M_MC_tCwCr) 348 1.2.2.2 nathanw #define K_MC_tCwCr_DEFAULT 4 349 1.2.2.2 nathanw #define V_MC_tCwCr_DEFAULT V_MC_tCwCr(K_MC_tCwCr_DEFAULT) 350 1.2.2.2 nathanw 351 1.2.2.2 nathanw #define S_MC_tRCr 28 352 1.2.2.2 nathanw #define M_MC_tRCr _SB_MAKEMASK(4,S_MC_tRCr) 353 1.2.2.2 nathanw #define V_MC_tRCr(x) _SB_MAKEVALUE(x,S_MC_tRCr) 354 1.2.2.2 nathanw #define G_MC_tRCr(x) _SB_GETVALUE(x,S_MC_tRCr,M_MC_tRCr) 355 1.2.2.2 nathanw #define K_MC_tRCr_DEFAULT 9 356 1.2.2.2 nathanw #define V_MC_tRCr_DEFAULT V_MC_tRCr(K_MC_tRCr_DEFAULT) 357 1.2.2.2 nathanw 358 1.2.2.2 nathanw #define S_MC_tRCw 24 359 1.2.2.2 nathanw #define M_MC_tRCw _SB_MAKEMASK(4,S_MC_tRCw) 360 1.2.2.2 nathanw #define V_MC_tRCw(x) _SB_MAKEVALUE(x,S_MC_tRCw) 361 1.2.2.2 nathanw #define G_MC_tRCw(x) _SB_GETVALUE(x,S_MC_tRCw,M_MC_tRCw) 362 1.2.2.2 nathanw #define K_MC_tRCw_DEFAULT 10 363 1.2.2.2 nathanw #define V_MC_tRCw_DEFAULT V_MC_tRCw(K_MC_tRCw_DEFAULT) 364 1.2.2.2 nathanw 365 1.2.2.2 nathanw #define S_MC_tRRD 20 366 1.2.2.2 nathanw #define M_MC_tRRD _SB_MAKEMASK(4,S_MC_tRRD) 367 1.2.2.2 nathanw #define V_MC_tRRD(x) _SB_MAKEVALUE(x,S_MC_tRRD) 368 1.2.2.2 nathanw #define G_MC_tRRD(x) _SB_GETVALUE(x,S_MC_tRRD,M_MC_tRRD) 369 1.2.2.2 nathanw #define K_MC_tRRD_DEFAULT 2 370 1.2.2.2 nathanw #define V_MC_tRRD_DEFAULT V_MC_tRRD(K_MC_tRRD_DEFAULT) 371 1.2.2.2 nathanw 372 1.2.2.2 nathanw #define S_MC_tRP 16 373 1.2.2.2 nathanw #define M_MC_tRP _SB_MAKEMASK(4,S_MC_tRP) 374 1.2.2.2 nathanw #define V_MC_tRP(x) _SB_MAKEVALUE(x,S_MC_tRP) 375 1.2.2.2 nathanw #define G_MC_tRP(x) _SB_GETVALUE(x,S_MC_tRP,M_MC_tRP) 376 1.2.2.2 nathanw #define K_MC_tRP_DEFAULT 4 377 1.2.2.2 nathanw #define V_MC_tRP_DEFAULT V_MC_tRP(K_MC_tRP_DEFAULT) 378 1.2.2.2 nathanw 379 1.2.2.2 nathanw #define S_MC_tCwD 8 380 1.2.2.2 nathanw #define M_MC_tCwD _SB_MAKEMASK(4,S_MC_tCwD) 381 1.2.2.2 nathanw #define V_MC_tCwD(x) _SB_MAKEVALUE(x,S_MC_tCwD) 382 1.2.2.2 nathanw #define G_MC_tCwD(x) _SB_GETVALUE(x,S_MC_tCwD,M_MC_tCwD) 383 1.2.2.2 nathanw #define K_MC_tCwD_DEFAULT 1 384 1.2.2.2 nathanw #define V_MC_tCwD_DEFAULT V_MC_tCwD(K_MC_tCwD_DEFAULT) 385 1.2.2.2 nathanw 386 1.2.2.2 nathanw #define M_tCrDh _SB_MAKEMASK1(7) 387 1.2.2.2 nathanw #define M_MC_tCrDh M_tCrDh 388 1.2.2.2 nathanw 389 1.2.2.2 nathanw #define S_MC_tCrD 4 390 1.2.2.2 nathanw #define M_MC_tCrD _SB_MAKEMASK(3,S_MC_tCrD) 391 1.2.2.2 nathanw #define V_MC_tCrD(x) _SB_MAKEVALUE(x,S_MC_tCrD) 392 1.2.2.2 nathanw #define G_MC_tCrD(x) _SB_GETVALUE(x,S_MC_tCrD,M_MC_tCrD) 393 1.2.2.2 nathanw #define K_MC_tCrD_DEFAULT 2 394 1.2.2.2 nathanw #define V_MC_tCrD_DEFAULT V_MC_tCrD(K_MC_tCrD_DEFAULT) 395 1.2.2.2 nathanw 396 1.2.2.2 nathanw #define S_MC_tRCD 0 397 1.2.2.2 nathanw #define M_MC_tRCD _SB_MAKEMASK(4,S_MC_tRCD) 398 1.2.2.2 nathanw #define V_MC_tRCD(x) _SB_MAKEVALUE(x,S_MC_tRCD) 399 1.2.2.2 nathanw #define G_MC_tRCD(x) _SB_GETVALUE(x,S_MC_tRCD,M_MC_tRCD) 400 1.2.2.2 nathanw #define K_MC_tRCD_DEFAULT 3 401 1.2.2.2 nathanw #define V_MC_tRCD_DEFAULT V_MC_tRCD(K_MC_tRCD_DEFAULT) 402 1.2.2.2 nathanw 403 1.2.2.2 nathanw #define V_MC_TIMING_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) | \ 404 1.2.2.2 nathanw V_MC_tRFC(K_MC_tRFC_DEFAULT) | \ 405 1.2.2.2 nathanw V_MC_tCwCr(K_MC_tCwCr_DEFAULT) | \ 406 1.2.2.2 nathanw V_MC_tRCr(K_MC_tRCr_DEFAULT) | \ 407 1.2.2.2 nathanw V_MC_tRCw(K_MC_tRCw_DEFAULT) | \ 408 1.2.2.2 nathanw V_MC_tRRD(K_MC_tRRD_DEFAULT) | \ 409 1.2.2.2 nathanw V_MC_tRP(K_MC_tRP_DEFAULT) | \ 410 1.2.2.2 nathanw V_MC_tCwD(K_MC_tCwD_DEFAULT) | \ 411 1.2.2.2 nathanw V_MC_tCrD(K_MC_tCrD_DEFAULT) | \ 412 1.2.2.2 nathanw V_MC_tRCD(K_MC_tRCD_DEFAULT) | \ 413 1.2.2.2 nathanw M_MC_r2rIDLE_TWOCYCLES 414 1.2.2.2 nathanw 415 1.2.2.2 nathanw /* 416 1.2.2.2 nathanw * Errata says these are not the default 417 1.2.2.2 nathanw * M_MC_w2rIDLE_TWOCYCLES | \ 418 1.2.2.2 nathanw * M_MC_r2wIDLE_TWOCYCLES | \ 419 1.2.2.2 nathanw */ 420 1.2.2.2 nathanw 421 1.2.2.2 nathanw 422 1.2.2.2 nathanw /* 423 1.2.2.2 nathanw * Chip Select Start Address Register (Table 6-17) 424 1.2.2.2 nathanw */ 425 1.2.2.2 nathanw 426 1.2.2.2 nathanw #define S_MC_CS0_START 0 427 1.2.2.2 nathanw #define M_MC_CS0_START _SB_MAKEMASK(16,S_MC_CS0_START) 428 1.2.2.2 nathanw #define V_MC_CS0_START(x) _SB_MAKEVALUE(x,S_MC_CS0_START) 429 1.2.2.2 nathanw #define G_MC_CS0_START(x) _SB_GETVALUE(x,S_MC_CS0_START,M_MC_CS0_START) 430 1.2.2.2 nathanw 431 1.2.2.2 nathanw #define S_MC_CS1_START 16 432 1.2.2.2 nathanw #define M_MC_CS1_START _SB_MAKEMASK(16,S_MC_CS1_START) 433 1.2.2.2 nathanw #define V_MC_CS1_START(x) _SB_MAKEVALUE(x,S_MC_CS1_START) 434 1.2.2.2 nathanw #define G_MC_CS1_START(x) _SB_GETVALUE(x,S_MC_CS1_START,M_MC_CS1_START) 435 1.2.2.2 nathanw 436 1.2.2.2 nathanw #define S_MC_CS2_START 32 437 1.2.2.2 nathanw #define M_MC_CS2_START _SB_MAKEMASK(16,S_MC_CS2_START) 438 1.2.2.2 nathanw #define V_MC_CS2_START(x) _SB_MAKEVALUE(x,S_MC_CS2_START) 439 1.2.2.2 nathanw #define G_MC_CS2_START(x) _SB_GETVALUE(x,S_MC_CS2_START,M_MC_CS2_START) 440 1.2.2.2 nathanw 441 1.2.2.2 nathanw #define S_MC_CS3_START 48 442 1.2.2.2 nathanw #define M_MC_CS3_START _SB_MAKEMASK(16,S_MC_CS3_START) 443 1.2.2.2 nathanw #define V_MC_CS3_START(x) _SB_MAKEVALUE(x,S_MC_CS3_START) 444 1.2.2.2 nathanw #define G_MC_CS3_START(x) _SB_GETVALUE(x,S_MC_CS3_START,M_MC_CS3_START) 445 1.2.2.2 nathanw 446 1.2.2.2 nathanw /* 447 1.2.2.2 nathanw * Chip Select End Address Register (Table 6-18) 448 1.2.2.2 nathanw */ 449 1.2.2.2 nathanw 450 1.2.2.2 nathanw #define S_MC_CS0_END 0 451 1.2.2.2 nathanw #define M_MC_CS0_END _SB_MAKEMASK(16,S_MC_CS0_END) 452 1.2.2.2 nathanw #define V_MC_CS0_END(x) _SB_MAKEVALUE(x,S_MC_CS0_END) 453 1.2.2.2 nathanw #define G_MC_CS0_END(x) _SB_GETVALUE(x,S_MC_CS0_END,M_MC_CS0_END) 454 1.2.2.2 nathanw 455 1.2.2.2 nathanw #define S_MC_CS1_END 16 456 1.2.2.2 nathanw #define M_MC_CS1_END _SB_MAKEMASK(16,S_MC_CS1_END) 457 1.2.2.2 nathanw #define V_MC_CS1_END(x) _SB_MAKEVALUE(x,S_MC_CS1_END) 458 1.2.2.2 nathanw #define G_MC_CS1_END(x) _SB_GETVALUE(x,S_MC_CS1_END,M_MC_CS1_END) 459 1.2.2.2 nathanw 460 1.2.2.2 nathanw #define S_MC_CS2_END 32 461 1.2.2.2 nathanw #define M_MC_CS2_END _SB_MAKEMASK(16,S_MC_CS2_END) 462 1.2.2.2 nathanw #define V_MC_CS2_END(x) _SB_MAKEVALUE(x,S_MC_CS2_END) 463 1.2.2.2 nathanw #define G_MC_CS2_END(x) _SB_GETVALUE(x,S_MC_CS2_END,M_MC_CS2_END) 464 1.2.2.2 nathanw 465 1.2.2.2 nathanw #define S_MC_CS3_END 48 466 1.2.2.2 nathanw #define M_MC_CS3_END _SB_MAKEMASK(16,S_MC_CS3_END) 467 1.2.2.2 nathanw #define V_MC_CS3_END(x) _SB_MAKEVALUE(x,S_MC_CS3_END) 468 1.2.2.2 nathanw #define G_MC_CS3_END(x) _SB_GETVALUE(x,S_MC_CS3_END,M_MC_CS3_END) 469 1.2.2.2 nathanw 470 1.2.2.2 nathanw /* 471 1.2.2.2 nathanw * Chip Select Interleave Register (Table 6-19) 472 1.2.2.2 nathanw */ 473 1.2.2.2 nathanw 474 1.2.2.2 nathanw #define S_MC_INTLV_RESERVED 0 475 1.2.2.2 nathanw #define M_MC_INTLV_RESERVED _SB_MAKEMASK(5,S_MC_INTLV_RESERVED) 476 1.2.2.2 nathanw 477 1.2.2.2 nathanw #define S_MC_INTERLEAVE 7 478 1.2.2.2 nathanw #define M_MC_INTERLEAVE _SB_MAKEMASK(18,S_MC_INTERLEAVE) 479 1.2.2.2 nathanw #define V_MC_INTERLEAVE(x) _SB_MAKEVALUE(x,S_MC_INTERLEAVE) 480 1.2.2.2 nathanw 481 1.2.2.2 nathanw #define S_MC_INTLV_MBZ 25 482 1.2.2.2 nathanw #define M_MC_INTLV_MBZ _SB_MAKEMASK(39,S_MC_INTLV_MBZ) 483 1.2.2.2 nathanw 484 1.2.2.2 nathanw /* 485 1.2.2.2 nathanw * Row Address Bits Register (Table 6-20) 486 1.2.2.2 nathanw */ 487 1.2.2.2 nathanw 488 1.2.2.2 nathanw #define S_MC_RAS_RESERVED 0 489 1.2.2.2 nathanw #define M_MC_RAS_RESERVED _SB_MAKEMASK(5,S_MC_RAS_RESERVED) 490 1.2.2.2 nathanw 491 1.2.2.2 nathanw #define S_MC_RAS_SELECT 12 492 1.2.2.2 nathanw #define M_MC_RAS_SELECT _SB_MAKEMASK(25,S_MC_RAS_SELECT) 493 1.2.2.2 nathanw #define V_MC_RAS_SELECT(x) _SB_MAKEVALUE(x,S_MC_RAS_SELECT) 494 1.2.2.2 nathanw 495 1.2.2.2 nathanw #define S_MC_RAS_MBZ 37 496 1.2.2.2 nathanw #define M_MC_RAS_MBZ _SB_MAKEMASK(27,S_MC_RAS_MBZ) 497 1.2.2.2 nathanw 498 1.2.2.2 nathanw 499 1.2.2.2 nathanw /* 500 1.2.2.2 nathanw * Column Address Bits Register (Table 6-21) 501 1.2.2.2 nathanw */ 502 1.2.2.2 nathanw 503 1.2.2.2 nathanw #define S_MC_CAS_RESERVED 0 504 1.2.2.2 nathanw #define M_MC_CAS_RESERVED _SB_MAKEMASK(5,S_MC_CAS_RESERVED) 505 1.2.2.2 nathanw 506 1.2.2.2 nathanw #define S_MC_CAS_SELECT 5 507 1.2.2.2 nathanw #define M_MC_CAS_SELECT _SB_MAKEMASK(18,S_MC_CAS_SELECT) 508 1.2.2.2 nathanw #define V_MC_CAS_SELECT(x) _SB_MAKEVALUE(x,S_MC_CAS_SELECT) 509 1.2.2.2 nathanw 510 1.2.2.2 nathanw #define S_MC_CAS_MBZ 23 511 1.2.2.2 nathanw #define M_MC_CAS_MBZ _SB_MAKEMASK(41,S_MC_CAS_MBZ) 512 1.2.2.2 nathanw 513 1.2.2.2 nathanw 514 1.2.2.2 nathanw /* 515 1.2.2.2 nathanw * Bank Address Address Bits Register (Table 6-22) 516 1.2.2.2 nathanw */ 517 1.2.2.2 nathanw 518 1.2.2.2 nathanw #define S_MC_BA_RESERVED 0 519 1.2.2.2 nathanw #define M_MC_BA_RESERVED _SB_MAKEMASK(5,S_MC_BA_RESERVED) 520 1.2.2.2 nathanw 521 1.2.2.2 nathanw #define S_MC_BA_SELECT 5 522 1.2.2.2 nathanw #define M_MC_BA_SELECT _SB_MAKEMASK(20,S_MC_BA_SELECT) 523 1.2.2.2 nathanw #define V_MC_BA_SELECT(x) _SB_MAKEVALUE(x,S_MC_BA_SELECT) 524 1.2.2.2 nathanw 525 1.2.2.2 nathanw #define S_MC_BA_MBZ 25 526 1.2.2.2 nathanw #define M_MC_BA_MBZ _SB_MAKEMASK(39,S_MC_BA_MBZ) 527 1.2.2.2 nathanw 528 1.2.2.2 nathanw /* 529 1.2.2.2 nathanw * Chip Select Attribute Register (Table 6-23) 530 1.2.2.2 nathanw */ 531 1.2.2.2 nathanw 532 1.2.2.2 nathanw #define K_MC_CS_ATTR_CLOSED 0 533 1.2.2.2 nathanw #define K_MC_CS_ATTR_CASCHECK 1 534 1.2.2.2 nathanw #define K_MC_CS_ATTR_HINT 2 535 1.2.2.2 nathanw #define K_MC_CS_ATTR_OPEN 3 536 1.2.2.2 nathanw 537 1.2.2.2 nathanw #define S_MC_CS0_PAGE 0 538 1.2.2.2 nathanw #define M_MC_CS0_PAGE _SB_MAKEMASK(2,S_MC_CS0_PAGE) 539 1.2.2.2 nathanw #define V_MC_CS0_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS0_PAGE) 540 1.2.2.2 nathanw #define G_MC_CS0_PAGE(x) _SB_GETVALUE(x,S_MC_CS0_PAGE,M_MC_CS0_PAGE) 541 1.2.2.2 nathanw 542 1.2.2.2 nathanw #define S_MC_CS1_PAGE 16 543 1.2.2.2 nathanw #define M_MC_CS1_PAGE _SB_MAKEMASK(2,S_MC_CS1_PAGE) 544 1.2.2.2 nathanw #define V_MC_CS1_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS1_PAGE) 545 1.2.2.2 nathanw #define G_MC_CS1_PAGE(x) _SB_GETVALUE(x,S_MC_CS1_PAGE,M_MC_CS1_PAGE) 546 1.2.2.2 nathanw 547 1.2.2.2 nathanw #define S_MC_CS2_PAGE 32 548 1.2.2.2 nathanw #define M_MC_CS2_PAGE _SB_MAKEMASK(2,S_MC_CS2_PAGE) 549 1.2.2.2 nathanw #define V_MC_CS2_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS2_PAGE) 550 1.2.2.2 nathanw #define G_MC_CS2_PAGE(x) _SB_GETVALUE(x,S_MC_CS2_PAGE,M_MC_CS2_PAGE) 551 1.2.2.2 nathanw 552 1.2.2.2 nathanw #define S_MC_CS3_PAGE 48 553 1.2.2.2 nathanw #define M_MC_CS3_PAGE _SB_MAKEMASK(2,S_MC_CS3_PAGE) 554 1.2.2.2 nathanw #define V_MC_CS3_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS3_PAGE) 555 1.2.2.2 nathanw #define G_MC_CS3_PAGE(x) _SB_GETVALUE(x,S_MC_CS3_PAGE,M_MC_CS3_PAGE) 556 1.2.2.2 nathanw 557 1.2.2.2 nathanw /* 558 1.2.2.2 nathanw * ECC Test ECC Register (Table 6-25) 559 1.2.2.2 nathanw */ 560 1.2.2.2 nathanw 561 1.2.2.2 nathanw #define S_MC_ECC_INVERT 0 562 1.2.2.2 nathanw #define M_MC_ECC_INVERT _SB_MAKEMASK(8,S_MC_ECC_INVERT) 563 1.2.2.2 nathanw 564 1.2.2.2 nathanw 565 1.2.2.2 nathanw #endif 566
Indexes created Sat Nov 01 05:10:12 GMT 2025