sb1250_regs.h revision 1.1
1 /* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * Register Definitions File: sb1250_regs.h 5 * 6 * This module contains the addresses of the on-chip peripherals 7 * on the SB1250. 8 * 9 * SB1250 specification level: 0.2 10 * 11 * Author: Mitch Lichtenberg (mitch (at) sibyte.com) 12 * 13 ********************************************************************* 14 * 15 * Copyright 2000,2001 16 * Broadcom Corporation. All rights reserved. 17 * 18 * This software is furnished under license and may be used and 19 * copied only in accordance with the following terms and 20 * conditions. Subject to these conditions, you may download, 21 * copy, install, use, modify and distribute modified or unmodified 22 * copies of this software in source and/or binary form. No title 23 * or ownership is transferred hereby. 24 * 25 * 1) Any source code used, modified or distributed must reproduce 26 * and retain this copyright notice and list of conditions as 27 * they appear in the source file. 28 * 29 * 2) No right is granted to use any trade name, trademark, or 30 * logo of Broadcom Corporation. Neither the "Broadcom 31 * Corporation" name nor any trademark or logo of Broadcom 32 * Corporation may be used to endorse or promote products 33 * derived from this software without the prior written 34 * permission of Broadcom Corporation. 35 * 36 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 37 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 38 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 39 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 40 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 41 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 42 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 43 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 44 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 45 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 46 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 47 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 48 * THE POSSIBILITY OF SUCH DAMAGE. 49 ********************************************************************* */ 50 51 52 #ifndef _SB1250_REGS_H 53 #define _SB1250_REGS_H 54 55 #include "sb1250_defs.h" 56 57 58 /* ********************************************************************* 59 * Some general notes: 60 * 61 * For the most part, when there is more than one peripheral 62 * of the same type on the SOC, the constants below will be 63 * offsets from the base of each peripheral. For example, 64 * the MAC registers are described as offsets from the first 65 * MAC register, and there will be a MAC_REGISTER() macro 66 * to calculate the base address of a given MAC. 67 * 68 * The information in this file is based on the SB1250 SOC 69 * manual version 0.2, July 2000. 70 ********************************************************************* */ 71 72 73 /* ********************************************************************* 74 * Memory Controller Registers 75 ********************************************************************* */ 76 77 #define A_MC_BASE_0 0x0010051000 78 #define A_MC_BASE_1 0x0010052000 79 #define MC_REGISTER_SPACING 0x1000 80 81 #define A_MC_BASE(ctlid) \ 82 ((ctlid) * MC_REGISTER_SPACING + A_MC_BASE_0) 83 #define A_MC_REGISTER(ctlid,reg) (A_MC_BASE(ctlid) + (reg)) 84 85 #define R_MC_CONFIG 0x0000000100 86 #define R_MC_DRAMCMD 0x0000000120 87 #define R_MC_DRAMMODE 0x0000000140 88 #define R_MC_TIMING1 0x0000000160 89 #define R_MC_TIMING2 0x0000000180 90 #define R_MC_CS_START 0x00000001A0 91 #define R_MC_CS_END 0x00000001C0 92 #define R_MC_CS_INTERLEAVE 0x00000001E0 93 #define S_MC_CS_STARTEND 16 94 95 #define R_MC_CSX_BASE 0x0000000200 96 #define R_MC_CSX_ROW 0x0000000000 /* relative to CSX_BASE, above */ 97 #define R_MC_CSX_COL 0x0000000020 /* relative to CSX_BASE, above */ 98 #define R_MC_CSX_BA 0x0000000040 /* relative to CSX_BASE, above */ 99 #define MC_CSX_SPACING 0x0000000060 /* relative to CSX_BASE, above */ 100 101 #define R_MC_CS0_ROW 0x0000000200 102 #define R_MC_CS0_COL 0x0000000220 103 #define R_MC_CS0_BA 0x0000000240 104 #define R_MC_CS1_ROW 0x0000000260 105 #define R_MC_CS1_COL 0x0000000280 106 #define R_MC_CS1_BA 0x00000002A0 107 #define R_MC_CS2_ROW 0x00000002C0 108 #define R_MC_CS2_COL 0x00000002E0 109 #define R_MC_CS2_BA 0x0000000300 110 #define R_MC_CS3_ROW 0x0000000320 111 #define R_MC_CS3_COL 0x0000000340 112 #define R_MC_CS3_BA 0x0000000360 113 #define R_MC_CS_ATTR 0x0000000380 114 #define R_MC_TEST_DATA 0x0000000400 115 #define R_MC_TEST_ECC 0x0000000420 116 #define R_MC_MCLK_CFG 0x0000000500 117 118 /* ********************************************************************* 119 * L2 Cache Control Registers 120 ********************************************************************* */ 121 122 #define A_L2_READ_ADDRESS 0x0010040018 123 #define A_L2_EEC_ADDRESS 0x0010040038 124 #define A_L2_WAY_DISABLE 0x0010041000 125 #define A_L2_MAKEDISABLE(x) (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8)) 126 #define A_L2_MGMT_TAG_BASE 0x00D0000000 127 128 /* ********************************************************************* 129 * PCI Interface Registers 130 ********************************************************************* */ 131 132 #define A_PCI_TYPE00_HEADER 0x00DE000000 133 #define A_PCI_TYPE01_HEADER 0x00DE000800 134 135 136 /* ********************************************************************* 137 * Ethernet DMA and MACs 138 ********************************************************************* */ 139 140 #define A_MAC_BASE_0 0x0010064000 141 #define A_MAC_BASE_1 0x0010065000 142 #define A_MAC_BASE_2 0x0010066000 143 144 #define MAC_SPACING 0x1000 145 #define MAC_DMA_TXRX_SPACING 0x0400 146 #define MAC_DMA_CHANNEL_SPACING 0x0100 147 #define DMA_RX 0 148 #define DMA_TX 1 149 #define MAC_NUM_DMACHAN 2 /* channels per direction */ 150 151 #define MAC_NUM_PORTS 3 152 153 #define A_MAC_CHANNEL_BASE(macnum) (A_MAC_BASE_0 + MAC_SPACING * (macnum)) 154 155 #define A_MAC_REGISTER(macnum,reg) \ 156 (A_MAC_BASE_0 + MAC_SPACING * (macnum) + (reg)) 157 158 159 #define R_MAC_DMA_CHANNELS 0x800 /* Relative to A_MAC_CHANNEL_BASE */ 160 161 #define A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) \ 162 ((A_MAC_CHANNEL_BASE(macnum)) + \ 163 R_MAC_DMA_CHANNELS + \ 164 (MAC_DMA_TXRX_SPACING*(txrx)) + \ 165 (MAC_DMA_CHANNEL_SPACING*(chan))) 166 167 #define R_MAC_DMA_CHANNEL_BASE(txrx,chan) \ 168 (R_MAC_DMA_CHANNELS + \ 169 (MAC_DMA_TXRX_SPACING*(txrx)) + \ 170 (MAC_DMA_CHANNEL_SPACING*(chan))) 171 172 #define A_MAC_DMA_REGISTER(macnum,txrx,chan,reg) \ 173 (A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) + \ 174 (reg)) 175 176 #define R_MAC_DMA_REGISTER(txrx,chan,reg) \ 177 (R_MAC_DMA_CHANNEL_BASE(txrx,chan) + \ 178 (reg)) 179 180 /* 181 * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE 182 */ 183 184 #define R_MAC_DMA_CONFIG0 0x00000000 185 #define R_MAC_DMA_CONFIG1 0x00000008 186 #define R_MAC_DMA_DSCR_BASE 0x00000010 187 #define R_MAC_DMA_DSCR_CNT 0x00000018 188 #define R_MAC_DMA_CUR_DSCRA 0x00000020 189 #define R_MAC_DMA_CUR_DSCRB 0x00000028 190 #define R_MAC_DMA_CUR_DSCRADDR 0x00000030 191 192 /* 193 * RMON Counters 194 */ 195 196 #define R_MAC_RMON_TX_BYTES 0x00000000 197 #define R_MAC_RMON_COLLISIONS 0x00000008 198 #define R_MAC_RMON_LATE_COL 0x00000010 199 #define R_MAC_RMON_EX_COL 0x00000018 200 #define R_MAC_RMON_FCS_ERROR 0x00000020 201 #define R_MAC_RMON_TX_ABORT 0x00000028 202 /* Counter #6 (0x30) now reserved */ 203 #define R_MAC_RMON_TX_BAD 0x00000038 204 #define R_MAC_RMON_TX_GOOD 0x00000040 205 #define R_MAC_RMON_TX_RUNT 0x00000048 206 #define R_MAC_RMON_TX_OVERSIZE 0x00000050 207 #define R_MAC_RMON_RX_BYTES 0x00000080 208 #define R_MAC_RMON_RX_MCAST 0x00000088 209 #define R_MAC_RMON_RX_BCAST 0x00000090 210 #define R_MAC_RMON_RX_BAD 0x00000098 211 #define R_MAC_RMON_RX_GOOD 0x000000A0 212 #define R_MAC_RMON_RX_RUNT 0x000000A8 213 #define R_MAC_RMON_RX_OVERSIZE 0x000000B0 214 #define R_MAC_RMON_RX_FCS_ERROR 0x000000B8 215 #define R_MAC_RMON_RX_LENGTH_ERROR 0x000000C0 216 #define R_MAC_RMON_RX_CODE_ERROR 0x000000C8 217 #define R_MAC_RMON_RX_ALIGN_ERROR 0x000000D0 218 219 /* Updated to spec 0.2 */ 220 #define R_MAC_CFG 0x00000100 221 #define R_MAC_THRSH_CFG 0x00000108 222 #define R_MAC_VLANTAG 0x00000110 223 #define R_MAC_FRAMECFG 0x00000118 224 #define R_MAC_EOPCNT 0x00000120 225 #define R_MAC_FIFO_PTRS 0x00000130 226 #define R_MAC_ADFILTER_CFG 0x00000200 227 #define R_MAC_ETHERNET_ADDR 0x00000208 228 #define R_MAC_PKT_TYPE 0x00000210 229 #define R_MAC_HASH_BASE 0x00000240 230 #define R_MAC_ADDR_BASE 0x00000280 231 #define R_MAC_CHLO0_BASE 0x00000300 232 #define R_MAC_CHUP0_BASE 0x00000320 233 #define R_MAC_ENABLE 0x00000400 234 #define R_MAC_STATUS 0x00000408 235 #define R_MAC_INT_MASK 0x00000410 236 #define R_MAC_TXD_CTL 0x00000420 237 #define R_MAC_MDIO 0x00000428 238 #define R_MAC_DEBUG_STATUS 0x00000448 239 240 #define MAC_HASH_COUNT 8 241 #define MAC_ADDR_COUNT 8 242 #define MAC_CHMAP_COUNT 4 243 244 245 /* ********************************************************************* 246 * DUART Registers 247 ********************************************************************* */ 248 249 250 #define R_DUART_NUM_PORTS 2 251 252 #define A_DUART 0x0010060000 253 254 #define A_DUART_REG(r) 255 256 #define DUART_CHANREG_SPACING 0x100 257 #define A_DUART_CHANREG(chan,reg) \ 258 (A_DUART + DUART_CHANREG_SPACING * (chan) + (reg)) 259 #define R_DUART_CHANREG(chan,reg) \ 260 (DUART_CHANREG_SPACING*(chan) + (reg)) 261 262 #define R_DUART_MODE_REG_1 0x100 263 #define R_DUART_MODE_REG_2 0x110 264 #define R_DUART_STATUS 0x120 265 #define R_DUART_CLK_SEL 0x130 266 #define R_DUART_CMD 0x150 267 #define R_DUART_RX_HOLD 0x160 268 #define R_DUART_TX_HOLD 0x170 269 270 /* 271 * The IMR and ISR can't be addressed with A_DUART_CHANREG, 272 * so use this macro instead. 273 */ 274 275 #define R_DUART_AUX_CTRL 0x310 276 #define R_DUART_ISR_A 0x320 277 #define R_DUART_IMR_A 0x330 278 #define R_DUART_ISR_B 0x340 279 #define R_DUART_IMR_B 0x350 280 #define R_DUART_OUT_PORT 0x360 281 #define R_DUART_OPCR 0x370 282 283 #define R_DUART_SET_OPR 0x3B0 284 #define R_DUART_CLEAR_OPR 0x3C0 285 286 #define DUART_IMRISR_SPACING 0x20 287 288 #define R_DUART_IMRREG(chan) \ 289 (R_DUART_IMR_A + (chan) * DUART_IMRISR_SPACING) 290 #define R_DUART_ISRREG(chan) \ 291 (R_DUART_ISR_A + (chan) * DUART_IMRISR_SPACING) 292 293 #define A_DUART_IMRREG(chan) (A_DUART + R_DUART_IMRREG(chan)) 294 #define A_DUART_ISRREG(chan) (A_DUART + R_DUART_ISRREG(chan)) 295 296 /* 297 * These constants are the absolute addresses. 298 */ 299 300 #define A_DUART_MODE_REG_1_A 0x0010060100 301 #define A_DUART_MODE_REG_2_A 0x0010060110 302 #define A_DUART_STATUS_A 0x0010060120 303 #define A_DUART_CLK_SEL_A 0x0010060130 304 #define A_DUART_CMD_A 0x0010060150 305 #define A_DUART_RX_HOLD_A 0x0010060160 306 #define A_DUART_TX_HOLD_A 0x0010060170 307 308 #define A_DUART_MODE_REG_1_B 0x0010060200 309 #define A_DUART_MODE_REG_2_B 0x0010060210 310 #define A_DUART_STATUS_B 0x0010060220 311 #define A_DUART_CLK_SEL_B 0x0010060230 312 #define A_DUART_CMD_B 0x0010060250 313 #define A_DUART_RX_HOLD_B 0x0010060260 314 #define A_DUART_TX_HOLD_B 0x0010060270 315 316 #define A_DUART_INPORT_CHNG 0x0010060300 317 #define A_DUART_AUX_CTRL 0x0010060310 318 #define A_DUART_ISR_A 0x0010060320 319 #define A_DUART_IMR_A 0x0010060330 320 #define A_DUART_ISR_B 0x0010060340 321 #define A_DUART_IMR_B 0x0010060350 322 #define A_DUART_OUT_PORT 0x0010060360 323 #define A_DUART_OPCR 0x0010060370 324 #define A_DUART_IN_PORT 0x0010060380 325 #define A_DUART_ISR 0x0010060390 326 #define A_DUART_IMR 0x00100603A0 327 #define A_DUART_SET_OPR 0x00100603B0 328 #define A_DUART_CLEAR_OPR 0x00100603C0 329 #define A_DUART_INPORT_CHNG_A 0x00100603D0 330 #define A_DUART_INPORT_CHNG_B 0x00100603E0 331 332 /* ********************************************************************* 333 * Synchronous Serial Registers 334 ********************************************************************* */ 335 336 337 #define A_SER_BASE_0 0x0010060400 338 #define A_SER_BASE_1 0x0010060800 339 #define SER_SPACING 0x400 340 341 #define SER_DMA_TXRX_SPACING 0x80 342 343 #define SER_NUM_PORTS 2 344 345 #define A_SER_CHANNEL_BASE(sernum) \ 346 (A_SER_BASE_0 + \ 347 SER_SPACING*(sernum)) 348 349 #define A_SER_REGISTER(sernum,reg) \ 350 (A_SER_BASE_0 + \ 351 SER_SPACING*(sernum) + (reg)) 352 353 354 #define R_SER_DMA_CHANNELS 0 /* Relative to A_SER_BASE_x */ 355 356 #define A_SER_DMA_CHANNEL_BASE(sernum,txrx) \ 357 ((A_SER_CHANNEL_BASE(sernum)) + \ 358 R_SER_DMA_CHANNELS + \ 359 (SER_DMA_TXRX_SPACING*(txrx))) 360 361 #define A_SER_DMA_REGISTER(sernum,txrx,reg) \ 362 (A_SER_DMA_CHANNEL_BASE(sernum,txrx) + \ 363 (reg)) 364 365 366 /* 367 * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE 368 */ 369 370 #define R_SER_DMA_CONFIG0 0x00000000 371 #define R_SER_DMA_CONFIG1 0x00000008 372 #define R_SER_DMA_DSCR_BASE 0x00000010 373 #define R_SER_DMA_DSCR_CNT 0x00000018 374 #define R_SER_DMA_CUR_DSCRA 0x00000020 375 #define R_SER_DMA_CUR_DSCRB 0x00000028 376 #define R_SER_DMA_CUR_DSCRADDR 0x00000030 377 378 #define R_SER_DMA_CONFIG0_RX 0x00000000 379 #define R_SER_DMA_CONFIG1_RX 0x00000008 380 #define R_SER_DMA_DSCR_BASE_RX 0x00000010 381 #define R_SER_DMA_DSCR_COUNT_RX 0x00000018 382 #define R_SER_DMA_CUR_DSCR_A_RX 0x00000020 383 #define R_SER_DMA_CUR_DSCR_B_RX 0x00000028 384 #define R_SER_DMA_CUR_DSCR_ADDR_RX 0x00000030 385 386 #define R_SER_DMA_CONFIG0_TX 0x00000080 387 #define R_SER_DMA_CONFIG1_TX 0x00000088 388 #define R_SER_DMA_DSCR_BASE_TX 0x00000090 389 #define R_SER_DMA_DSCR_COUNT_TX 0x00000098 390 #define R_SER_DMA_CUR_DSCR_A_TX 0x000000A0 391 #define R_SER_DMA_CUR_DSCR_B_TX 0x000000A8 392 #define R_SER_DMA_CUR_DSCR_ADDR_TX 0x000000B0 393 394 #define R_SER_MODE 0x00000100 395 #define R_SER_MINFRM_SZ 0x00000108 396 #define R_SER_MAXFRM_SZ 0x00000110 397 #define R_SER_ADDR 0x00000118 398 #define R_SER_USR0_ADDR 0x00000120 399 #define R_SER_USR1_ADDR 0x00000128 400 #define R_SER_USR2_ADDR 0x00000130 401 #define R_SER_USR3_ADDR 0x00000138 402 #define R_SER_CMD 0x00000140 403 #define R_SER_TX_RD_THRSH 0x00000160 404 #define R_SER_TX_WR_THRSH 0x00000168 405 #define R_SER_RX_RD_THRSH 0x00000170 406 #define R_SER_LINE_MODE 0x00000178 407 #define R_SER_DMA_ENABLE 0x00000180 408 #define R_SER_INT_MASK 0x00000190 409 #define R_SER_STATUS 0x00000188 410 #define R_SER_STATUS_DEBUG 0x000001A8 411 #define R_SER_RX_TABLE_BASE 0x00000200 412 #define SER_RX_TABLE_COUNT 16 413 #define R_SER_TX_TABLE_BASE 0x00000300 414 #define SER_TX_TABLE_COUNT 16 415 416 /* RMON Counters */ 417 #define R_SER_RMON_TX_BYTE_LO 0x000001C0 418 #define R_SER_RMON_TX_BYTE_HI 0x000001C8 419 #define R_SER_RMON_RX_BYTE_LO 0x000001D0 420 #define R_SER_RMON_RX_BYTE_HI 0x000001D8 421 #define R_SER_RMON_TX_UNDERRUN 0x000001E0 422 #define R_SER_RMON_RX_OVERFLOW 0x000001E8 423 #define R_SER_RMON_RX_ERRORS 0x000001F0 424 #define R_SER_RMON_RX_BADADDR 0x000001F8 425 426 /* ********************************************************************* 427 * Generic Bus Registers 428 ********************************************************************* */ 429 430 #define IO_EXT_CFG_COUNT 8 431 432 #define A_IO_EXT_BASE 0x0010061000 433 #define A_IO_EXT_REG(r) (A_IO_EXT_BASE + (r)) 434 435 #define A_IO_EXT_CFG_BASE 0x0010061000 436 #define A_IO_EXT_MULT_SIZE_BASE 0x0010061100 437 #define A_IO_EXT_START_ADDR_BASE 0x0010061200 438 #define A_IO_EXT_TIME_CFG0_BASE 0x0010061600 439 #define A_IO_EXT_TIME_CFG1_BASE 0x0010061700 440 441 #define IO_EXT_REGISTER_SPACING 8 442 #define A_IO_EXT_CS_BASE(cs) \ 443 (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs)) 444 #define R_IO_EXT_REG(reg,cs) ((cs) * IO_EXT_REGISTER_SPACING + (reg)) 445 446 #define R_IO_EXT_CFG 0x0000 447 #define R_IO_EXT_MULT_SIZE 0x0100 448 #define R_IO_EXT_START_ADDR 0x0200 449 #define R_IO_EXT_TIME_CFG0 0x0600 450 #define R_IO_EXT_TIME_CFG1 0x0700 451 452 453 #define A_IO_INTERRUPT_STATUS 0x0010061A00 454 #define A_IO_INTERRUPT_DATA0 0x0010061A10 455 #define A_IO_INTERRUPT_DATA1 0x0010061A18 456 #define A_IO_INTERRUPT_DATA2 0x0010061A20 457 #define A_IO_INTERRUPT_DATA3 0x0010061A28 458 #define A_IO_INTERRUPT_ADDR0 0x0010061A30 459 #define A_IO_INTERRUPT_ADDR1 0x0010061A40 460 #define A_IO_INTERRUPT_PARITY 0x0010061A50 461 #define A_IO_PCMCIA_CFG 0x0010061A60 462 #define A_IO_PCMCIA_STATUS 0x0010061A70 463 #define A_IO_DRIVE_0 0x0010061300 464 #define A_IO_DRIVE_1 0x0010061308 465 #define A_IO_DRIVE_2 0x0010061310 466 #define A_IO_DRIVE_3 0x0010061318 467 468 #define R_IO_INTERRUPT_STATUS 0x0A00 469 #define R_IO_INTERRUPT_DATA0 0x0A10 470 #define R_IO_INTERRUPT_DATA1 0x0A18 471 #define R_IO_INTERRUPT_DATA2 0x0A20 472 #define R_IO_INTERRUPT_DATA3 0x0A28 473 #define R_IO_INTERRUPT_ADDR0 0x0A30 474 #define R_IO_INTERRUPT_ADDR1 0x0A40 475 #define R_IO_INTERRUPT_PARITY 0x0A50 476 #define R_IO_PCMCIA_CFG 0x0A60 477 #define R_IO_PCMCIA_STATUS 0x0A70 478 479 /* ********************************************************************* 480 * GPIO Registers 481 ********************************************************************* */ 482 483 #define A_GPIO_CLR_EDGE 0x0010061A80 484 #define A_GPIO_INT_TYPE 0x0010061A88 485 #define A_GPIO_INPUT_INVERT 0x0010061A90 486 #define A_GPIO_GLITCH 0x0010061A98 487 #define A_GPIO_READ 0x0010061AA0 488 #define A_GPIO_DIRECTION 0x0010061AA8 489 #define A_GPIO_PIN_CLR 0x0010061AB0 490 #define A_GPIO_PIN_SET 0x0010061AB8 491 492 #define A_GPIO_BASE 0x0010061A80 493 494 #define R_GPIO_CLR_EDGE 0x00 495 #define R_GPIO_INT_TYPE 0x08 496 #define R_GPIO_INPUT_INVERT 0x10 497 #define R_GPIO_GLITCH 0x18 498 #define R_GPIO_READ 0x20 499 #define R_GPIO_DIRECTION 0x28 500 #define R_GPIO_PIN_CLR 0x30 501 #define R_GPIO_PIN_SET 0x38 502 503 /* ********************************************************************* 504 * SMBus Registers 505 ********************************************************************* */ 506 507 #define A_SMB_XTRA_0 0x0010060000 508 #define A_SMB_XTRA_1 0x0010060008 509 #define A_SMB_FREQ_0 0x0010060010 510 #define A_SMB_FREQ_1 0x0010060018 511 #define A_SMB_STATUS_0 0x0010060020 512 #define A_SMB_STATUS_1 0x0010060028 513 #define A_SMB_CMD_0 0x0010060030 514 #define A_SMB_CMD_1 0x0010060038 515 #define A_SMB_START_0 0x0010060040 516 #define A_SMB_START_1 0x0010060048 517 #define A_SMB_DATA_0 0x0010060050 518 #define A_SMB_DATA_1 0x0010060058 519 #define A_SMB_CONTROL_0 0x0010060060 520 #define A_SMB_CONTROL_1 0x0010060068 521 #define A_SMB_PEC_0 0x0010060070 522 #define A_SMB_PEC_1 0x0010060078 523 524 #define A_SMB_0 0x0010060000 525 #define A_SMB_1 0x0010060008 526 #define SMB_REGISTER_SPACING 0x8 527 #define A_SMB_BASE(idx) (A_SMB_0 + (idx) * SMB_REGISTER_SPACING) 528 #define A_SMB_REGISTER(idx,reg) (A_SMB_BASE(idx) + (reg)) 529 530 #define R_SMB_XTRA 0x0000000000 531 #define R_SMB_FREQ 0x0000000010 532 #define R_SMB_STATUS 0x0000000020 533 #define R_SMB_CMD 0x0000000030 534 #define R_SMB_START 0x0000000040 535 #define R_SMB_DATA 0x0000000050 536 #define R_SMB_CONTROL 0x0000000060 537 #define R_SMB_PEC 0x0000000070 538 539 /* ********************************************************************* 540 * Timer Registers 541 ********************************************************************* */ 542 543 /* 544 * Watchdog timers 545 */ 546 547 #define A_SCD_WDOG_0 0x0010020050 548 #define A_SCD_WDOG_1 0x0010020150 549 #define SCD_WDOG_SPACING 0x100 550 #define SCD_NUM_WDOGS 2 551 #define A_SCD_WDOG_BASE(w) (A_SCD_WDOG_0 + SCD_WDOG_SPACING * (w)) 552 #define A_SCD_WDOG_REGISTER(w,r) (A_SCD_WDOG_BASE(w) + (r)) 553 554 #define R_SCD_WDOG_INIT 0x0000000000 555 #define R_SCD_WDOG_CNT 0x0000000008 556 #define R_SCD_WDOG_CFG 0x0000000010 557 558 #define A_SCD_WDOG_INIT_0 0x0010020050 559 #define A_SCD_WDOG_CNT_0 0x0010020058 560 #define A_SCD_WDOG_CFG_0 0x0010020060 561 562 #define A_SCD_WDOG_INIT_1 0x0010020150 563 #define A_SCD_WDOG_CNT_1 0x0010020158 564 #define A_SCD_WDOG_CFG_1 0x0010020160 565 566 /* 567 * Generic timers 568 */ 569 570 #define A_SCD_TIMER_0 0x0010020070 571 #define A_SCD_TIMER_1 0x0010020078 572 #define A_SCD_TIMER_2 0x0010020170 573 #define A_SCD_TIMER_3 0x0010020178 574 #define SCD_NUM_TIMERS 4 575 #define A_SCD_TIMER_BASE(w) \ 576 (A_SCD_TIMER_0 + 0x08 * ((w) & 1) + 0x100 * (((w) & 2) >> 1)) 577 #define A_SCD_TIMER_REGISTER(w,r) (A_SCD_TIMER_BASE(w) + (r)) 578 579 #define R_SCD_TIMER_INIT 0x0000000000 580 #define R_SCD_TIMER_CNT 0x0000000010 581 #define R_SCD_TIMER_CFG 0x0000000020 582 583 #define A_SCD_TIMER_INIT_0 0x0010020070 584 #define A_SCD_TIMER_CNT_0 0x0010020080 585 #define A_SCD_TIMER_CFG_0 0x0010020090 586 587 #define A_SCD_TIMER_INIT_1 0x0010020078 588 #define A_SCD_TIMER_CNT_1 0x0010020088 589 #define A_SCD_TIMER_CFG_1 0x0010020098 590 591 #define A_SCD_TIMER_INIT_2 0x0010020170 592 #define A_SCD_TIMER_CNT_2 0x0010020180 593 #define A_SCD_TIMER_CFG_2 0x0010020190 594 595 #define A_SCD_TIMER_INIT_3 0x0010020178 596 #define A_SCD_TIMER_CNT_3 0x0010020188 597 #define A_SCD_TIMER_CFG_3 0x0010020198 598 599 /* ********************************************************************* 600 * System Control Registers 601 ********************************************************************* */ 602 603 #define A_SCD_SYSTEM_REVISION 0x0010020000 604 #define A_SCD_SYSTEM_CFG 0x0010020008 605 606 #define A_SCD_SCRATCH 0x0010020C10 /* PASS2 */ 607 608 /* ********************************************************************* 609 * System Address Trap Registers 610 ********************************************************************* */ 611 612 #define A_ADDR_TRAP_INDEX 0x00100200B0 613 #define A_ADDR_TRAP_REG 0x00100200B8 614 #define A_ADDR_TRAP_UP_0 0x0010020400 615 #define A_ADDR_TRAP_UP_1 0x0010020408 616 #define A_ADDR_TRAP_UP_2 0x0010020410 617 #define A_ADDR_TRAP_UP_3 0x0010020418 618 #define A_ADDR_TRAP_DOWN_0 0x0010020420 619 #define A_ADDR_TRAP_DOWN_1 0x0010020428 620 #define A_ADDR_TRAP_DOWN_2 0x0010020430 621 #define A_ADDR_TRAP_DOWN_3 0x0010020438 622 #define A_ADDR_TRAP_CFG_0 0x0010020440 623 #define A_ADDR_TRAP_CFG_1 0x0010020448 624 #define A_ADDR_TRAP_CFG_2 0x0010020450 625 #define A_ADDR_TRAP_CFG_3 0x0010020458 626 627 628 /* ********************************************************************* 629 * System Interrupt Mapper Registers 630 ********************************************************************* */ 631 632 #define A_IMR_CPU0_BASE 0x0010020000 633 #define A_IMR_CPU1_BASE 0x0010022000 634 #define IMR_REGISTER_SPACING 0x2000 635 636 #define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING) 637 #define A_IMR_REGISTER(cpu,reg) (A_IMR_MAPPER(cpu)+(reg)) 638 639 #define R_IMR_INTERRUPT_DIAG 0x0010 640 #define R_IMR_INTERRUPT_MASK 0x0028 641 #define R_IMR_INTERRUPT_TRACE 0x0038 642 #define R_IMR_INTERRUPT_SOURCE_STATUS 0x0040 643 #define R_IMR_LDT_INTERRUPT_SET 0x0048 644 #define R_IMR_LDT_INTERRUPT 0x0018 645 #define R_IMR_LDT_INTERRUPT_CLR 0x0020 646 #define R_IMR_MAILBOX_CPU 0x00c0 647 #define R_IMR_ALIAS_MAILBOX_CPU 0x1000 648 #define R_IMR_MAILBOX_SET_CPU 0x00C8 649 #define R_IMR_ALIAS_MAILBOX_SET_CPU 0x1008 650 #define R_IMR_MAILBOX_CLR_CPU 0x00D0 651 #define R_IMR_INTERRUPT_STATUS_BASE 0x0100 652 #define R_IMR_INTERRUPT_STATUS_COUNT 7 653 #define R_IMR_INTERRUPT_MAP_BASE 0x0200 654 #define R_IMR_INTERRUPT_MAP_COUNT 64 655 656 /* ********************************************************************* 657 * System Performance Counter Registers 658 ********************************************************************* */ 659 660 #define A_SCD_PERF_CNT_CFG 0x00100204C0 661 #define A_SCD_PERF_CNT_0 0x00100204D0 662 #define A_SCD_PERF_CNT_1 0x00100204D8 663 #define A_SCD_PERF_CNT_2 0x00100204E0 664 #define A_SCD_PERF_CNT_3 0x00100204E8 665 666 /* ********************************************************************* 667 * System Bus Watcher Registers 668 ********************************************************************* */ 669 670 #define A_SCD_BUS_ERR_STATUS 0x0010020880 671 #define A_BUS_ERR_DATA_0 0x00100208A0 672 #define A_BUS_ERR_DATA_1 0x00100208A8 673 #define A_BUS_ERR_DATA_2 0x00100208B0 674 #define A_BUS_ERR_DATA_3 0x00100208B8 675 #define A_BUS_L2_ERRORS 0x00100208C0 676 #define A_BUS_MEM_IO_ERRORS 0x00100208C8 677 678 /* ********************************************************************* 679 * System Debug Controller Registers 680 ********************************************************************* */ 681 682 #define A_SCD_JTAG_BASE 0x0010000000 683 684 /* ********************************************************************* 685 * System Trace Buffer Registers 686 ********************************************************************* */ 687 688 #define A_SCD_TRACE_CFG 0x0010020A00 689 #define A_SCD_TRACE_READ 0x0010020A08 690 #define A_SCD_TRACE_EVENT_0 0x0010020A20 691 #define A_SCD_TRACE_EVENT_1 0x0010020A28 692 #define A_SCD_TRACE_EVENT_2 0x0010020A30 693 #define A_SCD_TRACE_EVENT_3 0x0010020A38 694 #define A_SCD_TRACE_SEQUENCE_0 0x0010020A40 695 #define A_SCD_TRACE_SEQUENCE_1 0x0010020A48 696 #define A_SCD_TRACE_SEQUENCE_2 0x0010020A50 697 #define A_SCD_TRACE_SEQUENCE_3 0x0010020A58 698 #define A_SCD_TRACE_EVENT_4 0x0010020A60 699 #define A_SCD_TRACE_EVENT_5 0x0010020A68 700 #define A_SCD_TRACE_EVENT_6 0x0010020A70 701 #define A_SCD_TRACE_EVENT_7 0x0010020A78 702 #define A_SCD_TRACE_SEQUENCE_4 0x0010020A80 703 #define A_SCD_TRACE_SEQUENCE_5 0x0010020A88 704 #define A_SCD_TRACE_SEQUENCE_6 0x0010020A90 705 #define A_SCD_TRACE_SEQUENCE_7 0x0010020A98 706 707 /* ********************************************************************* 708 * System Generic DMA Registers 709 ********************************************************************* */ 710 711 #define A_DM_0 0x0010020B00 712 #define A_DM_1 0x0010020B20 713 #define A_DM_2 0x0010020B40 714 #define A_DM_3 0x0010020B60 715 #define DM_REGISTER_SPACING 0x20 716 #define DM_NUM_CHANNELS 4 717 #define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING)) 718 #define A_DM_REGISTER(idx,reg) (A_DM_BASE(idx) + (reg)) 719 720 #define R_DM_DSCR_BASE 0x0000000000 721 #define R_DM_DSCR_COUNT 0x0000000008 722 #define R_DM_CUR_DSCR_ADDR 0x0000000010 723 #define R_DM_DSCR_BASE_DEBUG 0x0000000018 724 725 726 /* ********************************************************************* 727 * Physical Address Map 728 ********************************************************************* */ 729 730 #define A_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) 731 #define A_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) 732 #define A_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) 733 #define A_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000) 734 #define A_PHYS_GENBUS _SB_MAKE64(0x0010090000) 735 #define A_PHYS_GENBUS_END _SB_MAKE64(0x0040000000) 736 #define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000) 737 #define A_PHYS_LDTPCI_IO_MATCH_BITS_32 _SB_MAKE64(0x0060000000) 738 #define A_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000) 739 #define A_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000) 740 #define A_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000) 741 #define A_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000) 742 #define A_PHYS_LDT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000) 743 #define A_PHYS_LDTPCI_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000) 744 #define A_PHYS_LDTPCI_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000) 745 #define A_PHYS_LDT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000) 746 #define A_PHYS_LDTPCI_IO_MATCH_BITS _SB_MAKE64(0x00FC000000) 747 #define A_PHYS_LDTPCI_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000) 748 #define A_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000) 749 #define A_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024)) 750 #define A_PHYS_LDT_EXP _SB_MAKE64(0x8000000000) 751 #define A_PHYS_PCI_FULLACCESS_BYTES _SB_MAKE64(0xF000000000) 752 #define A_PHYS_PCI_FULLACCESS_BITS _SB_MAKE64(0xF100000000) 753 #define A_PHYS_RESERVED _SB_MAKE64(0xF200000000) 754 #define A_PHYS_RESERVED_SPECIAL_LDT _SB_MAKE64(0xFD00000000) 755 756 #define A_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000) 757 #define PHYS_L2CACHE_NUM_WAYS 4 758 #define A_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000080000) 759 #define A_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0180000) 760 #define A_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D01A0000) 761 #define A_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D01C0000) 762 #define A_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D01E0000) 763 764 #endif /* _SB1250_REGS_H */ 765
Indexes created Thu Oct 02 10:09:58 GMT 2025