sb1250_regs.h revision 1.4
1 /* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * Register Definitions File: sb1250_regs.h 5 * 6 * This module contains the addresses of the on-chip peripherals 7 * on the SB1250. 8 * 9 * SB1250 specification level: 01/02/2002 10 * 11 * Author: Mitch Lichtenberg (mpl (at) broadcom.com) 12 * 13 ********************************************************************* 14 * 15 * Copyright 2000,2001 16 * Broadcom Corporation. All rights reserved. 17 * 18 * This software is furnished under license and may be used and 19 * copied only in accordance with the following terms and 20 * conditions. Subject to these conditions, you may download, 21 * copy, install, use, modify and distribute modified or unmodified 22 * copies of this software in source and/or binary form. No title 23 * or ownership is transferred hereby. 24 * 25 * 1) Any source code used, modified or distributed must reproduce 26 * and retain this copyright notice and list of conditions as 27 * they appear in the source file. 28 * 29 * 2) No right is granted to use any trade name, trademark, or 30 * logo of Broadcom Corporation. Neither the "Broadcom 31 * Corporation" name nor any trademark or logo of Broadcom 32 * Corporation may be used to endorse or promote products 33 * derived from this software without the prior written 34 * permission of Broadcom Corporation. 35 * 36 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 37 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 38 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 39 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 40 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 41 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 42 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 43 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 44 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 45 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 46 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 47 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 48 * THE POSSIBILITY OF SUCH DAMAGE. 49 ********************************************************************* */ 50 51 52 #ifndef _SB1250_REGS_H 53 #define _SB1250_REGS_H 54 55 #include "sb1250_defs.h" 56 57 58 /* ********************************************************************* 59 * Some general notes: 60 * 61 * For the most part, when there is more than one peripheral 62 * of the same type on the SOC, the constants below will be 63 * offsets from the base of each peripheral. For example, 64 * the MAC registers are described as offsets from the first 65 * MAC register, and there will be a MAC_REGISTER() macro 66 * to calculate the base address of a given MAC. 67 * 68 * The information in this file is based on the SB1250 SOC 69 * manual version 0.2, July 2000. 70 ********************************************************************* */ 71 72 73 /* ********************************************************************* 74 * Memory Controller Registers 75 ********************************************************************* */ 76 77 #define A_MC_BASE_0 0x0010051000 78 #define A_MC_BASE_1 0x0010052000 79 #define MC_REGISTER_SPACING 0x1000 80 81 #define A_MC_BASE(ctlid) ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0) 82 #define A_MC_REGISTER(ctlid,reg) (A_MC_BASE(ctlid)+(reg)) 83 84 #define R_MC_CONFIG 0x0000000100 85 #define R_MC_DRAMCMD 0x0000000120 86 #define R_MC_DRAMMODE 0x0000000140 87 #define R_MC_TIMING1 0x0000000160 88 #define R_MC_TIMING2 0x0000000180 89 #define R_MC_CS_START 0x00000001A0 90 #define R_MC_CS_END 0x00000001C0 91 #define R_MC_CS_INTERLEAVE 0x00000001E0 92 #define S_MC_CS_STARTEND 16 93 94 #define R_MC_CSX_BASE 0x0000000200 95 #define R_MC_CSX_ROW 0x0000000000 /* relative to CSX_BASE, above */ 96 #define R_MC_CSX_COL 0x0000000020 /* relative to CSX_BASE, above */ 97 #define R_MC_CSX_BA 0x0000000040 /* relative to CSX_BASE, above */ 98 #define MC_CSX_SPACING 0x0000000060 /* relative to CSX_BASE, above */ 99 100 #define R_MC_CS0_ROW 0x0000000200 101 #define R_MC_CS0_COL 0x0000000220 102 #define R_MC_CS0_BA 0x0000000240 103 #define R_MC_CS1_ROW 0x0000000260 104 #define R_MC_CS1_COL 0x0000000280 105 #define R_MC_CS1_BA 0x00000002A0 106 #define R_MC_CS2_ROW 0x00000002C0 107 #define R_MC_CS2_COL 0x00000002E0 108 #define R_MC_CS2_BA 0x0000000300 109 #define R_MC_CS3_ROW 0x0000000320 110 #define R_MC_CS3_COL 0x0000000340 111 #define R_MC_CS3_BA 0x0000000360 112 #define R_MC_CS_ATTR 0x0000000380 113 #define R_MC_TEST_DATA 0x0000000400 114 #define R_MC_TEST_ECC 0x0000000420 115 #define R_MC_MCLK_CFG 0x0000000500 116 117 /* ********************************************************************* 118 * L2 Cache Control Registers 119 ********************************************************************* */ 120 121 #define A_L2_READ_ADDRESS 0x0010040018 122 #define A_L2_EEC_ADDRESS 0x0010040038 123 #define A_L2_WAY_DISABLE 0x0010041000 124 #define A_L2_MAKEDISABLE(x) (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8)) 125 #define A_L2_MGMT_TAG_BASE 0x00D0000000 126 127 #define A_L2_CACHE_DISABLE 0x0010042000 /* PASS2 */ 128 #define A_L2_MAKECACHEDISABLE(x) (A_L2_CACHE_DISABLE | (((x)&0x0F) << 8)) /* PASS2 */ 129 #define A_L2_MISC_CONFIG 0x0010043000 /* PASS2 */ 130 131 132 /* ********************************************************************* 133 * PCI Interface Registers 134 ********************************************************************* */ 135 136 #define A_PCI_TYPE00_HEADER 0x00DE000000 137 #define A_PCI_TYPE01_HEADER 0x00DE000800 138 139 140 /* ********************************************************************* 141 * Ethernet DMA and MACs 142 ********************************************************************* */ 143 144 #define A_MAC_BASE_0 0x0010064000 145 #define A_MAC_BASE_1 0x0010065000 146 #define A_MAC_BASE_2 0x0010066000 147 148 #define MAC_SPACING 0x1000 149 #define MAC_DMA_TXRX_SPACING 0x0400 150 #define MAC_DMA_CHANNEL_SPACING 0x0100 151 #define DMA_RX 0 152 #define DMA_TX 1 153 #define MAC_NUM_DMACHAN 2 /* channels per direction */ 154 155 #define MAC_NUM_PORTS 3 156 157 #define A_MAC_CHANNEL_BASE(macnum) \ 158 (A_MAC_BASE_0 + \ 159 MAC_SPACING*(macnum)) 160 161 #define A_MAC_REGISTER(macnum,reg) \ 162 (A_MAC_BASE_0 + \ 163 MAC_SPACING*(macnum) + (reg)) 164 165 166 #define R_MAC_DMA_CHANNELS 0x800 /* Relative to A_MAC_CHANNEL_BASE */ 167 168 #define A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) \ 169 ((A_MAC_CHANNEL_BASE(macnum)) + \ 170 R_MAC_DMA_CHANNELS + \ 171 (MAC_DMA_TXRX_SPACING*(txrx)) + \ 172 (MAC_DMA_CHANNEL_SPACING*(chan))) 173 174 #define R_MAC_DMA_CHANNEL_BASE(txrx,chan) \ 175 (R_MAC_DMA_CHANNELS + \ 176 (MAC_DMA_TXRX_SPACING*(txrx)) + \ 177 (MAC_DMA_CHANNEL_SPACING*(chan))) 178 179 #define A_MAC_DMA_REGISTER(macnum,txrx,chan,reg) \ 180 (A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) + \ 181 (reg)) 182 183 #define R_MAC_DMA_REGISTER(txrx,chan,reg) \ 184 (R_MAC_DMA_CHANNEL_BASE(txrx,chan) + \ 185 (reg)) 186 187 /* 188 * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE 189 */ 190 191 #define R_MAC_DMA_CONFIG0 0x00000000 192 #define R_MAC_DMA_CONFIG1 0x00000008 193 #define R_MAC_DMA_DSCR_BASE 0x00000010 194 #define R_MAC_DMA_DSCR_CNT 0x00000018 195 #define R_MAC_DMA_CUR_DSCRA 0x00000020 196 #define R_MAC_DMA_CUR_DSCRB 0x00000028 197 #define R_MAC_DMA_CUR_DSCRADDR 0x00000030 198 199 /* 200 * RMON Counters 201 */ 202 203 #define R_MAC_RMON_TX_BYTES 0x00000000 204 #define R_MAC_RMON_COLLISIONS 0x00000008 205 #define R_MAC_RMON_LATE_COL 0x00000010 206 #define R_MAC_RMON_EX_COL 0x00000018 207 #define R_MAC_RMON_FCS_ERROR 0x00000020 208 #define R_MAC_RMON_TX_ABORT 0x00000028 209 /* Counter #6 (0x30) now reserved */ 210 #define R_MAC_RMON_TX_BAD 0x00000038 211 #define R_MAC_RMON_TX_GOOD 0x00000040 212 #define R_MAC_RMON_TX_RUNT 0x00000048 213 #define R_MAC_RMON_TX_OVERSIZE 0x00000050 214 #define R_MAC_RMON_RX_BYTES 0x00000080 215 #define R_MAC_RMON_RX_MCAST 0x00000088 216 #define R_MAC_RMON_RX_BCAST 0x00000090 217 #define R_MAC_RMON_RX_BAD 0x00000098 218 #define R_MAC_RMON_RX_GOOD 0x000000A0 219 #define R_MAC_RMON_RX_RUNT 0x000000A8 220 #define R_MAC_RMON_RX_OVERSIZE 0x000000B0 221 #define R_MAC_RMON_RX_FCS_ERROR 0x000000B8 222 #define R_MAC_RMON_RX_LENGTH_ERROR 0x000000C0 223 #define R_MAC_RMON_RX_CODE_ERROR 0x000000C8 224 #define R_MAC_RMON_RX_ALIGN_ERROR 0x000000D0 225 226 /* Updated to spec 0.2 */ 227 #define R_MAC_CFG 0x00000100 228 #define R_MAC_THRSH_CFG 0x00000108 229 #define R_MAC_VLANTAG 0x00000110 230 #define R_MAC_FRAMECFG 0x00000118 231 #define R_MAC_EOPCNT 0x00000120 232 #define R_MAC_FIFO_PTRS 0x00000130 233 #define R_MAC_ADFILTER_CFG 0x00000200 234 #define R_MAC_ETHERNET_ADDR 0x00000208 235 #define R_MAC_PKT_TYPE 0x00000210 236 #define R_MAC_HASH_BASE 0x00000240 237 #define R_MAC_ADDR_BASE 0x00000280 238 #define R_MAC_CHLO0_BASE 0x00000300 239 #define R_MAC_CHUP0_BASE 0x00000320 240 #define R_MAC_ENABLE 0x00000400 241 #define R_MAC_STATUS 0x00000408 242 #define R_MAC_INT_MASK 0x00000410 243 #define R_MAC_TXD_CTL 0x00000420 244 #define R_MAC_MDIO 0x00000428 245 #define R_MAC_STATUS1 0x00000430 /* PASS2 */ 246 #define R_MAC_DEBUG_STATUS 0x00000448 247 248 #define MAC_HASH_COUNT 8 249 #define MAC_ADDR_COUNT 8 250 #define MAC_CHMAP_COUNT 4 251 252 253 /* ********************************************************************* 254 * DUART Registers 255 ********************************************************************* */ 256 257 258 #define R_DUART_NUM_PORTS 2 259 260 #define A_DUART 0x0010060000 261 262 #define A_DUART_REG(r) 263 264 #define DUART_CHANREG_SPACING 0x100 265 #define A_DUART_CHANREG(chan,reg) (A_DUART + DUART_CHANREG_SPACING*(chan) + (reg)) 266 #define R_DUART_CHANREG(chan,reg) (DUART_CHANREG_SPACING*(chan) + (reg)) 267 268 #define R_DUART_MODE_REG_1 0x100 269 #define R_DUART_MODE_REG_2 0x110 270 #define R_DUART_STATUS 0x120 271 #define R_DUART_CLK_SEL 0x130 272 #define R_DUART_CMD 0x150 273 #define R_DUART_RX_HOLD 0x160 274 #define R_DUART_TX_HOLD 0x170 275 276 #define R_DUART_FULL_CTL 0x140 /* PASS2 */ 277 #define R_DUART_OPCR_X 0x180 /* PASS2 */ 278 #define R_DUART_AUXCTL_X 0x190 /* PASS2 */ 279 280 281 /* 282 * The IMR and ISR can't be addressed with A_DUART_CHANREG, 283 * so use this macro instead. 284 */ 285 286 #define R_DUART_AUX_CTRL 0x310 287 #define R_DUART_ISR_A 0x320 288 #define R_DUART_IMR_A 0x330 289 #define R_DUART_ISR_B 0x340 290 #define R_DUART_IMR_B 0x350 291 #define R_DUART_OUT_PORT 0x360 292 #define R_DUART_OPCR 0x370 293 294 #define R_DUART_SET_OPR 0x3B0 295 #define R_DUART_CLEAR_OPR 0x3C0 296 297 #define DUART_IMRISR_SPACING 0x20 298 299 #define R_DUART_IMRREG(chan) (R_DUART_IMR_A + (chan)*DUART_IMRISR_SPACING) 300 #define R_DUART_ISRREG(chan) (R_DUART_ISR_A + (chan)*DUART_IMRISR_SPACING) 301 302 #define A_DUART_IMRREG(chan) (A_DUART + R_DUART_IMRREG(chan)) 303 #define A_DUART_ISRREG(chan) (A_DUART + R_DUART_ISRREG(chan)) 304 305 306 307 308 /* 309 * These constants are the absolute addresses. 310 */ 311 312 #define A_DUART_MODE_REG_1_A 0x0010060100 313 #define A_DUART_MODE_REG_2_A 0x0010060110 314 #define A_DUART_STATUS_A 0x0010060120 315 #define A_DUART_CLK_SEL_A 0x0010060130 316 #define A_DUART_CMD_A 0x0010060150 317 #define A_DUART_RX_HOLD_A 0x0010060160 318 #define A_DUART_TX_HOLD_A 0x0010060170 319 320 #define A_DUART_MODE_REG_1_B 0x0010060200 321 #define A_DUART_MODE_REG_2_B 0x0010060210 322 #define A_DUART_STATUS_B 0x0010060220 323 #define A_DUART_CLK_SEL_B 0x0010060230 324 #define A_DUART_CMD_B 0x0010060250 325 #define A_DUART_RX_HOLD_B 0x0010060260 326 #define A_DUART_TX_HOLD_B 0x0010060270 327 328 #define A_DUART_INPORT_CHNG 0x0010060300 329 #define A_DUART_AUX_CTRL 0x0010060310 330 #define A_DUART_ISR_A 0x0010060320 331 #define A_DUART_IMR_A 0x0010060330 332 #define A_DUART_ISR_B 0x0010060340 333 #define A_DUART_IMR_B 0x0010060350 334 #define A_DUART_OUT_PORT 0x0010060360 335 #define A_DUART_OPCR 0x0010060370 336 #define A_DUART_IN_PORT 0x0010060380 337 #define A_DUART_ISR 0x0010060390 338 #define A_DUART_IMR 0x00100603A0 339 #define A_DUART_SET_OPR 0x00100603B0 340 #define A_DUART_CLEAR_OPR 0x00100603C0 341 #define A_DUART_INPORT_CHNG_A 0x00100603D0 342 #define A_DUART_INPORT_CHNG_B 0x00100603E0 343 344 #define A_DUART_FULL_CTL_A 0x0010060140 /* PASS2 */ 345 #define A_DUART_FULL_CTL_B 0x0010060240 /* PASS2 */ 346 347 #define A_DUART_OPCR_A 0x0010060180 /* PASS2 */ 348 #define A_DUART_OPCR_B 0x0010060280 /* PASS2 */ 349 350 #define A_DUART_INPORT_CHNG_DEBUG 0x00100603F0 /* PASS2 */ 351 352 353 /* ********************************************************************* 354 * Synchronous Serial Registers 355 ********************************************************************* */ 356 357 358 #define A_SER_BASE_0 0x0010060400 359 #define A_SER_BASE_1 0x0010060800 360 #define SER_SPACING 0x400 361 362 #define SER_DMA_TXRX_SPACING 0x80 363 364 #define SER_NUM_PORTS 2 365 366 #define A_SER_CHANNEL_BASE(sernum) \ 367 (A_SER_BASE_0 + \ 368 SER_SPACING*(sernum)) 369 370 #define A_SER_REGISTER(sernum,reg) \ 371 (A_SER_BASE_0 + \ 372 SER_SPACING*(sernum) + (reg)) 373 374 375 #define R_SER_DMA_CHANNELS 0 /* Relative to A_SER_BASE_x */ 376 377 #define A_SER_DMA_CHANNEL_BASE(sernum,txrx) \ 378 ((A_SER_CHANNEL_BASE(sernum)) + \ 379 R_SER_DMA_CHANNELS + \ 380 (SER_DMA_TXRX_SPACING*(txrx))) 381 382 #define A_SER_DMA_REGISTER(sernum,txrx,reg) \ 383 (A_SER_DMA_CHANNEL_BASE(sernum,txrx) + \ 384 (reg)) 385 386 387 /* 388 * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE 389 */ 390 391 #define R_SER_DMA_CONFIG0 0x00000000 392 #define R_SER_DMA_CONFIG1 0x00000008 393 #define R_SER_DMA_DSCR_BASE 0x00000010 394 #define R_SER_DMA_DSCR_CNT 0x00000018 395 #define R_SER_DMA_CUR_DSCRA 0x00000020 396 #define R_SER_DMA_CUR_DSCRB 0x00000028 397 #define R_SER_DMA_CUR_DSCRADDR 0x00000030 398 399 #define R_SER_DMA_CONFIG0_RX 0x00000000 400 #define R_SER_DMA_CONFIG1_RX 0x00000008 401 #define R_SER_DMA_DSCR_BASE_RX 0x00000010 402 #define R_SER_DMA_DSCR_COUNT_RX 0x00000018 403 #define R_SER_DMA_CUR_DSCR_A_RX 0x00000020 404 #define R_SER_DMA_CUR_DSCR_B_RX 0x00000028 405 #define R_SER_DMA_CUR_DSCR_ADDR_RX 0x00000030 406 407 #define R_SER_DMA_CONFIG0_TX 0x00000080 408 #define R_SER_DMA_CONFIG1_TX 0x00000088 409 #define R_SER_DMA_DSCR_BASE_TX 0x00000090 410 #define R_SER_DMA_DSCR_COUNT_TX 0x00000098 411 #define R_SER_DMA_CUR_DSCR_A_TX 0x000000A0 412 #define R_SER_DMA_CUR_DSCR_B_TX 0x000000A8 413 #define R_SER_DMA_CUR_DSCR_ADDR_TX 0x000000B0 414 415 #define R_SER_MODE 0x00000100 416 #define R_SER_MINFRM_SZ 0x00000108 417 #define R_SER_MAXFRM_SZ 0x00000110 418 #define R_SER_ADDR 0x00000118 419 #define R_SER_USR0_ADDR 0x00000120 420 #define R_SER_USR1_ADDR 0x00000128 421 #define R_SER_USR2_ADDR 0x00000130 422 #define R_SER_USR3_ADDR 0x00000138 423 #define R_SER_CMD 0x00000140 424 #define R_SER_TX_RD_THRSH 0x00000160 425 #define R_SER_TX_WR_THRSH 0x00000168 426 #define R_SER_RX_RD_THRSH 0x00000170 427 #define R_SER_LINE_MODE 0x00000178 428 #define R_SER_DMA_ENABLE 0x00000180 429 #define R_SER_INT_MASK 0x00000190 430 #define R_SER_STATUS 0x00000188 431 #define R_SER_STATUS_DEBUG 0x000001A8 432 #define R_SER_RX_TABLE_BASE 0x00000200 433 #define SER_RX_TABLE_COUNT 16 434 #define R_SER_TX_TABLE_BASE 0x00000300 435 #define SER_TX_TABLE_COUNT 16 436 437 /* RMON Counters */ 438 #define R_SER_RMON_TX_BYTE_LO 0x000001C0 439 #define R_SER_RMON_TX_BYTE_HI 0x000001C8 440 #define R_SER_RMON_RX_BYTE_LO 0x000001D0 441 #define R_SER_RMON_RX_BYTE_HI 0x000001D8 442 #define R_SER_RMON_TX_UNDERRUN 0x000001E0 443 #define R_SER_RMON_RX_OVERFLOW 0x000001E8 444 #define R_SER_RMON_RX_ERRORS 0x000001F0 445 #define R_SER_RMON_RX_BADADDR 0x000001F8 446 447 /* ********************************************************************* 448 * Generic Bus Registers 449 ********************************************************************* */ 450 451 #define IO_EXT_CFG_COUNT 8 452 453 #define A_IO_EXT_BASE 0x0010061000 454 #define A_IO_EXT_REG(r) (A_IO_EXT_BASE + (r)) 455 456 #define A_IO_EXT_CFG_BASE 0x0010061000 457 #define A_IO_EXT_MULT_SIZE_BASE 0x0010061100 458 #define A_IO_EXT_START_ADDR_BASE 0x0010061200 459 #define A_IO_EXT_TIME_CFG0_BASE 0x0010061600 460 #define A_IO_EXT_TIME_CFG1_BASE 0x0010061700 461 462 #define IO_EXT_REGISTER_SPACING 8 463 #define A_IO_EXT_CS_BASE(cs) (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs)) 464 #define R_IO_EXT_REG(reg,cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg)) 465 466 #define R_IO_EXT_CFG 0x0000 467 #define R_IO_EXT_MULT_SIZE 0x0100 468 #define R_IO_EXT_START_ADDR 0x0200 469 #define R_IO_EXT_TIME_CFG0 0x0600 470 #define R_IO_EXT_TIME_CFG1 0x0700 471 472 473 #define A_IO_INTERRUPT_STATUS 0x0010061A00 474 #define A_IO_INTERRUPT_DATA0 0x0010061A10 475 #define A_IO_INTERRUPT_DATA1 0x0010061A18 476 #define A_IO_INTERRUPT_DATA2 0x0010061A20 477 #define A_IO_INTERRUPT_DATA3 0x0010061A28 478 #define A_IO_INTERRUPT_ADDR0 0x0010061A30 479 #define A_IO_INTERRUPT_ADDR1 0x0010061A40 480 #define A_IO_INTERRUPT_PARITY 0x0010061A50 481 #define A_IO_PCMCIA_CFG 0x0010061A60 482 #define A_IO_PCMCIA_STATUS 0x0010061A70 483 #define A_IO_DRIVE_0 0x0010061300 484 #define A_IO_DRIVE_1 0x0010061308 485 #define A_IO_DRIVE_2 0x0010061310 486 #define A_IO_DRIVE_3 0x0010061318 487 488 #define R_IO_INTERRUPT_STATUS 0x0A00 489 #define R_IO_INTERRUPT_DATA0 0x0A10 490 #define R_IO_INTERRUPT_DATA1 0x0A18 491 #define R_IO_INTERRUPT_DATA2 0x0A20 492 #define R_IO_INTERRUPT_DATA3 0x0A28 493 #define R_IO_INTERRUPT_ADDR0 0x0A30 494 #define R_IO_INTERRUPT_ADDR1 0x0A40 495 #define R_IO_INTERRUPT_PARITY 0x0A50 496 #define R_IO_PCMCIA_CFG 0x0A60 497 #define R_IO_PCMCIA_STATUS 0x0A70 498 499 /* ********************************************************************* 500 * GPIO Registers 501 ********************************************************************* */ 502 503 #define A_GPIO_CLR_EDGE 0x0010061A80 504 #define A_GPIO_INT_TYPE 0x0010061A88 505 #define A_GPIO_INPUT_INVERT 0x0010061A90 506 #define A_GPIO_GLITCH 0x0010061A98 507 #define A_GPIO_READ 0x0010061AA0 508 #define A_GPIO_DIRECTION 0x0010061AA8 509 #define A_GPIO_PIN_CLR 0x0010061AB0 510 #define A_GPIO_PIN_SET 0x0010061AB8 511 512 #define A_GPIO_BASE 0x0010061A80 513 514 #define R_GPIO_CLR_EDGE 0x00 515 #define R_GPIO_INT_TYPE 0x08 516 #define R_GPIO_INPUT_INVERT 0x10 517 #define R_GPIO_GLITCH 0x18 518 #define R_GPIO_READ 0x20 519 #define R_GPIO_DIRECTION 0x28 520 #define R_GPIO_PIN_CLR 0x30 521 #define R_GPIO_PIN_SET 0x38 522 523 /* ********************************************************************* 524 * SMBus Registers 525 ********************************************************************* */ 526 527 #define A_SMB_XTRA_0 0x0010060000 528 #define A_SMB_XTRA_1 0x0010060008 529 #define A_SMB_FREQ_0 0x0010060010 530 #define A_SMB_FREQ_1 0x0010060018 531 #define A_SMB_STATUS_0 0x0010060020 532 #define A_SMB_STATUS_1 0x0010060028 533 #define A_SMB_CMD_0 0x0010060030 534 #define A_SMB_CMD_1 0x0010060038 535 #define A_SMB_START_0 0x0010060040 536 #define A_SMB_START_1 0x0010060048 537 #define A_SMB_DATA_0 0x0010060050 538 #define A_SMB_DATA_1 0x0010060058 539 #define A_SMB_CONTROL_0 0x0010060060 540 #define A_SMB_CONTROL_1 0x0010060068 541 #define A_SMB_PEC_0 0x0010060070 542 #define A_SMB_PEC_1 0x0010060078 543 544 #define A_SMB_0 0x0010060000 545 #define A_SMB_1 0x0010060008 546 #define SMB_REGISTER_SPACING 0x8 547 #define A_SMB_BASE(idx) (A_SMB_0+(idx)*SMB_REGISTER_SPACING) 548 #define A_SMB_REGISTER(idx,reg) (A_SMB_BASE(idx)+(reg)) 549 550 #define R_SMB_XTRA 0x0000000000 551 #define R_SMB_FREQ 0x0000000010 552 #define R_SMB_STATUS 0x0000000020 553 #define R_SMB_CMD 0x0000000030 554 #define R_SMB_START 0x0000000040 555 #define R_SMB_DATA 0x0000000050 556 #define R_SMB_CONTROL 0x0000000060 557 #define R_SMB_PEC 0x0000000070 558 559 /* ********************************************************************* 560 * Timer Registers 561 ********************************************************************* */ 562 563 /* 564 * Watchdog timers 565 */ 566 567 #define A_SCD_WDOG_0 0x0010020050 568 #define A_SCD_WDOG_1 0x0010020150 569 #define SCD_WDOG_SPACING 0x100 570 #define SCD_NUM_WDOGS 2 571 #define A_SCD_WDOG_BASE(w) (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w)) 572 #define A_SCD_WDOG_REGISTER(w,r) (A_SCD_WDOG_BASE(w) + (r)) 573 574 #define R_SCD_WDOG_INIT 0x0000000000 575 #define R_SCD_WDOG_CNT 0x0000000008 576 #define R_SCD_WDOG_CFG 0x0000000010 577 578 #define A_SCD_WDOG_INIT_0 0x0010020050 579 #define A_SCD_WDOG_CNT_0 0x0010020058 580 #define A_SCD_WDOG_CFG_0 0x0010020060 581 582 #define A_SCD_WDOG_INIT_1 0x0010020150 583 #define A_SCD_WDOG_CNT_1 0x0010020158 584 #define A_SCD_WDOG_CFG_1 0x0010020160 585 586 /* 587 * Generic timers 588 */ 589 590 #define A_SCD_TIMER_0 0x0010020070 591 #define A_SCD_TIMER_1 0x0010020078 592 #define A_SCD_TIMER_2 0x0010020170 593 #define A_SCD_TIMER_3 0x0010020178 594 #define SCD_NUM_TIMERS 4 595 #define A_SCD_TIMER_BASE(w) (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1)) 596 #define A_SCD_TIMER_REGISTER(w,r) (A_SCD_TIMER_BASE(w) + (r)) 597 598 #define R_SCD_TIMER_INIT 0x0000000000 599 #define R_SCD_TIMER_CNT 0x0000000010 600 #define R_SCD_TIMER_CFG 0x0000000020 601 602 #define A_SCD_TIMER_INIT_0 0x0010020070 603 #define A_SCD_TIMER_CNT_0 0x0010020080 604 #define A_SCD_TIMER_CFG_0 0x0010020090 605 606 #define A_SCD_TIMER_INIT_1 0x0010020078 607 #define A_SCD_TIMER_CNT_1 0x0010020088 608 #define A_SCD_TIMER_CFG_1 0x0010020098 609 610 #define A_SCD_TIMER_INIT_2 0x0010020170 611 #define A_SCD_TIMER_CNT_2 0x0010020180 612 #define A_SCD_TIMER_CFG_2 0x0010020190 613 614 #define A_SCD_TIMER_INIT_3 0x0010020178 615 #define A_SCD_TIMER_CNT_3 0x0010020188 616 #define A_SCD_TIMER_CFG_3 0x0010020198 617 618 #define A_SCD_SCRATCH 0x0010020C10 /* PASS2 */ 619 620 #define A_SCD_ZBBUS_CYCLE_COUNT 0x0010030000 /* PASS2 */ 621 #define A_SCD_ZBBUS_CYCLE_CP0 0x0010020C00 /* PASS2 */ 622 #define A_SCD_ZBBUS_CYCLE_CP1 0x0010020C08 /* PASS2 */ 623 624 625 /* ********************************************************************* 626 * System Control Registers 627 ********************************************************************* */ 628 629 #define A_SCD_SYSTEM_REVISION 0x0010020000 630 #define A_SCD_SYSTEM_CFG 0x0010020008 631 632 /* ********************************************************************* 633 * System Address Trap Registers 634 ********************************************************************* */ 635 636 #define A_ADDR_TRAP_INDEX 0x00100200B0 637 #define A_ADDR_TRAP_REG 0x00100200B8 638 #define A_ADDR_TRAP_UP_0 0x0010020400 639 #define A_ADDR_TRAP_UP_1 0x0010020408 640 #define A_ADDR_TRAP_UP_2 0x0010020410 641 #define A_ADDR_TRAP_UP_3 0x0010020418 642 #define A_ADDR_TRAP_DOWN_0 0x0010020420 643 #define A_ADDR_TRAP_DOWN_1 0x0010020428 644 #define A_ADDR_TRAP_DOWN_2 0x0010020430 645 #define A_ADDR_TRAP_DOWN_3 0x0010020438 646 #define A_ADDR_TRAP_CFG_0 0x0010020440 647 #define A_ADDR_TRAP_CFG_1 0x0010020448 648 #define A_ADDR_TRAP_CFG_2 0x0010020450 649 #define A_ADDR_TRAP_CFG_3 0x0010020458 650 #define A_ADDR_TRAP_REG_DEBUG 0x0010020460 /* PASS2 */ 651 652 653 /* ********************************************************************* 654 * System Interrupt Mapper Registers 655 ********************************************************************* */ 656 657 #define A_IMR_CPU0_BASE 0x0010020000 658 #define A_IMR_CPU1_BASE 0x0010022000 659 #define IMR_REGISTER_SPACING 0x2000 660 661 #define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING) 662 #define A_IMR_REGISTER(cpu,reg) (A_IMR_MAPPER(cpu)+(reg)) 663 664 #define R_IMR_INTERRUPT_DIAG 0x0010 665 #define R_IMR_INTERRUPT_MASK 0x0028 666 #define R_IMR_INTERRUPT_TRACE 0x0038 667 #define R_IMR_INTERRUPT_SOURCE_STATUS 0x0040 668 #define R_IMR_LDT_INTERRUPT_SET 0x0048 669 #define R_IMR_LDT_INTERRUPT 0x0018 670 #define R_IMR_LDT_INTERRUPT_CLR 0x0020 671 #define R_IMR_MAILBOX_CPU 0x00c0 672 #define R_IMR_ALIAS_MAILBOX_CPU 0x1000 673 #define R_IMR_MAILBOX_SET_CPU 0x00C8 674 #define R_IMR_ALIAS_MAILBOX_SET_CPU 0x1008 675 #define R_IMR_MAILBOX_CLR_CPU 0x00D0 676 #define R_IMR_INTERRUPT_STATUS_BASE 0x0100 677 #define R_IMR_INTERRUPT_STATUS_COUNT 7 678 #define R_IMR_INTERRUPT_MAP_BASE 0x0200 679 #define R_IMR_INTERRUPT_MAP_COUNT 64 680 681 /* ********************************************************************* 682 * System Performance Counter Registers 683 ********************************************************************* */ 684 685 #define A_SCD_PERF_CNT_CFG 0x00100204C0 686 #define A_SCD_PERF_CNT_0 0x00100204D0 687 #define A_SCD_PERF_CNT_1 0x00100204D8 688 #define A_SCD_PERF_CNT_2 0x00100204E0 689 #define A_SCD_PERF_CNT_3 0x00100204E8 690 691 /* ********************************************************************* 692 * System Bus Watcher Registers 693 ********************************************************************* */ 694 695 #define A_SCD_BUS_ERR_STATUS 0x0010020880 696 #define A_SCD_BUS_ERR_STATUS_DEBUG 0x00100208D0 /* PASS2 */ 697 #define A_BUS_ERR_DATA_0 0x00100208A0 698 #define A_BUS_ERR_DATA_1 0x00100208A8 699 #define A_BUS_ERR_DATA_2 0x00100208B0 700 #define A_BUS_ERR_DATA_3 0x00100208B8 701 #define A_BUS_L2_ERRORS 0x00100208C0 702 #define A_BUS_MEM_IO_ERRORS 0x00100208C8 703 704 /* ********************************************************************* 705 * System Debug Controller Registers 706 ********************************************************************* */ 707 708 #define A_SCD_JTAG_BASE 0x0010000000 709 710 /* ********************************************************************* 711 * System Trace Buffer Registers 712 ********************************************************************* */ 713 714 #define A_SCD_TRACE_CFG 0x0010020A00 715 #define A_SCD_TRACE_READ 0x0010020A08 716 #define A_SCD_TRACE_EVENT_0 0x0010020A20 717 #define A_SCD_TRACE_EVENT_1 0x0010020A28 718 #define A_SCD_TRACE_EVENT_2 0x0010020A30 719 #define A_SCD_TRACE_EVENT_3 0x0010020A38 720 #define A_SCD_TRACE_SEQUENCE_0 0x0010020A40 721 #define A_SCD_TRACE_SEQUENCE_1 0x0010020A48 722 #define A_SCD_TRACE_SEQUENCE_2 0x0010020A50 723 #define A_SCD_TRACE_SEQUENCE_3 0x0010020A58 724 #define A_SCD_TRACE_EVENT_4 0x0010020A60 725 #define A_SCD_TRACE_EVENT_5 0x0010020A68 726 #define A_SCD_TRACE_EVENT_6 0x0010020A70 727 #define A_SCD_TRACE_EVENT_7 0x0010020A78 728 #define A_SCD_TRACE_SEQUENCE_4 0x0010020A80 729 #define A_SCD_TRACE_SEQUENCE_5 0x0010020A88 730 #define A_SCD_TRACE_SEQUENCE_6 0x0010020A90 731 #define A_SCD_TRACE_SEQUENCE_7 0x0010020A98 732 733 /* ********************************************************************* 734 * System Generic DMA Registers 735 ********************************************************************* */ 736 737 #define A_DM_0 0x0010020B00 738 #define A_DM_1 0x0010020B20 739 #define A_DM_2 0x0010020B40 740 #define A_DM_3 0x0010020B60 741 #define DM_REGISTER_SPACING 0x20 742 #define DM_NUM_CHANNELS 4 743 #define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING)) 744 #define A_DM_REGISTER(idx,reg) (A_DM_BASE(idx) + (reg)) 745 746 #define R_DM_DSCR_BASE 0x0000000000 747 #define R_DM_DSCR_COUNT 0x0000000008 748 #define R_DM_CUR_DSCR_ADDR 0x0000000010 749 #define R_DM_DSCR_BASE_DEBUG 0x0000000018 750 751 752 /* ********************************************************************* 753 * Physical Address Map 754 ********************************************************************* */ 755 756 #define A_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) 757 #define A_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) 758 #define A_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) 759 #define A_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000) 760 #define A_PHYS_GENBUS _SB_MAKE64(0x0010090000) 761 #define A_PHYS_GENBUS_END _SB_MAKE64(0x0040000000) 762 #define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000) 763 #define A_PHYS_LDTPCI_IO_MATCH_BITS_32 _SB_MAKE64(0x0060000000) 764 #define A_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000) 765 #define A_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000) 766 #define A_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000) 767 #define A_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000) 768 #define A_PHYS_LDT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000) 769 #define A_PHYS_LDTPCI_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000) 770 #define A_PHYS_LDTPCI_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000) 771 #define A_PHYS_LDT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000) 772 #define A_PHYS_LDTPCI_IO_MATCH_BITS _SB_MAKE64(0x00FC000000) 773 #define A_PHYS_LDTPCI_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000) 774 #define A_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000) 775 #define A_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024)) 776 #define A_PHYS_LDT_EXP _SB_MAKE64(0x8000000000) 777 #define A_PHYS_PCI_FULLACCESS_BYTES _SB_MAKE64(0xF000000000) 778 #define A_PHYS_PCI_FULLACCESS_BITS _SB_MAKE64(0xF100000000) 779 #define A_PHYS_RESERVED _SB_MAKE64(0xF200000000) 780 #define A_PHYS_RESERVED_SPECIAL_LDT _SB_MAKE64(0xFD00000000) 781 782 #define A_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000) 783 #define PHYS_L2CACHE_NUM_WAYS 4 784 #define A_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000080000) 785 #define A_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0180000) 786 #define A_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D01A0000) 787 #define A_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D01C0000) 788 #define A_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D01E0000) 789 790 791 #endif 792
Indexes created Thu Oct 02 01:09:59 GMT 2025