sb1250_regs.h revision 1.5
1 /* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * Register Definitions File: sb1250_regs.h 5 * 6 * This module contains the addresses of the on-chip peripherals 7 * on the SB1250. 8 * 9 * SB1250 specification level: 01/02/2002 10 * 11 * Author: Mitch Lichtenberg (mpl (at) broadcom.com) 12 * 13 ********************************************************************* 14 * 15 * Copyright 2000,2001 16 * Broadcom Corporation. All rights reserved. 17 * 18 * This software is furnished under license and may be used and 19 * copied only in accordance with the following terms and 20 * conditions. Subject to these conditions, you may download, 21 * copy, install, use, modify and distribute modified or unmodified 22 * copies of this software in source and/or binary form. No title 23 * or ownership is transferred hereby. 24 * 25 * 1) Any source code used, modified or distributed must reproduce 26 * and retain this copyright notice and list of conditions as 27 * they appear in the source file. 28 * 29 * 2) No right is granted to use any trade name, trademark, or 30 * logo of Broadcom Corporation. Neither the "Broadcom 31 * Corporation" name nor any trademark or logo of Broadcom 32 * Corporation may be used to endorse or promote products 33 * derived from this software without the prior written 34 * permission of Broadcom Corporation. 35 * 36 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 37 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 38 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 39 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 40 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 41 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 42 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 43 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 44 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 45 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 46 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 47 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 48 * THE POSSIBILITY OF SUCH DAMAGE. 49 ********************************************************************* */ 50 51 52 #ifndef _SB1250_REGS_H 53 #define _SB1250_REGS_H 54 55 #include "sb1250_defs.h" 56 57 58 /* ********************************************************************* 59 * Some general notes: 60 * 61 * For the most part, when there is more than one peripheral 62 * of the same type on the SOC, the constants below will be 63 * offsets from the base of each peripheral. For example, 64 * the MAC registers are described as offsets from the first 65 * MAC register, and there will be a MAC_REGISTER() macro 66 * to calculate the base address of a given MAC. 67 * 68 * The information in this file is based on the SB1250 SOC 69 * manual version 0.2, July 2000. 70 ********************************************************************* */ 71 72 73 /* ********************************************************************* 74 * Memory Controller Registers 75 ********************************************************************* */ 76 77 /* 78 * XXX: can't remove MC base 0 if 112x, since it's used by other macros, 79 * since there is one reg there (but it could get its addr/offset constant). 80 */ 81 #define A_MC_BASE_0 0x0010051000 82 #define A_MC_BASE_1 0x0010052000 83 #define MC_REGISTER_SPACING 0x1000 84 85 #define A_MC_BASE(ctlid) ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0) 86 #define A_MC_REGISTER(ctlid,reg) (A_MC_BASE(ctlid)+(reg)) 87 88 #define R_MC_CONFIG 0x0000000100 89 #define R_MC_DRAMCMD 0x0000000120 90 #define R_MC_DRAMMODE 0x0000000140 91 #define R_MC_TIMING1 0x0000000160 92 #define R_MC_TIMING2 0x0000000180 93 #define R_MC_CS_START 0x00000001A0 94 #define R_MC_CS_END 0x00000001C0 95 #define R_MC_CS_INTERLEAVE 0x00000001E0 96 #define S_MC_CS_STARTEND 16 97 98 #define R_MC_CSX_BASE 0x0000000200 99 #define R_MC_CSX_ROW 0x0000000000 /* relative to CSX_BASE, above */ 100 #define R_MC_CSX_COL 0x0000000020 /* relative to CSX_BASE, above */ 101 #define R_MC_CSX_BA 0x0000000040 /* relative to CSX_BASE, above */ 102 #define MC_CSX_SPACING 0x0000000060 /* relative to CSX_BASE, above */ 103 104 #define R_MC_CS0_ROW 0x0000000200 105 #define R_MC_CS0_COL 0x0000000220 106 #define R_MC_CS0_BA 0x0000000240 107 #define R_MC_CS1_ROW 0x0000000260 108 #define R_MC_CS1_COL 0x0000000280 109 #define R_MC_CS1_BA 0x00000002A0 110 #define R_MC_CS2_ROW 0x00000002C0 111 #define R_MC_CS2_COL 0x00000002E0 112 #define R_MC_CS2_BA 0x0000000300 113 #define R_MC_CS3_ROW 0x0000000320 114 #define R_MC_CS3_COL 0x0000000340 115 #define R_MC_CS3_BA 0x0000000360 116 #define R_MC_CS_ATTR 0x0000000380 117 #define R_MC_TEST_DATA 0x0000000400 118 #define R_MC_TEST_ECC 0x0000000420 119 #define R_MC_MCLK_CFG 0x0000000500 120 121 /* ********************************************************************* 122 * L2 Cache Control Registers 123 ********************************************************************* */ 124 125 #define A_L2_READ_TAG 0x0010040018 126 #define A_L2_ECC_TAG 0x0010040038 127 #if SIBYTE_HDR_FEATURE(112x, PASS1) 128 #define A_L2_READ_MISC 0x0010040058 129 #endif /* 112x PASS1 */ 130 #define A_L2_WAY_DISABLE 0x0010041000 131 #define A_L2_MAKEDISABLE(x) (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8)) 132 #define A_L2_MGMT_TAG_BASE 0x00D0000000 133 134 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 135 #define A_L2_CACHE_DISABLE 0x0010042000 136 #define A_L2_MAKECACHEDISABLE(x) (A_L2_CACHE_DISABLE | (((x)&0x0F) << 8)) 137 #define A_L2_MISC_CONFIG 0x0010043000 138 #endif /* 1250 PASS2 || 112x PASS1 */ 139 140 /* Backward-compatibility definitions. */ 141 /* XXX: discourage people from using these constants. */ 142 #define A_L2_READ_ADDRESS A_L2_READ_TAG 143 #define A_L2_EEC_ADDRESS A_L2_ECC_TAG 144 145 146 /* ********************************************************************* 147 * PCI Interface Registers 148 ********************************************************************* */ 149 150 #define A_PCI_TYPE00_HEADER 0x00DE000000 151 #define A_PCI_TYPE01_HEADER 0x00DE000800 152 153 154 /* ********************************************************************* 155 * Ethernet DMA and MACs 156 ********************************************************************* */ 157 158 #define A_MAC_BASE_0 0x0010064000 159 #define A_MAC_BASE_1 0x0010065000 160 #if SIBYTE_HDR_FEATURE_CHIP(1250) 161 #define A_MAC_BASE_2 0x0010066000 162 #endif /* 1250 */ 163 164 #define MAC_SPACING 0x1000 165 #define MAC_DMA_TXRX_SPACING 0x0400 166 #define MAC_DMA_CHANNEL_SPACING 0x0100 167 #define DMA_RX 0 168 #define DMA_TX 1 169 #define MAC_NUM_DMACHAN 2 /* channels per direction */ 170 171 /* XXX: not correct; depends on SOC type. */ 172 #define MAC_NUM_PORTS 3 173 174 #define A_MAC_CHANNEL_BASE(macnum) \ 175 (A_MAC_BASE_0 + \ 176 MAC_SPACING*(macnum)) 177 178 #define A_MAC_REGISTER(macnum,reg) \ 179 (A_MAC_BASE_0 + \ 180 MAC_SPACING*(macnum) + (reg)) 181 182 183 #define R_MAC_DMA_CHANNELS 0x800 /* Relative to A_MAC_CHANNEL_BASE */ 184 185 #define A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) \ 186 ((A_MAC_CHANNEL_BASE(macnum)) + \ 187 R_MAC_DMA_CHANNELS + \ 188 (MAC_DMA_TXRX_SPACING*(txrx)) + \ 189 (MAC_DMA_CHANNEL_SPACING*(chan))) 190 191 #define R_MAC_DMA_CHANNEL_BASE(txrx,chan) \ 192 (R_MAC_DMA_CHANNELS + \ 193 (MAC_DMA_TXRX_SPACING*(txrx)) + \ 194 (MAC_DMA_CHANNEL_SPACING*(chan))) 195 196 #define A_MAC_DMA_REGISTER(macnum,txrx,chan,reg) \ 197 (A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) + \ 198 (reg)) 199 200 #define R_MAC_DMA_REGISTER(txrx,chan,reg) \ 201 (R_MAC_DMA_CHANNEL_BASE(txrx,chan) + \ 202 (reg)) 203 204 /* 205 * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE 206 */ 207 208 #define R_MAC_DMA_CONFIG0 0x00000000 209 #define R_MAC_DMA_CONFIG1 0x00000008 210 #define R_MAC_DMA_DSCR_BASE 0x00000010 211 #define R_MAC_DMA_DSCR_CNT 0x00000018 212 #define R_MAC_DMA_CUR_DSCRA 0x00000020 213 #define R_MAC_DMA_CUR_DSCRB 0x00000028 214 #define R_MAC_DMA_CUR_DSCRADDR 0x00000030 215 #if SIBYTE_HDR_FEATURE(112x, PASS1) 216 #define R_MAC_DMA_OODPKTLOST_RX 0x00000038 /* rx only */ 217 #endif /* 112x PASS1 */ 218 219 /* 220 * RMON Counters 221 */ 222 223 #define R_MAC_RMON_TX_BYTES 0x00000000 224 #define R_MAC_RMON_COLLISIONS 0x00000008 225 #define R_MAC_RMON_LATE_COL 0x00000010 226 #define R_MAC_RMON_EX_COL 0x00000018 227 #define R_MAC_RMON_FCS_ERROR 0x00000020 228 #define R_MAC_RMON_TX_ABORT 0x00000028 229 /* Counter #6 (0x30) now reserved */ 230 #define R_MAC_RMON_TX_BAD 0x00000038 231 #define R_MAC_RMON_TX_GOOD 0x00000040 232 #define R_MAC_RMON_TX_RUNT 0x00000048 233 #define R_MAC_RMON_TX_OVERSIZE 0x00000050 234 #define R_MAC_RMON_RX_BYTES 0x00000080 235 #define R_MAC_RMON_RX_MCAST 0x00000088 236 #define R_MAC_RMON_RX_BCAST 0x00000090 237 #define R_MAC_RMON_RX_BAD 0x00000098 238 #define R_MAC_RMON_RX_GOOD 0x000000A0 239 #define R_MAC_RMON_RX_RUNT 0x000000A8 240 #define R_MAC_RMON_RX_OVERSIZE 0x000000B0 241 #define R_MAC_RMON_RX_FCS_ERROR 0x000000B8 242 #define R_MAC_RMON_RX_LENGTH_ERROR 0x000000C0 243 #define R_MAC_RMON_RX_CODE_ERROR 0x000000C8 244 #define R_MAC_RMON_RX_ALIGN_ERROR 0x000000D0 245 246 /* Updated to spec 0.2 */ 247 #define R_MAC_CFG 0x00000100 248 #define R_MAC_THRSH_CFG 0x00000108 249 #define R_MAC_VLANTAG 0x00000110 250 #define R_MAC_FRAMECFG 0x00000118 251 #define R_MAC_EOPCNT 0x00000120 252 #define R_MAC_FIFO_PTRS 0x00000130 253 #define R_MAC_ADFILTER_CFG 0x00000200 254 #define R_MAC_ETHERNET_ADDR 0x00000208 255 #define R_MAC_PKT_TYPE 0x00000210 256 #if SIBYTE_HDR_FEATURE(112x, PASS1) 257 #define R_MAC_ADMASK0 0x00000218 258 #define R_MAC_ADMASK1 0x00000220 259 #endif /* 112x PASS1 */ 260 #define R_MAC_HASH_BASE 0x00000240 261 #define R_MAC_ADDR_BASE 0x00000280 262 #define R_MAC_CHLO0_BASE 0x00000300 263 #define R_MAC_CHUP0_BASE 0x00000320 264 #define R_MAC_ENABLE 0x00000400 265 #define R_MAC_STATUS 0x00000408 266 #define R_MAC_INT_MASK 0x00000410 267 #define R_MAC_TXD_CTL 0x00000420 268 #define R_MAC_MDIO 0x00000428 269 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 270 #define R_MAC_STATUS1 0x00000430 271 #endif /* 1250 PASS2 || 112x PASS1 */ 272 #define R_MAC_DEBUG_STATUS 0x00000448 273 274 #define MAC_HASH_COUNT 8 275 #define MAC_ADDR_COUNT 8 276 #define MAC_CHMAP_COUNT 4 277 278 279 /* ********************************************************************* 280 * DUART Registers 281 ********************************************************************* */ 282 283 284 #define R_DUART_NUM_PORTS 2 285 286 #define A_DUART 0x0010060000 287 288 #define A_DUART_REG(r) 289 290 #define DUART_CHANREG_SPACING 0x100 291 #define A_DUART_CHANREG(chan,reg) (A_DUART + DUART_CHANREG_SPACING*(chan) + (reg)) 292 #define R_DUART_CHANREG(chan,reg) (DUART_CHANREG_SPACING*(chan) + (reg)) 293 294 #define R_DUART_MODE_REG_1 0x100 295 #define R_DUART_MODE_REG_2 0x110 296 #define R_DUART_STATUS 0x120 297 #define R_DUART_CLK_SEL 0x130 298 #define R_DUART_CMD 0x150 299 #define R_DUART_RX_HOLD 0x160 300 #define R_DUART_TX_HOLD 0x170 301 302 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 303 #define R_DUART_FULL_CTL 0x140 304 #define R_DUART_OPCR_X 0x180 305 #define R_DUART_AUXCTL_X 0x190 306 #endif /* 1250 PASS2 || 112x PASS1 */ 307 308 309 /* 310 * The IMR and ISR can't be addressed with A_DUART_CHANREG, 311 * so use this macro instead. 312 */ 313 314 #define R_DUART_AUX_CTRL 0x310 315 #define R_DUART_ISR_A 0x320 316 #define R_DUART_IMR_A 0x330 317 #define R_DUART_ISR_B 0x340 318 #define R_DUART_IMR_B 0x350 319 #define R_DUART_OUT_PORT 0x360 320 #define R_DUART_OPCR 0x370 321 322 #define R_DUART_SET_OPR 0x3B0 323 #define R_DUART_CLEAR_OPR 0x3C0 324 325 #define DUART_IMRISR_SPACING 0x20 326 327 #define R_DUART_IMRREG(chan) (R_DUART_IMR_A + (chan)*DUART_IMRISR_SPACING) 328 #define R_DUART_ISRREG(chan) (R_DUART_ISR_A + (chan)*DUART_IMRISR_SPACING) 329 330 #define A_DUART_IMRREG(chan) (A_DUART + R_DUART_IMRREG(chan)) 331 #define A_DUART_ISRREG(chan) (A_DUART + R_DUART_ISRREG(chan)) 332 333 334 335 336 /* 337 * These constants are the absolute addresses. 338 */ 339 340 #define A_DUART_MODE_REG_1_A 0x0010060100 341 #define A_DUART_MODE_REG_2_A 0x0010060110 342 #define A_DUART_STATUS_A 0x0010060120 343 #define A_DUART_CLK_SEL_A 0x0010060130 344 #define A_DUART_CMD_A 0x0010060150 345 #define A_DUART_RX_HOLD_A 0x0010060160 346 #define A_DUART_TX_HOLD_A 0x0010060170 347 348 #define A_DUART_MODE_REG_1_B 0x0010060200 349 #define A_DUART_MODE_REG_2_B 0x0010060210 350 #define A_DUART_STATUS_B 0x0010060220 351 #define A_DUART_CLK_SEL_B 0x0010060230 352 #define A_DUART_CMD_B 0x0010060250 353 #define A_DUART_RX_HOLD_B 0x0010060260 354 #define A_DUART_TX_HOLD_B 0x0010060270 355 356 #define A_DUART_INPORT_CHNG 0x0010060300 357 #define A_DUART_AUX_CTRL 0x0010060310 358 #define A_DUART_ISR_A 0x0010060320 359 #define A_DUART_IMR_A 0x0010060330 360 #define A_DUART_ISR_B 0x0010060340 361 #define A_DUART_IMR_B 0x0010060350 362 #define A_DUART_OUT_PORT 0x0010060360 363 #define A_DUART_OPCR 0x0010060370 364 #define A_DUART_IN_PORT 0x0010060380 365 #define A_DUART_ISR 0x0010060390 366 #define A_DUART_IMR 0x00100603A0 367 #define A_DUART_SET_OPR 0x00100603B0 368 #define A_DUART_CLEAR_OPR 0x00100603C0 369 #define A_DUART_INPORT_CHNG_A 0x00100603D0 370 #define A_DUART_INPORT_CHNG_B 0x00100603E0 371 372 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 373 #define A_DUART_FULL_CTL_A 0x0010060140 374 #define A_DUART_FULL_CTL_B 0x0010060240 375 376 #define A_DUART_OPCR_A 0x0010060180 377 #define A_DUART_OPCR_B 0x0010060280 378 379 #define A_DUART_INPORT_CHNG_DEBUG 0x00100603F0 380 #endif /* 1250 PASS2 || 112x PASS1 */ 381 382 383 /* ********************************************************************* 384 * Synchronous Serial Registers 385 ********************************************************************* */ 386 387 388 #define A_SER_BASE_0 0x0010060400 389 #define A_SER_BASE_1 0x0010060800 390 #define SER_SPACING 0x400 391 392 #define SER_DMA_TXRX_SPACING 0x80 393 394 #define SER_NUM_PORTS 2 395 396 #define A_SER_CHANNEL_BASE(sernum) \ 397 (A_SER_BASE_0 + \ 398 SER_SPACING*(sernum)) 399 400 #define A_SER_REGISTER(sernum,reg) \ 401 (A_SER_BASE_0 + \ 402 SER_SPACING*(sernum) + (reg)) 403 404 405 #define R_SER_DMA_CHANNELS 0 /* Relative to A_SER_BASE_x */ 406 407 #define A_SER_DMA_CHANNEL_BASE(sernum,txrx) \ 408 ((A_SER_CHANNEL_BASE(sernum)) + \ 409 R_SER_DMA_CHANNELS + \ 410 (SER_DMA_TXRX_SPACING*(txrx))) 411 412 #define A_SER_DMA_REGISTER(sernum,txrx,reg) \ 413 (A_SER_DMA_CHANNEL_BASE(sernum,txrx) + \ 414 (reg)) 415 416 417 /* 418 * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE 419 */ 420 421 #define R_SER_DMA_CONFIG0 0x00000000 422 #define R_SER_DMA_CONFIG1 0x00000008 423 #define R_SER_DMA_DSCR_BASE 0x00000010 424 #define R_SER_DMA_DSCR_CNT 0x00000018 425 #define R_SER_DMA_CUR_DSCRA 0x00000020 426 #define R_SER_DMA_CUR_DSCRB 0x00000028 427 #define R_SER_DMA_CUR_DSCRADDR 0x00000030 428 429 #define R_SER_DMA_CONFIG0_RX 0x00000000 430 #define R_SER_DMA_CONFIG1_RX 0x00000008 431 #define R_SER_DMA_DSCR_BASE_RX 0x00000010 432 #define R_SER_DMA_DSCR_COUNT_RX 0x00000018 433 #define R_SER_DMA_CUR_DSCR_A_RX 0x00000020 434 #define R_SER_DMA_CUR_DSCR_B_RX 0x00000028 435 #define R_SER_DMA_CUR_DSCR_ADDR_RX 0x00000030 436 437 #define R_SER_DMA_CONFIG0_TX 0x00000080 438 #define R_SER_DMA_CONFIG1_TX 0x00000088 439 #define R_SER_DMA_DSCR_BASE_TX 0x00000090 440 #define R_SER_DMA_DSCR_COUNT_TX 0x00000098 441 #define R_SER_DMA_CUR_DSCR_A_TX 0x000000A0 442 #define R_SER_DMA_CUR_DSCR_B_TX 0x000000A8 443 #define R_SER_DMA_CUR_DSCR_ADDR_TX 0x000000B0 444 445 #define R_SER_MODE 0x00000100 446 #define R_SER_MINFRM_SZ 0x00000108 447 #define R_SER_MAXFRM_SZ 0x00000110 448 #define R_SER_ADDR 0x00000118 449 #define R_SER_USR0_ADDR 0x00000120 450 #define R_SER_USR1_ADDR 0x00000128 451 #define R_SER_USR2_ADDR 0x00000130 452 #define R_SER_USR3_ADDR 0x00000138 453 #define R_SER_CMD 0x00000140 454 #define R_SER_TX_RD_THRSH 0x00000160 455 #define R_SER_TX_WR_THRSH 0x00000168 456 #define R_SER_RX_RD_THRSH 0x00000170 457 #define R_SER_LINE_MODE 0x00000178 458 #define R_SER_DMA_ENABLE 0x00000180 459 #define R_SER_INT_MASK 0x00000190 460 #define R_SER_STATUS 0x00000188 461 #define R_SER_STATUS_DEBUG 0x000001A8 462 #define R_SER_RX_TABLE_BASE 0x00000200 463 #define SER_RX_TABLE_COUNT 16 464 #define R_SER_TX_TABLE_BASE 0x00000300 465 #define SER_TX_TABLE_COUNT 16 466 467 /* RMON Counters */ 468 #define R_SER_RMON_TX_BYTE_LO 0x000001C0 469 #define R_SER_RMON_TX_BYTE_HI 0x000001C8 470 #define R_SER_RMON_RX_BYTE_LO 0x000001D0 471 #define R_SER_RMON_RX_BYTE_HI 0x000001D8 472 #define R_SER_RMON_TX_UNDERRUN 0x000001E0 473 #define R_SER_RMON_RX_OVERFLOW 0x000001E8 474 #define R_SER_RMON_RX_ERRORS 0x000001F0 475 #define R_SER_RMON_RX_BADADDR 0x000001F8 476 477 /* ********************************************************************* 478 * Generic Bus Registers 479 ********************************************************************* */ 480 481 #define IO_EXT_CFG_COUNT 8 482 483 #define A_IO_EXT_BASE 0x0010061000 484 #define A_IO_EXT_REG(r) (A_IO_EXT_BASE + (r)) 485 486 #define A_IO_EXT_CFG_BASE 0x0010061000 487 #define A_IO_EXT_MULT_SIZE_BASE 0x0010061100 488 #define A_IO_EXT_START_ADDR_BASE 0x0010061200 489 #define A_IO_EXT_TIME_CFG0_BASE 0x0010061600 490 #define A_IO_EXT_TIME_CFG1_BASE 0x0010061700 491 492 #define IO_EXT_REGISTER_SPACING 8 493 #define A_IO_EXT_CS_BASE(cs) (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs)) 494 #define R_IO_EXT_REG(reg,cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg)) 495 496 #define R_IO_EXT_CFG 0x0000 497 #define R_IO_EXT_MULT_SIZE 0x0100 498 #define R_IO_EXT_START_ADDR 0x0200 499 #define R_IO_EXT_TIME_CFG0 0x0600 500 #define R_IO_EXT_TIME_CFG1 0x0700 501 502 503 #define A_IO_INTERRUPT_STATUS 0x0010061A00 504 #define A_IO_INTERRUPT_DATA0 0x0010061A10 505 #define A_IO_INTERRUPT_DATA1 0x0010061A18 506 #define A_IO_INTERRUPT_DATA2 0x0010061A20 507 #define A_IO_INTERRUPT_DATA3 0x0010061A28 508 #define A_IO_INTERRUPT_ADDR0 0x0010061A30 509 #define A_IO_INTERRUPT_ADDR1 0x0010061A40 510 #define A_IO_INTERRUPT_PARITY 0x0010061A50 511 #define A_IO_PCMCIA_CFG 0x0010061A60 512 #define A_IO_PCMCIA_STATUS 0x0010061A70 513 #define A_IO_DRIVE_0 0x0010061300 514 #define A_IO_DRIVE_1 0x0010061308 515 #define A_IO_DRIVE_2 0x0010061310 516 #define A_IO_DRIVE_3 0x0010061318 517 #define A_IO_DRIVE_BASE A_IO_DRIVE_0 518 #define IO_DRIVE_REGISTER_SPACING 8 519 #define R_IO_DRIVE(x) ((x)*IO_DRIVE_REGISTER_SPACING) 520 #define A_IO_DRIVE(x) (A_IO_DRIVE_BASE + R_IO_DRIVE(x)) 521 522 #define R_IO_INTERRUPT_STATUS 0x0A00 523 #define R_IO_INTERRUPT_DATA0 0x0A10 524 #define R_IO_INTERRUPT_DATA1 0x0A18 525 #define R_IO_INTERRUPT_DATA2 0x0A20 526 #define R_IO_INTERRUPT_DATA3 0x0A28 527 #define R_IO_INTERRUPT_ADDR0 0x0A30 528 #define R_IO_INTERRUPT_ADDR1 0x0A40 529 #define R_IO_INTERRUPT_PARITY 0x0A50 530 #define R_IO_PCMCIA_CFG 0x0A60 531 #define R_IO_PCMCIA_STATUS 0x0A70 532 533 /* ********************************************************************* 534 * GPIO Registers 535 ********************************************************************* */ 536 537 #define A_GPIO_CLR_EDGE 0x0010061A80 538 #define A_GPIO_INT_TYPE 0x0010061A88 539 #define A_GPIO_INPUT_INVERT 0x0010061A90 540 #define A_GPIO_GLITCH 0x0010061A98 541 #define A_GPIO_READ 0x0010061AA0 542 #define A_GPIO_DIRECTION 0x0010061AA8 543 #define A_GPIO_PIN_CLR 0x0010061AB0 544 #define A_GPIO_PIN_SET 0x0010061AB8 545 546 #define A_GPIO_BASE 0x0010061A80 547 548 #define R_GPIO_CLR_EDGE 0x00 549 #define R_GPIO_INT_TYPE 0x08 550 #define R_GPIO_INPUT_INVERT 0x10 551 #define R_GPIO_GLITCH 0x18 552 #define R_GPIO_READ 0x20 553 #define R_GPIO_DIRECTION 0x28 554 #define R_GPIO_PIN_CLR 0x30 555 #define R_GPIO_PIN_SET 0x38 556 557 /* ********************************************************************* 558 * SMBus Registers 559 ********************************************************************* */ 560 561 #define A_SMB_XTRA_0 0x0010060000 562 #define A_SMB_XTRA_1 0x0010060008 563 #define A_SMB_FREQ_0 0x0010060010 564 #define A_SMB_FREQ_1 0x0010060018 565 #define A_SMB_STATUS_0 0x0010060020 566 #define A_SMB_STATUS_1 0x0010060028 567 #define A_SMB_CMD_0 0x0010060030 568 #define A_SMB_CMD_1 0x0010060038 569 #define A_SMB_START_0 0x0010060040 570 #define A_SMB_START_1 0x0010060048 571 #define A_SMB_DATA_0 0x0010060050 572 #define A_SMB_DATA_1 0x0010060058 573 #define A_SMB_CONTROL_0 0x0010060060 574 #define A_SMB_CONTROL_1 0x0010060068 575 #define A_SMB_PEC_0 0x0010060070 576 #define A_SMB_PEC_1 0x0010060078 577 578 #define A_SMB_0 0x0010060000 579 #define A_SMB_1 0x0010060008 580 #define SMB_REGISTER_SPACING 0x8 581 #define A_SMB_BASE(idx) (A_SMB_0+(idx)*SMB_REGISTER_SPACING) 582 #define A_SMB_REGISTER(idx,reg) (A_SMB_BASE(idx)+(reg)) 583 584 #define R_SMB_XTRA 0x0000000000 585 #define R_SMB_FREQ 0x0000000010 586 #define R_SMB_STATUS 0x0000000020 587 #define R_SMB_CMD 0x0000000030 588 #define R_SMB_START 0x0000000040 589 #define R_SMB_DATA 0x0000000050 590 #define R_SMB_CONTROL 0x0000000060 591 #define R_SMB_PEC 0x0000000070 592 593 /* ********************************************************************* 594 * Timer Registers 595 ********************************************************************* */ 596 597 /* 598 * Watchdog timers 599 */ 600 601 #define A_SCD_WDOG_0 0x0010020050 602 #define A_SCD_WDOG_1 0x0010020150 603 #define SCD_WDOG_SPACING 0x100 604 #define SCD_NUM_WDOGS 2 605 #define A_SCD_WDOG_BASE(w) (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w)) 606 #define A_SCD_WDOG_REGISTER(w,r) (A_SCD_WDOG_BASE(w) + (r)) 607 608 #define R_SCD_WDOG_INIT 0x0000000000 609 #define R_SCD_WDOG_CNT 0x0000000008 610 #define R_SCD_WDOG_CFG 0x0000000010 611 612 #define A_SCD_WDOG_INIT_0 0x0010020050 613 #define A_SCD_WDOG_CNT_0 0x0010020058 614 #define A_SCD_WDOG_CFG_0 0x0010020060 615 616 #define A_SCD_WDOG_INIT_1 0x0010020150 617 #define A_SCD_WDOG_CNT_1 0x0010020158 618 #define A_SCD_WDOG_CFG_1 0x0010020160 619 620 /* 621 * Generic timers 622 */ 623 624 #define A_SCD_TIMER_0 0x0010020070 625 #define A_SCD_TIMER_1 0x0010020078 626 #define A_SCD_TIMER_2 0x0010020170 627 #define A_SCD_TIMER_3 0x0010020178 628 #define SCD_NUM_TIMERS 4 629 #define A_SCD_TIMER_BASE(w) (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1)) 630 #define A_SCD_TIMER_REGISTER(w,r) (A_SCD_TIMER_BASE(w) + (r)) 631 632 #define R_SCD_TIMER_INIT 0x0000000000 633 #define R_SCD_TIMER_CNT 0x0000000010 634 #define R_SCD_TIMER_CFG 0x0000000020 635 636 #define A_SCD_TIMER_INIT_0 0x0010020070 637 #define A_SCD_TIMER_CNT_0 0x0010020080 638 #define A_SCD_TIMER_CFG_0 0x0010020090 639 640 #define A_SCD_TIMER_INIT_1 0x0010020078 641 #define A_SCD_TIMER_CNT_1 0x0010020088 642 #define A_SCD_TIMER_CFG_1 0x0010020098 643 644 #define A_SCD_TIMER_INIT_2 0x0010020170 645 #define A_SCD_TIMER_CNT_2 0x0010020180 646 #define A_SCD_TIMER_CFG_2 0x0010020190 647 648 #define A_SCD_TIMER_INIT_3 0x0010020178 649 #define A_SCD_TIMER_CNT_3 0x0010020188 650 #define A_SCD_TIMER_CFG_3 0x0010020198 651 652 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 653 #define A_SCD_SCRATCH 0x0010020C10 654 655 #define A_SCD_ZBBUS_CYCLE_COUNT 0x0010030000 656 #define A_SCD_ZBBUS_CYCLE_CP0 0x0010020C00 657 #define A_SCD_ZBBUS_CYCLE_CP1 0x0010020C08 658 #endif /* 1250 PASS2 || 112x PASS1 */ 659 660 661 /* ********************************************************************* 662 * System Control Registers 663 ********************************************************************* */ 664 665 #define A_SCD_SYSTEM_REVISION 0x0010020000 666 #define A_SCD_SYSTEM_CFG 0x0010020008 667 668 /* ********************************************************************* 669 * System Address Trap Registers 670 ********************************************************************* */ 671 672 #define A_ADDR_TRAP_INDEX 0x00100200B0 673 #define A_ADDR_TRAP_REG 0x00100200B8 674 #define A_ADDR_TRAP_UP_0 0x0010020400 675 #define A_ADDR_TRAP_UP_1 0x0010020408 676 #define A_ADDR_TRAP_UP_2 0x0010020410 677 #define A_ADDR_TRAP_UP_3 0x0010020418 678 #define A_ADDR_TRAP_DOWN_0 0x0010020420 679 #define A_ADDR_TRAP_DOWN_1 0x0010020428 680 #define A_ADDR_TRAP_DOWN_2 0x0010020430 681 #define A_ADDR_TRAP_DOWN_3 0x0010020438 682 #define A_ADDR_TRAP_CFG_0 0x0010020440 683 #define A_ADDR_TRAP_CFG_1 0x0010020448 684 #define A_ADDR_TRAP_CFG_2 0x0010020450 685 #define A_ADDR_TRAP_CFG_3 0x0010020458 686 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 687 #define A_ADDR_TRAP_REG_DEBUG 0x0010020460 688 #endif /* 1250 PASS2 || 112x PASS1 */ 689 690 691 /* ********************************************************************* 692 * System Interrupt Mapper Registers 693 ********************************************************************* */ 694 695 #define A_IMR_CPU0_BASE 0x0010020000 696 #define A_IMR_CPU1_BASE 0x0010022000 697 #define IMR_REGISTER_SPACING 0x2000 698 #define IMR_REGISTER_SPACING_SHIFT 13 699 700 #define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING) 701 #define A_IMR_REGISTER(cpu,reg) (A_IMR_MAPPER(cpu)+(reg)) 702 703 #define R_IMR_INTERRUPT_DIAG 0x0010 704 #define R_IMR_INTERRUPT_MASK 0x0028 705 #define R_IMR_INTERRUPT_TRACE 0x0038 706 #define R_IMR_INTERRUPT_SOURCE_STATUS 0x0040 707 #define R_IMR_LDT_INTERRUPT_SET 0x0048 708 #define R_IMR_LDT_INTERRUPT 0x0018 709 #define R_IMR_LDT_INTERRUPT_CLR 0x0020 710 #define R_IMR_MAILBOX_CPU 0x00c0 711 #define R_IMR_ALIAS_MAILBOX_CPU 0x1000 712 #define R_IMR_MAILBOX_SET_CPU 0x00C8 713 #define R_IMR_ALIAS_MAILBOX_SET_CPU 0x1008 714 #define R_IMR_MAILBOX_CLR_CPU 0x00D0 715 #define R_IMR_INTERRUPT_STATUS_BASE 0x0100 716 #define R_IMR_INTERRUPT_STATUS_COUNT 7 717 #define R_IMR_INTERRUPT_MAP_BASE 0x0200 718 #define R_IMR_INTERRUPT_MAP_COUNT 64 719 720 /* ********************************************************************* 721 * System Performance Counter Registers 722 ********************************************************************* */ 723 724 #define A_SCD_PERF_CNT_CFG 0x00100204C0 725 #define A_SCD_PERF_CNT_0 0x00100204D0 726 #define A_SCD_PERF_CNT_1 0x00100204D8 727 #define A_SCD_PERF_CNT_2 0x00100204E0 728 #define A_SCD_PERF_CNT_3 0x00100204E8 729 730 /* ********************************************************************* 731 * System Bus Watcher Registers 732 ********************************************************************* */ 733 734 #define A_SCD_BUS_ERR_STATUS 0x0010020880 735 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 736 #define A_SCD_BUS_ERR_STATUS_DEBUG 0x00100208D0 737 #endif /* 1250 PASS2 || 112x PASS1 */ 738 #define A_BUS_ERR_DATA_0 0x00100208A0 739 #define A_BUS_ERR_DATA_1 0x00100208A8 740 #define A_BUS_ERR_DATA_2 0x00100208B0 741 #define A_BUS_ERR_DATA_3 0x00100208B8 742 #define A_BUS_L2_ERRORS 0x00100208C0 743 #define A_BUS_MEM_IO_ERRORS 0x00100208C8 744 745 /* ********************************************************************* 746 * System Debug Controller Registers 747 ********************************************************************* */ 748 749 #define A_SCD_JTAG_BASE 0x0010000000 750 751 /* ********************************************************************* 752 * System Trace Buffer Registers 753 ********************************************************************* */ 754 755 #define A_SCD_TRACE_CFG 0x0010020A00 756 #define A_SCD_TRACE_READ 0x0010020A08 757 #define A_SCD_TRACE_EVENT_0 0x0010020A20 758 #define A_SCD_TRACE_EVENT_1 0x0010020A28 759 #define A_SCD_TRACE_EVENT_2 0x0010020A30 760 #define A_SCD_TRACE_EVENT_3 0x0010020A38 761 #define A_SCD_TRACE_SEQUENCE_0 0x0010020A40 762 #define A_SCD_TRACE_SEQUENCE_1 0x0010020A48 763 #define A_SCD_TRACE_SEQUENCE_2 0x0010020A50 764 #define A_SCD_TRACE_SEQUENCE_3 0x0010020A58 765 #define A_SCD_TRACE_EVENT_4 0x0010020A60 766 #define A_SCD_TRACE_EVENT_5 0x0010020A68 767 #define A_SCD_TRACE_EVENT_6 0x0010020A70 768 #define A_SCD_TRACE_EVENT_7 0x0010020A78 769 #define A_SCD_TRACE_SEQUENCE_4 0x0010020A80 770 #define A_SCD_TRACE_SEQUENCE_5 0x0010020A88 771 #define A_SCD_TRACE_SEQUENCE_6 0x0010020A90 772 #define A_SCD_TRACE_SEQUENCE_7 0x0010020A98 773 774 /* ********************************************************************* 775 * System Generic DMA Registers 776 ********************************************************************* */ 777 778 #define A_DM_0 0x0010020B00 779 #define A_DM_1 0x0010020B20 780 #define A_DM_2 0x0010020B40 781 #define A_DM_3 0x0010020B60 782 #define DM_REGISTER_SPACING 0x20 783 #define DM_NUM_CHANNELS 4 784 #define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING)) 785 #define A_DM_REGISTER(idx,reg) (A_DM_BASE(idx) + (reg)) 786 787 #define R_DM_DSCR_BASE 0x0000000000 788 #define R_DM_DSCR_COUNT 0x0000000008 789 #define R_DM_CUR_DSCR_ADDR 0x0000000010 790 #define R_DM_DSCR_BASE_DEBUG 0x0000000018 791 792 #if SIBYTE_HDR_FEATURE(112x, PASS1) 793 #define A_DM_PARTIAL_0 0x0010020ba0 794 #define A_DM_PARTIAL_1 0x0010020ba8 795 #define A_DM_PARTIAL_2 0x0010020bb0 796 #define A_DM_PARTIAL_3 0x0010020bb8 797 #define DM_PARTIAL_REGISTER_SPACING 0x8 798 #define A_DM_PARTIAL(idx) (A_DM_PARTIAL_0 + ((idx) * DM_PARTIAL_REGISTER_SPACING)) 799 #endif /* 112x PASS1 */ 800 801 #if SIBYTE_HDR_FEATURE(112x, PASS1) 802 #define A_DM_CRC_0 0x0010020b80 803 #define A_DM_CRC_1 0x0010020b90 804 #define DM_CRC_REGISTER_SPACING 0x10 805 #define DM_CRC_NUM_CHANNELS 2 806 #define A_DM_CRC_BASE(idx) (A_DM_CRC_0 + ((idx) * DM_CRC_REGISTER_SPACING)) 807 #define A_DM_CRC_REGISTER(idx,reg) (A_DM_CRC_BASE(idx) + (reg)) 808 809 #define R_CRC_DEF_0 0x00 810 #define R_CTCP_DEF_0 0x08 811 #endif /* 112x PASS1 */ 812 813 /* ********************************************************************* 814 * Physical Address Map 815 ********************************************************************* */ 816 817 #define A_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) 818 #define A_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) 819 #define A_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) 820 #define A_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000) 821 #define A_PHYS_GENBUS _SB_MAKE64(0x0010090000) 822 #define A_PHYS_GENBUS_END _SB_MAKE64(0x0040000000) 823 #define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000) 824 #define A_PHYS_LDTPCI_IO_MATCH_BITS_32 _SB_MAKE64(0x0060000000) 825 #define A_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000) 826 #define A_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000) 827 #define A_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000) 828 #define A_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000) 829 #define A_PHYS_LDT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000) 830 #define A_PHYS_LDTPCI_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000) 831 #define A_PHYS_LDTPCI_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000) 832 #define A_PHYS_LDT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000) 833 #define A_PHYS_LDTPCI_IO_MATCH_BITS _SB_MAKE64(0x00FC000000) 834 #define A_PHYS_LDTPCI_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000) 835 #define A_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000) 836 #define A_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024)) 837 #define A_PHYS_LDT_EXP _SB_MAKE64(0x8000000000) 838 #define A_PHYS_PCI_FULLACCESS_BYTES _SB_MAKE64(0xF000000000) 839 #define A_PHYS_PCI_FULLACCESS_BITS _SB_MAKE64(0xF100000000) 840 #define A_PHYS_RESERVED _SB_MAKE64(0xF200000000) 841 #define A_PHYS_RESERVED_SPECIAL_LDT _SB_MAKE64(0xFD00000000) 842 843 #define A_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000) 844 #define PHYS_L2CACHE_NUM_WAYS 4 845 #define A_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000080000) 846 #define A_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0180000) 847 #define A_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D01A0000) 848 #define A_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D01C0000) 849 #define A_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D01E0000) 850 851 852 #endif 853
Indexes created Thu Oct 02 01:09:59 GMT 2025