sb1250_regs.h revision 1.6
1 /* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * Register Definitions File: sb1250_regs.h 5 * 6 * This module contains the addresses of the on-chip peripherals 7 * on the SB1250. 8 * 9 * SB1250 specification level: 01/02/2002 10 * 11 * Author: Mitch Lichtenberg (mpl (at) broadcom.com) 12 * 13 ********************************************************************* 14 * 15 * Copyright 2000,2001,2002,2003 16 * Broadcom Corporation. All rights reserved. 17 * 18 * This software is furnished under license and may be used and 19 * copied only in accordance with the following terms and 20 * conditions. Subject to these conditions, you may download, 21 * copy, install, use, modify and distribute modified or unmodified 22 * copies of this software in source and/or binary form. No title 23 * or ownership is transferred hereby. 24 * 25 * 1) Any source code used, modified or distributed must reproduce 26 * and retain this copyright notice and list of conditions 27 * as they appear in the source file. 28 * 29 * 2) No right is granted to use any trade name, trademark, or 30 * logo of Broadcom Corporation. The "Broadcom Corporation" 31 * name may not be used to endorse or promote products derived 32 * from this software without the prior written permission of 33 * Broadcom Corporation. 34 * 35 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 36 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 37 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 38 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 39 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 40 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 41 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 42 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 43 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 44 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 45 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 46 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 47 * THE POSSIBILITY OF SUCH DAMAGE. 48 ********************************************************************* */ 49 50 51 #ifndef _SB1250_REGS_H 52 #define _SB1250_REGS_H 53 54 #include "sb1250_defs.h" 55 56 57 /* ********************************************************************* 58 * Some general notes: 59 * 60 * For the most part, when there is more than one peripheral 61 * of the same type on the SOC, the constants below will be 62 * offsets from the base of each peripheral. For example, 63 * the MAC registers are described as offsets from the first 64 * MAC register, and there will be a MAC_REGISTER() macro 65 * to calculate the base address of a given MAC. 66 * 67 * The information in this file is based on the SB1250 SOC 68 * manual version 0.2, July 2000. 69 ********************************************************************* */ 70 71 72 /* ********************************************************************* 73 * Memory Controller Registers 74 ********************************************************************* */ 75 76 /* 77 * XXX: can't remove MC base 0 if 112x, since it's used by other macros, 78 * since there is one reg there (but it could get its addr/offset constant). 79 */ 80 #define A_MC_BASE_0 0x0010051000 81 #define A_MC_BASE_1 0x0010052000 82 #define MC_REGISTER_SPACING 0x1000 83 84 #define A_MC_BASE(ctlid) ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0) 85 #define A_MC_REGISTER(ctlid,reg) (A_MC_BASE(ctlid)+(reg)) 86 87 #define R_MC_CONFIG 0x0000000100 88 #define R_MC_DRAMCMD 0x0000000120 89 #define R_MC_DRAMMODE 0x0000000140 90 #define R_MC_TIMING1 0x0000000160 91 #define R_MC_TIMING2 0x0000000180 92 #define R_MC_CS_START 0x00000001A0 93 #define R_MC_CS_END 0x00000001C0 94 #define R_MC_CS_INTERLEAVE 0x00000001E0 95 #define S_MC_CS_STARTEND 16 96 97 #define R_MC_CSX_BASE 0x0000000200 98 #define R_MC_CSX_ROW 0x0000000000 /* relative to CSX_BASE, above */ 99 #define R_MC_CSX_COL 0x0000000020 /* relative to CSX_BASE, above */ 100 #define R_MC_CSX_BA 0x0000000040 /* relative to CSX_BASE, above */ 101 #define MC_CSX_SPACING 0x0000000060 /* relative to CSX_BASE, above */ 102 103 #define R_MC_CS0_ROW 0x0000000200 104 #define R_MC_CS0_COL 0x0000000220 105 #define R_MC_CS0_BA 0x0000000240 106 #define R_MC_CS1_ROW 0x0000000260 107 #define R_MC_CS1_COL 0x0000000280 108 #define R_MC_CS1_BA 0x00000002A0 109 #define R_MC_CS2_ROW 0x00000002C0 110 #define R_MC_CS2_COL 0x00000002E0 111 #define R_MC_CS2_BA 0x0000000300 112 #define R_MC_CS3_ROW 0x0000000320 113 #define R_MC_CS3_COL 0x0000000340 114 #define R_MC_CS3_BA 0x0000000360 115 #define R_MC_CS_ATTR 0x0000000380 116 #define R_MC_TEST_DATA 0x0000000400 117 #define R_MC_TEST_ECC 0x0000000420 118 #define R_MC_MCLK_CFG 0x0000000500 119 120 /* ********************************************************************* 121 * L2 Cache Control Registers 122 ********************************************************************* */ 123 124 #define A_L2_READ_TAG 0x0010040018 125 #define A_L2_ECC_TAG 0x0010040038 126 #if SIBYTE_HDR_FEATURE(112x, PASS1) 127 #define A_L2_READ_MISC 0x0010040058 128 #endif /* 112x PASS1 */ 129 #define A_L2_WAY_DISABLE 0x0010041000 130 #define A_L2_MAKEDISABLE(x) (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8)) 131 #define A_L2_MGMT_TAG_BASE 0x00D0000000 132 133 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 134 #define A_L2_CACHE_DISABLE 0x0010042000 135 #define A_L2_MAKECACHEDISABLE(x) (A_L2_CACHE_DISABLE | (((x)&0x0F) << 8)) 136 #define A_L2_MISC_CONFIG 0x0010043000 137 #endif /* 1250 PASS2 || 112x PASS1 */ 138 139 /* Backward-compatibility definitions. */ 140 /* XXX: discourage people from using these constants. */ 141 #define A_L2_READ_ADDRESS A_L2_READ_TAG 142 #define A_L2_EEC_ADDRESS A_L2_ECC_TAG 143 144 145 /* ********************************************************************* 146 * PCI Interface Registers 147 ********************************************************************* */ 148 149 #define A_PCI_TYPE00_HEADER 0x00DE000000 150 #define A_PCI_TYPE01_HEADER 0x00DE000800 151 152 153 /* ********************************************************************* 154 * Ethernet DMA and MACs 155 ********************************************************************* */ 156 157 #define A_MAC_BASE_0 0x0010064000 158 #define A_MAC_BASE_1 0x0010065000 159 #if SIBYTE_HDR_FEATURE_CHIP(1250) 160 #define A_MAC_BASE_2 0x0010066000 161 #endif /* 1250 */ 162 163 #define MAC_SPACING 0x1000 164 #define MAC_DMA_TXRX_SPACING 0x0400 165 #define MAC_DMA_CHANNEL_SPACING 0x0100 166 #define DMA_RX 0 167 #define DMA_TX 1 168 #define MAC_NUM_DMACHAN 2 /* channels per direction */ 169 170 /* XXX: not correct; depends on SOC type. */ 171 #define MAC_NUM_PORTS 3 172 173 #define A_MAC_CHANNEL_BASE(macnum) \ 174 (A_MAC_BASE_0 + \ 175 MAC_SPACING*(macnum)) 176 177 #define A_MAC_REGISTER(macnum,reg) \ 178 (A_MAC_BASE_0 + \ 179 MAC_SPACING*(macnum) + (reg)) 180 181 182 #define R_MAC_DMA_CHANNELS 0x800 /* Relative to A_MAC_CHANNEL_BASE */ 183 184 #define A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) \ 185 ((A_MAC_CHANNEL_BASE(macnum)) + \ 186 R_MAC_DMA_CHANNELS + \ 187 (MAC_DMA_TXRX_SPACING*(txrx)) + \ 188 (MAC_DMA_CHANNEL_SPACING*(chan))) 189 190 #define R_MAC_DMA_CHANNEL_BASE(txrx,chan) \ 191 (R_MAC_DMA_CHANNELS + \ 192 (MAC_DMA_TXRX_SPACING*(txrx)) + \ 193 (MAC_DMA_CHANNEL_SPACING*(chan))) 194 195 #define A_MAC_DMA_REGISTER(macnum,txrx,chan,reg) \ 196 (A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) + \ 197 (reg)) 198 199 #define R_MAC_DMA_REGISTER(txrx,chan,reg) \ 200 (R_MAC_DMA_CHANNEL_BASE(txrx,chan) + \ 201 (reg)) 202 203 /* 204 * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE 205 */ 206 207 #define R_MAC_DMA_CONFIG0 0x00000000 208 #define R_MAC_DMA_CONFIG1 0x00000008 209 #define R_MAC_DMA_DSCR_BASE 0x00000010 210 #define R_MAC_DMA_DSCR_CNT 0x00000018 211 #define R_MAC_DMA_CUR_DSCRA 0x00000020 212 #define R_MAC_DMA_CUR_DSCRB 0x00000028 213 #define R_MAC_DMA_CUR_DSCRADDR 0x00000030 214 #if SIBYTE_HDR_FEATURE(112x, PASS1) 215 #define R_MAC_DMA_OODPKTLOST_RX 0x00000038 /* rx only */ 216 #endif /* 112x PASS1 */ 217 218 /* 219 * RMON Counters 220 */ 221 222 #define R_MAC_RMON_TX_BYTES 0x00000000 223 #define R_MAC_RMON_COLLISIONS 0x00000008 224 #define R_MAC_RMON_LATE_COL 0x00000010 225 #define R_MAC_RMON_EX_COL 0x00000018 226 #define R_MAC_RMON_FCS_ERROR 0x00000020 227 #define R_MAC_RMON_TX_ABORT 0x00000028 228 /* Counter #6 (0x30) now reserved */ 229 #define R_MAC_RMON_TX_BAD 0x00000038 230 #define R_MAC_RMON_TX_GOOD 0x00000040 231 #define R_MAC_RMON_TX_RUNT 0x00000048 232 #define R_MAC_RMON_TX_OVERSIZE 0x00000050 233 #define R_MAC_RMON_RX_BYTES 0x00000080 234 #define R_MAC_RMON_RX_MCAST 0x00000088 235 #define R_MAC_RMON_RX_BCAST 0x00000090 236 #define R_MAC_RMON_RX_BAD 0x00000098 237 #define R_MAC_RMON_RX_GOOD 0x000000A0 238 #define R_MAC_RMON_RX_RUNT 0x000000A8 239 #define R_MAC_RMON_RX_OVERSIZE 0x000000B0 240 #define R_MAC_RMON_RX_FCS_ERROR 0x000000B8 241 #define R_MAC_RMON_RX_LENGTH_ERROR 0x000000C0 242 #define R_MAC_RMON_RX_CODE_ERROR 0x000000C8 243 #define R_MAC_RMON_RX_ALIGN_ERROR 0x000000D0 244 245 /* Updated to spec 0.2 */ 246 #define R_MAC_CFG 0x00000100 247 #define R_MAC_THRSH_CFG 0x00000108 248 #define R_MAC_VLANTAG 0x00000110 249 #define R_MAC_FRAMECFG 0x00000118 250 #define R_MAC_EOPCNT 0x00000120 251 #define R_MAC_FIFO_PTRS 0x00000130 252 #define R_MAC_ADFILTER_CFG 0x00000200 253 #define R_MAC_ETHERNET_ADDR 0x00000208 254 #define R_MAC_PKT_TYPE 0x00000210 255 #if SIBYTE_HDR_FEATURE(112x, PASS1) 256 #define R_MAC_ADMASK0 0x00000218 257 #define R_MAC_ADMASK1 0x00000220 258 #endif /* 112x PASS1 */ 259 #define R_MAC_HASH_BASE 0x00000240 260 #define R_MAC_ADDR_BASE 0x00000280 261 #define R_MAC_CHLO0_BASE 0x00000300 262 #define R_MAC_CHUP0_BASE 0x00000320 263 #define R_MAC_ENABLE 0x00000400 264 #define R_MAC_STATUS 0x00000408 265 #define R_MAC_INT_MASK 0x00000410 266 #define R_MAC_TXD_CTL 0x00000420 267 #define R_MAC_MDIO 0x00000428 268 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 269 #define R_MAC_STATUS1 0x00000430 270 #endif /* 1250 PASS2 || 112x PASS1 */ 271 #define R_MAC_DEBUG_STATUS 0x00000448 272 273 #define MAC_HASH_COUNT 8 274 #define MAC_ADDR_COUNT 8 275 #define MAC_CHMAP_COUNT 4 276 277 278 /* ********************************************************************* 279 * DUART Registers 280 ********************************************************************* */ 281 282 283 #define R_DUART_NUM_PORTS 2 284 285 #define A_DUART 0x0010060000 286 287 #define A_DUART_REG(r) 288 289 #define DUART_CHANREG_SPACING 0x100 290 #define A_DUART_CHANREG(chan,reg) (A_DUART + DUART_CHANREG_SPACING*(chan) + (reg)) 291 #define R_DUART_CHANREG(chan,reg) (DUART_CHANREG_SPACING*(chan) + (reg)) 292 293 #define R_DUART_MODE_REG_1 0x100 294 #define R_DUART_MODE_REG_2 0x110 295 #define R_DUART_STATUS 0x120 296 #define R_DUART_CLK_SEL 0x130 297 #define R_DUART_CMD 0x150 298 #define R_DUART_RX_HOLD 0x160 299 #define R_DUART_TX_HOLD 0x170 300 301 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 302 #define R_DUART_FULL_CTL 0x140 303 #define R_DUART_OPCR_X 0x180 304 #define R_DUART_AUXCTL_X 0x190 305 #endif /* 1250 PASS2 || 112x PASS1 */ 306 307 308 /* 309 * The IMR and ISR can't be addressed with A_DUART_CHANREG, 310 * so use this macro instead. 311 */ 312 313 #define R_DUART_AUX_CTRL 0x310 314 #define R_DUART_ISR_A 0x320 315 #define R_DUART_IMR_A 0x330 316 #define R_DUART_ISR_B 0x340 317 #define R_DUART_IMR_B 0x350 318 #define R_DUART_OUT_PORT 0x360 319 #define R_DUART_OPCR 0x370 320 321 #define R_DUART_SET_OPR 0x3B0 322 #define R_DUART_CLEAR_OPR 0x3C0 323 324 #define DUART_IMRISR_SPACING 0x20 325 326 #define R_DUART_IMRREG(chan) (R_DUART_IMR_A + (chan)*DUART_IMRISR_SPACING) 327 #define R_DUART_ISRREG(chan) (R_DUART_ISR_A + (chan)*DUART_IMRISR_SPACING) 328 329 #define A_DUART_IMRREG(chan) (A_DUART + R_DUART_IMRREG(chan)) 330 #define A_DUART_ISRREG(chan) (A_DUART + R_DUART_ISRREG(chan)) 331 332 333 334 335 /* 336 * These constants are the absolute addresses. 337 */ 338 339 #define A_DUART_MODE_REG_1_A 0x0010060100 340 #define A_DUART_MODE_REG_2_A 0x0010060110 341 #define A_DUART_STATUS_A 0x0010060120 342 #define A_DUART_CLK_SEL_A 0x0010060130 343 #define A_DUART_CMD_A 0x0010060150 344 #define A_DUART_RX_HOLD_A 0x0010060160 345 #define A_DUART_TX_HOLD_A 0x0010060170 346 347 #define A_DUART_MODE_REG_1_B 0x0010060200 348 #define A_DUART_MODE_REG_2_B 0x0010060210 349 #define A_DUART_STATUS_B 0x0010060220 350 #define A_DUART_CLK_SEL_B 0x0010060230 351 #define A_DUART_CMD_B 0x0010060250 352 #define A_DUART_RX_HOLD_B 0x0010060260 353 #define A_DUART_TX_HOLD_B 0x0010060270 354 355 #define A_DUART_INPORT_CHNG 0x0010060300 356 #define A_DUART_AUX_CTRL 0x0010060310 357 #define A_DUART_ISR_A 0x0010060320 358 #define A_DUART_IMR_A 0x0010060330 359 #define A_DUART_ISR_B 0x0010060340 360 #define A_DUART_IMR_B 0x0010060350 361 #define A_DUART_OUT_PORT 0x0010060360 362 #define A_DUART_OPCR 0x0010060370 363 #define A_DUART_IN_PORT 0x0010060380 364 #define A_DUART_ISR 0x0010060390 365 #define A_DUART_IMR 0x00100603A0 366 #define A_DUART_SET_OPR 0x00100603B0 367 #define A_DUART_CLEAR_OPR 0x00100603C0 368 #define A_DUART_INPORT_CHNG_A 0x00100603D0 369 #define A_DUART_INPORT_CHNG_B 0x00100603E0 370 371 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 372 #define A_DUART_FULL_CTL_A 0x0010060140 373 #define A_DUART_FULL_CTL_B 0x0010060240 374 375 #define A_DUART_OPCR_A 0x0010060180 376 #define A_DUART_OPCR_B 0x0010060280 377 378 #define A_DUART_INPORT_CHNG_DEBUG 0x00100603F0 379 #endif /* 1250 PASS2 || 112x PASS1 */ 380 381 382 /* ********************************************************************* 383 * Synchronous Serial Registers 384 ********************************************************************* */ 385 386 387 #define A_SER_BASE_0 0x0010060400 388 #define A_SER_BASE_1 0x0010060800 389 #define SER_SPACING 0x400 390 391 #define SER_DMA_TXRX_SPACING 0x80 392 393 #define SER_NUM_PORTS 2 394 395 #define A_SER_CHANNEL_BASE(sernum) \ 396 (A_SER_BASE_0 + \ 397 SER_SPACING*(sernum)) 398 399 #define A_SER_REGISTER(sernum,reg) \ 400 (A_SER_BASE_0 + \ 401 SER_SPACING*(sernum) + (reg)) 402 403 404 #define R_SER_DMA_CHANNELS 0 /* Relative to A_SER_BASE_x */ 405 406 #define A_SER_DMA_CHANNEL_BASE(sernum,txrx) \ 407 ((A_SER_CHANNEL_BASE(sernum)) + \ 408 R_SER_DMA_CHANNELS + \ 409 (SER_DMA_TXRX_SPACING*(txrx))) 410 411 #define A_SER_DMA_REGISTER(sernum,txrx,reg) \ 412 (A_SER_DMA_CHANNEL_BASE(sernum,txrx) + \ 413 (reg)) 414 415 416 /* 417 * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE 418 */ 419 420 #define R_SER_DMA_CONFIG0 0x00000000 421 #define R_SER_DMA_CONFIG1 0x00000008 422 #define R_SER_DMA_DSCR_BASE 0x00000010 423 #define R_SER_DMA_DSCR_CNT 0x00000018 424 #define R_SER_DMA_CUR_DSCRA 0x00000020 425 #define R_SER_DMA_CUR_DSCRB 0x00000028 426 #define R_SER_DMA_CUR_DSCRADDR 0x00000030 427 428 #define R_SER_DMA_CONFIG0_RX 0x00000000 429 #define R_SER_DMA_CONFIG1_RX 0x00000008 430 #define R_SER_DMA_DSCR_BASE_RX 0x00000010 431 #define R_SER_DMA_DSCR_COUNT_RX 0x00000018 432 #define R_SER_DMA_CUR_DSCR_A_RX 0x00000020 433 #define R_SER_DMA_CUR_DSCR_B_RX 0x00000028 434 #define R_SER_DMA_CUR_DSCR_ADDR_RX 0x00000030 435 436 #define R_SER_DMA_CONFIG0_TX 0x00000080 437 #define R_SER_DMA_CONFIG1_TX 0x00000088 438 #define R_SER_DMA_DSCR_BASE_TX 0x00000090 439 #define R_SER_DMA_DSCR_COUNT_TX 0x00000098 440 #define R_SER_DMA_CUR_DSCR_A_TX 0x000000A0 441 #define R_SER_DMA_CUR_DSCR_B_TX 0x000000A8 442 #define R_SER_DMA_CUR_DSCR_ADDR_TX 0x000000B0 443 444 #define R_SER_MODE 0x00000100 445 #define R_SER_MINFRM_SZ 0x00000108 446 #define R_SER_MAXFRM_SZ 0x00000110 447 #define R_SER_ADDR 0x00000118 448 #define R_SER_USR0_ADDR 0x00000120 449 #define R_SER_USR1_ADDR 0x00000128 450 #define R_SER_USR2_ADDR 0x00000130 451 #define R_SER_USR3_ADDR 0x00000138 452 #define R_SER_CMD 0x00000140 453 #define R_SER_TX_RD_THRSH 0x00000160 454 #define R_SER_TX_WR_THRSH 0x00000168 455 #define R_SER_RX_RD_THRSH 0x00000170 456 #define R_SER_LINE_MODE 0x00000178 457 #define R_SER_DMA_ENABLE 0x00000180 458 #define R_SER_INT_MASK 0x00000190 459 #define R_SER_STATUS 0x00000188 460 #define R_SER_STATUS_DEBUG 0x000001A8 461 #define R_SER_RX_TABLE_BASE 0x00000200 462 #define SER_RX_TABLE_COUNT 16 463 #define R_SER_TX_TABLE_BASE 0x00000300 464 #define SER_TX_TABLE_COUNT 16 465 466 /* RMON Counters */ 467 #define R_SER_RMON_TX_BYTE_LO 0x000001C0 468 #define R_SER_RMON_TX_BYTE_HI 0x000001C8 469 #define R_SER_RMON_RX_BYTE_LO 0x000001D0 470 #define R_SER_RMON_RX_BYTE_HI 0x000001D8 471 #define R_SER_RMON_TX_UNDERRUN 0x000001E0 472 #define R_SER_RMON_RX_OVERFLOW 0x000001E8 473 #define R_SER_RMON_RX_ERRORS 0x000001F0 474 #define R_SER_RMON_RX_BADADDR 0x000001F8 475 476 /* ********************************************************************* 477 * Generic Bus Registers 478 ********************************************************************* */ 479 480 #define IO_EXT_CFG_COUNT 8 481 482 #define A_IO_EXT_BASE 0x0010061000 483 #define A_IO_EXT_REG(r) (A_IO_EXT_BASE + (r)) 484 485 #define A_IO_EXT_CFG_BASE 0x0010061000 486 #define A_IO_EXT_MULT_SIZE_BASE 0x0010061100 487 #define A_IO_EXT_START_ADDR_BASE 0x0010061200 488 #define A_IO_EXT_TIME_CFG0_BASE 0x0010061600 489 #define A_IO_EXT_TIME_CFG1_BASE 0x0010061700 490 491 #define IO_EXT_REGISTER_SPACING 8 492 #define A_IO_EXT_CS_BASE(cs) (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs)) 493 #define R_IO_EXT_REG(reg,cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg)) 494 495 #define R_IO_EXT_CFG 0x0000 496 #define R_IO_EXT_MULT_SIZE 0x0100 497 #define R_IO_EXT_START_ADDR 0x0200 498 #define R_IO_EXT_TIME_CFG0 0x0600 499 #define R_IO_EXT_TIME_CFG1 0x0700 500 501 502 #define A_IO_INTERRUPT_STATUS 0x0010061A00 503 #define A_IO_INTERRUPT_DATA0 0x0010061A10 504 #define A_IO_INTERRUPT_DATA1 0x0010061A18 505 #define A_IO_INTERRUPT_DATA2 0x0010061A20 506 #define A_IO_INTERRUPT_DATA3 0x0010061A28 507 #define A_IO_INTERRUPT_ADDR0 0x0010061A30 508 #define A_IO_INTERRUPT_ADDR1 0x0010061A40 509 #define A_IO_INTERRUPT_PARITY 0x0010061A50 510 #define A_IO_PCMCIA_CFG 0x0010061A60 511 #define A_IO_PCMCIA_STATUS 0x0010061A70 512 #define A_IO_DRIVE_0 0x0010061300 513 #define A_IO_DRIVE_1 0x0010061308 514 #define A_IO_DRIVE_2 0x0010061310 515 #define A_IO_DRIVE_3 0x0010061318 516 #define A_IO_DRIVE_BASE A_IO_DRIVE_0 517 #define IO_DRIVE_REGISTER_SPACING 8 518 #define R_IO_DRIVE(x) ((x)*IO_DRIVE_REGISTER_SPACING) 519 #define A_IO_DRIVE(x) (A_IO_DRIVE_BASE + R_IO_DRIVE(x)) 520 521 #define R_IO_INTERRUPT_STATUS 0x0A00 522 #define R_IO_INTERRUPT_DATA0 0x0A10 523 #define R_IO_INTERRUPT_DATA1 0x0A18 524 #define R_IO_INTERRUPT_DATA2 0x0A20 525 #define R_IO_INTERRUPT_DATA3 0x0A28 526 #define R_IO_INTERRUPT_ADDR0 0x0A30 527 #define R_IO_INTERRUPT_ADDR1 0x0A40 528 #define R_IO_INTERRUPT_PARITY 0x0A50 529 #define R_IO_PCMCIA_CFG 0x0A60 530 #define R_IO_PCMCIA_STATUS 0x0A70 531 532 /* ********************************************************************* 533 * GPIO Registers 534 ********************************************************************* */ 535 536 #define A_GPIO_CLR_EDGE 0x0010061A80 537 #define A_GPIO_INT_TYPE 0x0010061A88 538 #define A_GPIO_INPUT_INVERT 0x0010061A90 539 #define A_GPIO_GLITCH 0x0010061A98 540 #define A_GPIO_READ 0x0010061AA0 541 #define A_GPIO_DIRECTION 0x0010061AA8 542 #define A_GPIO_PIN_CLR 0x0010061AB0 543 #define A_GPIO_PIN_SET 0x0010061AB8 544 545 #define A_GPIO_BASE 0x0010061A80 546 547 #define R_GPIO_CLR_EDGE 0x00 548 #define R_GPIO_INT_TYPE 0x08 549 #define R_GPIO_INPUT_INVERT 0x10 550 #define R_GPIO_GLITCH 0x18 551 #define R_GPIO_READ 0x20 552 #define R_GPIO_DIRECTION 0x28 553 #define R_GPIO_PIN_CLR 0x30 554 #define R_GPIO_PIN_SET 0x38 555 556 /* ********************************************************************* 557 * SMBus Registers 558 ********************************************************************* */ 559 560 #define A_SMB_XTRA_0 0x0010060000 561 #define A_SMB_XTRA_1 0x0010060008 562 #define A_SMB_FREQ_0 0x0010060010 563 #define A_SMB_FREQ_1 0x0010060018 564 #define A_SMB_STATUS_0 0x0010060020 565 #define A_SMB_STATUS_1 0x0010060028 566 #define A_SMB_CMD_0 0x0010060030 567 #define A_SMB_CMD_1 0x0010060038 568 #define A_SMB_START_0 0x0010060040 569 #define A_SMB_START_1 0x0010060048 570 #define A_SMB_DATA_0 0x0010060050 571 #define A_SMB_DATA_1 0x0010060058 572 #define A_SMB_CONTROL_0 0x0010060060 573 #define A_SMB_CONTROL_1 0x0010060068 574 #define A_SMB_PEC_0 0x0010060070 575 #define A_SMB_PEC_1 0x0010060078 576 577 #define A_SMB_0 0x0010060000 578 #define A_SMB_1 0x0010060008 579 #define SMB_REGISTER_SPACING 0x8 580 #define A_SMB_BASE(idx) (A_SMB_0+(idx)*SMB_REGISTER_SPACING) 581 #define A_SMB_REGISTER(idx,reg) (A_SMB_BASE(idx)+(reg)) 582 583 #define R_SMB_XTRA 0x0000000000 584 #define R_SMB_FREQ 0x0000000010 585 #define R_SMB_STATUS 0x0000000020 586 #define R_SMB_CMD 0x0000000030 587 #define R_SMB_START 0x0000000040 588 #define R_SMB_DATA 0x0000000050 589 #define R_SMB_CONTROL 0x0000000060 590 #define R_SMB_PEC 0x0000000070 591 592 /* ********************************************************************* 593 * Timer Registers 594 ********************************************************************* */ 595 596 /* 597 * Watchdog timers 598 */ 599 600 #define A_SCD_WDOG_0 0x0010020050 601 #define A_SCD_WDOG_1 0x0010020150 602 #define SCD_WDOG_SPACING 0x100 603 #define SCD_NUM_WDOGS 2 604 #define A_SCD_WDOG_BASE(w) (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w)) 605 #define A_SCD_WDOG_REGISTER(w,r) (A_SCD_WDOG_BASE(w) + (r)) 606 607 #define R_SCD_WDOG_INIT 0x0000000000 608 #define R_SCD_WDOG_CNT 0x0000000008 609 #define R_SCD_WDOG_CFG 0x0000000010 610 611 #define A_SCD_WDOG_INIT_0 0x0010020050 612 #define A_SCD_WDOG_CNT_0 0x0010020058 613 #define A_SCD_WDOG_CFG_0 0x0010020060 614 615 #define A_SCD_WDOG_INIT_1 0x0010020150 616 #define A_SCD_WDOG_CNT_1 0x0010020158 617 #define A_SCD_WDOG_CFG_1 0x0010020160 618 619 /* 620 * Generic timers 621 */ 622 623 #define A_SCD_TIMER_0 0x0010020070 624 #define A_SCD_TIMER_1 0x0010020078 625 #define A_SCD_TIMER_2 0x0010020170 626 #define A_SCD_TIMER_3 0x0010020178 627 #define SCD_NUM_TIMERS 4 628 #define A_SCD_TIMER_BASE(w) (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1)) 629 #define A_SCD_TIMER_REGISTER(w,r) (A_SCD_TIMER_BASE(w) + (r)) 630 631 #define R_SCD_TIMER_INIT 0x0000000000 632 #define R_SCD_TIMER_CNT 0x0000000010 633 #define R_SCD_TIMER_CFG 0x0000000020 634 635 #define A_SCD_TIMER_INIT_0 0x0010020070 636 #define A_SCD_TIMER_CNT_0 0x0010020080 637 #define A_SCD_TIMER_CFG_0 0x0010020090 638 639 #define A_SCD_TIMER_INIT_1 0x0010020078 640 #define A_SCD_TIMER_CNT_1 0x0010020088 641 #define A_SCD_TIMER_CFG_1 0x0010020098 642 643 #define A_SCD_TIMER_INIT_2 0x0010020170 644 #define A_SCD_TIMER_CNT_2 0x0010020180 645 #define A_SCD_TIMER_CFG_2 0x0010020190 646 647 #define A_SCD_TIMER_INIT_3 0x0010020178 648 #define A_SCD_TIMER_CNT_3 0x0010020188 649 #define A_SCD_TIMER_CFG_3 0x0010020198 650 651 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 652 #define A_SCD_SCRATCH 0x0010020C10 653 654 #define A_SCD_ZBBUS_CYCLE_COUNT 0x0010030000 655 #define A_SCD_ZBBUS_CYCLE_CP0 0x0010020C00 656 #define A_SCD_ZBBUS_CYCLE_CP1 0x0010020C08 657 #endif /* 1250 PASS2 || 112x PASS1 */ 658 659 660 /* ********************************************************************* 661 * System Control Registers 662 ********************************************************************* */ 663 664 #define A_SCD_SYSTEM_REVISION 0x0010020000 665 #define A_SCD_SYSTEM_CFG 0x0010020008 666 667 /* ********************************************************************* 668 * System Address Trap Registers 669 ********************************************************************* */ 670 671 #define A_ADDR_TRAP_INDEX 0x00100200B0 672 #define A_ADDR_TRAP_REG 0x00100200B8 673 #define A_ADDR_TRAP_UP_0 0x0010020400 674 #define A_ADDR_TRAP_UP_1 0x0010020408 675 #define A_ADDR_TRAP_UP_2 0x0010020410 676 #define A_ADDR_TRAP_UP_3 0x0010020418 677 #define A_ADDR_TRAP_DOWN_0 0x0010020420 678 #define A_ADDR_TRAP_DOWN_1 0x0010020428 679 #define A_ADDR_TRAP_DOWN_2 0x0010020430 680 #define A_ADDR_TRAP_DOWN_3 0x0010020438 681 #define A_ADDR_TRAP_CFG_0 0x0010020440 682 #define A_ADDR_TRAP_CFG_1 0x0010020448 683 #define A_ADDR_TRAP_CFG_2 0x0010020450 684 #define A_ADDR_TRAP_CFG_3 0x0010020458 685 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 686 #define A_ADDR_TRAP_REG_DEBUG 0x0010020460 687 #endif /* 1250 PASS2 || 112x PASS1 */ 688 689 690 /* ********************************************************************* 691 * System Interrupt Mapper Registers 692 ********************************************************************* */ 693 694 #define A_IMR_CPU0_BASE 0x0010020000 695 #define A_IMR_CPU1_BASE 0x0010022000 696 #define IMR_REGISTER_SPACING 0x2000 697 #define IMR_REGISTER_SPACING_SHIFT 13 698 699 #define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING) 700 #define A_IMR_REGISTER(cpu,reg) (A_IMR_MAPPER(cpu)+(reg)) 701 702 #define R_IMR_INTERRUPT_DIAG 0x0010 703 #define R_IMR_INTERRUPT_MASK 0x0028 704 #define R_IMR_INTERRUPT_TRACE 0x0038 705 #define R_IMR_INTERRUPT_SOURCE_STATUS 0x0040 706 #define R_IMR_LDT_INTERRUPT_SET 0x0048 707 #define R_IMR_LDT_INTERRUPT 0x0018 708 #define R_IMR_LDT_INTERRUPT_CLR 0x0020 709 #define R_IMR_MAILBOX_CPU 0x00c0 710 #define R_IMR_ALIAS_MAILBOX_CPU 0x1000 711 #define R_IMR_MAILBOX_SET_CPU 0x00C8 712 #define R_IMR_ALIAS_MAILBOX_SET_CPU 0x1008 713 #define R_IMR_MAILBOX_CLR_CPU 0x00D0 714 #define R_IMR_INTERRUPT_STATUS_BASE 0x0100 715 #define R_IMR_INTERRUPT_STATUS_COUNT 7 716 #define R_IMR_INTERRUPT_MAP_BASE 0x0200 717 #define R_IMR_INTERRUPT_MAP_COUNT 64 718 719 /* ********************************************************************* 720 * System Performance Counter Registers 721 ********************************************************************* */ 722 723 #define A_SCD_PERF_CNT_CFG 0x00100204C0 724 #define A_SCD_PERF_CNT_0 0x00100204D0 725 #define A_SCD_PERF_CNT_1 0x00100204D8 726 #define A_SCD_PERF_CNT_2 0x00100204E0 727 #define A_SCD_PERF_CNT_3 0x00100204E8 728 729 /* ********************************************************************* 730 * System Bus Watcher Registers 731 ********************************************************************* */ 732 733 #define A_SCD_BUS_ERR_STATUS 0x0010020880 734 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 735 #define A_SCD_BUS_ERR_STATUS_DEBUG 0x00100208D0 736 #endif /* 1250 PASS2 || 112x PASS1 */ 737 #define A_BUS_ERR_DATA_0 0x00100208A0 738 #define A_BUS_ERR_DATA_1 0x00100208A8 739 #define A_BUS_ERR_DATA_2 0x00100208B0 740 #define A_BUS_ERR_DATA_3 0x00100208B8 741 #define A_BUS_L2_ERRORS 0x00100208C0 742 #define A_BUS_MEM_IO_ERRORS 0x00100208C8 743 744 /* ********************************************************************* 745 * System Debug Controller Registers 746 ********************************************************************* */ 747 748 #define A_SCD_JTAG_BASE 0x0010000000 749 750 /* ********************************************************************* 751 * System Trace Buffer Registers 752 ********************************************************************* */ 753 754 #define A_SCD_TRACE_CFG 0x0010020A00 755 #define A_SCD_TRACE_READ 0x0010020A08 756 #define A_SCD_TRACE_EVENT_0 0x0010020A20 757 #define A_SCD_TRACE_EVENT_1 0x0010020A28 758 #define A_SCD_TRACE_EVENT_2 0x0010020A30 759 #define A_SCD_TRACE_EVENT_3 0x0010020A38 760 #define A_SCD_TRACE_SEQUENCE_0 0x0010020A40 761 #define A_SCD_TRACE_SEQUENCE_1 0x0010020A48 762 #define A_SCD_TRACE_SEQUENCE_2 0x0010020A50 763 #define A_SCD_TRACE_SEQUENCE_3 0x0010020A58 764 #define A_SCD_TRACE_EVENT_4 0x0010020A60 765 #define A_SCD_TRACE_EVENT_5 0x0010020A68 766 #define A_SCD_TRACE_EVENT_6 0x0010020A70 767 #define A_SCD_TRACE_EVENT_7 0x0010020A78 768 #define A_SCD_TRACE_SEQUENCE_4 0x0010020A80 769 #define A_SCD_TRACE_SEQUENCE_5 0x0010020A88 770 #define A_SCD_TRACE_SEQUENCE_6 0x0010020A90 771 #define A_SCD_TRACE_SEQUENCE_7 0x0010020A98 772 773 /* ********************************************************************* 774 * System Generic DMA Registers 775 ********************************************************************* */ 776 777 #define A_DM_0 0x0010020B00 778 #define A_DM_1 0x0010020B20 779 #define A_DM_2 0x0010020B40 780 #define A_DM_3 0x0010020B60 781 #define DM_REGISTER_SPACING 0x20 782 #define DM_NUM_CHANNELS 4 783 #define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING)) 784 #define A_DM_REGISTER(idx,reg) (A_DM_BASE(idx) + (reg)) 785 786 #define R_DM_DSCR_BASE 0x0000000000 787 #define R_DM_DSCR_COUNT 0x0000000008 788 #define R_DM_CUR_DSCR_ADDR 0x0000000010 789 #define R_DM_DSCR_BASE_DEBUG 0x0000000018 790 791 #if SIBYTE_HDR_FEATURE(112x, PASS1) 792 #define A_DM_PARTIAL_0 0x0010020ba0 793 #define A_DM_PARTIAL_1 0x0010020ba8 794 #define A_DM_PARTIAL_2 0x0010020bb0 795 #define A_DM_PARTIAL_3 0x0010020bb8 796 #define DM_PARTIAL_REGISTER_SPACING 0x8 797 #define A_DM_PARTIAL(idx) (A_DM_PARTIAL_0 + ((idx) * DM_PARTIAL_REGISTER_SPACING)) 798 #endif /* 112x PASS1 */ 799 800 #if SIBYTE_HDR_FEATURE(112x, PASS1) 801 #define A_DM_CRC_0 0x0010020b80 802 #define A_DM_CRC_1 0x0010020b90 803 #define DM_CRC_REGISTER_SPACING 0x10 804 #define DM_CRC_NUM_CHANNELS 2 805 #define A_DM_CRC_BASE(idx) (A_DM_CRC_0 + ((idx) * DM_CRC_REGISTER_SPACING)) 806 #define A_DM_CRC_REGISTER(idx,reg) (A_DM_CRC_BASE(idx) + (reg)) 807 808 #define R_CRC_DEF_0 0x00 809 #define R_CTCP_DEF_0 0x08 810 #endif /* 112x PASS1 */ 811 812 /* ********************************************************************* 813 * Physical Address Map 814 ********************************************************************* */ 815 816 #define A_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) 817 #define A_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) 818 #define A_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) 819 #define A_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000) 820 #define A_PHYS_GENBUS _SB_MAKE64(0x0010090000) 821 #define A_PHYS_GENBUS_END _SB_MAKE64(0x0040000000) 822 #define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000) 823 #define A_PHYS_LDTPCI_IO_MATCH_BITS_32 _SB_MAKE64(0x0060000000) 824 #define A_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000) 825 #define A_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000) 826 #define A_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000) 827 #define A_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000) 828 #define A_PHYS_LDT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000) 829 #define A_PHYS_LDTPCI_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000) 830 #define A_PHYS_LDTPCI_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000) 831 #define A_PHYS_LDT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000) 832 #define A_PHYS_LDTPCI_IO_MATCH_BITS _SB_MAKE64(0x00FC000000) 833 #define A_PHYS_LDTPCI_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000) 834 #define A_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000) 835 #define A_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024)) 836 #define A_PHYS_LDT_EXP _SB_MAKE64(0x8000000000) 837 #define A_PHYS_PCI_FULLACCESS_BYTES _SB_MAKE64(0xF000000000) 838 #define A_PHYS_PCI_FULLACCESS_BITS _SB_MAKE64(0xF100000000) 839 #define A_PHYS_RESERVED _SB_MAKE64(0xF200000000) 840 #define A_PHYS_RESERVED_SPECIAL_LDT _SB_MAKE64(0xFD00000000) 841 842 #define A_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000) 843 #define PHYS_L2CACHE_NUM_WAYS 4 844 #define A_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000080000) 845 #define A_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0180000) 846 #define A_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D01A0000) 847 #define A_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D01C0000) 848 #define A_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D01E0000) 849 850 851 #endif 852
Indexes created Thu Oct 02 01:09:59 GMT 2025