sb1250_uart.h revision 1.2.2.2
1 1.2.2.2 nathanw /* ********************************************************************* 2 1.2.2.2 nathanw * SB1250 Board Support Package 3 1.2.2.2 nathanw * 4 1.2.2.2 nathanw * UART Constants File: sb1250_uart.h 5 1.2.2.2 nathanw * 6 1.2.2.2 nathanw * This module contains constants and macros useful for 7 1.2.2.2 nathanw * manipulating the SB1250's UARTs 8 1.2.2.2 nathanw * 9 1.2.2.2 nathanw * SB1250 specification level: User's manual 1/02/02 10 1.2.2.2 nathanw * 11 1.2.2.2 nathanw * Author: Mitch Lichtenberg (mpl (at) broadcom.com) 12 1.2.2.2 nathanw * 13 1.2.2.2 nathanw ********************************************************************* 14 1.2.2.2 nathanw * 15 1.2.2.2 nathanw * Copyright 2000,2001 16 1.2.2.2 nathanw * Broadcom Corporation. All rights reserved. 17 1.2.2.2 nathanw * 18 1.2.2.2 nathanw * This software is furnished under license and may be used and 19 1.2.2.2 nathanw * copied only in accordance with the following terms and 20 1.2.2.2 nathanw * conditions. Subject to these conditions, you may download, 21 1.2.2.2 nathanw * copy, install, use, modify and distribute modified or unmodified 22 1.2.2.2 nathanw * copies of this software in source and/or binary form. No title 23 1.2.2.2 nathanw * or ownership is transferred hereby. 24 1.2.2.2 nathanw * 25 1.2.2.2 nathanw * 1) Any source code used, modified or distributed must reproduce 26 1.2.2.2 nathanw * and retain this copyright notice and list of conditions as 27 1.2.2.2 nathanw * they appear in the source file. 28 1.2.2.2 nathanw * 29 1.2.2.2 nathanw * 2) No right is granted to use any trade name, trademark, or 30 1.2.2.2 nathanw * logo of Broadcom Corporation. Neither the "Broadcom 31 1.2.2.2 nathanw * Corporation" name nor any trademark or logo of Broadcom 32 1.2.2.2 nathanw * Corporation may be used to endorse or promote products 33 1.2.2.2 nathanw * derived from this software without the prior written 34 1.2.2.2 nathanw * permission of Broadcom Corporation. 35 1.2.2.2 nathanw * 36 1.2.2.2 nathanw * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 37 1.2.2.2 nathanw * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 38 1.2.2.2 nathanw * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 39 1.2.2.2 nathanw * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 40 1.2.2.2 nathanw * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 41 1.2.2.2 nathanw * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 42 1.2.2.2 nathanw * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 43 1.2.2.2 nathanw * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 44 1.2.2.2 nathanw * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 45 1.2.2.2 nathanw * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 46 1.2.2.2 nathanw * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 47 1.2.2.2 nathanw * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 48 1.2.2.2 nathanw * THE POSSIBILITY OF SUCH DAMAGE. 49 1.2.2.2 nathanw ********************************************************************* */ 50 1.2.2.2 nathanw 51 1.2.2.2 nathanw 52 1.2.2.2 nathanw #ifndef _SB1250_UART_H 53 1.2.2.2 nathanw #define _SB1250_UART_H 54 1.2.2.2 nathanw 55 1.2.2.2 nathanw #include "sb1250_defs.h" 56 1.2.2.2 nathanw 57 1.2.2.2 nathanw /* ********************************************************************** 58 1.2.2.2 nathanw * DUART Registers 59 1.2.2.2 nathanw ********************************************************************** */ 60 1.2.2.2 nathanw 61 1.2.2.2 nathanw /* 62 1.2.2.2 nathanw * DUART Mode Register #1 (Table 10-3) 63 1.2.2.2 nathanw * Register: DUART_MODE_REG_1_A 64 1.2.2.2 nathanw * Register: DUART_MODE_REG_1_B 65 1.2.2.2 nathanw */ 66 1.2.2.2 nathanw 67 1.2.2.2 nathanw #define S_DUART_BITS_PER_CHAR 0 68 1.2.2.2 nathanw #define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2,S_DUART_BITS_PER_CHAR) 69 1.2.2.2 nathanw #define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x,S_DUART_BITS_PER_CHAR) 70 1.2.2.2 nathanw 71 1.2.2.2 nathanw #define K_DUART_BITS_PER_CHAR_RSV0 0 72 1.2.2.2 nathanw #define K_DUART_BITS_PER_CHAR_RSV1 1 73 1.2.2.2 nathanw #define K_DUART_BITS_PER_CHAR_7 2 74 1.2.2.2 nathanw #define K_DUART_BITS_PER_CHAR_8 3 75 1.2.2.2 nathanw 76 1.2.2.2 nathanw #define V_DUART_BITS_PER_CHAR_RSV0 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV0) 77 1.2.2.2 nathanw #define V_DUART_BITS_PER_CHAR_RSV1 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV1) 78 1.2.2.2 nathanw #define V_DUART_BITS_PER_CHAR_7 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_7) 79 1.2.2.2 nathanw #define V_DUART_BITS_PER_CHAR_8 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_8) 80 1.2.2.2 nathanw 81 1.2.2.2 nathanw 82 1.2.2.2 nathanw #define M_DUART_PARITY_TYPE_EVEN 0x00 83 1.2.2.2 nathanw #define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2) 84 1.2.2.2 nathanw 85 1.2.2.2 nathanw #define S_DUART_PARITY_MODE 3 86 1.2.2.2 nathanw #define M_DUART_PARITY_MODE _SB_MAKEMASK(2,S_DUART_PARITY_MODE) 87 1.2.2.2 nathanw #define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x,S_DUART_PARITY_MODE) 88 1.2.2.2 nathanw 89 1.2.2.2 nathanw #define K_DUART_PARITY_MODE_ADD 0 90 1.2.2.2 nathanw #define K_DUART_PARITY_MODE_ADD_FIXED 1 91 1.2.2.2 nathanw #define K_DUART_PARITY_MODE_NONE 2 92 1.2.2.2 nathanw 93 1.2.2.2 nathanw #define V_DUART_PARITY_MODE_ADD V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD) 94 1.2.2.2 nathanw #define V_DUART_PARITY_MODE_ADD_FIXED V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD_FIXED) 95 1.2.2.2 nathanw #define V_DUART_PARITY_MODE_NONE V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_NONE) 96 1.2.2.2 nathanw 97 1.2.2.2 nathanw #define M_DUART_ERR_MODE _SB_MAKEMASK1(5) /* must be zero */ 98 1.2.2.2 nathanw 99 1.2.2.2 nathanw #define M_DUART_RX_IRQ_SEL_RXRDY 0 100 1.2.2.2 nathanw #define M_DUART_RX_IRQ_SEL_RXFULL _SB_MAKEMASK1(6) 101 1.2.2.2 nathanw 102 1.2.2.2 nathanw #define M_DUART_RX_RTS_ENA _SB_MAKEMASK1(7) 103 1.2.2.2 nathanw 104 1.2.2.2 nathanw /* 105 1.2.2.2 nathanw * DUART Mode Register #2 (Table 10-4) 106 1.2.2.2 nathanw * Register: DUART_MODE_REG_2_A 107 1.2.2.2 nathanw * Register: DUART_MODE_REG_2_B 108 1.2.2.2 nathanw */ 109 1.2.2.2 nathanw 110 1.2.2.2 nathanw #define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3,0) /* ignored */ 111 1.2.2.2 nathanw 112 1.2.2.2 nathanw #define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3) 113 1.2.2.2 nathanw #define M_DUART_STOP_BIT_LEN_1 0 114 1.2.2.2 nathanw 115 1.2.2.2 nathanw #define M_DUART_TX_CTS_ENA _SB_MAKEMASK1(4) 116 1.2.2.2 nathanw 117 1.2.2.2 nathanw 118 1.2.2.2 nathanw #define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */ 119 1.2.2.2 nathanw 120 1.2.2.2 nathanw #define S_DUART_CHAN_MODE 6 121 1.2.2.2 nathanw #define M_DUART_CHAN_MODE _SB_MAKEMASK(2,S_DUART_CHAN_MODE) 122 1.2.2.2 nathanw #define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x,S_DUART_CHAN_MODE) 123 1.2.2.2 nathanw 124 1.2.2.2 nathanw #define K_DUART_CHAN_MODE_NORMAL 0 125 1.2.2.2 nathanw #define K_DUART_CHAN_MODE_LCL_LOOP 2 126 1.2.2.2 nathanw #define K_DUART_CHAN_MODE_REM_LOOP 3 127 1.2.2.2 nathanw 128 1.2.2.2 nathanw #define V_DUART_CHAN_MODE_NORMAL V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_NORMAL) 129 1.2.2.2 nathanw #define V_DUART_CHAN_MODE_LCL_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_LCL_LOOP) 130 1.2.2.2 nathanw #define V_DUART_CHAN_MODE_REM_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_REM_LOOP) 131 1.2.2.2 nathanw 132 1.2.2.2 nathanw /* 133 1.2.2.2 nathanw * DUART Command Register (Table 10-5) 134 1.2.2.2 nathanw * Register: DUART_CMD_A 135 1.2.2.2 nathanw * Register: DUART_CMD_B 136 1.2.2.2 nathanw */ 137 1.2.2.2 nathanw 138 1.2.2.2 nathanw #define M_DUART_RX_EN _SB_MAKEMASK1(0) 139 1.2.2.2 nathanw #define M_DUART_RX_DIS _SB_MAKEMASK1(1) 140 1.2.2.2 nathanw #define M_DUART_TX_EN _SB_MAKEMASK1(2) 141 1.2.2.2 nathanw #define M_DUART_TX_DIS _SB_MAKEMASK1(3) 142 1.2.2.2 nathanw 143 1.2.2.2 nathanw #define S_DUART_MISC_CMD 4 144 1.2.2.2 nathanw #define M_DUART_MISC_CMD _SB_MAKEMASK(3,S_DUART_MISC_CMD) 145 1.2.2.2 nathanw #define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x,S_DUART_MISC_CMD) 146 1.2.2.2 nathanw 147 1.2.2.2 nathanw #define K_DUART_MISC_CMD_NOACTION0 0 148 1.2.2.2 nathanw #define K_DUART_MISC_CMD_NOACTION1 1 149 1.2.2.2 nathanw #define K_DUART_MISC_CMD_RESET_RX 2 150 1.2.2.2 nathanw #define K_DUART_MISC_CMD_RESET_TX 3 151 1.2.2.2 nathanw #define K_DUART_MISC_CMD_NOACTION4 4 152 1.2.2.2 nathanw #define K_DUART_MISC_CMD_RESET_BREAK_INT 5 153 1.2.2.2 nathanw #define K_DUART_MISC_CMD_START_BREAK 6 154 1.2.2.2 nathanw #define K_DUART_MISC_CMD_STOP_BREAK 7 155 1.2.2.2 nathanw 156 1.2.2.2 nathanw #define V_DUART_MISC_CMD_NOACTION0 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION0) 157 1.2.2.2 nathanw #define V_DUART_MISC_CMD_NOACTION1 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION1) 158 1.2.2.2 nathanw #define V_DUART_MISC_CMD_RESET_RX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_RX) 159 1.2.2.2 nathanw #define V_DUART_MISC_CMD_RESET_TX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_TX) 160 1.2.2.2 nathanw #define V_DUART_MISC_CMD_NOACTION4 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION4) 161 1.2.2.2 nathanw #define V_DUART_MISC_CMD_RESET_BREAK_INT V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_BREAK_INT) 162 1.2.2.2 nathanw #define V_DUART_MISC_CMD_START_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK) 163 1.2.2.2 nathanw #define V_DUART_MISC_CMD_STOP_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK) 164 1.2.2.2 nathanw 165 1.2.2.2 nathanw #define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7) 166 1.2.2.2 nathanw 167 1.2.2.2 nathanw /* 168 1.2.2.2 nathanw * DUART Status Register (Table 10-6) 169 1.2.2.2 nathanw * Register: DUART_STATUS_A 170 1.2.2.2 nathanw * Register: DUART_STATUS_B 171 1.2.2.2 nathanw * READ-ONLY 172 1.2.2.2 nathanw */ 173 1.2.2.2 nathanw 174 1.2.2.2 nathanw #define M_DUART_RX_RDY _SB_MAKEMASK1(0) 175 1.2.2.2 nathanw #define M_DUART_RX_FFUL _SB_MAKEMASK1(1) 176 1.2.2.2 nathanw #define M_DUART_TX_RDY _SB_MAKEMASK1(2) 177 1.2.2.2 nathanw #define M_DUART_TX_EMT _SB_MAKEMASK1(3) 178 1.2.2.2 nathanw #define M_DUART_OVRUN_ERR _SB_MAKEMASK1(4) 179 1.2.2.2 nathanw #define M_DUART_PARITY_ERR _SB_MAKEMASK1(5) 180 1.2.2.2 nathanw #define M_DUART_FRM_ERR _SB_MAKEMASK1(6) 181 1.2.2.2 nathanw #define M_DUART_RCVD_BRK _SB_MAKEMASK1(7) 182 1.2.2.2 nathanw 183 1.2.2.2 nathanw /* 184 1.2.2.2 nathanw * DUART Baud Rate Register (Table 10-7) 185 1.2.2.2 nathanw * Register: DUART_CLK_SEL_A 186 1.2.2.2 nathanw * Register: DUART_CLK_SEL_B 187 1.2.2.2 nathanw */ 188 1.2.2.2 nathanw 189 1.2.2.2 nathanw #define M_DUART_CLK_COUNTER _SB_MAKEMASK(12,0) 190 1.2.2.2 nathanw #define V_DUART_BAUD_RATE(x) (100000000/((x)*20)-1) 191 1.2.2.2 nathanw 192 1.2.2.2 nathanw /* 193 1.2.2.2 nathanw * DUART Data Registers (Table 10-8 and 10-9) 194 1.2.2.2 nathanw * Register: DUART_RX_HOLD_A 195 1.2.2.2 nathanw * Register: DUART_RX_HOLD_B 196 1.2.2.2 nathanw * Register: DUART_TX_HOLD_A 197 1.2.2.2 nathanw * Register: DUART_TX_HOLD_B 198 1.2.2.2 nathanw */ 199 1.2.2.2 nathanw 200 1.2.2.2 nathanw #define M_DUART_RX_DATA _SB_MAKEMASK(8,0) 201 1.2.2.2 nathanw #define M_DUART_TX_DATA _SB_MAKEMASK(8,0) 202 1.2.2.2 nathanw 203 1.2.2.2 nathanw /* 204 1.2.2.2 nathanw * DUART Input Port Register (Table 10-10) 205 1.2.2.2 nathanw * Register: DUART_IN_PORT 206 1.2.2.2 nathanw */ 207 1.2.2.2 nathanw 208 1.2.2.2 nathanw #define M_DUART_IN_PIN0_VAL _SB_MAKEMASK1(0) 209 1.2.2.2 nathanw #define M_DUART_IN_PIN1_VAL _SB_MAKEMASK1(1) 210 1.2.2.2 nathanw #define M_DUART_IN_PIN2_VAL _SB_MAKEMASK1(2) 211 1.2.2.2 nathanw #define M_DUART_IN_PIN3_VAL _SB_MAKEMASK1(3) 212 1.2.2.2 nathanw #define M_DUART_IN_PIN4_VAL _SB_MAKEMASK1(4) 213 1.2.2.2 nathanw #define M_DUART_IN_PIN5_VAL _SB_MAKEMASK1(5) 214 1.2.2.2 nathanw #define M_DUART_RIN0_PIN _SB_MAKEMASK1(6) 215 1.2.2.2 nathanw #define M_DUART_RIN1_PIN _SB_MAKEMASK1(7) 216 1.2.2.2 nathanw 217 1.2.2.2 nathanw /* 218 1.2.2.2 nathanw * DUART Input Port Change Status Register (Tables 10-11, 10-12, and 10-13) 219 1.2.2.2 nathanw * Register: DUART_INPORT_CHNG 220 1.2.2.2 nathanw */ 221 1.2.2.2 nathanw 222 1.2.2.2 nathanw #define S_DUART_IN_PIN_VAL 0 223 1.2.2.2 nathanw #define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4,S_DUART_IN_PIN_VAL) 224 1.2.2.2 nathanw 225 1.2.2.2 nathanw #define S_DUART_IN_PIN_CHNG 4 226 1.2.2.2 nathanw #define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4,S_DUART_IN_PIN_CHNG) 227 1.2.2.2 nathanw 228 1.2.2.2 nathanw 229 1.2.2.2 nathanw /* 230 1.2.2.2 nathanw * DUART Output port control register (Table 10-14) 231 1.2.2.2 nathanw * Register: DUART_OPCR 232 1.2.2.2 nathanw */ 233 1.2.2.2 nathanw 234 1.2.2.2 nathanw #define M_DUART_OPCR_RESERVED0 _SB_MAKEMASK1(0) /* must be zero */ 235 1.2.2.2 nathanw #define M_DUART_OPC2_SEL _SB_MAKEMASK1(1) 236 1.2.2.2 nathanw #define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */ 237 1.2.2.2 nathanw #define M_DUART_OPC3_SEL _SB_MAKEMASK1(3) 238 1.2.2.2 nathanw #define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4,4) /* must be zero */ 239 1.2.2.2 nathanw 240 1.2.2.2 nathanw /* 241 1.2.2.2 nathanw * DUART Aux Control Register (Table 10-15) 242 1.2.2.2 nathanw * Register: DUART_AUX_CTRL 243 1.2.2.2 nathanw */ 244 1.2.2.2 nathanw 245 1.2.2.2 nathanw #define M_DUART_IP0_CHNG_ENA _SB_MAKEMASK1(0) 246 1.2.2.2 nathanw #define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1) 247 1.2.2.2 nathanw #define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2) 248 1.2.2.2 nathanw #define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3) 249 1.2.2.2 nathanw #define M_DUART_ACR_RESERVED _SB_MAKEMASK(4,4) 250 1.2.2.2 nathanw 251 1.2.2.2 nathanw #define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0) 252 1.2.2.2 nathanw #define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2) 253 1.2.2.2 nathanw 254 1.2.2.2 nathanw /* 255 1.2.2.2 nathanw * DUART Interrupt Status Register (Table 10-16) 256 1.2.2.2 nathanw * Register: DUART_ISR 257 1.2.2.2 nathanw */ 258 1.2.2.2 nathanw 259 1.2.2.2 nathanw #define M_DUART_ISR_TX_A _SB_MAKEMASK1(0) 260 1.2.2.2 nathanw #define M_DUART_ISR_RX_A _SB_MAKEMASK1(1) 261 1.2.2.2 nathanw #define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2) 262 1.2.2.2 nathanw #define M_DUART_ISR_IN_A _SB_MAKEMASK1(3) 263 1.2.2.2 nathanw #define M_DUART_ISR_TX_B _SB_MAKEMASK1(4) 264 1.2.2.2 nathanw #define M_DUART_ISR_RX_B _SB_MAKEMASK1(5) 265 1.2.2.2 nathanw #define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6) 266 1.2.2.2 nathanw #define M_DUART_ISR_IN_B _SB_MAKEMASK1(7) 267 1.2.2.2 nathanw 268 1.2.2.2 nathanw /* 269 1.2.2.2 nathanw * DUART Channel A Interrupt Status Register (Table 10-17) 270 1.2.2.2 nathanw * DUART Channel B Interrupt Status Register (Table 10-18) 271 1.2.2.2 nathanw * Register: DUART_ISR_A 272 1.2.2.2 nathanw * Register: DUART_ISR_B 273 1.2.2.2 nathanw */ 274 1.2.2.2 nathanw 275 1.2.2.2 nathanw #define M_DUART_ISR_TX _SB_MAKEMASK1(0) 276 1.2.2.2 nathanw #define M_DUART_ISR_RX _SB_MAKEMASK1(1) 277 1.2.2.2 nathanw #define M_DUART_ISR_BRK _SB_MAKEMASK1(2) 278 1.2.2.2 nathanw #define M_DUART_ISR_IN _SB_MAKEMASK1(3) 279 1.2.2.2 nathanw #define M_DUART_ISR_RESERVED _SB_MAKEMASK(4,4) 280 1.2.2.2 nathanw 281 1.2.2.2 nathanw /* 282 1.2.2.2 nathanw * DUART Interrupt Mask Register (Table 10-19) 283 1.2.2.2 nathanw * Register: DUART_IMR 284 1.2.2.2 nathanw */ 285 1.2.2.2 nathanw 286 1.2.2.2 nathanw #define M_DUART_IMR_TX_A _SB_MAKEMASK1(0) 287 1.2.2.2 nathanw #define M_DUART_IMR_RX_A _SB_MAKEMASK1(1) 288 1.2.2.2 nathanw #define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2) 289 1.2.2.2 nathanw #define M_DUART_IMR_IN_A _SB_MAKEMASK1(3) 290 1.2.2.2 nathanw #define M_DUART_IMR_ALL_A _SB_MAKEMASK(4,0) 291 1.2.2.2 nathanw 292 1.2.2.2 nathanw #define M_DUART_IMR_TX_B _SB_MAKEMASK1(4) 293 1.2.2.2 nathanw #define M_DUART_IMR_RX_B _SB_MAKEMASK1(5) 294 1.2.2.2 nathanw #define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6) 295 1.2.2.2 nathanw #define M_DUART_IMR_IN_B _SB_MAKEMASK1(7) 296 1.2.2.2 nathanw #define M_DUART_IMR_ALL_B _SB_MAKEMASK(4,4) 297 1.2.2.2 nathanw 298 1.2.2.2 nathanw /* 299 1.2.2.2 nathanw * DUART Channel A Interrupt Mask Register (Table 10-20) 300 1.2.2.2 nathanw * DUART Channel B Interrupt Mask Register (Table 10-21) 301 1.2.2.2 nathanw * Register: DUART_IMR_A 302 1.2.2.2 nathanw * Register: DUART_IMR_B 303 1.2.2.2 nathanw */ 304 1.2.2.2 nathanw 305 1.2.2.2 nathanw #define M_DUART_IMR_TX _SB_MAKEMASK1(0) 306 1.2.2.2 nathanw #define M_DUART_IMR_RX _SB_MAKEMASK1(1) 307 1.2.2.2 nathanw #define M_DUART_IMR_BRK _SB_MAKEMASK1(2) 308 1.2.2.2 nathanw #define M_DUART_IMR_IN _SB_MAKEMASK1(3) 309 1.2.2.2 nathanw #define M_DUART_IMR_ALL _SB_MAKEMASK(4,0) 310 1.2.2.2 nathanw #define M_DUART_IMR_RESERVED _SB_MAKEMASK(4,4) 311 1.2.2.2 nathanw 312 1.2.2.2 nathanw 313 1.2.2.2 nathanw /* 314 1.2.2.2 nathanw * DUART Output Port Set Register (Table 10-22) 315 1.2.2.2 nathanw * Register: DUART_SET_OPR 316 1.2.2.2 nathanw */ 317 1.2.2.2 nathanw 318 1.2.2.2 nathanw #define M_DUART_SET_OPR0 _SB_MAKEMASK1(0) 319 1.2.2.2 nathanw #define M_DUART_SET_OPR1 _SB_MAKEMASK1(1) 320 1.2.2.2 nathanw #define M_DUART_SET_OPR2 _SB_MAKEMASK1(2) 321 1.2.2.2 nathanw #define M_DUART_SET_OPR3 _SB_MAKEMASK1(3) 322 1.2.2.2 nathanw #define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4,4) 323 1.2.2.2 nathanw 324 1.2.2.2 nathanw /* 325 1.2.2.2 nathanw * DUART Output Port Clear Register (Table 10-23) 326 1.2.2.2 nathanw * Register: DUART_CLEAR_OPR 327 1.2.2.2 nathanw */ 328 1.2.2.2 nathanw 329 1.2.2.2 nathanw #define M_DUART_CLR_OPR0 _SB_MAKEMASK1(0) 330 1.2.2.2 nathanw #define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1) 331 1.2.2.2 nathanw #define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2) 332 1.2.2.2 nathanw #define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3) 333 1.2.2.2 nathanw #define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4,4) 334 1.2.2.2 nathanw 335 1.2.2.2 nathanw /* 336 1.2.2.2 nathanw * DUART Output Port RTS Register (Table 10-24) 337 1.2.2.2 nathanw * Register: DUART_OUT_PORT 338 1.2.2.2 nathanw */ 339 1.2.2.2 nathanw 340 1.2.2.2 nathanw #define M_DUART_OUT_PIN_SET0 _SB_MAKEMASK1(0) 341 1.2.2.2 nathanw #define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1) 342 1.2.2.2 nathanw #define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2) 343 1.2.2.2 nathanw #define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3) 344 1.2.2.2 nathanw #define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4,4) 345 1.2.2.2 nathanw 346 1.2.2.2 nathanw #define M_DUART_OUT_PIN_SET(chan) \ 347 1.2.2.2 nathanw (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1) 348 1.2.2.2 nathanw #define M_DUART_OUT_PIN_CLR(chan) \ 349 1.2.2.2 nathanw (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1) 350 1.2.2.2 nathanw 351 1.2.2.2 nathanw #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 352 1.2.2.2 nathanw /* 353 1.2.2.2 nathanw * Full Interrupt Control Register 354 1.2.2.2 nathanw */ 355 1.2.2.2 nathanw 356 1.2.2.2 nathanw #define S_DUART_SIG_FULL _SB_MAKE64(0) 357 1.2.2.2 nathanw #define M_DUART_SIG_FULL _SB_MAKEMASK(4,S_DUART_SIG_FULL) 358 1.2.2.2 nathanw #define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x,S_DUART_SIG_FULL) 359 1.2.2.2 nathanw #define G_DUART_SIG_FULL(x) _SB_GETVALUE(x,S_DUART_SIG_FULL,M_DUART_SIG_FULL) 360 1.2.2.2 nathanw 361 1.2.2.2 nathanw #define S_DUART_INT_TIME _SB_MAKE64(4) 362 1.2.2.2 nathanw #define M_DUART_INT_TIME _SB_MAKEMASK(4,S_DUART_INT_TIME) 363 1.2.2.2 nathanw #define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x,S_DUART_INT_TIME) 364 1.2.2.2 nathanw #define G_DUART_INT_TIME(x) _SB_GETVALUE(x,S_DUART_INT_TIME,M_DUART_INT_TIME) 365 1.2.2.2 nathanw #endif /* 1250 PASS2 || 112x PASS1 */ 366 1.2.2.2 nathanw 367 1.2.2.2 nathanw 368 1.2.2.2 nathanw /* ********************************************************************** */ 369 1.2.2.2 nathanw 370 1.2.2.2 nathanw 371 1.2.2.2 nathanw #endif 372
Indexes created Thu Oct 23 22:10:10 GMT 2025