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sb1250_wid.h revision 1.1 
      1 /*  *********************************************************************
      2     *  SB1250 Board Support Package
      3     *
      4     *  Wafer ID bit definitions			File: sb1250_wid.h
      5     *
      6     *  Some preproduction BCM1250 samples use the wafer ID (WID) bits
      7     *  in the system_revision register in the SCD to determine which
      8     *  portions of the L1 and L2 caches are usable.
      9     *
     10     *  This file describes the WID register layout.
     11     *
     12     *  Author:  Mitch Lichtenberg (mpl (at) broadcom.com)
     13     *
     14     *********************************************************************
     15     *
     16     *  Copyright 2000,2001
     17     *  Broadcom Corporation. All rights reserved.
     18     *
     19     *  This software is furnished under license and may be used and
     20     *  copied only in accordance with the following terms and
     21     *  conditions.  Subject to these conditions, you may download,
     22     *  copy, install, use, modify and distribute modified or unmodified
     23     *  copies of this software in source and/or binary form.  No title
     24     *  or ownership is transferred hereby.
     25     *
     26     *  1) Any source code used, modified or distributed must reproduce
     27     *     and retain this copyright notice and list of conditions as
     28     *     they appear in the source file.
     29     *
     30     *  2) No right is granted to use any trade name, trademark, or
     31     *     logo of Broadcom Corporation. Neither the "Broadcom
     32     *     Corporation" name nor any trademark or logo of Broadcom
     33     *     Corporation may be used to endorse or promote products
     34     *     derived from this software without the prior written
     35     *     permission of Broadcom Corporation.
     36     *
     37     *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
     38     *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
     39     *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
     40     *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
     41     *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
     42     *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
     43     *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     44     *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
     45     *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
     46     *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
     47     *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
     48     *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
     49     *     THE POSSIBILITY OF SUCH DAMAGE.
     50     ********************************************************************* */
     51 
     52 
     53 #ifndef _SB1250_WID_H
     54 #define _SB1250_WID_H
     55 
     56 #include "sb1250_defs.h"
     57 
     58 /*
     59  * To make things easier to work with, we'll assume that the
     60  * WID bits have been shifted from their normal home
     61  * in scd_system_revision[63:32] to bits [31..0].
     62  *
     63  * That is, we've already shifted right by S_SYS_WID
     64  */
     65 
     66 #define S_WID_BIN             0
     67 #define M_WID_BIN             _SB_MAKEMASK(3,S_WID_BIN)
     68 #define V_WID_BIN(x)          _SB_MAKEVALUE(x,S_WID_BIN)
     69 #define G_WID_BIN(x)          _SB_GETVALUE(x,S_WID_BIN,M_WID_BIN)
     70 
     71                                         /* CPUs  L1I    L1D    L2   */
     72 #define K_WID_BIN_2CPU_FI_1D_H2	0	/*  2    full   1/4    1/2  */
     73 #define K_WID_BIN_2CPU_FI_FD_F2	1	/*  2    full   full   full */
     74 #define K_WID_BIN_2CPU_FI_FD_H2 2 	/*  2    full   full   1/2  */
     75 #define K_WID_BIN_2CPU_3I_3D_F2 3       /*  2    3/4    3/4    full */
     76 #define K_WID_BIN_2CPU_3I_3D_H2 4	/*  2    3/4    3/4    1/2  */
     77 #define K_WID_BIN_1CPU_FI_FD_F2 5	/*  1    full   full   full */
     78 #define K_WID_BIN_1CPU_FI_FD_H2 6       /*  1    full   full   1/2  */
     79 #define K_WID_BIN_2CPU_1I_1D_Q2 7       /*  2    1/4    1/4    1/4  */
     80 
     81 /*
     82  * '1' bits in this mask represent bins with only one CPU
     83  */
     84 
     85 #define M_WID_BIN_1CPU (_SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_F2) | \
     86                         _SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_H2))
     87 
     88 
     89 /*
     90  * '1' bits in this mask represent bins with a good L2
     91  */
     92 
     93 #define M_WID_BIN_F2 (_SB_MAKEMASK1(K_WID_BIN_2CPU_FI_FD_F2) | \
     94                       _SB_MAKEMASK1(K_WID_BIN_2CPU_3I_3D_F2) | \
     95                       _SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_F2))
     96 
     97 /*
     98  * '1' bits in this mask represent bins with 1/2 L2
     99  */
    100 
    101 #define M_WID_BIN_H2   (_SB_MAKEMASK1(K_WID_BIN_2CPU_FI_1D_H2) | \
    102                         _SB_MAKEMASK1(K_WID_BIN_2CPU_FI_FD_H2) | \
    103                         _SB_MAKEMASK1(K_WID_BIN_2CPU_3I_3D_H2) | \
    104                         _SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_H2) )
    105 
    106 /*
    107  * '1' bits in this mask represent bins with 1/4 L2
    108  */
    109 
    110 #define M_WID_BIN_Q2   (_SB_MAKEMASK1(K_WID_BIN_2CPU_1I_1D_Q2))
    111 
    112 /*
    113  * '1' bits in this mask represent bins with 3/4 L1
    114  */
    115 
    116 #define M_WID_BIN_3ID  (_SB_MAKEMASK1(K_WID_BIN_2CPU_3I_3D_F2) | \
    117 			_SB_MAKEMASK1(K_WID_BIN_2CPU_3I_3D_H2))
    118 
    119 /*
    120  * '1' bits in this mask represent bins with a full L1I
    121  */
    122 
    123 #define M_WID_BIN_FI   (_SB_MAKEMASK1(K_WID_BIN_2CPU_FI_1D_H2) | \
    124 			_SB_MAKEMASK1(K_WID_BIN_2CPU_FI_FD_F2) | \
    125 			_SB_MAKEMASK1(K_WID_BIN_2CPU_FI_FD_H2) | \
    126 			_SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_F2) | \
    127 			_SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_H2))
    128 
    129 /*
    130  * '1' bits in this mask represent bins with a full L1D
    131  */
    132 
    133 #define M_WID_BIN_FD   (_SB_MAKEMASK1(K_WID_BIN_2CPU_FI_FD_F2) | \
    134 			_SB_MAKEMASK1(K_WID_BIN_2CPU_FI_FD_H2) | \
    135 			_SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_F2) | \
    136 			_SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_H2))
    137 
    138 /*
    139  * '1' bits in this mask represent bins with a full L1 (both I and D)
    140  */
    141 
    142 #define M_WID_BIN_FID  (_SB_MAKEMASK1(K_WID_BIN_2CPU_FI_FD_F2) | \
    143 			_SB_MAKEMASK1(K_WID_BIN_2CPU_FI_FD_H2) | \
    144 			_SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_F2) | \
    145 			_SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_H2))
    146 
    147 #define S_WID_L2QTR           3
    148 #define M_WID_L2QTR           _SB_MAKEMASK(2,S_WID_L2QTR)
    149 #define V_WID_L2QTR(x)        _SB_MAKEVALUE(x,S_WID_L2QTR)
    150 #define G_WID_L2QTR(x)        _SB_GETVALUE(x,S_WID_L2QTR,M_WID_L2QTR)
    151 
    152 #define M_WID_L2HALF	      _SB_MAKEMASK1(4)
    153 
    154 #define S_WID_CPU0_L1I        5
    155 #define M_WID_CPU0_L1I        _SB_MAKEMASK(2,S_WID_CPU0_L1I)
    156 #define V_WID_CPU0_L1I(x)     _SB_MAKEVALUE(x,S_WID_CPU0_L1I)
    157 #define G_WID_CPU0_L1I(x)     _SB_GETVALUE(x,S_WID_CPU0_L1I,M_WID_CPU0_L1I)
    158 
    159 #define S_WID_CPU0_L1D        7
    160 #define M_WID_CPU0_L1D        _SB_MAKEMASK(2,S_WID_CPU0_L1D)
    161 #define V_WID_CPU0_L1D(x)     _SB_MAKEVALUE(x,S_WID_CPU0_L1D)
    162 #define G_WID_CPU0_L1D(x)     _SB_GETVALUE(x,S_WID_CPU0_L1D,M_WID_CPU0_L1D)
    163 
    164 #define S_WID_CPU1_L1I        9
    165 #define M_WID_CPU1_L1I        _SB_MAKEMASK(2,S_WID_CPU1_L1I)
    166 #define V_WID_CPU1_L1I(x)     _SB_MAKEVALUE(x,S_WID_CPU1_L1I)
    167 #define G_WID_CPU1_L1I(x)     _SB_GETVALUE(x,S_WID_CPU1_L1I,M_WID_CPU1_L1I)
    168 
    169 #define S_WID_CPU1_L1D        11
    170 #define M_WID_CPU1_L1D        _SB_MAKEMASK(2,S_WID_CPU1_L1D)
    171 #define V_WID_CPU1_L1D(x)     _SB_MAKEVALUE(x,S_WID_CPU1_L1D)
    172 #define G_WID_CPU1_L1D(x)     _SB_GETVALUE(x,S_WID_CPU1_L1D,M_WID_CPU1_L1D)
    173 
    174 /*
    175  * The macros below assume that the CPU bits have been shifted into the
    176  * low-order 4 bits.
    177  */
    178 
    179 #define S_WID_CPUX_L1I        0
    180 #define M_WID_CPUX_L1I        _SB_MAKEMASK(2,S_WID_CPUX_L1I)
    181 #define V_WID_CPUX_L1I(x)     _SB_MAKEVALUE(x,S_WID_CPUX_L1I)
    182 #define G_WID_CPUX_L1I(x)     _SB_GETVALUE(x,S_WID_CPUX_L1I,M_WID_CPUX_L1I)
    183 
    184 #define S_WID_CPUX_L1D        2
    185 #define M_WID_CPUX_L1D        _SB_MAKEMASK(2,S_WID_CPUX_L1D)
    186 #define V_WID_CPUX_L1D(x)     _SB_MAKEVALUE(x,S_WID_CPUX_L1D)
    187 #define G_WID_CPUX_L1D(x)     _SB_GETVALUE(x,S_WID_CPUX_L1D,M_WID_CPUX_L1D)
    188 
    189 #define S_WID_CPU0	      5
    190 #define S_WID_CPU1	      9
    191 
    192 #define S_WID_WAFERID        13
    193 #define M_WID_WAFERID        _SB_MAKEMASK(5,S_WID_WAFERID)
    194 #define V_WID_WAFERID(x)     _SB_MAKEVALUE(x,S_WID_WAFERID)
    195 #define G_WID_WAFERID(x)     _SB_GETVALUE(x,S_WID_WAFERID,M_WID_WAFERID)
    196 
    197 #define S_WID_LOTID        18
    198 #define M_WID_LOTID        _SB_MAKEMASK(14,S_WID_LOTID)
    199 #define V_WID_LOTID(x)     _SB_MAKEVALUE(x,S_WID_LOTID)
    200 #define G_WID_LOTID(x)     _SB_GETVALUE(x,S_WID_LOTID,M_WID_LOTID)
    201 
    202 /*
    203  * Now, to make things even more confusing, the fuses on the chip
    204  * don't exactly correspond to the bits in the register. The mask
    205  * below represents bits that need to be swapped with the ones to
    206  * their left.  So, if bit 10 is set, swap bits 10 and 11
    207  */
    208 
    209 #define M_WID_SWAPBITS	(_SB_MAKEMASK1(2) | _SB_MAKEMASK1(4) | _SB_MAKEMASK1(10) | \
    210                          _SB_MAKEMASK1(20) | _SB_MAKEMASK1(18) | _SB_MAKEMASK1(26) )
    211 
    212 #ifdef __ASSEMBLER__
    213 #define WID_UNCONVOLUTE(wid,t1,t2,t3) \
    214        li    t1,M_WID_SWAPBITS ; \
    215        and   t1,t1,wid ; \
    216        sll   t1,t1,1 ; \
    217        li    t2,(M_WID_SWAPBITS << 1); \
    218        and   t2,t2,wid ; \
    219        srl   t2,t2,1 ; \
    220        li    t3, ~((M_WID_SWAPBITS | (M_WID_SWAPBITS << 1))) ; \
    221        and   wid,wid,t3 ; \
    222        or    wid,wid,t1 ; \
    223        or    wid,wid,t2
    224 #else
    225 #define WID_UNCONVOLUTE(wid) \
    226      (((wid) & ~((M_WID_SWAPBITS | (M_WID_SWAPBITS << 1)))) | \
    227       (((wid) & M_WID_SWAPBITS) << 1) |  \
    228       (((wid) & (M_WID_SWAPBITS<<1)) >> 1))
    229 #endif
    230 
    231 
    232 
    233 #endif
    234