sbbrz_pci.c revision 1.1.2.3
1 /* $NetBSD: sbbrz_pci.c,v 1.1.2.3 2010/01/21 08:31:24 matt Exp $ */ 2 3 /* 4 * Copyright 2000, 2001 5 * Broadcom Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and copied only 8 * in accordance with the following terms and conditions. Subject to these 9 * conditions, you may download, copy, install, use, modify and distribute 10 * modified or unmodified copies of this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce and 14 * retain this copyright notice and list of conditions as they appear in 15 * the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Broadcom Corporation. Neither the "Broadcom Corporation" name nor any 19 * trademark or logo of Broadcom Corporation may be used to endorse or 20 * promote products derived from this software without the prior written 21 * permission of Broadcom Corporation. 22 * 23 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR 26 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE 27 * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE 28 * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* from: $NetBSD: apecs_pci.c,v 1.18 2000/06/29 08:58:45 mrg Exp */ 37 38 /* 39 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 40 * All rights reserved. 41 * 42 * Author: Chris G. Demetriou 43 * 44 * Permission to use, copy, modify and distribute this software and 45 * its documentation is hereby granted, provided that both the copyright 46 * notice and this permission notice appear in all copies of the 47 * software, derivative works or modified versions, and any portions 48 * thereof, and that both notices appear in supporting documentation. 49 * 50 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 51 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 52 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 53 * 54 * Carnegie Mellon requests users of this software to return to 55 * 56 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 57 * School of Computer Science 58 * Carnegie Mellon University 59 * Pittsburgh PA 15213-3890 60 * 61 * any improvements or extensions that they make and grant Carnegie the 62 * rights to redistribute these changes. 63 */ 64 65 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 66 67 __KERNEL_RCSID(0, "$NetBSD: sbbrz_pci.c,v 1.1.2.3 2010/01/21 08:31:24 matt Exp $"); 68 69 #include <sys/param.h> 70 #include <sys/systm.h> 71 #include <sys/kernel.h> 72 #include <sys/device.h> 73 #include <uvm/uvm_extern.h> 74 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 78 #include <machine/locore.h> 79 #include <mips/sibyte/include/sb1250_regs.h> 80 #include <mips/sibyte/include/sb1250_scd.h> 81 #include <mips/sibyte/include/sb1250_int.h> 82 #include <mips/sibyte/pci/sbbrzvar.h> 83 84 void sbbrz_pci_attach_hook(device_t, device_t, 85 struct pcibus_attach_args *); 86 static int sbbrz_pci_bus_maxdevs(void *, int); 87 static pcitag_t sbbrz_pci_make_tag(void *, int, int, int); 88 static void sbbrz_pci_decompose_tag(void *, pcitag_t, int *, int *, int *); 89 90 static pcireg_t sbbrz_pci_conf_read(void *, pcitag_t, int); 91 static void sbbrz_pci_conf_write(void *, pcitag_t, int, pcireg_t); 92 #ifdef PCI_NETBSD_CONFIGURE 93 static void sbbrz_pci_conf_interrupt(void *, int, int, int, int, int *); 94 #endif 95 96 static int sbbrz_pci_intr_map(struct pci_attach_args *, 97 pci_intr_handle_t *); 98 static const char * 99 sbbrz_pci_intr_string(void *, pci_intr_handle_t); 100 static const struct evcnt * 101 sbbrz_pci_intr_evcnt(void *, pci_intr_handle_t); 102 static void * sbbrz_pci_intr_establish(void *, pci_intr_handle_t, 103 int, int (*)(void *), void *); 104 static void sbbrz_pci_intr_disestablish(void *, void *); 105 106 107 void 108 sbbrz_pci_init(pci_chipset_tag_t pc, void *v) 109 { 110 111 pc->pc_conf_v = v; 112 pc->pc_attach_hook = sbbrz_pci_attach_hook; 113 pc->pc_bus_maxdevs = sbbrz_pci_bus_maxdevs; 114 pc->pc_make_tag = sbbrz_pci_make_tag; 115 pc->pc_decompose_tag = sbbrz_pci_decompose_tag; 116 pc->pc_conf_read = sbbrz_pci_conf_read; 117 pc->pc_conf_write = sbbrz_pci_conf_write; 118 pc->pc_intr_map = sbbrz_pci_intr_map; 119 pc->pc_intr_string = sbbrz_pci_intr_string; 120 pc->pc_intr_evcnt = sbbrz_pci_intr_evcnt; 121 pc->pc_intr_establish = sbbrz_pci_intr_establish; 122 pc->pc_intr_disestablish = sbbrz_pci_intr_disestablish; 123 #ifdef PCI_NETBSD_CONFIGURE 124 pc->pc_conf_interrupt = sbbrz_pci_conf_interrupt; 125 #endif 126 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 127 pc->pc_pciide_compat_intr_establish = sbbrz_pciide_compat_intr_establish; 128 #endif 129 } 130 131 void 132 sbbrz_pci_attach_hook(device_t parent, device_t self, 133 struct pcibus_attach_args *pba) 134 { 135 } 136 137 int 138 sbbrz_pci_bus_maxdevs(void *cpv, int busno) 139 { 140 uint64_t regval; 141 int host; 142 143 /* If not the PCI bus directly off the 1250, always up to 32 devs. */ 144 if (busno != 0) 145 return 32; 146 147 /* If the PCI on the 1250, 32 devices if host mode, otherwise only 2. */ 148 regval = mips3_ld((void *)MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_CFG)); 149 host = (regval & M_SYS_PCI_HOST) != 0; 150 151 return (host ? 32 : 2); 152 } 153 154 pcitag_t 155 sbbrz_pci_make_tag(void *cpv, int b, int d, int f) 156 { 157 158 return (b << 16) | (d << 11) | (f << 8); 159 } 160 161 void 162 sbbrz_pci_decompose_tag(void *cpv, pcitag_t tag, 163 int *bp, int *dp, int *fp) 164 { 165 166 if (bp != NULL) 167 *bp = (tag >> 16) & 0xff; 168 if (dp != NULL) 169 *dp = (tag >> 11) & 0x1f; 170 if (fp != NULL) 171 *fp = (tag >> 8) & 0x7; 172 } 173 174 pcireg_t 175 sbbrz_pci_conf_read(void *cpv, pcitag_t tag, int offset) 176 { 177 uint64_t addr; 178 pcitag_t tmptag; 179 180 #ifdef DIAGNOSTIC 181 if ((offset & 0x3) != 0) 182 panic ("pci_conf_read: misaligned"); 183 #endif 184 185 addr = A_PHYS_LDTPCI_CFG_MATCH_BITS + tag + offset; 186 #if 0 187 addr = mips3_ld((void *)MIPS_PHYS_TO_KSEG1(addr)); 188 tmptag = mips3_lw_a64(addr); 189 printf("s_c_r KSEG1: %"PRIx64"\n", (uint64_t)tmptag); 190 #endif 191 addr = MIPS_PHYS_TO_XKPHYS(MIPS3_TLB_ATTR_UNCACHED, addr); 192 193 tmptag = mips3_lw_a64(addr); 194 printf("s_c_r XKSEG (%"PRIx64"): %"PRIx64"\n", addr, (uint64_t)tmptag); 195 196 197 #ifdef _punt_on_64 198 if (badaddr64(addr, 4) != 0) 199 return 0xffffffff; 200 #endif 201 202 #if not_yet 203 return mips3_lw_a64(addr); 204 #else 205 return tmptag; 206 #endif 207 } 208 209 void 210 sbbrz_pci_conf_write(void *cpv, pcitag_t tag, int offset, pcireg_t data) 211 { 212 uint64_t addr; 213 214 #ifdef DIAGNOSTIC 215 if ((offset & 0x3) != 0) 216 panic ("pci_conf_write: misaligned"); 217 #endif 218 219 addr = A_PHYS_LDTPCI_CFG_MATCH_BITS + tag + offset; 220 addr = MIPS_PHYS_TO_XKPHYS(MIPS3_TLB_ATTR_UNCACHED, addr); 221 printf("s_c_W XKSEG (%"PRIx64"): %"PRIx64"\n", addr, (uint64_t)data); 222 223 return mips3_sw_a64(addr, data); 224 } 225 226 int 227 sbbrz_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 228 { 229 int bus, device, func; 230 sbbrz_pci_decompose_tag(NULL, pa->pa_intrtag, &bus, &device, &func); 231 *ihp = 0; 232 if (pa->pa_intrpin == PCI_INTERRUPT_PIN_NONE) 233 return EINVAL; 234 if (bus == 0) { 235 *ihp = K_INT_PCI_INTA 236 + (((device-5) + pa->pa_intrswiz + pa->pa_intrpin - PCI_INTERRUPT_PIN_A) % 4); 237 return 0; 238 } 239 return EOPNOTSUPP; 240 } 241 242 const char * 243 sbbrz_pci_intr_string(void *v, pci_intr_handle_t ih) 244 { 245 switch (ih) { 246 default: return NULL; 247 case K_INT_PCI_INTA: return "pci inta"; 248 case K_INT_PCI_INTB: return "pci intb"; 249 case K_INT_PCI_INTC: return "pci intc"; 250 case K_INT_PCI_INTD: return "pci intd"; 251 } 252 } 253 254 const struct evcnt * 255 sbbrz_pci_intr_evcnt(void *v, pci_intr_handle_t ih) 256 { 257 return NULL; 258 } 259 260 void * 261 sbbrz_pci_intr_establish(void *v, pci_intr_handle_t ih, int level, 262 int (*handler)(void *), void *arg) 263 { 264 return cpu_intr_establish(ih, level, 265 (void (*)(void *, uint32_t, vaddr_t))handler, arg); 266 } 267 268 void 269 sbbrz_pci_intr_disestablish(void *v, void *ih) 270 { 271 } 272
Indexes created Tue Oct 14 21:09:58 GMT 2025