vme_pcc.c revision 1.13
1 /* $NetBSD: vme_pcc.c,v 1.13 2000/11/24 09:27:42 scw Exp $ */ 2 3 /*- 4 * Copyright (c) 1996-2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * VME support specific to the Type 1 VMEchip found on the 41 * MVME-147. 42 * 43 * For a manual on the MVME-147, call: 408.991.8634. (Yes, this 44 * is the Sunnyvale sales office.) 45 */ 46 47 #include <sys/param.h> 48 #include <sys/kernel.h> 49 #include <sys/systm.h> 50 #include <sys/device.h> 51 #include <sys/malloc.h> 52 #include <sys/kcore.h> 53 54 #include <machine/cpu.h> 55 #include <machine/bus.h> 56 57 #include <dev/vme/vmereg.h> 58 #include <dev/vme/vmevar.h> 59 60 #include <mvme68k/mvme68k/isr.h> 61 62 #include <mvme68k/dev/pccreg.h> 63 #include <mvme68k/dev/pccvar.h> 64 #include <mvme68k/dev/mvmebus.h> 65 #include <mvme68k/dev/vme_pccreg.h> 66 #include <mvme68k/dev/vme_pccvar.h> 67 68 69 int vme_pcc_match(struct device *, struct cfdata *, void *); 70 void vme_pcc_attach(struct device *, struct device *, void *); 71 72 struct cfattach vmepcc_ca = { 73 sizeof(struct vme_pcc_softc), vme_pcc_match, vme_pcc_attach 74 }; 75 76 extern struct cfdriver vmepcc_cd; 77 78 extern phys_ram_seg_t mem_clusters[]; 79 static int vme_pcc_attached; 80 81 void vme_pcc_intr_establish(void *, int, int, int, int, 82 int (*)(void *), void *); 83 void vme_pcc_intr_disestablish(void *, int, int, int); 84 85 86 static struct mvmebus_range vme_pcc_masters[] = { 87 {VME_AM_A24 | 88 MVMEBUS_AM_CAP_DATA | MVMEBUS_AM_CAP_PROG | 89 MVMEBUS_AM_CAP_SUPER | MVMEBUS_AM_CAP_USER, 90 VME_D32 | VME_D16 | VME_D8, 91 VME1_A24D32_LOC_START, 92 VME1_A24_MASK, 93 VME1_A24D32_START, 94 VME1_A24D32_END}, 95 96 {VME_AM_A32 | 97 MVMEBUS_AM_CAP_DATA | MVMEBUS_AM_CAP_PROG | 98 MVMEBUS_AM_CAP_SUPER | MVMEBUS_AM_CAP_USER, 99 VME_D32 | VME_D16 | VME_D8, 100 VME1_A32D32_LOC_START, 101 VME1_A32_MASK, 102 VME1_A32D32_START, 103 VME1_A32D32_END}, 104 105 {VME_AM_A24 | 106 MVMEBUS_AM_CAP_DATA | MVMEBUS_AM_CAP_PROG | 107 MVMEBUS_AM_CAP_SUPER | MVMEBUS_AM_CAP_USER, 108 VME_D16 | VME_D8, 109 VME1_A24D16_LOC_START, 110 VME1_A24_MASK, 111 VME1_A24D16_START, 112 VME1_A24D16_END}, 113 114 {VME_AM_A32 | 115 MVMEBUS_AM_CAP_DATA | MVMEBUS_AM_CAP_PROG | 116 MVMEBUS_AM_CAP_SUPER | MVMEBUS_AM_CAP_USER, 117 VME_D16 | VME_D8, 118 VME1_A32D16_LOC_START, 119 VME1_A32_MASK, 120 VME1_A32D16_START, 121 VME1_A32D16_END}, 122 123 {VME_AM_A16 | 124 MVMEBUS_AM_CAP_DATA | 125 MVMEBUS_AM_CAP_SUPER | MVMEBUS_AM_CAP_USER, 126 VME_D16 | VME_D8, 127 VME1_A16D16_LOC_START, 128 VME1_A16_MASK, 129 VME1_A16D16_START, 130 VME1_A16D16_END} 131 }; 132 #define VME1_NMASTERS (sizeof(vme_pcc_masters)/sizeof(struct mvmebus_range)) 133 134 135 /* ARGSUSED */ 136 int 137 vme_pcc_match(parent, cf, aux) 138 struct device *parent; 139 struct cfdata *cf; 140 void *aux; 141 { 142 struct pcc_attach_args *pa; 143 144 pa = aux; 145 146 /* Only one VME chip, please. */ 147 if (vme_pcc_attached) 148 return (0); 149 150 if (strcmp(pa->pa_name, vmepcc_cd.cd_name)) 151 return (0); 152 153 return (1); 154 } 155 156 void 157 vme_pcc_attach(parent, self, aux) 158 struct device *parent; 159 struct device *self; 160 void *aux; 161 { 162 struct pcc_attach_args *pa; 163 struct vme_pcc_softc *sc; 164 vme_am_t am; 165 u_int8_t reg; 166 167 sc = (struct vme_pcc_softc *) self; 168 pa = aux; 169 170 /* Map the VMEchip's registers */ 171 bus_space_map(pa->pa_bust, pa->pa_offset, VME1REG_SIZE, 0, 172 &sc->sc_bush); 173 174 /* Initialise stuff used by the mvme68k common VMEbus front-end */ 175 sc->sc_mvmebus.sc_bust = pa->pa_bust; 176 sc->sc_mvmebus.sc_dmat = pa->pa_dmat; 177 sc->sc_mvmebus.sc_chip = sc; 178 sc->sc_mvmebus.sc_nmasters = VME1_NMASTERS; 179 sc->sc_mvmebus.sc_masters = &vme_pcc_masters[0]; 180 sc->sc_mvmebus.sc_nslaves = VME1_NSLAVES; 181 sc->sc_mvmebus.sc_slaves = &sc->sc_slave[0]; 182 sc->sc_mvmebus.sc_intr_establish = vme_pcc_intr_establish; 183 sc->sc_mvmebus.sc_intr_disestablish = vme_pcc_intr_disestablish; 184 185 /* Initialize the chip. */ 186 reg = vme1_reg_read(sc, VME1REG_SCON) & ~VME1_SCON_SYSFAIL; 187 vme1_reg_write(sc, VME1REG_SCON, reg); 188 189 printf(": Type 1 VMEchip, scon jumper %s\n", 190 (reg & VME1_SCON_SWITCH) ? "enabled" : "disabled"); 191 192 /* 193 * Adjust the start address of the first range in vme_pcc_masters[] 194 * according to how much onboard memory exists. Disable the first 195 * range if onboard memory >= 16Mb, and adjust the start of the 196 * second range (A32D32). 197 */ 198 vme_pcc_masters[0].vr_vmestart = (vme_addr_t) mem_clusters[0].size; 199 if (mem_clusters[0].size >= 0x01000000) { 200 vme_pcc_masters[0].vr_am = MVMEBUS_AM_DISABLED; 201 vme_pcc_masters[1].vr_vmestart += 202 (vme_addr_t) (mem_clusters[0].size - 0x01000000); 203 } 204 205 am = 0; 206 reg = vme1_reg_read(sc, VME1REG_SLADDRMOD); 207 if ((reg & VME1_SLMOD_DATA) != 0) 208 am |= MVMEBUS_AM_CAP_DATA; 209 if ((reg & VME1_SLMOD_PRGRM) != 0) 210 am |= MVMEBUS_AM_CAP_PROG; 211 if ((reg & VME1_SLMOD_SUPER) != 0) 212 am |= MVMEBUS_AM_CAP_SUPER; 213 if ((reg & VME1_SLMOD_USER) != 0) 214 am |= MVMEBUS_AM_CAP_USER; 215 if ((reg & VME1_SLMOD_BLOCK) != 0) 216 am |= MVMEBUS_AM_CAP_BLK; 217 218 #ifdef notyet 219 if ((reg & VME1_SLMOD_SHORT) != 0) { 220 sc->sc_slave[VME1_SLAVE_A16].vr_am = am | VME_AM_A16; 221 sc->sc_slave[VME1_SLAVE_A16].vr_mask = 0xffffu; 222 } else 223 #endif 224 sc->sc_slave[VME1_SLAVE_A16].vr_am = MVMEBUS_AM_DISABLED; 225 226 if (pcc_slave_base_addr < 0x01000000u && (reg & VME1_SLMOD_STND) != 0) { 227 sc->sc_slave[VME1_SLAVE_A24].vr_am = am | VME_AM_A24; 228 sc->sc_slave[VME1_SLAVE_A24].vr_datasize = VME_D32 | 229 VME_D16 | VME_D8; 230 sc->sc_slave[VME1_SLAVE_A24].vr_mask = 0xffffffu; 231 sc->sc_slave[VME1_SLAVE_A24].vr_locstart = 0; 232 sc->sc_slave[VME1_SLAVE_A24].vr_vmestart = pcc_slave_base_addr; 233 sc->sc_slave[VME1_SLAVE_A24].vr_vmeend = (pcc_slave_base_addr + 234 mem_clusters[0].size - 1) & 0x00ffffffu; 235 } else 236 sc->sc_slave[VME1_SLAVE_A24].vr_am = MVMEBUS_AM_DISABLED; 237 238 if ((reg & VME1_SLMOD_EXTED) != 0) { 239 sc->sc_slave[VME1_SLAVE_A32].vr_am = am | VME_AM_A32; 240 sc->sc_slave[VME1_SLAVE_A32].vr_datasize = VME_D32 | 241 VME_D16 | VME_D8; 242 sc->sc_slave[VME1_SLAVE_A32].vr_mask = 0xffffffffu; 243 sc->sc_slave[VME1_SLAVE_A32].vr_locstart = 0; 244 sc->sc_slave[VME1_SLAVE_A32].vr_vmestart = pcc_slave_base_addr; 245 sc->sc_slave[VME1_SLAVE_A32].vr_vmeend = 246 pcc_slave_base_addr + mem_clusters[0].size - 1; 247 } else 248 sc->sc_slave[VME1_SLAVE_A32].vr_am = MVMEBUS_AM_DISABLED; 249 250 vme_pcc_attached = 1; 251 252 mvmebus_attach(&sc->sc_mvmebus); 253 } 254 255 void 256 vme_pcc_intr_establish(csc, prior, level, vector, first, func, arg) 257 void *csc; 258 int prior, level, vector, first; 259 int (*func)(void *); 260 void *arg; 261 { 262 struct vme_pcc_softc *sc = csc; 263 264 if (prior != level) 265 panic("vme_pcc_intr_establish: cpu priority != VMEbus irq level"); 266 267 isrlink_vectored(func, arg, prior, vector); 268 269 if (first) { 270 /* 271 * There had better not be another VMEbus master responding 272 * to this interrupt level... 273 */ 274 vme1_reg_write(sc, VME1REG_IRQEN, 275 vme1_reg_read(sc, VME1REG_IRQEN) | VME1_IRQ_VME(level)); 276 } 277 } 278 279 void 280 vme_pcc_intr_disestablish(csc, level, vector, last) 281 void *csc; 282 int level, vector, last; 283 { 284 struct vme_pcc_softc *sc = csc; 285 286 isrunlink_vectored(vector); 287 288 if (last) { 289 vme1_reg_write(sc, VME1REG_IRQEN, 290 vme1_reg_read(sc, VME1REG_IRQEN) & ~VME1_IRQ_VME(level)); 291 } 292 } 293
Indexes created Sat Oct 18 17:09:52 GMT 2025