pci_machdep.c revision 1.2
1 #include <sys/param.h> 2 #include <sys/device.h> 3 #include <dev/pci/pcireg.h> 4 #include <dev/pci/pcivar.h> 5 6 #include <arm32/footbridge/dc21285reg.h> 7 8 void 9 netwinder_pci_attach_hook (struct device *parent, 10 struct device *self, struct pcibus_attach_args *pba) 11 { 12 pcireg_t regval; 13 pcireg_t intreg; 14 pcitag_t tag; 15 16 /* 17 * Initialize the TULIP 18 */ 19 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 9, 0); 20 pci_conf_write(pba->pba_pc, tag, 21 PCI_COMMAND_STATUS_REG, 22 PCI_COMMAND_IO_ENABLE| 23 PCI_COMMAND_MASTER_ENABLE); 24 intreg = pci_conf_read(pba->pba_pc, tag, PCI_INTERRUPT_REG); 25 intreg = PCI_INTERRUPT_CODE( 26 PCI_INTERRUPT_LATENCY(intreg), 27 PCI_INTERRUPT_GRANT(intreg), 28 PCI_INTERRUPT_PIN(intreg), 29 0x40|IRQ_IN_L1); 30 pci_conf_write(pba->pba_pc, tag, PCI_INTERRUPT_REG, intreg); 31 pci_conf_write(pba->pba_pc, tag, 0x10, 0x400 | PCI_MAPREG_TYPE_IO); 32 pci_conf_write(pba->pba_pc, tag, 0x14, 0); 33 34 /* 35 * Initialize the PCI NE2000 36 */ 37 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 12, 0); 38 pci_conf_write(pba->pba_pc, tag, 39 PCI_COMMAND_STATUS_REG, 40 PCI_COMMAND_IO_ENABLE| 41 PCI_COMMAND_MASTER_ENABLE); 42 intreg = pci_conf_read(pba->pba_pc, tag, PCI_INTERRUPT_REG); 43 intreg = PCI_INTERRUPT_CODE( 44 PCI_INTERRUPT_LATENCY(intreg), 45 PCI_INTERRUPT_GRANT(intreg), 46 PCI_INTERRUPT_PIN(intreg), 47 0x40|IRQ_IN_L0); 48 pci_conf_write(pba->pba_pc, tag, PCI_INTERRUPT_REG, intreg); 49 pci_conf_write(pba->pba_pc, tag, 0x10, 0x300 | PCI_MAPREG_TYPE_IO); 50 51 #if 0 52 /* 53 * Initialize the PCI-ISA Bridge 54 */ 55 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 11, 0); 56 pci_conf_write(pba->pba_pc, tag, 57 PCI_COMMAND_STATUS_REG, 58 PCI_COMMAND_IO_ENABLE| 59 PCI_COMMAND_MEM_ENABLE| 60 PCI_COMMAND_MASTER_ENABLE); 61 pci_conf_write(pba->pba_pc, tag, 0x10, 0); 62 pci_conf_write(pba->pba_pc, tag, 0x48, 63 pci_conf_read(pba->pba_pc, tag, 0x48)|0xff); 64 65 regval = pci_conf_read(pba->pba_pc, tag, 0x40); 66 regval &= 0xff00ff00; 67 regval |= 0x00000022; 68 pci_conf_write(pba->pba_pc, tag, 0x40, regval); 69 70 regval = pci_conf_read(pba->pba_pc, tag, 0x80); 71 regval &= 0x0000ff00; 72 regval |= 0xe0010002; 73 pci_conf_write(pba->pba_pc, tag, 0x80, regval); 74 #endif 75 76 /* 77 * Initialize the PCIIDE Controller 78 */ 79 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 11, 1); 80 pci_conf_write(pba->pba_pc, tag, 81 PCI_COMMAND_STATUS_REG, 82 PCI_COMMAND_IO_ENABLE| 83 PCI_COMMAND_MASTER_ENABLE); 84 85 regval = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG); 86 regval = PCI_CLASS_CODE(PCI_CLASS(regval), PCI_SUBCLASS(regval), 0x8A); 87 pci_conf_write(pba->pba_pc, tag, PCI_CLASS_REG, regval); 88 89 regval = pci_conf_read(pba->pba_pc, tag, 0x40); 90 regval &= ~0x10; /* disable secondary port */ 91 pci_conf_write(pba->pba_pc, tag, 0x40, regval); 92 93 pci_conf_write(pba->pba_pc, tag, 0x10, 0x01f0 | PCI_MAPREG_TYPE_IO); 94 pci_conf_write(pba->pba_pc, tag, 0x14, 0x03f4 | PCI_MAPREG_TYPE_IO); 95 pci_conf_write(pba->pba_pc, tag, 0x18, 0x0170 | PCI_MAPREG_TYPE_IO); 96 pci_conf_write(pba->pba_pc, tag, 0x1c, 0x0374 | PCI_MAPREG_TYPE_IO); 97 pci_conf_write(pba->pba_pc, tag, 0x20, 0xe800 | PCI_MAPREG_TYPE_IO); 98 intreg = pci_conf_read(pba->pba_pc, tag, PCI_INTERRUPT_REG); 99 intreg = PCI_INTERRUPT_CODE( 100 PCI_INTERRUPT_LATENCY(intreg), 101 PCI_INTERRUPT_GRANT(intreg), 102 PCI_INTERRUPT_PIN(intreg), 103 0x8e); 104 pci_conf_write(pba->pba_pc, tag, PCI_INTERRUPT_REG, intreg); 105 106 /* 107 * Make sure we are in legacy mode 108 */ 109 regval = pci_conf_read(pba->pba_pc, tag, 0x40); 110 regval &= ~0x800; 111 pci_conf_write(pba->pba_pc, tag, 0x40, regval); 112 } 113
Indexes created Wed Sep 24 02:09:48 GMT 2025