pci_machdep.c revision 1.4
1 /* $NetBSD: pci_machdep.c,v 1.4 2003/07/15 02:59:25 lukem Exp $ */ 2 3 #include <sys/cdefs.h> 4 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.4 2003/07/15 02:59:25 lukem Exp $"); 5 6 #include <sys/param.h> 7 #include <sys/device.h> 8 #include <dev/pci/pcireg.h> 9 #include <dev/pci/pcivar.h> 10 11 #include <arm/footbridge/dc21285reg.h> 12 13 void 14 netwinder_pci_attach_hook (struct device *parent, 15 struct device *self, struct pcibus_attach_args *pba) 16 { 17 pcireg_t regval; 18 pcireg_t intreg; 19 pcitag_t tag; 20 21 /* 22 * Initialize the TULIP 23 */ 24 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 9, 0); 25 pci_conf_write(pba->pba_pc, tag, 26 PCI_COMMAND_STATUS_REG, 27 PCI_COMMAND_IO_ENABLE| 28 PCI_COMMAND_MASTER_ENABLE); 29 intreg = pci_conf_read(pba->pba_pc, tag, PCI_INTERRUPT_REG); 30 intreg = PCI_INTERRUPT_CODE( 31 PCI_INTERRUPT_LATENCY(intreg), 32 PCI_INTERRUPT_GRANT(intreg), 33 PCI_INTERRUPT_PIN(intreg), 34 0x40|IRQ_IN_L1); 35 pci_conf_write(pba->pba_pc, tag, PCI_INTERRUPT_REG, intreg); 36 pci_conf_write(pba->pba_pc, tag, 0x10, 0x400 | PCI_MAPREG_TYPE_IO); 37 pci_conf_write(pba->pba_pc, tag, 0x14, 0); 38 39 /* 40 * Initialize the PCI NE2000 41 */ 42 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 12, 0); 43 pci_conf_write(pba->pba_pc, tag, 44 PCI_COMMAND_STATUS_REG, 45 PCI_COMMAND_IO_ENABLE| 46 PCI_COMMAND_MASTER_ENABLE); 47 intreg = pci_conf_read(pba->pba_pc, tag, PCI_INTERRUPT_REG); 48 intreg = PCI_INTERRUPT_CODE( 49 PCI_INTERRUPT_LATENCY(intreg), 50 PCI_INTERRUPT_GRANT(intreg), 51 PCI_INTERRUPT_PIN(intreg), 52 0x40|IRQ_IN_L0); 53 pci_conf_write(pba->pba_pc, tag, PCI_INTERRUPT_REG, intreg); 54 pci_conf_write(pba->pba_pc, tag, 0x10, 0x300 | PCI_MAPREG_TYPE_IO); 55 56 #if 0 57 /* 58 * Initialize the PCI-ISA Bridge 59 */ 60 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 11, 0); 61 pci_conf_write(pba->pba_pc, tag, 62 PCI_COMMAND_STATUS_REG, 63 PCI_COMMAND_IO_ENABLE| 64 PCI_COMMAND_MEM_ENABLE| 65 PCI_COMMAND_MASTER_ENABLE); 66 pci_conf_write(pba->pba_pc, tag, 0x10, 0); 67 pci_conf_write(pba->pba_pc, tag, 0x48, 68 pci_conf_read(pba->pba_pc, tag, 0x48)|0xff); 69 70 regval = pci_conf_read(pba->pba_pc, tag, 0x40); 71 regval &= 0xff00ff00; 72 regval |= 0x00000022; 73 pci_conf_write(pba->pba_pc, tag, 0x40, regval); 74 75 regval = pci_conf_read(pba->pba_pc, tag, 0x80); 76 regval &= 0x0000ff00; 77 regval |= 0xe0010002; 78 pci_conf_write(pba->pba_pc, tag, 0x80, regval); 79 #endif 80 81 /* 82 * Initialize the PCIIDE Controller 83 */ 84 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 11, 1); 85 pci_conf_write(pba->pba_pc, tag, 86 PCI_COMMAND_STATUS_REG, 87 PCI_COMMAND_IO_ENABLE| 88 PCI_COMMAND_MASTER_ENABLE); 89 90 regval = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG); 91 regval = PCI_CLASS_CODE(PCI_CLASS(regval), PCI_SUBCLASS(regval), 0x8A); 92 pci_conf_write(pba->pba_pc, tag, PCI_CLASS_REG, regval); 93 94 regval = pci_conf_read(pba->pba_pc, tag, 0x40); 95 regval &= ~0x10; /* disable secondary port */ 96 pci_conf_write(pba->pba_pc, tag, 0x40, regval); 97 98 pci_conf_write(pba->pba_pc, tag, 0x10, 0x01f0 | PCI_MAPREG_TYPE_IO); 99 pci_conf_write(pba->pba_pc, tag, 0x14, 0x03f4 | PCI_MAPREG_TYPE_IO); 100 pci_conf_write(pba->pba_pc, tag, 0x18, 0x0170 | PCI_MAPREG_TYPE_IO); 101 pci_conf_write(pba->pba_pc, tag, 0x1c, 0x0374 | PCI_MAPREG_TYPE_IO); 102 pci_conf_write(pba->pba_pc, tag, 0x20, 0xe800 | PCI_MAPREG_TYPE_IO); 103 intreg = pci_conf_read(pba->pba_pc, tag, PCI_INTERRUPT_REG); 104 intreg = PCI_INTERRUPT_CODE( 105 PCI_INTERRUPT_LATENCY(intreg), 106 PCI_INTERRUPT_GRANT(intreg), 107 PCI_INTERRUPT_PIN(intreg), 108 0x8e); 109 pci_conf_write(pba->pba_pc, tag, PCI_INTERRUPT_REG, intreg); 110 111 /* 112 * Make sure we are in legacy mode 113 */ 114 regval = pci_conf_read(pba->pba_pc, tag, 0x40); 115 regval &= ~0x800; 116 pci_conf_write(pba->pba_pc, tag, 0x40, regval); 117 } 118
Indexes created Fri Sep 26 08:10:20 GMT 2025