Home | History | Annotate | Line # | Download | only in include
      1 /*	$NetBSD: cpu.h,v 1.55 2024/01/20 00:15:32 thorpej Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1988 University of Utah.
      5  * Copyright (c) 1982, 1990, 1993
      6  *	The Regents of the University of California.  All rights reserved.
      7  *
      8  * This code is derived from software contributed to Berkeley by
      9  * the Systems Programming Group of the University of Utah Computer
     10  * Science Department.
     11  *
     12  * Redistribution and use in source and binary forms, with or without
     13  * modification, are permitted provided that the following conditions
     14  * are met:
     15  * 1. Redistributions of source code must retain the above copyright
     16  *    notice, this list of conditions and the following disclaimer.
     17  * 2. Redistributions in binary form must reproduce the above copyright
     18  *    notice, this list of conditions and the following disclaimer in the
     19  *    documentation and/or other materials provided with the distribution.
     20  * 3. Neither the name of the University nor the names of its contributors
     21  *    may be used to endorse or promote products derived from this software
     22  *    without specific prior written permission.
     23  *
     24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     34  * SUCH DAMAGE.
     35  *
     36  * from: Utah $Hdr: cpu.h 1.16 91/03/25$
     37  *
     38  *	@(#)cpu.h	8.4 (Berkeley) 1/5/94
     39  */
     40 
     41 #ifndef _NEWS68K_CPU_H_
     42 #define _NEWS68K_CPU_H_
     43 
     44 #if defined(_KERNEL_OPT)
     45 #include "opt_lockdebug.h"
     46 #include "opt_newsconf.h"
     47 #endif
     48 
     49 /*
     50  * Get common m68k CPU definitions.
     51  */
     52 #include <m68k/cpu.h>
     53 
     54 #if defined(_KERNEL)
     55 /*
     56  * Exported definitions unique to news68k cpu support.
     57  */
     58 
     59 /*
     60  * XXX news1700 L2 cache would be corrupted with DC_BE and IC_BE...
     61  * XXX Should these be defined in machine/cpu.h?
     62  */
     63 #undef CACHE_ON
     64 #undef CACHE_CLR
     65 #undef IC_CLEAR
     66 #undef DC_CLEAR
     67 #define CACHE_ON	(DC_WA|DC_CLR|DC_ENABLE|IC_CLR|IC_ENABLE)
     68 #define CACHE_CLR	CACHE_ON
     69 #define IC_CLEAR	(DC_WA|DC_ENABLE|IC_CLR|IC_ENABLE)
     70 #define DC_CLEAR	(DC_WA|DC_CLR|DC_ENABLE|IC_ENABLE)
     71 
     72 #define DCIC_CLR	(DC_CLR|IC_CLR)
     73 #define CACHE_BE	(DC_BE|IC_BE)
     74 
     75 #define	cpu_set_hw_ast(l)						\
     76 	do {								\
     77 		extern volatile u_char *ctrl_ast;			\
     78 		__USE(l);						\
     79 		*ctrl_ast = 0xff;					\
     80 	} while (/*CONSTCOND*/0)
     81 
     82 #if defined(news1700)
     83 #define CACHE_HAVE_PAC
     84 #endif
     85 
     86 extern int systype;
     87 #define NEWS1700	0
     88 #define NEWS1200	1
     89 
     90 extern int cpuspeed;
     91 extern char *intiobase, *intiolimit, *extiobase;
     92 extern u_int intiobase_phys, intiotop_phys;
     93 extern u_int extiobase_phys, extiotop_phys;
     94 
     95 extern void *romcallvec;
     96 
     97 struct frame;
     98 
     99 void doboot(int)
    100 	__attribute__((__noreturn__));
    101 void nmihand(struct frame *);
    102 void ecacheon(void);
    103 void ecacheoff(void);
    104 
    105 /* machdep.c functions */
    106 int badaddr(void *, int);
    107 int badbaddr(void *);
    108 
    109 #endif
    110 
    111 /* physical memory sections */
    112 #define ROMBASE		0xe0000000
    113 
    114 #define INTIOBASE1700	0xe0c00000
    115 #define INTIOTOP1700	0xe1d00000 /* XXX */
    116 #define EXTIOBASE1700	0xf0f00000
    117 #define EXTIOTOP1700	0xf1000000 /* XXX */
    118 #define CTRL_POWER1700	0xe1380000
    119 #define CTRL_LED1700	0xe0dc0000
    120 
    121 #define INTIOBASE1200	0xe1000000
    122 #define INTIOTOP1200	0xe1d00000 /* XXX */
    123 #define EXTIOBASE1200	0xe4000000
    124 #define EXTIOTOP1200	0xe4020000 /* XXX */
    125 #define CTRL_POWER1200	0xe1000000
    126 #define CTRL_LED1200	0xe1500001
    127 
    128 #define MAXADDR		0xfffff000
    129 
    130 /*
    131  * Internal IO space:
    132  *
    133  * Internal IO space is mapped in the kernel from ``intiobase'' to
    134  * ``intiolimit'' (defined in locore.s).  Since it is always mapped,
    135  * conversion between physical and kernel virtual addresses is easy.
    136  */
    137 #define ISIIOVA(va) \
    138 	((char *)(va) >= intiobase && (char *)(va) < intiolimit)
    139 #define IIOV(pa)	(((u_int)(pa) - intiobase_phys) + (u_int)intiobase)
    140 #define ISIIOPA(pa) \
    141 	((u_int)(pa) >= intiobase_phys && (u_int)(pa) < intiotop_phys)
    142 #define IIOP(va)	(((u_int)(va) - (u_int)intiobase) + intiobase_phys)
    143 #define IIOPOFF(pa)	((u_int)(pa) - intiobase_phys)
    144 
    145 /* XXX EIO space mapping should be modified like hp300 XXX */
    146 #define	EIOSIZE		(extiotop_phys - extiobase_phys)
    147 #define ISEIOVA(va) \
    148 	((char *)(va) >= extiobase && (char *)(va) < (char *)EIOSIZE)
    149 #define EIOV(pa)	(((u_int)(pa) - extiobase_phys) + (u_int)extiobase)
    150 
    151 #if defined(CACHE_HAVE_PAC) || defined(CACHE_HAVE_VAC)
    152 #define M68K_CACHEOPS_MACHDEP
    153 #endif
    154 
    155 #ifdef CACHE_HAVE_PAC
    156 #define M68K_CACHEOPS_MACHDEP_PCIA
    157 #endif
    158 
    159 #ifdef CACHE_HAVE_VAC
    160 #define M68K_CACHEOPS_MACHDEP_DCIA
    161 #define M68K_CACHEOPS_MACHDEP_DCIS
    162 #define M68K_CACHEOPS_MACHDEP_DCIU
    163 #endif
    164 
    165 #endif /* !_NEWS68K_CPU_H_ */
    166