cpu.h revision 1.50 1 1.50 thorpej /* $NetBSD: cpu.h,v 1.50 2024/01/15 00:35:23 thorpej Exp $ */
2 1.1 tsutsui
3 1.1 tsutsui /*
4 1.38 rmind * Copyright (c) 1988 University of Utah.
5 1.1 tsutsui * Copyright (c) 1982, 1990, 1993
6 1.1 tsutsui * The Regents of the University of California. All rights reserved.
7 1.16 agc *
8 1.16 agc * This code is derived from software contributed to Berkeley by
9 1.16 agc * the Systems Programming Group of the University of Utah Computer
10 1.16 agc * Science Department.
11 1.16 agc *
12 1.16 agc * Redistribution and use in source and binary forms, with or without
13 1.16 agc * modification, are permitted provided that the following conditions
14 1.16 agc * are met:
15 1.16 agc * 1. Redistributions of source code must retain the above copyright
16 1.16 agc * notice, this list of conditions and the following disclaimer.
17 1.16 agc * 2. Redistributions in binary form must reproduce the above copyright
18 1.16 agc * notice, this list of conditions and the following disclaimer in the
19 1.16 agc * documentation and/or other materials provided with the distribution.
20 1.16 agc * 3. Neither the name of the University nor the names of its contributors
21 1.16 agc * may be used to endorse or promote products derived from this software
22 1.16 agc * without specific prior written permission.
23 1.16 agc *
24 1.16 agc * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 1.16 agc * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 1.16 agc * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 1.16 agc * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 1.16 agc * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 1.16 agc * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 1.16 agc * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 1.16 agc * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 1.16 agc * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 1.16 agc * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 1.16 agc * SUCH DAMAGE.
35 1.16 agc *
36 1.16 agc * from: Utah $Hdr: cpu.h 1.16 91/03/25$
37 1.16 agc *
38 1.16 agc * @(#)cpu.h 8.4 (Berkeley) 1/5/94
39 1.16 agc */
40 1.1 tsutsui
41 1.1 tsutsui #ifndef _NEWS68K_CPU_H_
42 1.2 tsutsui #define _NEWS68K_CPU_H_
43 1.1 tsutsui
44 1.10 mrg #if defined(_KERNEL_OPT)
45 1.4 thorpej #include "opt_lockdebug.h"
46 1.36 mrg #include "opt_m68k_arch.h"
47 1.4 thorpej #endif
48 1.4 thorpej
49 1.1 tsutsui /*
50 1.1 tsutsui * Get common m68k CPU definitions.
51 1.1 tsutsui */
52 1.1 tsutsui #include <m68k/cpu.h>
53 1.1 tsutsui
54 1.41 tsutsui #if defined(_KERNEL)
55 1.41 tsutsui /*
56 1.41 tsutsui * Exported definitions unique to news68k cpu support.
57 1.41 tsutsui */
58 1.41 tsutsui
59 1.1 tsutsui /*
60 1.1 tsutsui * XXX news1700 L2 cache would be corrupted with DC_BE and IC_BE...
61 1.1 tsutsui * XXX Should these be defined in machine/cpu.h?
62 1.1 tsutsui */
63 1.1 tsutsui #undef CACHE_ON
64 1.1 tsutsui #undef CACHE_CLR
65 1.1 tsutsui #undef IC_CLEAR
66 1.1 tsutsui #undef DC_CLEAR
67 1.1 tsutsui #define CACHE_ON (DC_WA|DC_CLR|DC_ENABLE|IC_CLR|IC_ENABLE)
68 1.1 tsutsui #define CACHE_CLR CACHE_ON
69 1.1 tsutsui #define IC_CLEAR (DC_WA|DC_ENABLE|IC_CLR|IC_ENABLE)
70 1.1 tsutsui #define DC_CLEAR (DC_WA|DC_CLR|DC_ENABLE|IC_ENABLE)
71 1.1 tsutsui
72 1.7 tsutsui #define DCIC_CLR (DC_CLR|IC_CLR)
73 1.7 tsutsui #define CACHE_BE (DC_BE|IC_BE)
74 1.2 tsutsui
75 1.1 tsutsui /*
76 1.1 tsutsui * Get interrupt glue.
77 1.1 tsutsui */
78 1.1 tsutsui #include <machine/intr.h>
79 1.1 tsutsui
80 1.1 tsutsui /*
81 1.1 tsutsui * Arguments to hardclock and gatherstats encapsulate the previous
82 1.43 flxd * machine state in an opaque clockframe. On the news68k, we use
83 1.50 thorpej * what the locore.s glue puts on the stack before calling C-code.
84 1.1 tsutsui */
85 1.1 tsutsui struct clockframe {
86 1.50 thorpej u_int cf_regs[4]; /* d0,d1,a0,a1 */
87 1.50 thorpej u_short cf_sr; /* sr at time of interrupt */
88 1.50 thorpej u_long cf_pc; /* pc at time of interrupt */
89 1.50 thorpej u_short cf_vo; /* vector offset (4-word frame) */
90 1.50 thorpej } __attribute__((packed));
91 1.1 tsutsui
92 1.50 thorpej #define CLKF_USERMODE(framep) (((framep)->cf_sr & PSL_S) == 0)
93 1.50 thorpej #define CLKF_PC(framep) ((framep)->cf_pc)
94 1.1 tsutsui #if 0
95 1.1 tsutsui /* We would like to do it this way... */
96 1.50 thorpej #define CLKF_INTR(framep) (((framep)->cf_sr & PSL_M) == 0)
97 1.1 tsutsui #else
98 1.1 tsutsui /* but until we start using PSL_M, we have to do this instead */
99 1.32 tsutsui #include <machine/intr.h>
100 1.32 tsutsui #define CLKF_INTR(framep) (idepth > 1) /* XXX */
101 1.1 tsutsui #endif
102 1.1 tsutsui
103 1.1 tsutsui
104 1.1 tsutsui /*
105 1.1 tsutsui * Preempt the current process if in interrupt from user mode,
106 1.1 tsutsui * or after the current trap/syscall if in system mode.
107 1.1 tsutsui */
108 1.46 ad #define cpu_need_resched(ci,l,flags) do { \
109 1.42 christos __USE(flags); \
110 1.42 christos aston(); \
111 1.42 christos } while (/*CONSTCOND*/0)
112 1.1 tsutsui
113 1.1 tsutsui /*
114 1.1 tsutsui * Give a profiling tick to the current process when the user profiling
115 1.43 flxd * buffer pages are invalid. On the news68k, request an ast to send us
116 1.1 tsutsui * through trap, marking the proc as needing a profiling tick.
117 1.1 tsutsui */
118 1.24 tsutsui #define cpu_need_proftick(l) \
119 1.34 rmind do { (l)->l_pflag |= LP_OWEUPC; aston(); } while (/* CONSTCOND */0)
120 1.1 tsutsui
121 1.1 tsutsui /*
122 1.1 tsutsui * Notify the current process (p) that it has a signal pending,
123 1.1 tsutsui * process as soon as possible.
124 1.1 tsutsui */
125 1.24 tsutsui #define cpu_signotify(l) aston()
126 1.1 tsutsui
127 1.1 tsutsui extern int astpending; /* need to trap before returning to user mode */
128 1.3 tsutsui extern volatile u_char *ctrl_ast;
129 1.27 tsutsui #define aston() \
130 1.27 tsutsui do { astpending++; *ctrl_ast = 0xff; } while (/* CONSTCOND */0)
131 1.4 thorpej
132 1.2 tsutsui #if defined(news1700) || defined(news1200)
133 1.2 tsutsui #ifndef M68030
134 1.1 tsutsui #define M68030
135 1.1 tsutsui #endif
136 1.2 tsutsui #define M68K_MMU_MOTOROLA
137 1.2 tsutsui #endif
138 1.2 tsutsui
139 1.2 tsutsui #if defined(news1700)
140 1.2 tsutsui #define CACHE_HAVE_PAC
141 1.2 tsutsui #endif
142 1.1 tsutsui
143 1.2 tsutsui extern int systype;
144 1.2 tsutsui #define NEWS1700 0
145 1.2 tsutsui #define NEWS1200 1
146 1.2 tsutsui
147 1.2 tsutsui extern int cpuspeed;
148 1.7 tsutsui extern char *intiobase, *intiolimit, *extiobase;
149 1.2 tsutsui extern u_int intiobase_phys, intiotop_phys;
150 1.2 tsutsui extern u_int extiobase_phys, extiotop_phys;
151 1.2 tsutsui extern u_int intrcnt[];
152 1.1 tsutsui
153 1.40 tsutsui extern void *romcallvec;
154 1.1 tsutsui
155 1.1 tsutsui struct frame;
156 1.1 tsutsui
157 1.13 tsutsui void doboot(int)
158 1.1 tsutsui __attribute__((__noreturn__));
159 1.13 tsutsui void nmihand(struct frame *);
160 1.13 tsutsui void ecacheon(void);
161 1.13 tsutsui void ecacheoff(void);
162 1.1 tsutsui
163 1.1 tsutsui /* machdep.c functions */
164 1.26 christos int badaddr(void *, int);
165 1.26 christos int badbaddr(void *);
166 1.1 tsutsui
167 1.1 tsutsui #endif
168 1.1 tsutsui
169 1.1 tsutsui /* physical memory sections */
170 1.22 tsutsui #define ROMBASE 0xe0000000
171 1.2 tsutsui
172 1.22 tsutsui #define INTIOBASE1700 0xe0c00000
173 1.22 tsutsui #define INTIOTOP1700 0xe1d00000 /* XXX */
174 1.22 tsutsui #define EXTIOBASE1700 0xf0f00000
175 1.22 tsutsui #define EXTIOTOP1700 0xf1000000 /* XXX */
176 1.22 tsutsui #define CTRL_POWER1700 0xe1380000
177 1.22 tsutsui #define CTRL_LED1700 0xe0dc0000
178 1.22 tsutsui
179 1.22 tsutsui #define INTIOBASE1200 0xe1000000
180 1.22 tsutsui #define INTIOTOP1200 0xe1d00000 /* XXX */
181 1.22 tsutsui #define EXTIOBASE1200 0xe4000000
182 1.22 tsutsui #define EXTIOTOP1200 0xe4020000 /* XXX */
183 1.22 tsutsui #define CTRL_POWER1200 0xe1000000
184 1.22 tsutsui #define CTRL_LED1200 0xe1500001
185 1.2 tsutsui
186 1.22 tsutsui #define MAXADDR 0xfffff000
187 1.1 tsutsui
188 1.1 tsutsui /*
189 1.1 tsutsui * Internal IO space:
190 1.1 tsutsui *
191 1.1 tsutsui * Internal IO space is mapped in the kernel from ``intiobase'' to
192 1.1 tsutsui * ``intiolimit'' (defined in locore.s). Since it is always mapped,
193 1.1 tsutsui * conversion between physical and kernel virtual addresses is easy.
194 1.1 tsutsui */
195 1.2 tsutsui #define ISIIOVA(va) \
196 1.1 tsutsui ((char *)(va) >= intiobase && (char *)(va) < intiolimit)
197 1.2 tsutsui #define IIOV(pa) (((u_int)(pa) - intiobase_phys) + (u_int)intiobase)
198 1.2 tsutsui #define ISIIOPA(pa) \
199 1.2 tsutsui ((u_int)(pa) >= intiobase_phys && (u_int)(pa) < intiotop_phys)
200 1.2 tsutsui #define IIOP(va) (((u_int)(va) - (u_int)intiobase) + intiobase_phys)
201 1.2 tsutsui #define IIOPOFF(pa) ((u_int)(pa) - intiobase_phys)
202 1.6 tsutsui
203 1.6 tsutsui /* XXX EIO space mapping should be modified like hp300 XXX */
204 1.6 tsutsui #define EIOSIZE (extiotop_phys - extiobase_phys)
205 1.6 tsutsui #define ISEIOVA(va) \
206 1.6 tsutsui ((char *)(va) >= extiobase && (char *)(va) < (char *)EIOSIZE)
207 1.6 tsutsui #define EIOV(pa) (((u_int)(pa) - extiobase_phys) + (u_int)extiobase)
208 1.12 chs
209 1.12 chs #if defined(CACHE_HAVE_PAC) || defined(CACHE_HAVE_VAC)
210 1.12 chs #define M68K_CACHEOPS_MACHDEP
211 1.12 chs #endif
212 1.12 chs
213 1.12 chs #ifdef CACHE_HAVE_PAC
214 1.12 chs #define M68K_CACHEOPS_MACHDEP_PCIA
215 1.12 chs #endif
216 1.12 chs
217 1.12 chs #ifdef CACHE_HAVE_VAC
218 1.12 chs #define M68K_CACHEOPS_MACHDEP_DCIA
219 1.12 chs #define M68K_CACHEOPS_MACHDEP_DCIS
220 1.12 chs #define M68K_CACHEOPS_MACHDEP_DCIU
221 1.12 chs #endif
222 1.1 tsutsui
223 1.1 tsutsui #endif /* !_NEWS68K_CPU_H_ */
224