1 /* $NetBSD: pq3ddrc.c,v 1.2 2020/07/06 09:34:16 rin Exp $ */ 2 /*- 3 * Copyright (c) 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #define DDRC_PRIVATE 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: pq3ddrc.c,v 1.2 2020/07/06 09:34:16 rin Exp $"); 41 42 #include "ioconf.h" 43 44 #include <sys/param.h> 45 #include <sys/bus.h> 46 #include <sys/cpu.h> 47 #include <sys/device.h> 48 #include <sys/intr.h> 49 50 #include <powerpc/booke/cpuvar.h> 51 #include <powerpc/booke/e500var.h> 52 #include <powerpc/booke/e500reg.h> 53 54 struct pq3ddrc_softc { 55 device_t sc_dev; 56 bus_space_tag_t sc_memt; 57 bus_space_handle_t sc_memh; 58 void *sc_ih; 59 struct evcnt sc_ev_sbe; 60 }; 61 62 static int pq3ddrc_match(device_t, cfdata_t, void *); 63 static void pq3ddrc_attach(device_t, device_t, void *); 64 65 CFATTACH_DECL_NEW(pq3ddrc, sizeof(struct pq3ddrc_softc), 66 pq3ddrc_match, pq3ddrc_attach, NULL, NULL); 67 68 static int 69 pq3ddrc_match(device_t parent, cfdata_t cf, void *aux) 70 { 71 if (!e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 72 return 0; 73 74 return 1; 75 } 76 77 static int 78 pq3ddrc_intr(void *arg) 79 { 80 struct pq3ddrc_softc * const sc = arg; 81 uint32_t v; 82 83 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, ERR_DETECT); 84 bus_space_write_4(sc->sc_memt, sc->sc_memh, ERR_DETECT, v); 85 86 if (v & ERR_SBEE) { 87 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, ERR_SBE); 88 sc->sc_ev_sbe.ev_count += __SHIFTIN(v, ERR_SBE_SBEC); 89 v &= ~ERR_SBE_SBEC; 90 bus_space_write_4(sc->sc_memt, sc->sc_memh, ERR_SBE, v); 91 } 92 93 return 1; 94 } 95 96 static void 97 pq3ddrc_attach(device_t parent, device_t self, void *aux) 98 { 99 struct cpunode_softc * const psc = device_private(parent); 100 struct pq3ddrc_softc * const sc = device_private(self); 101 struct cpunode_attach_args * const cna = aux; 102 struct cpunode_locators * const cnl = &cna->cna_locs; 103 uint32_t v; 104 105 psc->sc_children |= cna->cna_childmask; 106 sc->sc_dev = self; 107 sc->sc_memt = cna->cna_memt; 108 109 int error = bus_space_map(cna->cna_memt, cnl->cnl_addr, cnl->cnl_size, 110 0, &sc->sc_memh); 111 if (error) { 112 aprint_error(": failed to map registers: %d\n", error); 113 return; 114 } 115 116 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, DDR_SDRAM_CFG); 117 if ((v & SDRAM_CFG_ECC_EN) == 0) { 118 aprint_normal(": ECC disabled\n"); 119 return; 120 } 121 122 evcnt_attach_dynamic(&sc->sc_ev_sbe, EVCNT_TYPE_MISC, NULL, 123 device_xname(self), "single-bit ecc errors"); 124 125 /* 126 * Clear errors. 127 */ 128 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, ERR_DETECT); 129 bus_space_write_4(sc->sc_memt, sc->sc_memh, ERR_DETECT, v); 130 131 /* 132 * Make sure ECC errors are not disabled. 133 */ 134 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, ERR_DISABLE); 135 v &= ~(ERR_MBEE|ERR_SBEE); 136 bus_space_write_4(sc->sc_memt, sc->sc_memh, ERR_DISABLE, v); 137 138 /* 139 * Make sure ECC errors generate interrupts 140 */ 141 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, ERR_INT_EN); 142 v |= ERR_MBEE|ERR_SBEE; 143 bus_space_write_4(sc->sc_memt, sc->sc_memh, ERR_INT_EN, v); 144 145 sc->sc_ih = intr_establish(cnl->cnl_intrs[0], IPL_VM, 146 IST_ONCHIP, pq3ddrc_intr, sc); 147 if (sc->sc_ih == NULL) { 148 aprint_error_dev(self, "failed to establish interrupt %d\n", 149 cnl->cnl_intrs[0]); 150 } else { 151 aprint_normal_dev(self, "interrupting on irq %d\n", 152 cnl->cnl_intrs[0]); 153 } 154 } 155
Indexes created Mon Sep 22 05:09:51 GMT 2025