fpu_emu.c revision 1.1
1 /* $NetBSD: fpu_emu.c,v 1.1 2001/06/13 06:01:47 simonb Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1992, 1993 40 * The Regents of the University of California. All rights reserved. 41 * 42 * This software was developed by the Computer Systems Engineering group 43 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 44 * contributed to Berkeley. 45 * 46 * All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the University of 49 * California, Lawrence Berkeley Laboratory. 50 * 51 * Redistribution and use in source and binary forms, with or without 52 * modification, are permitted provided that the following conditions 53 * are met: 54 * 1. Redistributions of source code must retain the above copyright 55 * notice, this list of conditions and the following disclaimer. 56 * 2. Redistributions in binary form must reproduce the above copyright 57 * notice, this list of conditions and the following disclaimer in the 58 * documentation and/or other materials provided with the distribution. 59 * 3. All advertising materials mentioning features or use of this software 60 * must display the following acknowledgement: 61 * This product includes software developed by the University of 62 * California, Berkeley and its contributors. 63 * 4. Neither the name of the University nor the names of its contributors 64 * may be used to endorse or promote products derived from this software 65 * without specific prior written permission. 66 * 67 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 71 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 72 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 73 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 74 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 75 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 76 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 77 * SUCH DAMAGE. 78 * 79 * @(#)fpu.c 8.1 (Berkeley) 6/11/93 80 */ 81 82 #include "opt_ddb.h" 83 84 #include <sys/param.h> 85 #include <sys/proc.h> 86 #include <sys/signal.h> 87 #include <sys/systm.h> 88 #include <sys/syslog.h> 89 #include <sys/signalvar.h> 90 91 #include <powerpc/instr.h> 92 #include <machine/reg.h> 93 #include <machine/fpu.h> 94 95 #include <powerpc/fpu/fpu_emu.h> 96 #include <powerpc/fpu/fpu_extern.h> 97 98 99 /* FPSR exception masks */ 100 #define FPSR_EX_MSK (FPSCR_VX|FPSCR_OX|FPSCR_UX|FPSCR_ZX| \ 101 FPSCR_XX|FPSCR_VXSNAN|FPSCR_VXISI|FPSCR_VXIDI| \ 102 FPSCR_VXZDZ|FPSCR_VXIMZ|FPSCR_VXVC|FPSCR_VXSOFT|\ 103 FPSCR_VXSQRT|FPSCR_VXCVI) 104 #define FPSR_EX (FPSCR_VE|FPSCR_OE|FPSCR_UE|FPSCR_ZE|FPSCR_XE) 105 #define FPSR_EXOP (FPSR_EX_MSK&(~FPSR_EX)) 106 107 108 int fpe_debug = 0; 109 110 #ifdef DDB 111 extern vaddr_t opc_disasm(vaddr_t loc, int opcode); 112 #endif 113 114 #ifdef DEBUG 115 /* 116 * Dump a `fpn' structure. 117 */ 118 void 119 fpu_dumpfpn(struct fpn *fp) 120 { 121 static char *class[] = { 122 "SNAN", "QNAN", "ZERO", "NUM", "INF" 123 }; 124 125 printf("%s %c.%x %x %x %xE%d", class[fp->fp_class + 2], 126 fp->fp_sign ? '-' : ' ', 127 fp->fp_mant[0], fp->fp_mant[1], 128 fp->fp_mant[2], fp->fp_mant[3], 129 fp->fp_exp); 130 } 131 #endif 132 133 /* 134 * fpu_execute returns the following error numbers (0 = no error): 135 */ 136 #define FPE 1 /* take a floating point exception */ 137 #define NOTFPU 2 /* not an FPU instruction */ 138 #define FAULT 3 139 140 141 /* 142 * Emulate a floating-point instruction. 143 * Return zero for success, else signal number. 144 * (Typically: zero, SIGFPE, SIGILL, SIGSEGV) 145 */ 146 int 147 fpu_emulate(struct trapframe *frame, struct fpreg *fpf) 148 { 149 static union instr insn; 150 static struct fpemu fe; 151 static int lastill = 0; 152 int sig; 153 154 /* initialize insn.is_datasize to tell it is *not* initialized */ 155 fe.fe_fpstate = fpf; 156 fe.fe_cx = 0; 157 158 /* always set this (to avoid a warning) */ 159 160 if (copyin((void *) (frame->srr0), &insn.i_int, sizeof (insn.i_int))) { 161 #ifdef DEBUG 162 printf("fpu_emulate: fault reading opcode\n"); 163 #endif 164 return SIGSEGV; 165 } 166 167 DPRINTF(FPE_EX, ("fpu_emulate: emulating insn %x at %p\n", 168 insn.i_int, (void *)frame->srr0)); 169 170 171 if ((insn.i_any.i_opcd == OPC_TWI) || 172 ((insn.i_any.i_opcd == OPC_integer_31) && 173 (insn.i_x.i_xo == OPC31_TW))) { 174 /* Check for the two trap insns. */ 175 DPRINTF(FPE_EX, ("fpu_emulate: SIGTRAP\n")); 176 return (SIGTRAP); 177 } 178 sig = 0; 179 switch (fpu_execute(frame, &fe, &insn)) { 180 case 0: 181 DPRINTF(FPE_EX, ("fpu_emulate: success\n")); 182 frame->srr0 += 4; 183 break; 184 185 case FPE: 186 DPRINTF(FPE_EX, ("fpu_emulate: SIGFPE\n")); 187 sig = SIGFPE; 188 break; 189 190 case FAULT: 191 DPRINTF(FPE_EX, ("fpu_emulate: SIGSEGV\n")); 192 sig = SIGSEGV; 193 break; 194 195 case NOTFPU: 196 default: 197 DPRINTF(FPE_EX, ("fpu_emulate: SIGILL\n")); 198 if (fpe_debug & FPE_EX) { 199 printf("fpu_emulate: illegal insn %x at %p:", 200 insn.i_int, (void *) (frame->srr0)); 201 opc_disasm((vaddr_t)(frame->srr0), insn.i_int); 202 } 203 /* 204 * XXXX retry an illegal insn once due to cache issues. 205 */ 206 if (lastill == frame->srr0) { 207 sig = SIGILL; 208 if (fpe_debug & FPE_EX) 209 Debugger(); 210 } 211 lastill = frame->srr0; 212 break; 213 } 214 215 return (sig); 216 } 217 218 /* 219 * Execute an FPU instruction (one that runs entirely in the FPU; not 220 * FBfcc or STF, for instance). On return, fe->fe_fs->fs_fsr will be 221 * modified to reflect the setting the hardware would have left. 222 * 223 * Note that we do not catch all illegal opcodes, so you can, for instance, 224 * multiply two integers this way. 225 */ 226 int 227 fpu_execute(struct trapframe *tf, struct fpemu *fe, union instr *insn) 228 { 229 struct fpn *fp; 230 union instr instr = *insn; 231 int *a; 232 vaddr_t addr; 233 int ra, rb, rc, rt, type, mask, fsr, cx, bf, setcr, cond; 234 struct fpreg *fs; 235 236 /* Setup work. */ 237 fp = NULL; 238 fs = fe->fe_fpstate; 239 fe->fe_fpscr = ((int *)&fs->fpscr)[1]; 240 241 /* 242 * On PowerPC all floating point values are stored in registers 243 * as doubles, even when used for single precision operations. 244 */ 245 type = FTYPE_DBL; 246 cond = instr.i_any.i_rc; 247 setcr = 0; 248 249 #if defined(DDB) && defined(DEBUG) 250 if (fpe_debug & FPE_EX) { 251 vaddr_t loc = tf->srr0; 252 253 printf("Trying to emulate: %p ", (void *)loc); 254 opc_disasm(loc, instr.i_int); 255 } 256 #endif 257 258 /* 259 * `Decode' and execute instruction. 260 */ 261 262 if ((instr.i_any.i_opcd >= OPC_LFS && instr.i_any.i_opcd <= OPC_STFDU) || 263 instr.i_any.i_opcd == OPC_integer_31) { 264 /* 265 * Handle load/store insns: 266 * 267 * Convert to/from single if needed, calculate addr, 268 * and update index reg if needed. 269 */ 270 double buf; 271 size_t size = sizeof(float); 272 int store, update; 273 274 cond = 0; /* ld/st never set condition codes */ 275 276 277 if (instr.i_any.i_opcd == OPC_integer_31) { 278 if (instr.i_x.i_xo == OPC31_STFIWX) { 279 /* Store as integer */ 280 ra = instr.i_x.i_ra; 281 rb = instr.i_x.i_rb; 282 DPRINTF(FPE_INSN, ("reg %d has %x reg %d has %x\n", 283 ra, tf->fixreg[ra], rb, tf->fixreg[rb])); 284 285 addr = tf->fixreg[rb]; 286 if (ra != 0) 287 addr += tf->fixreg[ra]; 288 rt = instr.i_x.i_rt; 289 a = (int *)&fs->fpreg[rt]; 290 DPRINTF(FPE_INSN, 291 ("fpu_execute: Store INT %x at %p\n", 292 a[1], (void *)addr)); 293 if (copyout(&a[1], (void *)addr, sizeof(int))) 294 return (FAULT); 295 return (0); 296 } 297 298 if ((instr.i_x.i_xo & OPC31_FPMASK) != OPC31_FPOP) 299 /* Not an indexed FP load/store op */ 300 return (NOTFPU); 301 302 store = (instr.i_x.i_xo & 0x80); 303 if (instr.i_x.i_xo & 0x40) 304 size = sizeof(double); 305 else 306 type = FTYPE_SNG; 307 update = (instr.i_x.i_xo & 0x20); 308 309 /* calculate EA of load/store */ 310 ra = instr.i_x.i_ra; 311 rb = instr.i_x.i_rb; 312 DPRINTF(FPE_INSN, ("reg %d has %x reg %d has %x\n", 313 ra, tf->fixreg[ra], rb, tf->fixreg[rb])); 314 addr = tf->fixreg[rb]; 315 if (ra != 0) 316 addr += tf->fixreg[ra]; 317 rt = instr.i_x.i_rt; 318 } else { 319 store = instr.i_d.i_opcd & 0x4; 320 if (instr.i_d.i_opcd & 0x2) 321 size = sizeof(double); 322 else 323 type = FTYPE_SNG; 324 update = instr.i_d.i_opcd & 0x1; 325 326 /* calculate EA of load/store */ 327 ra = instr.i_d.i_ra; 328 addr = instr.i_d.i_d; 329 DPRINTF(FPE_INSN, ("reg %d has %x displ %lx\n", 330 ra, tf->fixreg[ra], addr)); 331 if (ra != 0) 332 addr += tf->fixreg[ra]; 333 rt = instr.i_d.i_rt; 334 } 335 336 if (update && ra == 0) 337 return (NOTFPU); 338 339 if (store) { 340 /* Store */ 341 if (type != FTYPE_DBL) { 342 DPRINTF(FPE_INSN, 343 ("fpu_execute: Store SNG at %p\n", 344 (void *)addr)); 345 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rt); 346 fpu_implode(fe, fp, type, (u_int *)&buf); 347 if (copyout(&buf, (void *)addr, size)) 348 return (FAULT); 349 } else { 350 DPRINTF(FPE_INSN, 351 ("fpu_execute: Store DBL at %p\n", 352 (void *)addr)); 353 if (copyout(&fs->fpreg[rt], (void *)addr, size)) 354 return (FAULT); 355 } 356 } else { 357 /* Load */ 358 DPRINTF(FPE_INSN, ("fpu_execute: Load from %p\n", 359 (void *)addr)); 360 if (copyin((const void *)addr, &fs->fpreg[rt], size)) 361 return (FAULT); 362 if (type != FTYPE_DBL) { 363 fpu_explode(fe, fp = &fe->fe_f1, type, rt); 364 fpu_implode(fe, fp, FTYPE_DBL, 365 (u_int *)&fs->fpreg[rt]); 366 } 367 } 368 if (update) 369 tf->fixreg[ra] = addr; 370 /* Complete. */ 371 return (0); 372 #ifdef notyet 373 } else if (instr.i_any.i_opcd == OPC_load_st_62) { 374 /* These are 64-bit extenstions */ 375 return (NOTFPU); 376 #endif 377 } else if (instr.i_any.i_opcd == OPC_sp_fp_59 || 378 instr.i_any.i_opcd == OPC_dp_fp_63) { 379 380 381 if (instr.i_any.i_opcd == OPC_dp_fp_63 && 382 !(instr.i_a.i_xo & OPC63M_MASK)) { 383 /* Format X */ 384 rt = instr.i_x.i_rt; 385 ra = instr.i_x.i_ra; 386 rb = instr.i_x.i_rb; 387 388 389 /* One of the special opcodes.... */ 390 switch (instr.i_x.i_xo) { 391 case OPC63_FCMPU: 392 DPRINTF(FPE_INSN, ("fpu_execute: FCMPU\n")); 393 rt >>= 2; 394 fpu_explode(fe, &fe->fe_f1, type, ra); 395 fpu_explode(fe, &fe->fe_f2, type, rb); 396 fpu_compare(fe, 0); 397 /* Make sure we do the condition regs. */ 398 cond = 0; 399 /* N.B.: i_rs is already left shifted by two. */ 400 bf = instr.i_x.i_rs & 0xfc; 401 setcr = 1; 402 break; 403 404 case OPC63_FRSP: 405 /* 406 * Convert to single: 407 * 408 * PowerPC uses this to round a double 409 * precision value to single precision, 410 * but values in registers are always 411 * stored in double precision format. 412 */ 413 DPRINTF(FPE_INSN, ("fpu_execute: FRSP\n")); 414 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rb); 415 fpu_implode(fe, fp, FTYPE_SNG, 416 (u_int *)&fs->fpreg[rt]); 417 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt); 418 type = FTYPE_DBL; 419 break; 420 case OPC63_FCTIW: 421 case OPC63_FCTIWZ: 422 DPRINTF(FPE_INSN, ("fpu_execute: FCTIW\n")); 423 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 424 type = FTYPE_INT; 425 break; 426 case OPC63_FCMPO: 427 DPRINTF(FPE_INSN, ("fpu_execute: FCMPO\n")); 428 rt >>= 2; 429 fpu_explode(fe, &fe->fe_f1, type, ra); 430 fpu_explode(fe, &fe->fe_f2, type, rb); 431 fpu_compare(fe, 1); 432 /* Make sure we do the condition regs. */ 433 cond = 0; 434 /* N.B.: i_rs is already left shifted by two. */ 435 bf = instr.i_x.i_rs & 0xfc; 436 setcr = 1; 437 break; 438 case OPC63_MTFSB1: 439 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB1\n")); 440 fe->fe_fpscr |= 441 (~(FPSCR_VX|FPSR_EX) & (1<<(31-rt))); 442 break; 443 case OPC63_FNEG: 444 DPRINTF(FPE_INSN, ("fpu_execute: FNEGABS\n")); 445 bcopy(&fs->fpreg[rb], &fs->fpreg[rt], 446 sizeof(double)); 447 a = (int *)&fs->fpreg[rt]; 448 *a ^= (1 << 31); 449 break; 450 case OPC63_MCRFS: 451 DPRINTF(FPE_INSN, ("fpu_execute: MCRFS\n")); 452 cond = 0; 453 rt &= 0x1c; 454 ra &= 0x1c; 455 /* Extract the bits we want */ 456 mask = (fe->fe_fpscr >> (28 - ra)) & 0xf; 457 /* Clear the bits we copied. */ 458 fe->fe_cx = 459 (FPSR_EX_MSK | (0xf << (28 - ra))); 460 fe->fe_fpscr &= fe->fe_cx; 461 /* Now shove them in the right part of cr */ 462 tf->cr &= ~(0xf << (28 - rt)); 463 tf->cr |= (mask << (28 - rt)); 464 break; 465 case OPC63_MTFSB0: 466 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB0\n")); 467 fe->fe_fpscr &= 468 ((FPSCR_VX|FPSR_EX) & ~(1<<(31-rt))); 469 break; 470 case OPC63_FMR: 471 DPRINTF(FPE_INSN, ("fpu_execute: FMR\n")); 472 bcopy(&fs->fpreg[rb], &fs->fpreg[rt], 473 sizeof(double)); 474 break; 475 case OPC63_MTFSFI: 476 DPRINTF(FPE_INSN, ("fpu_execute: MTFSFI\n")); 477 rb >>= 1; 478 rt &= 0x1c; /* Already left-shifted 4 */ 479 fe->fe_cx = rb << (28 - rt); 480 mask = 0xf<<(28 - rt); 481 fe->fe_fpscr = (fe->fe_fpscr & ~mask) | 482 fe->fe_cx; 483 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */ 484 break; 485 case OPC63_FNABS: 486 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 487 bcopy(&fs->fpreg[rb], &fs->fpreg[rt], 488 sizeof(double)); 489 a = (int *)&fs->fpreg[rt]; 490 *a |= (1 << 31); 491 break; 492 case OPC63_FABS: 493 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 494 bcopy(&fs->fpreg[rb], &fs->fpreg[rt], 495 sizeof(double)); 496 a = (int *)&fs->fpreg[rt]; 497 *a &= ~(1 << 31); 498 break; 499 case OPC63_MFFS: 500 DPRINTF(FPE_INSN, ("fpu_execute: MFFS\n")); 501 bcopy(&fs->fpscr, &fs->fpreg[rt], 502 sizeof(fs->fpscr)); 503 break; 504 case OPC63_MTFSF: 505 DPRINTF(FPE_INSN, ("fpu_execute: MTFSF\n")); 506 if ((rt = instr.i_xfl.i_flm) == -1) 507 mask = -1; 508 else { 509 mask = 0; 510 /* Convert 1 bit -> 4 bits */ 511 for (ra = 0; ra < 8; ra ++) 512 if (rt & (1<<ra)) 513 mask |= (0xf<<(4*ra)); 514 } 515 a = (int *)&fs->fpreg[rt]; 516 fe->fe_cx = mask & a[1]; 517 fe->fe_fpscr = (fe->fe_fpscr&~mask) | 518 (fe->fe_cx); 519 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */ 520 break; 521 case OPC63_FCTID: 522 case OPC63_FCTIDZ: 523 DPRINTF(FPE_INSN, ("fpu_execute: FCTID\n")); 524 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 525 type = FTYPE_LNG; 526 break; 527 case OPC63_FCFID: 528 DPRINTF(FPE_INSN, ("fpu_execute: FCFID\n")); 529 type = FTYPE_LNG; 530 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 531 type = FTYPE_DBL; 532 break; 533 default: 534 return (NOTFPU); 535 break; 536 } 537 } else { 538 /* Format A */ 539 rt = instr.i_a.i_frt; 540 ra = instr.i_a.i_fra; 541 rb = instr.i_a.i_frb; 542 rc = instr.i_a.i_frc; 543 544 type = FTYPE_SNG; 545 if (instr.i_any.i_opcd & 0x4) 546 type = FTYPE_DBL; 547 switch ((unsigned int)instr.i_a.i_xo) { 548 case OPC59_FDIVS: 549 DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n")); 550 fpu_explode(fe, &fe->fe_f1, type, ra); 551 fpu_explode(fe, &fe->fe_f2, type, rb); 552 fp = fpu_div(fe); 553 break; 554 case OPC59_FSUBS: 555 DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n")); 556 fpu_explode(fe, &fe->fe_f1, type, ra); 557 fpu_explode(fe, &fe->fe_f2, type, rb); 558 fp = fpu_sub(fe); 559 break; 560 case OPC59_FADDS: 561 DPRINTF(FPE_INSN, ("fpu_execute: FADD\n")); 562 fpu_explode(fe, &fe->fe_f1, type, ra); 563 fpu_explode(fe, &fe->fe_f2, type, rb); 564 fp = fpu_add(fe); 565 break; 566 case OPC59_FSQRTS: 567 DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n")); 568 fpu_explode(fe, &fe->fe_f1, type, rb); 569 fp = fpu_sqrt(fe); 570 break; 571 case OPC63M_FSEL: 572 DPRINTF(FPE_INSN, ("fpu_execute: FSEL\n")); 573 a = (int *)&fe->fe_fpstate->fpreg[ra]; 574 if ((*a & 0x80000000) && (*a & 0x7fffffff)) 575 /* fra < 0 */ 576 rc = rb; 577 DPRINTF(FPE_INSN, ("f%d => f%d\n", rc, rt)); 578 bcopy(&fs->fpreg[rc], &fs->fpreg[rt], 579 sizeof(double)); 580 break; 581 case OPC59_FRES: 582 DPRINTF(FPE_INSN, ("fpu_execute: FPRES\n")); 583 fpu_explode(fe, &fe->fe_f1, type, rb); 584 fp = fpu_sqrt(fe); 585 /* now we've gotta overwrite the dest reg */ 586 *((int *)&fe->fe_fpstate->fpreg[rt]) = 1; 587 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 588 fpu_div(fe); 589 break; 590 case OPC59_FMULS: 591 DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n")); 592 fpu_explode(fe, &fe->fe_f1, type, ra); 593 fpu_explode(fe, &fe->fe_f2, type, rc); 594 fp = fpu_mul(fe); 595 break; 596 case OPC63M_FRSQRTE: 597 /* Reciprocal sqrt() estimate */ 598 DPRINTF(FPE_INSN, ("fpu_execute: FRSQRTE\n")); 599 fpu_explode(fe, &fe->fe_f1, type, rb); 600 fe->fe_f2 = *fp; 601 /* now we've gotta overwrite the dest reg */ 602 *((int *)&fe->fe_fpstate->fpreg[rt]) = 1; 603 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 604 fpu_div(fe); 605 break; 606 case OPC59_FMSUBS: 607 DPRINTF(FPE_INSN, ("fpu_execute: FMULSUB\n")); 608 fpu_explode(fe, &fe->fe_f1, type, ra); 609 fpu_explode(fe, &fe->fe_f2, type, rc); 610 fp = fpu_mul(fe); 611 fe->fe_f1 = *fp; 612 fpu_explode(fe, &fe->fe_f2, type, rb); 613 fp = fpu_sub(fe); 614 break; 615 case OPC59_FMADDS: 616 DPRINTF(FPE_INSN, ("fpu_execute: FMULADD\n")); 617 fpu_explode(fe, &fe->fe_f1, type, ra); 618 fpu_explode(fe, &fe->fe_f2, type, rc); 619 fp = fpu_mul(fe); 620 fe->fe_f1 = *fp; 621 fpu_explode(fe, &fe->fe_f2, type, rb); 622 fp = fpu_add(fe); 623 break; 624 case OPC59_FNMSUBS: 625 DPRINTF(FPE_INSN, ("fpu_execute: FNMSUB\n")); 626 fpu_explode(fe, &fe->fe_f1, type, ra); 627 fpu_explode(fe, &fe->fe_f2, type, rc); 628 fp = fpu_mul(fe); 629 fe->fe_f1 = *fp; 630 fpu_explode(fe, &fe->fe_f2, type, rb); 631 fp = fpu_sub(fe); 632 /* Negate */ 633 fp->fp_sign ^= 1; 634 break; 635 case OPC59_FNMADDS: 636 DPRINTF(FPE_INSN, ("fpu_execute: FNMADD\n")); 637 fpu_explode(fe, &fe->fe_f1, type, ra); 638 fpu_explode(fe, &fe->fe_f2, type, rc); 639 fp = fpu_mul(fe); 640 fe->fe_f1 = *fp; 641 fpu_explode(fe, &fe->fe_f2, type, rb); 642 fp = fpu_add(fe); 643 /* Negate */ 644 fp->fp_sign ^= 1; 645 break; 646 default: 647 return (NOTFPU); 648 break; 649 } 650 } 651 } else { 652 return (NOTFPU); 653 } 654 655 /* 656 * ALU operation is complete. Collapse the result and then check 657 * for exceptions. If we got any, and they are enabled, do not 658 * alter the destination register, just stop with an exception. 659 * Otherwise set new current exceptions and accrue. 660 */ 661 if (fp) 662 fpu_implode(fe, fp, type, (u_int *)&fs->fpreg[rt]); 663 cx = fe->fe_cx; 664 fsr = fe->fe_fpscr; 665 if (cx != 0) { 666 fsr &= ~FPSCR_FX; 667 if ((cx^fsr)&FPSR_EX_MSK) 668 fsr |= FPSCR_FX; 669 mask = fsr & FPSR_EX; 670 mask <<= (25-3); 671 if (cx & mask) 672 fsr |= FPSCR_FEX; 673 if (cx & FPSCR_FPRF) { 674 /* Need to replace CC */ 675 fsr &= ~FPSCR_FPRF; 676 } 677 if (cx & (FPSR_EXOP)) 678 fsr |= FPSCR_VX; 679 fsr |= cx; 680 DPRINTF(FPE_INSN, ("fpu_execute: cx %x, fsr %x\n", cx, fsr)); 681 } 682 683 if (cond) { 684 cond = fsr & 0xf0000000; 685 /* Isolate condition codes */ 686 cond >>= 28; 687 /* Move fpu condition codes to cr[1] */ 688 tf->cr &= (0x0f000000); 689 tf->cr |= (cond<<24); 690 DPRINTF(FPE_INSN, ("fpu_execute: cr[1] <= %x\n", cond)); 691 } 692 693 if (setcr) { 694 cond = fsr & FPSCR_FPCC; 695 /* Isolate condition codes */ 696 cond <<= 16; 697 /* Move fpu condition codes to cr[1] */ 698 tf->cr &= ~(0xf0000000>>bf); 699 tf->cr |= (cond>>bf); 700 DPRINTF(FPE_INSN, ("fpu_execute: cr[%d] (cr=%x) <= %x\n", bf/4, tf->cr, cond)); 701 } 702 703 ((int *)&fs->fpscr)[1] = fsr; 704 if (fsr & FPSCR_FEX) 705 return(FPE); 706 return (0); /* success */ 707 } 708
Indexes created Mon Sep 22 21:09:42 GMT 2025