fpu_emu.c revision 1.18
1 /* $NetBSD: fpu_emu.c,v 1.18 2016/12/15 11:32:03 rin Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1992, 1993 40 * The Regents of the University of California. All rights reserved. 41 * 42 * This software was developed by the Computer Systems Engineering group 43 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 44 * contributed to Berkeley. 45 * 46 * All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the University of 49 * California, Lawrence Berkeley Laboratory. 50 * 51 * Redistribution and use in source and binary forms, with or without 52 * modification, are permitted provided that the following conditions 53 * are met: 54 * 1. Redistributions of source code must retain the above copyright 55 * notice, this list of conditions and the following disclaimer. 56 * 2. Redistributions in binary form must reproduce the above copyright 57 * notice, this list of conditions and the following disclaimer in the 58 * documentation and/or other materials provided with the distribution. 59 * 3. Neither the name of the University nor the names of its contributors 60 * may be used to endorse or promote products derived from this software 61 * without specific prior written permission. 62 * 63 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 64 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 65 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 66 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 67 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 68 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 69 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 70 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 71 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 72 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 73 * SUCH DAMAGE. 74 * 75 * @(#)fpu.c 8.1 (Berkeley) 6/11/93 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: fpu_emu.c,v 1.18 2016/12/15 11:32:03 rin Exp $"); 80 81 #include "opt_ddb.h" 82 83 #include <sys/param.h> 84 #include <sys/proc.h> 85 #include <sys/signal.h> 86 #include <sys/signalvar.h> 87 #include <sys/siginfo.h> 88 #include <sys/systm.h> 89 #include <sys/syslog.h> 90 #include <sys/evcnt.h> 91 92 #include <powerpc/instr.h> 93 #include <machine/reg.h> 94 #include <machine/fpu.h> 95 #include <machine/trap.h> 96 97 #include <powerpc/fpu/fpu_emu.h> 98 #include <powerpc/fpu/fpu_extern.h> 99 100 #define FPU_EMU_EVCNT_DECL(name) \ 101 static struct evcnt fpu_emu_ev_##name = \ 102 EVCNT_INITIALIZER(EVCNT_TYPE_TRAP, NULL, "fpemu", #name); \ 103 EVCNT_ATTACH_STATIC(fpu_emu_ev_##name) 104 105 #define FPU_EMU_EVCNT_INCR(name) \ 106 fpu_emu_ev_##name.ev_count++ 107 108 FPU_EMU_EVCNT_DECL(stfiwx); 109 FPU_EMU_EVCNT_DECL(fpstore); 110 FPU_EMU_EVCNT_DECL(fpload); 111 FPU_EMU_EVCNT_DECL(fcmpu); 112 FPU_EMU_EVCNT_DECL(frsp); 113 FPU_EMU_EVCNT_DECL(fctiw); 114 FPU_EMU_EVCNT_DECL(fcmpo); 115 FPU_EMU_EVCNT_DECL(mtfsb1); 116 FPU_EMU_EVCNT_DECL(fnegabs); 117 FPU_EMU_EVCNT_DECL(mcrfs); 118 FPU_EMU_EVCNT_DECL(mtfsb0); 119 FPU_EMU_EVCNT_DECL(fmr); 120 FPU_EMU_EVCNT_DECL(mtfsfi); 121 FPU_EMU_EVCNT_DECL(fnabs); 122 FPU_EMU_EVCNT_DECL(fabs); 123 FPU_EMU_EVCNT_DECL(mffs); 124 FPU_EMU_EVCNT_DECL(mtfsf); 125 FPU_EMU_EVCNT_DECL(fctid); 126 FPU_EMU_EVCNT_DECL(fcfid); 127 FPU_EMU_EVCNT_DECL(fdiv); 128 FPU_EMU_EVCNT_DECL(fsub); 129 FPU_EMU_EVCNT_DECL(fadd); 130 FPU_EMU_EVCNT_DECL(fsqrt); 131 FPU_EMU_EVCNT_DECL(fsel); 132 FPU_EMU_EVCNT_DECL(fpres); 133 FPU_EMU_EVCNT_DECL(fmul); 134 FPU_EMU_EVCNT_DECL(frsqrte); 135 FPU_EMU_EVCNT_DECL(fmulsub); 136 FPU_EMU_EVCNT_DECL(fmuladd); 137 FPU_EMU_EVCNT_DECL(fnmsub); 138 FPU_EMU_EVCNT_DECL(fnmadd); 139 140 /* FPSR exception masks */ 141 #define FPSR_EX_MSK (FPSCR_VX|FPSCR_OX|FPSCR_UX|FPSCR_ZX| \ 142 FPSCR_XX|FPSCR_VXSNAN|FPSCR_VXISI|FPSCR_VXIDI| \ 143 FPSCR_VXZDZ|FPSCR_VXIMZ|FPSCR_VXVC|FPSCR_VXSOFT|\ 144 FPSCR_VXSQRT|FPSCR_VXCVI) 145 #define FPSR_EX (FPSCR_VE|FPSCR_OE|FPSCR_UE|FPSCR_ZE|FPSCR_XE) 146 #define FPSR_EXOP (FPSR_EX_MSK&(~FPSR_EX)) 147 148 149 int fpe_debug = 0; 150 151 #ifdef DDB 152 extern vaddr_t opc_disasm(vaddr_t loc, int opcode); 153 #endif 154 155 #ifdef DEBUG 156 /* 157 * Dump a `fpn' structure. 158 */ 159 void 160 fpu_dumpfpn(struct fpn *fp) 161 { 162 static const char *class[] = { 163 "SNAN", "QNAN", "ZERO", "NUM", "INF" 164 }; 165 166 printf("%s %c.%x %x %x %xE%d", class[fp->fp_class + 2], 167 fp->fp_sign ? '-' : ' ', 168 fp->fp_mant[0], fp->fp_mant[1], 169 fp->fp_mant[2], fp->fp_mant[3], 170 fp->fp_exp); 171 } 172 #endif 173 174 /* 175 * fpu_execute returns the following error numbers (0 = no error): 176 */ 177 #define FPE 1 /* take a floating point exception */ 178 #define NOTFPU 2 /* not an FPU instruction */ 179 #define FAULT 3 180 181 182 /* 183 * Emulate a floating-point instruction. 184 * Return zero for success, else signal number. 185 * (Typically: zero, SIGFPE, SIGILL, SIGSEGV) 186 */ 187 bool 188 fpu_emulate(struct trapframe *tf, struct fpreg *fpf, ksiginfo_t *ksi) 189 { 190 union instr insn; 191 struct fpemu fe; 192 193 KSI_INIT_TRAP(ksi); 194 ksi->ksi_signo = 0; 195 ksi->ksi_addr = (void *)tf->tf_srr0; 196 197 /* initialize insn.is_datasize to tell it is *not* initialized */ 198 fe.fe_fpstate = fpf; 199 fe.fe_cx = 0; 200 201 /* always set this (to avoid a warning) */ 202 203 if (copyin((void *) (tf->tf_srr0), &insn.i_int, sizeof (insn.i_int))) { 204 #ifdef DEBUG 205 printf("fpu_emulate: fault reading opcode\n"); 206 #endif 207 ksi->ksi_signo = SIGSEGV; 208 ksi->ksi_trap = EXC_ISI; 209 ksi->ksi_code = SEGV_MAPERR; 210 ksi->ksi_addr = (void *)tf->tf_srr0; 211 return true; 212 } 213 214 DPRINTF(FPE_EX, ("fpu_emulate: emulating insn %x at %p\n", 215 insn.i_int, (void *)tf->tf_srr0)); 216 217 if ((insn.i_any.i_opcd == OPC_TWI) || 218 ((insn.i_any.i_opcd == OPC_integer_31) && 219 (insn.i_x.i_xo == OPC31_TW))) { 220 /* Check for the two trap insns. */ 221 DPRINTF(FPE_EX, ("fpu_emulate: SIGTRAP\n")); 222 ksi->ksi_signo = SIGTRAP; 223 ksi->ksi_trap = EXC_PGM; 224 ksi->ksi_code = TRAP_TRACE; 225 ksi->ksi_addr = (void *)tf->tf_srr0; 226 return true; 227 } 228 switch (fpu_execute(tf, &fe, &insn)) { 229 case 0: 230 DPRINTF(FPE_EX, ("fpu_emulate: success\n")); 231 tf->tf_srr0 += 4; 232 return true; 233 234 case FPE: 235 DPRINTF(FPE_EX, ("fpu_emulate: SIGFPE\n")); 236 ksi->ksi_signo = SIGFPE; 237 ksi->ksi_trap = EXC_PGM; 238 return true; 239 240 case FAULT: 241 DPRINTF(FPE_EX, ("fpu_emulate: SIGSEGV\n")); 242 ksi->ksi_signo = SIGSEGV; 243 ksi->ksi_trap = EXC_DSI; 244 ksi->ksi_code = SEGV_MAPERR; 245 ksi->ksi_addr = (void *)fe.fe_addr; 246 return true; 247 248 case NOTFPU: 249 default: 250 DPRINTF(FPE_EX, ("fpu_emulate: SIGILL\n")); 251 #if defined(DDB) && defined(DEBUG) 252 if (fpe_debug & FPE_EX) { 253 printf("fpu_emulate: illegal insn %x at %p:", 254 insn.i_int, (void *) (tf->tf_srr0)); 255 opc_disasm((vaddr_t)(tf->tf_srr0), insn.i_int); 256 } 257 #endif 258 #if defined(PPC_IBM4XX) && defined(DDB) && defined(DEBUG) 259 /* 260 * XXXX retry an illegal insn once due to cache issues. 261 */ 262 static int lastill = 0; 263 if (lastill == tf->tf_srr0) { 264 if (fpe_debug & FPE_EX) 265 Debugger(); 266 } 267 lastill = tf->tf_srr0; 268 #endif /* PPC_IBM4XX && DDB && DEBUG */ 269 return false; 270 } 271 } 272 273 /* 274 * Execute an FPU instruction (one that runs entirely in the FPU; not 275 * FBfcc or STF, for instance). On return, fe->fe_fs->fs_fsr will be 276 * modified to reflect the setting the hardware would have left. 277 * 278 * Note that we do not catch all illegal opcodes, so you can, for instance, 279 * multiply two integers this way. 280 */ 281 int 282 fpu_execute(struct trapframe *tf, struct fpemu *fe, union instr *insn) 283 { 284 struct fpn *fp; 285 union instr instr = *insn; 286 int *a; 287 vaddr_t addr; 288 int ra, rb, rc, rt, type, mask, fsr, cx, bf, setcr; 289 unsigned int cond; 290 struct fpreg *fs; 291 292 /* Setup work. */ 293 fp = NULL; 294 fs = fe->fe_fpstate; 295 fe->fe_fpscr = ((int *)&fs->fpscr)[1]; 296 297 /* 298 * On PowerPC all floating point values are stored in registers 299 * as doubles, even when used for single precision operations. 300 */ 301 type = FTYPE_DBL; 302 cond = instr.i_any.i_rc; 303 setcr = 0; 304 bf = 0; /* XXX gcc */ 305 306 #if defined(DDB) && defined(DEBUG) 307 if (fpe_debug & FPE_EX) { 308 vaddr_t loc = tf->tf_srr0; 309 310 printf("Trying to emulate: %p ", (void *)loc); 311 opc_disasm(loc, instr.i_int); 312 } 313 #endif 314 315 /* 316 * `Decode' and execute instruction. 317 */ 318 319 if ((instr.i_any.i_opcd >= OPC_LFS && instr.i_any.i_opcd <= OPC_STFDU) || 320 instr.i_any.i_opcd == OPC_integer_31) { 321 /* 322 * Handle load/store insns: 323 * 324 * Convert to/from single if needed, calculate addr, 325 * and update index reg if needed. 326 */ 327 uint64_t buf; 328 size_t size = sizeof(float); 329 int store, update; 330 331 cond = 0; /* ld/st never set condition codes */ 332 333 334 if (instr.i_any.i_opcd == OPC_integer_31) { 335 if (instr.i_x.i_xo == OPC31_STFIWX) { 336 FPU_EMU_EVCNT_INCR(stfiwx); 337 338 /* Store as integer */ 339 ra = instr.i_x.i_ra; 340 rb = instr.i_x.i_rb; 341 DPRINTF(FPE_INSN, ("reg %d has %lx reg %d has %lx\n", 342 ra, tf->tf_fixreg[ra], rb, tf->tf_fixreg[rb])); 343 344 addr = tf->tf_fixreg[rb]; 345 if (ra != 0) 346 addr += tf->tf_fixreg[ra]; 347 rt = instr.i_x.i_rt; 348 a = (int *)&fs->fpreg[rt]; 349 DPRINTF(FPE_INSN, 350 ("fpu_execute: Store INT %x at %p\n", 351 a[1], (void *)addr)); 352 if (copyout(&a[1], (void *)addr, sizeof(int))) { 353 fe->fe_addr = addr; 354 return (FAULT); 355 } 356 return (0); 357 } 358 359 if ((instr.i_x.i_xo & OPC31_FPMASK) != OPC31_FPOP) 360 /* Not an indexed FP load/store op */ 361 return (NOTFPU); 362 363 store = (instr.i_x.i_xo & 0x80); 364 if (instr.i_x.i_xo & 0x40) 365 size = sizeof(double); 366 else 367 type = FTYPE_SNG; 368 update = (instr.i_x.i_xo & 0x20); 369 370 /* calculate EA of load/store */ 371 ra = instr.i_x.i_ra; 372 rb = instr.i_x.i_rb; 373 DPRINTF(FPE_INSN, ("reg %d has %lx reg %d has %lx\n", 374 ra, tf->tf_fixreg[ra], rb, tf->tf_fixreg[rb])); 375 addr = tf->tf_fixreg[rb]; 376 if (ra != 0) 377 addr += tf->tf_fixreg[ra]; 378 rt = instr.i_x.i_rt; 379 } else { 380 store = instr.i_d.i_opcd & 0x4; 381 if (instr.i_d.i_opcd & 0x2) 382 size = sizeof(double); 383 else 384 type = FTYPE_SNG; 385 update = instr.i_d.i_opcd & 0x1; 386 387 /* calculate EA of load/store */ 388 ra = instr.i_d.i_ra; 389 addr = instr.i_d.i_d; 390 DPRINTF(FPE_INSN, ("reg %d has %lx displ %lx\n", 391 ra, tf->tf_fixreg[ra], addr)); 392 if (ra != 0) 393 addr += tf->tf_fixreg[ra]; 394 rt = instr.i_d.i_rt; 395 } 396 397 if (update && ra == 0) 398 return (NOTFPU); 399 400 if (store) { 401 /* Store */ 402 FPU_EMU_EVCNT_INCR(fpstore); 403 if (type != FTYPE_DBL) { 404 DPRINTF(FPE_INSN, 405 ("fpu_execute: Store SNG at %p\n", 406 (void *)addr)); 407 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rt); 408 fpu_implode(fe, fp, type, (void *)&buf); 409 if (copyout(&buf, (void *)addr, size)) { 410 fe->fe_addr = addr; 411 return (FAULT); 412 } 413 } else { 414 DPRINTF(FPE_INSN, 415 ("fpu_execute: Store DBL at %p\n", 416 (void *)addr)); 417 if (copyout(&fs->fpreg[rt], (void *)addr, size)) { 418 fe->fe_addr = addr; 419 return (FAULT); 420 } 421 } 422 } else { 423 /* Load */ 424 FPU_EMU_EVCNT_INCR(fpload); 425 DPRINTF(FPE_INSN, ("fpu_execute: Load from %p\n", 426 (void *)addr)); 427 if (copyin((const void *)addr, &fs->fpreg[rt], size)) { 428 fe->fe_addr = addr; 429 return (FAULT); 430 } 431 if (type != FTYPE_DBL) { 432 fpu_explode(fe, fp = &fe->fe_f1, type, rt); 433 fpu_implode(fe, fp, FTYPE_DBL, 434 (u_int *)&fs->fpreg[rt]); 435 } 436 } 437 if (update) 438 tf->tf_fixreg[ra] = addr; 439 /* Complete. */ 440 return (0); 441 #ifdef notyet 442 } else if (instr.i_any.i_opcd == OPC_load_st_62) { 443 /* These are 64-bit extenstions */ 444 return (NOTFPU); 445 #endif 446 } else if (instr.i_any.i_opcd == OPC_sp_fp_59 || 447 instr.i_any.i_opcd == OPC_dp_fp_63) { 448 449 450 if (instr.i_any.i_opcd == OPC_dp_fp_63 && 451 !(instr.i_a.i_xo & OPC63M_MASK)) { 452 /* Format X */ 453 rt = instr.i_x.i_rt; 454 ra = instr.i_x.i_ra; 455 rb = instr.i_x.i_rb; 456 457 458 /* One of the special opcodes.... */ 459 switch (instr.i_x.i_xo) { 460 case OPC63_FCMPU: 461 FPU_EMU_EVCNT_INCR(fcmpu); 462 DPRINTF(FPE_INSN, ("fpu_execute: FCMPU\n")); 463 rt >>= 2; 464 fpu_explode(fe, &fe->fe_f1, type, ra); 465 fpu_explode(fe, &fe->fe_f2, type, rb); 466 fpu_compare(fe, 0); 467 /* Make sure we do the condition regs. */ 468 cond = 0; 469 /* N.B.: i_rs is already left shifted by two. */ 470 bf = instr.i_x.i_rs & 0xfc; 471 setcr = 1; 472 break; 473 474 case OPC63_FRSP: 475 /* 476 * Convert to single: 477 * 478 * PowerPC uses this to round a double 479 * precision value to single precision, 480 * but values in registers are always 481 * stored in double precision format. 482 */ 483 FPU_EMU_EVCNT_INCR(frsp); 484 DPRINTF(FPE_INSN, ("fpu_execute: FRSP\n")); 485 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rb); 486 fpu_implode(fe, fp, FTYPE_SNG, 487 (u_int *)&fs->fpreg[rt]); 488 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt); 489 type = FTYPE_DBL; 490 break; 491 case OPC63_FCTIW: 492 case OPC63_FCTIWZ: 493 FPU_EMU_EVCNT_INCR(fctiw); 494 DPRINTF(FPE_INSN, ("fpu_execute: FCTIW\n")); 495 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 496 type = FTYPE_INT; 497 break; 498 case OPC63_FCMPO: 499 FPU_EMU_EVCNT_INCR(fcmpo); 500 DPRINTF(FPE_INSN, ("fpu_execute: FCMPO\n")); 501 rt >>= 2; 502 fpu_explode(fe, &fe->fe_f1, type, ra); 503 fpu_explode(fe, &fe->fe_f2, type, rb); 504 fpu_compare(fe, 1); 505 /* Make sure we do the condition regs. */ 506 cond = 0; 507 /* N.B.: i_rs is already left shifted by two. */ 508 bf = instr.i_x.i_rs & 0xfc; 509 setcr = 1; 510 break; 511 case OPC63_MTFSB1: 512 FPU_EMU_EVCNT_INCR(mtfsb1); 513 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB1\n")); 514 fe->fe_fpscr |= 515 (~(FPSCR_VX|FPSR_EX) & (1<<(31-rt))); 516 break; 517 case OPC63_FNEG: 518 FPU_EMU_EVCNT_INCR(fnegabs); 519 DPRINTF(FPE_INSN, ("fpu_execute: FNEGABS\n")); 520 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 521 sizeof(double)); 522 a = (int *)&fs->fpreg[rt]; 523 *a ^= (1 << 31); 524 break; 525 case OPC63_MCRFS: 526 FPU_EMU_EVCNT_INCR(mcrfs); 527 DPRINTF(FPE_INSN, ("fpu_execute: MCRFS\n")); 528 cond = 0; 529 rt &= 0x1c; 530 ra &= 0x1c; 531 /* Extract the bits we want */ 532 mask = (fe->fe_fpscr >> (28 - ra)) & 0xf; 533 /* Clear the bits we copied. */ 534 fe->fe_cx = 535 (FPSR_EX_MSK | (0xf << (28 - ra))); 536 fe->fe_fpscr &= fe->fe_cx; 537 /* Now shove them in the right part of cr */ 538 tf->tf_cr &= ~(0xf << (28 - rt)); 539 tf->tf_cr |= (mask << (28 - rt)); 540 break; 541 case OPC63_MTFSB0: 542 FPU_EMU_EVCNT_INCR(mtfsb0); 543 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB0\n")); 544 fe->fe_fpscr &= 545 ((FPSCR_VX|FPSR_EX) & ~(1<<(31-rt))); 546 break; 547 case OPC63_FMR: 548 FPU_EMU_EVCNT_INCR(fmr); 549 DPRINTF(FPE_INSN, ("fpu_execute: FMR\n")); 550 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 551 sizeof(double)); 552 break; 553 case OPC63_MTFSFI: 554 FPU_EMU_EVCNT_INCR(mtfsfi); 555 DPRINTF(FPE_INSN, ("fpu_execute: MTFSFI\n")); 556 rb >>= 1; 557 rt &= 0x1c; /* Already left-shifted 4 */ 558 fe->fe_cx = rb << (28 - rt); 559 mask = 0xf<<(28 - rt); 560 fe->fe_fpscr = (fe->fe_fpscr & ~mask) | 561 fe->fe_cx; 562 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */ 563 break; 564 case OPC63_FNABS: 565 FPU_EMU_EVCNT_INCR(fnabs); 566 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 567 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 568 sizeof(double)); 569 a = (int *)&fs->fpreg[rt]; 570 *a |= (1 << 31); 571 break; 572 case OPC63_FABS: 573 FPU_EMU_EVCNT_INCR(fabs); 574 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 575 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 576 sizeof(double)); 577 a = (int *)&fs->fpreg[rt]; 578 *a &= ~(1 << 31); 579 break; 580 case OPC63_MFFS: 581 FPU_EMU_EVCNT_INCR(mffs); 582 DPRINTF(FPE_INSN, ("fpu_execute: MFFS\n")); 583 memcpy(&fs->fpreg[rt], &fs->fpscr, 584 sizeof(fs->fpscr)); 585 break; 586 case OPC63_MTFSF: 587 FPU_EMU_EVCNT_INCR(mtfsf); 588 DPRINTF(FPE_INSN, ("fpu_execute: MTFSF\n")); 589 if ((rt = instr.i_xfl.i_flm) == -1) 590 mask = -1; 591 else { 592 mask = 0; 593 /* Convert 1 bit -> 4 bits */ 594 for (ra = 0; ra < 8; ra ++) 595 if (rt & (1<<ra)) 596 mask |= (0xf<<(4*ra)); 597 } 598 a = (int *)&fs->fpreg[rt]; 599 fe->fe_cx = mask & a[1]; 600 fe->fe_fpscr = (fe->fe_fpscr&~mask) | 601 (fe->fe_cx); 602 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */ 603 break; 604 case OPC63_FCTID: 605 case OPC63_FCTIDZ: 606 FPU_EMU_EVCNT_INCR(fctid); 607 DPRINTF(FPE_INSN, ("fpu_execute: FCTID\n")); 608 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 609 type = FTYPE_LNG; 610 break; 611 case OPC63_FCFID: 612 FPU_EMU_EVCNT_INCR(fcfid); 613 DPRINTF(FPE_INSN, ("fpu_execute: FCFID\n")); 614 type = FTYPE_LNG; 615 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 616 type = FTYPE_DBL; 617 break; 618 default: 619 return (NOTFPU); 620 break; 621 } 622 } else { 623 /* Format A */ 624 rt = instr.i_a.i_frt; 625 ra = instr.i_a.i_fra; 626 rb = instr.i_a.i_frb; 627 rc = instr.i_a.i_frc; 628 629 type = FTYPE_SNG; 630 if (instr.i_any.i_opcd & 0x4) 631 type = FTYPE_DBL; 632 switch ((unsigned int)instr.i_a.i_xo) { 633 case OPC59_FDIVS: 634 FPU_EMU_EVCNT_INCR(fdiv); 635 DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n")); 636 fpu_explode(fe, &fe->fe_f1, type, ra); 637 fpu_explode(fe, &fe->fe_f2, type, rb); 638 fp = fpu_div(fe); 639 break; 640 case OPC59_FSUBS: 641 FPU_EMU_EVCNT_INCR(fsub); 642 DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n")); 643 fpu_explode(fe, &fe->fe_f1, type, ra); 644 fpu_explode(fe, &fe->fe_f2, type, rb); 645 fp = fpu_sub(fe); 646 break; 647 case OPC59_FADDS: 648 FPU_EMU_EVCNT_INCR(fadd); 649 DPRINTF(FPE_INSN, ("fpu_execute: FADD\n")); 650 fpu_explode(fe, &fe->fe_f1, type, ra); 651 fpu_explode(fe, &fe->fe_f2, type, rb); 652 fp = fpu_add(fe); 653 break; 654 case OPC59_FSQRTS: 655 FPU_EMU_EVCNT_INCR(fsqrt); 656 DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n")); 657 fpu_explode(fe, &fe->fe_f1, type, rb); 658 fp = fpu_sqrt(fe); 659 break; 660 case OPC63M_FSEL: 661 FPU_EMU_EVCNT_INCR(fsel); 662 DPRINTF(FPE_INSN, ("fpu_execute: FSEL\n")); 663 a = (int *)&fe->fe_fpstate->fpreg[ra]; 664 if ((*a & 0x80000000) && (*a & 0x7fffffff)) 665 /* fra < 0 */ 666 rc = rb; 667 DPRINTF(FPE_INSN, ("f%d => f%d\n", rc, rt)); 668 memcpy(&fs->fpreg[rt], &fs->fpreg[rc], 669 sizeof(double)); 670 break; 671 case OPC59_FRES: 672 FPU_EMU_EVCNT_INCR(fpres); 673 DPRINTF(FPE_INSN, ("fpu_execute: FPRES\n")); 674 fpu_explode(fe, &fe->fe_f1, type, rb); 675 fp = fpu_sqrt(fe); 676 /* now we've gotta overwrite the dest reg */ 677 *((int *)&fe->fe_fpstate->fpreg[rt]) = 1; 678 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 679 fpu_div(fe); 680 break; 681 case OPC59_FMULS: 682 FPU_EMU_EVCNT_INCR(fmul); 683 DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n")); 684 fpu_explode(fe, &fe->fe_f1, type, ra); 685 fpu_explode(fe, &fe->fe_f2, type, rc); 686 fp = fpu_mul(fe); 687 break; 688 case OPC63M_FRSQRTE: 689 /* Reciprocal sqrt() estimate */ 690 FPU_EMU_EVCNT_INCR(frsqrte); 691 DPRINTF(FPE_INSN, ("fpu_execute: FRSQRTE\n")); 692 fpu_explode(fe, &fe->fe_f1, type, rb); 693 fp = fpu_sqrt(fe); 694 fe->fe_f2 = *fp; 695 /* now we've gotta overwrite the dest reg */ 696 *((int *)&fe->fe_fpstate->fpreg[rt]) = 1; 697 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 698 fpu_div(fe); 699 break; 700 case OPC59_FMSUBS: 701 FPU_EMU_EVCNT_INCR(fmulsub); 702 DPRINTF(FPE_INSN, ("fpu_execute: FMULSUB\n")); 703 fpu_explode(fe, &fe->fe_f1, type, ra); 704 fpu_explode(fe, &fe->fe_f2, type, rc); 705 fp = fpu_mul(fe); 706 fe->fe_f1 = *fp; 707 fpu_explode(fe, &fe->fe_f2, type, rb); 708 fp = fpu_sub(fe); 709 break; 710 case OPC59_FMADDS: 711 FPU_EMU_EVCNT_INCR(fmuladd); 712 DPRINTF(FPE_INSN, ("fpu_execute: FMULADD\n")); 713 fpu_explode(fe, &fe->fe_f1, type, ra); 714 fpu_explode(fe, &fe->fe_f2, type, rc); 715 fp = fpu_mul(fe); 716 fe->fe_f1 = *fp; 717 fpu_explode(fe, &fe->fe_f2, type, rb); 718 fp = fpu_add(fe); 719 break; 720 case OPC59_FNMSUBS: 721 FPU_EMU_EVCNT_INCR(fnmsub); 722 DPRINTF(FPE_INSN, ("fpu_execute: FNMSUB\n")); 723 fpu_explode(fe, &fe->fe_f1, type, ra); 724 fpu_explode(fe, &fe->fe_f2, type, rc); 725 fp = fpu_mul(fe); 726 fe->fe_f1 = *fp; 727 fpu_explode(fe, &fe->fe_f2, type, rb); 728 fp = fpu_sub(fe); 729 /* Negate */ 730 fp->fp_sign ^= 1; 731 break; 732 case OPC59_FNMADDS: 733 FPU_EMU_EVCNT_INCR(fnmadd); 734 DPRINTF(FPE_INSN, ("fpu_execute: FNMADD\n")); 735 fpu_explode(fe, &fe->fe_f1, type, ra); 736 fpu_explode(fe, &fe->fe_f2, type, rc); 737 fp = fpu_mul(fe); 738 fe->fe_f1 = *fp; 739 fpu_explode(fe, &fe->fe_f2, type, rb); 740 fp = fpu_add(fe); 741 /* Negate */ 742 fp->fp_sign ^= 1; 743 break; 744 default: 745 return (NOTFPU); 746 break; 747 } 748 } 749 } else { 750 return (NOTFPU); 751 } 752 753 /* 754 * ALU operation is complete. Collapse the result and then check 755 * for exceptions. If we got any, and they are enabled, do not 756 * alter the destination register, just stop with an exception. 757 * Otherwise set new current exceptions and accrue. 758 */ 759 if (fp) 760 fpu_implode(fe, fp, type, (u_int *)&fs->fpreg[rt]); 761 cx = fe->fe_cx; 762 fsr = fe->fe_fpscr; 763 if (cx != 0) { 764 fsr &= ~FPSCR_FX; 765 if ((cx^fsr)&FPSR_EX_MSK) 766 fsr |= FPSCR_FX; 767 mask = fsr & FPSR_EX; 768 mask <<= (25-3); 769 if (cx & mask) 770 fsr |= FPSCR_FEX; 771 if (cx & FPSCR_FPRF) { 772 /* Need to replace CC */ 773 fsr &= ~FPSCR_FPRF; 774 } 775 if (cx & (FPSR_EXOP)) 776 fsr |= FPSCR_VX; 777 fsr |= cx; 778 DPRINTF(FPE_INSN, ("fpu_execute: cx %x, fsr %x\n", cx, fsr)); 779 } 780 781 if (cond) { 782 cond = fsr & 0xf0000000; 783 /* Isolate condition codes */ 784 cond >>= 28; 785 /* Move fpu condition codes to cr[1] */ 786 tf->tf_cr &= (0x0f000000); 787 tf->tf_cr |= (cond<<24); 788 DPRINTF(FPE_INSN, ("fpu_execute: cr[1] <= %x\n", cond)); 789 } 790 791 if (setcr) { 792 cond = fsr & FPSCR_FPCC; 793 /* Isolate condition codes */ 794 cond <<= 16; 795 /* Move fpu condition codes to cr[1] */ 796 tf->tf_cr &= ~(0xf0000000>>bf); 797 tf->tf_cr |= (cond>>bf); 798 DPRINTF(FPE_INSN, ("fpu_execute: cr[%d] (cr=%x) <= %x\n", bf/4, tf->tf_cr, cond)); 799 } 800 801 ((int *)&fs->fpscr)[1] = fsr; 802 if (fsr & FPSCR_FEX) 803 return(FPE); 804 return (0); /* success */ 805 } 806
Indexes created Tue Sep 23 07:09:52 GMT 2025