fpu_emu.c revision 1.23
1 /* $NetBSD: fpu_emu.c,v 1.23 2020/07/06 09:34:16 rin Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1992, 1993 40 * The Regents of the University of California. All rights reserved. 41 * 42 * This software was developed by the Computer Systems Engineering group 43 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 44 * contributed to Berkeley. 45 * 46 * All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the University of 49 * California, Lawrence Berkeley Laboratory. 50 * 51 * Redistribution and use in source and binary forms, with or without 52 * modification, are permitted provided that the following conditions 53 * are met: 54 * 1. Redistributions of source code must retain the above copyright 55 * notice, this list of conditions and the following disclaimer. 56 * 2. Redistributions in binary form must reproduce the above copyright 57 * notice, this list of conditions and the following disclaimer in the 58 * documentation and/or other materials provided with the distribution. 59 * 3. Neither the name of the University nor the names of its contributors 60 * may be used to endorse or promote products derived from this software 61 * without specific prior written permission. 62 * 63 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 64 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 65 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 66 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 67 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 68 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 69 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 70 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 71 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 72 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 73 * SUCH DAMAGE. 74 * 75 * @(#)fpu.c 8.1 (Berkeley) 6/11/93 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: fpu_emu.c,v 1.23 2020/07/06 09:34:16 rin Exp $"); 80 81 #ifdef _KERNEL_OPT 82 #include "opt_ddb.h" 83 #endif 84 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/evcnt.h> 88 #include <sys/proc.h> 89 #include <sys/siginfo.h> 90 #include <sys/signal.h> 91 #include <sys/signalvar.h> 92 #include <sys/syslog.h> 93 94 #include <powerpc/instr.h> 95 #include <machine/fpu.h> 96 #include <machine/reg.h> 97 #include <machine/trap.h> 98 99 #include <powerpc/fpu/fpu_emu.h> 100 #include <powerpc/fpu/fpu_extern.h> 101 102 #define FPU_EMU_EVCNT_DECL(name) \ 103 static struct evcnt fpu_emu_ev_##name = \ 104 EVCNT_INITIALIZER(EVCNT_TYPE_TRAP, NULL, "fpemu", #name); \ 105 EVCNT_ATTACH_STATIC(fpu_emu_ev_##name) 106 107 #define FPU_EMU_EVCNT_INCR(name) \ 108 fpu_emu_ev_##name.ev_count++ 109 110 FPU_EMU_EVCNT_DECL(stfiwx); 111 FPU_EMU_EVCNT_DECL(fpstore); 112 FPU_EMU_EVCNT_DECL(fpload); 113 FPU_EMU_EVCNT_DECL(fcmpu); 114 FPU_EMU_EVCNT_DECL(frsp); 115 FPU_EMU_EVCNT_DECL(fctiw); 116 FPU_EMU_EVCNT_DECL(fcmpo); 117 FPU_EMU_EVCNT_DECL(mtfsb1); 118 FPU_EMU_EVCNT_DECL(fnegabs); 119 FPU_EMU_EVCNT_DECL(mcrfs); 120 FPU_EMU_EVCNT_DECL(mtfsb0); 121 FPU_EMU_EVCNT_DECL(fmr); 122 FPU_EMU_EVCNT_DECL(mtfsfi); 123 FPU_EMU_EVCNT_DECL(fnabs); 124 FPU_EMU_EVCNT_DECL(fabs); 125 FPU_EMU_EVCNT_DECL(mffs); 126 FPU_EMU_EVCNT_DECL(mtfsf); 127 FPU_EMU_EVCNT_DECL(fctid); 128 FPU_EMU_EVCNT_DECL(fcfid); 129 FPU_EMU_EVCNT_DECL(fdiv); 130 FPU_EMU_EVCNT_DECL(fsub); 131 FPU_EMU_EVCNT_DECL(fadd); 132 FPU_EMU_EVCNT_DECL(fsqrt); 133 FPU_EMU_EVCNT_DECL(fsel); 134 FPU_EMU_EVCNT_DECL(fpres); 135 FPU_EMU_EVCNT_DECL(fmul); 136 FPU_EMU_EVCNT_DECL(frsqrte); 137 FPU_EMU_EVCNT_DECL(fmulsub); 138 FPU_EMU_EVCNT_DECL(fmuladd); 139 FPU_EMU_EVCNT_DECL(fnmsub); 140 FPU_EMU_EVCNT_DECL(fnmadd); 141 142 /* FPSR exception masks */ 143 #define FPSR_EX_MSK (FPSCR_VX|FPSCR_OX|FPSCR_UX|FPSCR_ZX| \ 144 FPSCR_XX|FPSCR_VXSNAN|FPSCR_VXISI|FPSCR_VXIDI| \ 145 FPSCR_VXZDZ|FPSCR_VXIMZ|FPSCR_VXVC|FPSCR_VXSOFT|\ 146 FPSCR_VXSQRT|FPSCR_VXCVI) 147 #define FPSR_EX (FPSCR_VE|FPSCR_OE|FPSCR_UE|FPSCR_ZE|FPSCR_XE) 148 #define FPSR_EXOP (FPSR_EX_MSK&(~FPSR_EX)) 149 150 151 int fpe_debug = 0; 152 153 #ifdef DDB 154 extern vaddr_t opc_disasm(vaddr_t loc, int opcode); 155 #endif 156 157 #ifdef DEBUG 158 /* 159 * Dump a `fpn' structure. 160 */ 161 void 162 fpu_dumpfpn(struct fpn *fp) 163 { 164 static const char *class[] = { 165 "SNAN", "QNAN", "ZERO", "NUM", "INF" 166 }; 167 168 KASSERT(fp != NULL); 169 170 printf("%s %c.%x %x %x %xE%d\n", class[fp->fp_class + 2], 171 fp->fp_sign ? '-' : ' ', 172 fp->fp_mant[0], fp->fp_mant[1], 173 fp->fp_mant[2], fp->fp_mant[3], 174 fp->fp_exp); 175 } 176 #endif 177 178 /* 179 * fpu_execute returns the following error numbers (0 = no error): 180 */ 181 #define FPE 1 /* take a floating point exception */ 182 #define NOTFPU 2 /* not an FPU instruction */ 183 #define FAULT 3 184 185 186 /* 187 * Emulate a floating-point instruction. 188 * Return zero for success, else signal number. 189 * (Typically: zero, SIGFPE, SIGILL, SIGSEGV) 190 */ 191 bool 192 fpu_emulate(struct trapframe *tf, struct fpreg *fpf, ksiginfo_t *ksi) 193 { 194 union instr insn; 195 struct fpemu fe; 196 197 KSI_INIT_TRAP(ksi); 198 ksi->ksi_signo = 0; 199 ksi->ksi_addr = (void *)tf->tf_srr0; 200 201 /* initialize insn.is_datasize to tell it is *not* initialized */ 202 fe.fe_fpstate = fpf; 203 fe.fe_cx = 0; 204 205 /* always set this (to avoid a warning) */ 206 207 if (copyin((void *) (tf->tf_srr0), &insn.i_int, sizeof (insn.i_int))) { 208 #ifdef DEBUG 209 printf("fpu_emulate: fault reading opcode\n"); 210 #endif 211 ksi->ksi_signo = SIGSEGV; 212 ksi->ksi_trap = EXC_ISI; 213 ksi->ksi_code = SEGV_MAPERR; 214 ksi->ksi_addr = (void *)tf->tf_srr0; 215 return true; 216 } 217 218 DPRINTF(FPE_EX, ("fpu_emulate: emulating insn %x at %p\n", 219 insn.i_int, (void *)tf->tf_srr0)); 220 221 if ((insn.i_any.i_opcd == OPC_TWI) || 222 ((insn.i_any.i_opcd == OPC_integer_31) && 223 (insn.i_x.i_xo == OPC31_TW))) { 224 /* Check for the two trap insns. */ 225 DPRINTF(FPE_EX, ("fpu_emulate: SIGTRAP\n")); 226 ksi->ksi_signo = SIGTRAP; 227 ksi->ksi_trap = EXC_PGM; 228 ksi->ksi_code = TRAP_TRACE; 229 ksi->ksi_addr = (void *)tf->tf_srr0; 230 return true; 231 } 232 switch (fpu_execute(tf, &fe, &insn)) { 233 case 0: 234 DPRINTF(FPE_EX, ("fpu_emulate: success\n")); 235 tf->tf_srr0 += 4; 236 return true; 237 238 case FPE: 239 DPRINTF(FPE_EX, ("fpu_emulate: SIGFPE\n")); 240 ksi->ksi_signo = SIGFPE; 241 ksi->ksi_trap = EXC_PGM; 242 return true; 243 244 case FAULT: 245 DPRINTF(FPE_EX, ("fpu_emulate: SIGSEGV\n")); 246 ksi->ksi_signo = SIGSEGV; 247 ksi->ksi_trap = EXC_DSI; 248 ksi->ksi_code = SEGV_MAPERR; 249 ksi->ksi_addr = (void *)fe.fe_addr; 250 return true; 251 252 case NOTFPU: 253 default: 254 DPRINTF(FPE_EX, ("fpu_emulate: SIGILL\n")); 255 #if defined(DDB) && defined(DEBUG) 256 if (fpe_debug & FPE_EX) { 257 printf("fpu_emulate: illegal insn %x at %p:", 258 insn.i_int, (void *) (tf->tf_srr0)); 259 opc_disasm((vaddr_t)(tf->tf_srr0), insn.i_int); 260 } 261 #endif 262 #if defined(PPC_IBM4XX) && defined(DDB) && defined(DEBUG) 263 /* 264 * XXXX retry an illegal insn once due to cache issues. 265 */ 266 static int lastill = 0; 267 if (lastill == tf->tf_srr0) { 268 if (fpe_debug & FPE_EX) 269 Debugger(); 270 } 271 lastill = tf->tf_srr0; 272 #endif /* PPC_IBM4XX && DDB && DEBUG */ 273 return false; 274 } 275 } 276 277 /* 278 * Execute an FPU instruction (one that runs entirely in the FPU; not 279 * FBfcc or STF, for instance). On return, fe->fe_fs->fs_fsr will be 280 * modified to reflect the setting the hardware would have left. 281 * 282 * Note that we do not catch all illegal opcodes, so you can, for instance, 283 * multiply two integers this way. 284 */ 285 int 286 fpu_execute(struct trapframe *tf, struct fpemu *fe, union instr *insn) 287 { 288 struct fpn *fp; 289 union instr instr = *insn; 290 int *a; 291 vaddr_t addr; 292 int ra, rb, rc, rt, type, mask, fsr, cx, bf, setcr; 293 unsigned int cond; 294 struct fpreg *fs; 295 296 /* Setup work. */ 297 fp = NULL; 298 fs = fe->fe_fpstate; 299 fe->fe_fpscr = ((int *)&fs->fpscr)[1]; 300 301 /* 302 * On PowerPC all floating point values are stored in registers 303 * as doubles, even when used for single precision operations. 304 */ 305 type = FTYPE_DBL; 306 cond = instr.i_any.i_rc; 307 setcr = 0; 308 bf = 0; /* XXX gcc */ 309 310 #if defined(DDB) && defined(DEBUG) 311 if (fpe_debug & FPE_EX) { 312 vaddr_t loc = tf->tf_srr0; 313 314 printf("Trying to emulate: %p ", (void *)loc); 315 opc_disasm(loc, instr.i_int); 316 } 317 #endif 318 319 /* 320 * `Decode' and execute instruction. 321 */ 322 323 if ((instr.i_any.i_opcd >= OPC_LFS && instr.i_any.i_opcd <= OPC_STFDU) || 324 instr.i_any.i_opcd == OPC_integer_31) { 325 /* 326 * Handle load/store insns: 327 * 328 * Convert to/from single if needed, calculate addr, 329 * and update index reg if needed. 330 */ 331 uint64_t buf; 332 size_t size = sizeof(float); 333 int store, update; 334 335 cond = 0; /* ld/st never set condition codes */ 336 337 338 if (instr.i_any.i_opcd == OPC_integer_31) { 339 if (instr.i_x.i_xo == OPC31_STFIWX) { 340 FPU_EMU_EVCNT_INCR(stfiwx); 341 342 /* Store as integer */ 343 ra = instr.i_x.i_ra; 344 rb = instr.i_x.i_rb; 345 DPRINTF(FPE_INSN, ("reg %d has %lx reg %d has %lx\n", 346 ra, tf->tf_fixreg[ra], rb, tf->tf_fixreg[rb])); 347 348 addr = tf->tf_fixreg[rb]; 349 if (ra != 0) 350 addr += tf->tf_fixreg[ra]; 351 rt = instr.i_x.i_rt; 352 a = (int *)&fs->fpreg[rt]; 353 DPRINTF(FPE_INSN, 354 ("fpu_execute: Store INT %x at %p\n", 355 a[1], (void *)addr)); 356 if (copyout(&a[1], (void *)addr, sizeof(int))) { 357 fe->fe_addr = addr; 358 return (FAULT); 359 } 360 return (0); 361 } 362 363 if ((instr.i_x.i_xo & OPC31_FPMASK) != OPC31_FPOP) 364 /* Not an indexed FP load/store op */ 365 return (NOTFPU); 366 367 store = (instr.i_x.i_xo & 0x80); 368 if (instr.i_x.i_xo & 0x40) 369 size = sizeof(double); 370 else 371 type = FTYPE_SNG; 372 update = (instr.i_x.i_xo & 0x20); 373 374 /* calculate EA of load/store */ 375 ra = instr.i_x.i_ra; 376 rb = instr.i_x.i_rb; 377 DPRINTF(FPE_INSN, ("reg %d has %lx reg %d has %lx\n", 378 ra, tf->tf_fixreg[ra], rb, tf->tf_fixreg[rb])); 379 addr = tf->tf_fixreg[rb]; 380 if (ra != 0) 381 addr += tf->tf_fixreg[ra]; 382 rt = instr.i_x.i_rt; 383 } else { 384 store = instr.i_d.i_opcd & 0x4; 385 if (instr.i_d.i_opcd & 0x2) 386 size = sizeof(double); 387 else 388 type = FTYPE_SNG; 389 update = instr.i_d.i_opcd & 0x1; 390 391 /* calculate EA of load/store */ 392 ra = instr.i_d.i_ra; 393 addr = instr.i_d.i_d; 394 DPRINTF(FPE_INSN, ("reg %d has %lx displ %lx\n", 395 ra, tf->tf_fixreg[ra], addr)); 396 if (ra != 0) 397 addr += tf->tf_fixreg[ra]; 398 rt = instr.i_d.i_rt; 399 } 400 401 if (update && ra == 0) 402 return (NOTFPU); 403 404 if (store) { 405 /* Store */ 406 FPU_EMU_EVCNT_INCR(fpstore); 407 if (type != FTYPE_DBL) { 408 DPRINTF(FPE_INSN, 409 ("fpu_execute: Store SNG at %p\n", 410 (void *)addr)); 411 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rt); 412 fpu_implode(fe, fp, type, (void *)&buf); 413 if (copyout(&buf, (void *)addr, size)) { 414 fe->fe_addr = addr; 415 return (FAULT); 416 } 417 } else { 418 DPRINTF(FPE_INSN, 419 ("fpu_execute: Store DBL at %p\n", 420 (void *)addr)); 421 if (copyout(&fs->fpreg[rt], (void *)addr, size)) { 422 fe->fe_addr = addr; 423 return (FAULT); 424 } 425 } 426 } else { 427 /* Load */ 428 FPU_EMU_EVCNT_INCR(fpload); 429 DPRINTF(FPE_INSN, ("fpu_execute: Load from %p\n", 430 (void *)addr)); 431 if (copyin((const void *)addr, &fs->fpreg[rt], size)) { 432 fe->fe_addr = addr; 433 return (FAULT); 434 } 435 if (type != FTYPE_DBL) { 436 fpu_explode(fe, fp = &fe->fe_f1, type, rt); 437 fpu_implode(fe, fp, FTYPE_DBL, 438 (u_int *)&fs->fpreg[rt]); 439 } 440 } 441 if (update) 442 tf->tf_fixreg[ra] = addr; 443 /* Complete. */ 444 return (0); 445 #ifdef notyet 446 } else if (instr.i_any.i_opcd == OPC_load_st_62) { 447 /* These are 64-bit extenstions */ 448 return (NOTFPU); 449 #endif 450 } else if (instr.i_any.i_opcd == OPC_sp_fp_59 || 451 instr.i_any.i_opcd == OPC_dp_fp_63) { 452 453 454 if (instr.i_any.i_opcd == OPC_dp_fp_63 && 455 !(instr.i_a.i_xo & OPC63M_MASK)) { 456 /* Format X */ 457 rt = instr.i_x.i_rt; 458 ra = instr.i_x.i_ra; 459 rb = instr.i_x.i_rb; 460 461 462 /* One of the special opcodes.... */ 463 switch (instr.i_x.i_xo) { 464 case OPC63_FCMPU: 465 FPU_EMU_EVCNT_INCR(fcmpu); 466 DPRINTF(FPE_INSN, ("fpu_execute: FCMPU\n")); 467 rt >>= 2; 468 fpu_explode(fe, &fe->fe_f1, type, ra); 469 fpu_explode(fe, &fe->fe_f2, type, rb); 470 fpu_compare(fe, 0); 471 /* Make sure we do the condition regs. */ 472 cond = 0; 473 /* N.B.: i_rs is already left shifted by two. */ 474 bf = instr.i_x.i_rs & 0xfc; 475 setcr = 1; 476 break; 477 478 case OPC63_FRSP: 479 /* 480 * Convert to single: 481 * 482 * PowerPC uses this to round a double 483 * precision value to single precision, 484 * but values in registers are always 485 * stored in double precision format. 486 */ 487 FPU_EMU_EVCNT_INCR(frsp); 488 DPRINTF(FPE_INSN, ("fpu_execute: FRSP\n")); 489 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rb); 490 fpu_implode(fe, fp, FTYPE_SNG, 491 (u_int *)&fs->fpreg[rt]); 492 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt); 493 type = FTYPE_DBL; 494 break; 495 case OPC63_FCTIW: 496 case OPC63_FCTIWZ: 497 FPU_EMU_EVCNT_INCR(fctiw); 498 DPRINTF(FPE_INSN, ("fpu_execute: FCTIW\n")); 499 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 500 type = FTYPE_INT; 501 break; 502 case OPC63_FCMPO: 503 FPU_EMU_EVCNT_INCR(fcmpo); 504 DPRINTF(FPE_INSN, ("fpu_execute: FCMPO\n")); 505 rt >>= 2; 506 fpu_explode(fe, &fe->fe_f1, type, ra); 507 fpu_explode(fe, &fe->fe_f2, type, rb); 508 fpu_compare(fe, 1); 509 /* Make sure we do the condition regs. */ 510 cond = 0; 511 /* N.B.: i_rs is already left shifted by two. */ 512 bf = instr.i_x.i_rs & 0xfc; 513 setcr = 1; 514 break; 515 case OPC63_MTFSB1: 516 FPU_EMU_EVCNT_INCR(mtfsb1); 517 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB1\n")); 518 fe->fe_fpscr |= 519 (~(FPSCR_VX|FPSR_EX) & (1<<(31-rt))); 520 break; 521 case OPC63_FNEG: 522 FPU_EMU_EVCNT_INCR(fnegabs); 523 DPRINTF(FPE_INSN, ("fpu_execute: FNEGABS\n")); 524 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 525 sizeof(double)); 526 a = (int *)&fs->fpreg[rt]; 527 *a ^= (1 << 31); 528 break; 529 case OPC63_MCRFS: 530 FPU_EMU_EVCNT_INCR(mcrfs); 531 DPRINTF(FPE_INSN, ("fpu_execute: MCRFS\n")); 532 cond = 0; 533 rt &= 0x1c; 534 ra &= 0x1c; 535 /* Extract the bits we want */ 536 mask = (fe->fe_fpscr >> (28 - ra)) & 0xf; 537 /* Clear the bits we copied. */ 538 fe->fe_cx = 539 (FPSR_EX_MSK | (0xf << (28 - ra))); 540 fe->fe_fpscr &= fe->fe_cx; 541 /* Now shove them in the right part of cr */ 542 tf->tf_cr &= ~(0xf << (28 - rt)); 543 tf->tf_cr |= (mask << (28 - rt)); 544 break; 545 case OPC63_MTFSB0: 546 FPU_EMU_EVCNT_INCR(mtfsb0); 547 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB0\n")); 548 fe->fe_fpscr &= 549 ((FPSCR_VX|FPSR_EX) & ~(1<<(31-rt))); 550 break; 551 case OPC63_FMR: 552 FPU_EMU_EVCNT_INCR(fmr); 553 DPRINTF(FPE_INSN, ("fpu_execute: FMR\n")); 554 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 555 sizeof(double)); 556 break; 557 case OPC63_MTFSFI: 558 FPU_EMU_EVCNT_INCR(mtfsfi); 559 DPRINTF(FPE_INSN, ("fpu_execute: MTFSFI\n")); 560 rb >>= 1; 561 rt &= 0x1c; /* Already left-shifted 4 */ 562 fe->fe_cx = rb << (28 - rt); 563 mask = 0xf<<(28 - rt); 564 fe->fe_fpscr = (fe->fe_fpscr & ~mask) | 565 fe->fe_cx; 566 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */ 567 break; 568 case OPC63_FNABS: 569 FPU_EMU_EVCNT_INCR(fnabs); 570 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 571 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 572 sizeof(double)); 573 a = (int *)&fs->fpreg[rt]; 574 *a |= (1 << 31); 575 break; 576 case OPC63_FABS: 577 FPU_EMU_EVCNT_INCR(fabs); 578 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 579 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 580 sizeof(double)); 581 a = (int *)&fs->fpreg[rt]; 582 *a &= ~(1 << 31); 583 break; 584 case OPC63_MFFS: 585 FPU_EMU_EVCNT_INCR(mffs); 586 DPRINTF(FPE_INSN, ("fpu_execute: MFFS\n")); 587 memcpy(&fs->fpreg[rt], &fs->fpscr, 588 sizeof(fs->fpscr)); 589 break; 590 case OPC63_MTFSF: 591 FPU_EMU_EVCNT_INCR(mtfsf); 592 DPRINTF(FPE_INSN, ("fpu_execute: MTFSF\n")); 593 if ((rt = instr.i_xfl.i_flm) == -1) 594 mask = -1; 595 else { 596 mask = 0; 597 /* Convert 1 bit -> 4 bits */ 598 for (ra = 0; ra < 8; ra ++) 599 if (rt & (1<<ra)) 600 mask |= (0xf<<(4*ra)); 601 } 602 a = (int *)&fs->fpreg[rt]; 603 fe->fe_cx = mask & a[1]; 604 fe->fe_fpscr = (fe->fe_fpscr&~mask) | 605 (fe->fe_cx); 606 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */ 607 break; 608 case OPC63_FCTID: 609 case OPC63_FCTIDZ: 610 FPU_EMU_EVCNT_INCR(fctid); 611 DPRINTF(FPE_INSN, ("fpu_execute: FCTID\n")); 612 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 613 type = FTYPE_LNG; 614 break; 615 case OPC63_FCFID: 616 FPU_EMU_EVCNT_INCR(fcfid); 617 DPRINTF(FPE_INSN, ("fpu_execute: FCFID\n")); 618 type = FTYPE_LNG; 619 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 620 type = FTYPE_DBL; 621 break; 622 default: 623 return (NOTFPU); 624 break; 625 } 626 } else { 627 /* Format A */ 628 rt = instr.i_a.i_frt; 629 ra = instr.i_a.i_fra; 630 rb = instr.i_a.i_frb; 631 rc = instr.i_a.i_frc; 632 633 /* 634 * All arithmetic operations work on registers, which 635 * are stored as doubles. 636 */ 637 type = FTYPE_DBL; 638 switch ((unsigned int)instr.i_a.i_xo) { 639 case OPC59_FDIVS: 640 FPU_EMU_EVCNT_INCR(fdiv); 641 DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n")); 642 fpu_explode(fe, &fe->fe_f1, type, ra); 643 fpu_explode(fe, &fe->fe_f2, type, rb); 644 fp = fpu_div(fe); 645 break; 646 case OPC59_FSUBS: 647 FPU_EMU_EVCNT_INCR(fsub); 648 DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n")); 649 fpu_explode(fe, &fe->fe_f1, type, ra); 650 fpu_explode(fe, &fe->fe_f2, type, rb); 651 fp = fpu_sub(fe); 652 break; 653 case OPC59_FADDS: 654 FPU_EMU_EVCNT_INCR(fadd); 655 DPRINTF(FPE_INSN, ("fpu_execute: FADD\n")); 656 fpu_explode(fe, &fe->fe_f1, type, ra); 657 fpu_explode(fe, &fe->fe_f2, type, rb); 658 fp = fpu_add(fe); 659 break; 660 case OPC59_FSQRTS: 661 FPU_EMU_EVCNT_INCR(fsqrt); 662 DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n")); 663 fpu_explode(fe, &fe->fe_f1, type, rb); 664 fp = fpu_sqrt(fe); 665 break; 666 case OPC63M_FSEL: 667 FPU_EMU_EVCNT_INCR(fsel); 668 DPRINTF(FPE_INSN, ("fpu_execute: FSEL\n")); 669 a = (int *)&fe->fe_fpstate->fpreg[ra]; 670 if ((*a & 0x80000000) && (*a & 0x7fffffff)) 671 /* fra < 0 */ 672 rc = rb; 673 DPRINTF(FPE_INSN, ("f%d => f%d\n", rc, rt)); 674 memcpy(&fs->fpreg[rt], &fs->fpreg[rc], 675 sizeof(double)); 676 break; 677 case OPC59_FRES: 678 FPU_EMU_EVCNT_INCR(fpres); 679 DPRINTF(FPE_INSN, ("fpu_execute: FPRES\n")); 680 fpu_explode(fe, &fe->fe_f1, type, rb); 681 fp = fpu_sqrt(fe); 682 /* now we've gotta overwrite the dest reg */ 683 *((int *)&fe->fe_fpstate->fpreg[rt]) = 1; 684 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 685 fpu_div(fe); 686 break; 687 case OPC59_FMULS: 688 FPU_EMU_EVCNT_INCR(fmul); 689 DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n")); 690 fpu_explode(fe, &fe->fe_f1, type, ra); 691 fpu_explode(fe, &fe->fe_f2, type, rc); 692 fp = fpu_mul(fe); 693 break; 694 case OPC63M_FRSQRTE: 695 /* Reciprocal sqrt() estimate */ 696 FPU_EMU_EVCNT_INCR(frsqrte); 697 DPRINTF(FPE_INSN, ("fpu_execute: FRSQRTE\n")); 698 fpu_explode(fe, &fe->fe_f1, type, rb); 699 fp = fpu_sqrt(fe); 700 fe->fe_f2 = *fp; 701 /* now we've gotta overwrite the dest reg */ 702 *((int *)&fe->fe_fpstate->fpreg[rt]) = 1; 703 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 704 fpu_div(fe); 705 break; 706 case OPC59_FMSUBS: 707 FPU_EMU_EVCNT_INCR(fmulsub); 708 DPRINTF(FPE_INSN, ("fpu_execute: FMULSUB\n")); 709 fpu_explode(fe, &fe->fe_f1, type, ra); 710 fpu_explode(fe, &fe->fe_f2, type, rc); 711 fp = fpu_mul(fe); 712 fe->fe_f1 = *fp; 713 fpu_explode(fe, &fe->fe_f2, type, rb); 714 fp = fpu_sub(fe); 715 break; 716 case OPC59_FMADDS: 717 FPU_EMU_EVCNT_INCR(fmuladd); 718 DPRINTF(FPE_INSN, ("fpu_execute: FMULADD\n")); 719 fpu_explode(fe, &fe->fe_f1, type, ra); 720 fpu_explode(fe, &fe->fe_f2, type, rc); 721 fp = fpu_mul(fe); 722 fe->fe_f1 = *fp; 723 fpu_explode(fe, &fe->fe_f2, type, rb); 724 fp = fpu_add(fe); 725 break; 726 case OPC59_FNMSUBS: 727 FPU_EMU_EVCNT_INCR(fnmsub); 728 DPRINTF(FPE_INSN, ("fpu_execute: FNMSUB\n")); 729 fpu_explode(fe, &fe->fe_f1, type, ra); 730 fpu_explode(fe, &fe->fe_f2, type, rc); 731 fp = fpu_mul(fe); 732 fe->fe_f1 = *fp; 733 fpu_explode(fe, &fe->fe_f2, type, rb); 734 fp = fpu_sub(fe); 735 /* Negate */ 736 fp->fp_sign ^= 1; 737 break; 738 case OPC59_FNMADDS: 739 FPU_EMU_EVCNT_INCR(fnmadd); 740 DPRINTF(FPE_INSN, ("fpu_execute: FNMADD\n")); 741 fpu_explode(fe, &fe->fe_f1, type, ra); 742 fpu_explode(fe, &fe->fe_f2, type, rc); 743 fp = fpu_mul(fe); 744 fe->fe_f1 = *fp; 745 fpu_explode(fe, &fe->fe_f2, type, rb); 746 fp = fpu_add(fe); 747 /* Negate */ 748 fp->fp_sign ^= 1; 749 break; 750 default: 751 return (NOTFPU); 752 break; 753 } 754 755 /* If the instruction was single precision, round */ 756 if (!(instr.i_any.i_opcd & 0x4)) { 757 fpu_implode(fe, fp, FTYPE_SNG, 758 (u_int *)&fs->fpreg[rt]); 759 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt); 760 } 761 } 762 } else { 763 return (NOTFPU); 764 } 765 766 /* 767 * ALU operation is complete. Collapse the result and then check 768 * for exceptions. If we got any, and they are enabled, do not 769 * alter the destination register, just stop with an exception. 770 * Otherwise set new current exceptions and accrue. 771 */ 772 if (fp) 773 fpu_implode(fe, fp, type, (u_int *)&fs->fpreg[rt]); 774 cx = fe->fe_cx; 775 fsr = fe->fe_fpscr; 776 if (cx != 0) { 777 fsr &= ~FPSCR_FX; 778 if ((cx^fsr)&FPSR_EX_MSK) 779 fsr |= FPSCR_FX; 780 mask = fsr & FPSR_EX; 781 mask <<= (25-3); 782 if (cx & mask) 783 fsr |= FPSCR_FEX; 784 if (cx & FPSCR_FPRF) { 785 /* Need to replace CC */ 786 fsr &= ~FPSCR_FPRF; 787 } 788 if (cx & (FPSR_EXOP)) 789 fsr |= FPSCR_VX; 790 fsr |= cx; 791 DPRINTF(FPE_INSN, ("fpu_execute: cx %x, fsr %x\n", cx, fsr)); 792 } 793 794 if (cond) { 795 cond = fsr & 0xf0000000; 796 /* Isolate condition codes */ 797 cond >>= 28; 798 /* Move fpu condition codes to cr[1] */ 799 tf->tf_cr &= (0x0f000000); 800 tf->tf_cr |= (cond<<24); 801 DPRINTF(FPE_INSN, ("fpu_execute: cr[1] <= %x\n", cond)); 802 } 803 804 if (setcr) { 805 cond = fsr & FPSCR_FPCC; 806 /* Isolate condition codes */ 807 cond <<= 16; 808 /* Move fpu condition codes to cr[1] */ 809 tf->tf_cr &= ~(0xf0000000>>bf); 810 tf->tf_cr |= (cond>>bf); 811 DPRINTF(FPE_INSN, ("fpu_execute: cr[%d] (cr=%x) <= %x\n", bf/4, tf->tf_cr, cond)); 812 } 813 814 ((int *)&fs->fpscr)[1] = fsr; 815 if (fsr & FPSCR_FEX) 816 return(FPE); 817 return (0); /* success */ 818 } 819
Indexes created Tue Sep 23 14:10:03 GMT 2025